Ultralow Offset Voltage Dual Op Amp AD708 PIN CONFIGURATION Very high dc precision 30 μV maximum offset voltage 0.3 μV/°C maximum offset voltage drift 0.35 μV p-p maximum voltage noise (0.1 Hz to 10 Hz) 5 million V/V minimum open-loop gain 130 dB minimum CMRR 120 dB minimum PSRR Matching characteristics 30 μV maximum offset voltage match 0.3 μV/°C maximum offset voltage drift match 130 dB minimum CMRR match Available in 8-lead narrow body, PDIP, and hermetic CERDIP and CERDIP/883B packages OUTPUT A 1 –IN A 2 +IN A 3 –VS 4 AD708 – + A – B + TOP VIEW (Not to Scale) 8 +VS 7 OUTPUT B 6 –IN B 5 +IN B 05789-001 FEATURES Figure 1. PDIP (N) and CERDIP (Q) Packages GENERAL DESCRIPTION The AD708 is a high precision, dual monolithic operational amplifier. Each amplifier individually offers excellent dc precision with maximum offset voltage and offset voltage drift of any dual bipolar op amp. The matching specifications are among the best available in any dual op amp. In addition, the AD708 provides 5 V/μV minimum open-loop gain and guaranteed maximum input voltage noise of 350 nV p-p (0.1 Hz to 10 Hz). All dc specifications show excellent stability over temperature, with offset voltage drift typically 0.1 μV/°C and input bias current drift of 25 pA/°C maximum. The AD708 is available in four performance grades. The AD708J is rated over the commercial temperature range of 0°C to 70°C and is available in a narrow body, PDIP. The AD708A and AD708B are rated over the industrial temperature range of −40°C to +85°C and are available in a CERDIP. The AD708S is rated over the military temperature range of −55°C to +125°C and is available in a CERDIP military version processed to MIL-STD-883B. PRODUCT HIGHLIGHTS 1. The combination of outstanding matching and individual specifications make the AD708 ideal for constructing high gain, precision instrumentation amplifiers. 2. The low offset voltage drift and low noise of the AD708 allow the designer to amplify very small signals without sacrificing overall system performance. 3. The AD708 10 V/μV typical open-loop gain and 140 dB common-mode rejection make it ideal for precision applications. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD708 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 10 Pin Configuration............................................................................. 1 Crosstalk Performance .............................................................. 10 General Description ......................................................................... 1 Operation with a Gain of −100................................................. 11 Product Highlights ........................................................................... 1 High Precision Programmable Gain Amplifier ..................... 11 Revision History ............................................................................... 2 Bridge Signal Conditioner......................................................... 12 Specifications..................................................................................... 3 Precision Absolute Value Circuit ............................................. 12 Absolute Maximum Ratings............................................................ 5 Selection of Passive Components............................................. 12 ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 13 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 13 Matching Characteristics............................................................. 9 REVISION HISTORY 1/06—Rev. B to Rev. C Updated Format..................................................................Universal Removed TO-99 Package ..................................................Universal Deleted AD707 References................................................Universal Deleted LT1002 Reference............................................................... 1 Deleted Figure 1................................................................................ 1 Deleted Metalization Photograph .................................................. 5 Moved Figure 25, Figure 26, and Figure 27 to Theory of Operation section .................................................... 10 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 2/91—Rev. A to Rev. B Rev. C | Page 2 of 16 AD708 SPECIFICATIONS @ 25°C and ±15 V dc, unless otherwise noted. Table 1. Parameter INPUT OFFSET VOLTAGE 2 Conditions TMIN to TMAX Drift Long Term Stability INPUT BIAS CURRENT TMIN to TMAX Average Drift OFFSET CURRENT VCM = 0 V TMIN to TMAX Average Drift MATCHING CHARACTERISTICS 3 Offset Voltage AD708J/AD708A Min 1 Typ Max1 30 100 50 150 0.3 1.0 0.3 1.0 2.5 2.0 4.0 15 40 0.5 2.0 2.0 4.0 2 60 Offset Voltage Drift Input Bias Current TMIN to TMAX TMIN to TMAX Power Supply Rejection TMIN to TMAX Channel Separation INPUT VOLTAGE NOISE INPUT CURRENT NOISE COMMON-MODE REJECTION RATIO OPEN-LOOP GAIN POWER SUPPLY REJECTION RATIO FREQUENCY RESPONSE Closed-Loop Bandwidth Slew Rate INPUT RESISTANCE Differential Common Mode 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz VCM = ±13 V TMIN to TMAX VO = ±10 V RLOAD ≥ 2 kΩ TMIN to TMAX VS = ±3 V to ±18 V TMIN to TMAX AD708B Typ Max1 5 50 15 65 0.1 0.4 0.3 0.5 1.0 1.0 2.0 10 25 0.1 1.0 0.2 1.5 1 25 120 110 110 110 135 140 120 120 0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 3 3 110 110 0.5 0.15 130 130 120 120 140 0.6 18 13.0 11.0 35 0.9 0.27 0.18 140 130 130 0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 10 130 130 5 5 120 120 0.9 0.3 0.5 0.15 60 200 Rev. C | Page 3 of 16 Min1 AD708S Typ Max1 5 30 15 50 0.1 0.3 0.3 0.5 1 1.0 4 10 30 0.1 1 0.2 1.5 1 25 50 75 0.4 1.0 2.0 80 150 1.0 4.0 5.0 TMIN to TMAX Common-Mode Rejection Min1 30 50 0.3 1.0 2.0 130 130 120 120 140 μV μV μV/°C nA nA dB dB dB dB dB μV p-p nV/√Hz nV/√Hz nV/√Hz pA p-p pA/√Hz pA/√Hz pA/√Hz dB dB 130 130 0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 10 130 130 4 4 120 120 10 7 130 130 V/μV V/μV dB dB 0.9 0.3 0.5 0.15 0.9 0.3 MHz V/μs 200 400 MΩ GΩ 200 400 0.6 12 11.0 11.0 35 0.8 0.23 0.17 140 Unit μV μV μV/°C μV/month nA nA pA/°C nA nA pA/°C 0.35 12 11 11 35 0.8 0.23 0.17 AD708 Parameter OUTPUT VOLTAGE OPEN-LOOP OUTPUT RESISTANCE POWER SUPPLY Quiescent Current Power Consumption Operating Range Conditions RLOAD ≥ 10 kΩ RLOAD ≥ 2 kΩ RLOAD ≥ 1 kΩ TMIN to TMAX AD708J/AD708A Min 1 Typ Max1 13.5 14 12.5 13.0 12.0 12.5 12.0 13.0 60 4.5 135 12 VS = ±15 V VS = ±3 V ±3 5.5 165 18 ±18 1 Min1 13.5 12.5 12.0 12.0 AD708B Typ Max1 14.0 13.0 12.5 13.0 60 4.5 135 12 ±3 5.5 165 18 ±18 Min1 13.5 12.5 12.0 12.0 AD708S Typ Max1 14 13 12.5 13 60 4.5 135 12 ±3 5.5 165 18 ±18 Unit ±V ±V ±V ±V Ω mA mW mW V All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. 2 Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C. 3 Matching is defined as the difference between parameters of the two amplifiers. Rev. C | Page 4 of 16 AD708 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation 1 Input Voltage 2 Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range (Q) Storage Temperature Range (N) Lead Temperature (Soldering 60 sec) Rating ±22 V ±VS Indefinite +VS and −VS −65°C to +150°C −65°C to +125°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Thermal Characteristics 8-lead PDIP: θJC = 33°C/W, θJA = 100°C/W 8-lead CERDIP: θJC = 30°C/W, θJA = 110°C/W 2 For supply voltages less than ±22 V, the absolute maximum input voltage is equal to the supply voltage. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 5 of 16 AD708 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±15 V and TA = 25°C, unless otherwise noted. 8 –0.5 7 +V SUPPLY CURRENT (mA) –1.0 –1.5 1.5 1.0 6 5 4 3 2 –V –VS 1 0 5 10 15 20 0 25 05789-005 0.5 05789-002 COMMON-MODE VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES) +VS 0 3 6 SUPPLY VOLTAGE (±V) Figure 2. Input Common-Mode Range vs. Supply Voltage 100 15 18 21 24 0.3 0.4 256 UNITS TESTED –55°C TO +125°C 90 +VOUT 80 NUMBER OF UNITS –1.0 –1.5 RL = 10kΩ RL = 2kΩ 1.5 1.0 60 50 40 30 0 5 10 15 20 05789-006 –VS 70 20 –VOUT 0.5 05789-003 OUTPUT VOLTAGE SWING (±V) (REFERRED TO SUPPLY VOLTAGES) 12 Figure 5. Supply Current vs. Supply Voltage +VS –0.5 9 SUPPLY VOLTAGE (±V) 10 0 –0.4 25 –0.3 –0.2 SUPPLY VOLTAGE (±V) –0.1 0 0.1 0.2 OFFSET VOLTAGE DRIFT (µV/°C) Figure 3. Output Voltage Swing vs. Supply Voltage Figure 6. Typical Distribution of Offset Voltage Drift 35 100 IO = 1mA OUTPUT IMPEDANCE (Ω) 10 25 20 ±15V SUPPLIES 15 10 AV = +1000 1 AV = +1 0.1 0.01 0 10 100 1k 0.0001 0.1 10k LOAD RESISTANCE (Ω) 05789-007 0.001 5 05789-004 OUTPUT VOLTAGE (V p-p) 30 1 10 100 1k 10k FREQUENCY (Hz) Figure 7. Output Impedance vs. Frequency Figure 4. Output Voltage Swing vs. Load Resistance Rev. C | Page 6 of 16 100k 16 35 14 30 12 OPEN-LOOP GAIN (V/µV) 40 20 15 10 5 8 VOUT = ±10V 6 4 0 1 10 RL = 10kΩ RL = 2kΩ 2 0 –60 100 –40 –20 0 DIFFERENTIAL VOLTAGE (±V) 16 40 14 35 30 25 1/F CORNER 0.7Hz 15 100 120 140 RLOAD = 2kΩ 8 6 4 10 0 100 05789-012 2 05789-009 5 1 80 10 10 0.1 60 12 OPEN-LOOP GAIN (V/µV) INPUT VOLTAGE NOISE (nV/ Hz) 45 0 40 Figure 11. Open-Loop Gain vs. Temperature Figure 8. Input Bias Current vs. Differential Input Voltage 20 20 TEMPERATURE (°C) 0 5 10 15 25 20 SUPPLY VOLTAGE (V) FREQUENCY (Hz) Figure 9. Input Noise Spectral Density Figure 12. Open-Loop Gain vs. Supply Voltage 140 RL = 2kΩ CL = 1000pF 1s OPEN-LOOP GAIN (dB) 100 30 60 80 90 PHASE MARGIN = 43° 60 120 40 150 GAIN 20 180 05789-010 0 –20 TIME (1s/DIV) 05789-013 VOLTAGE NOISE (100nV/DIV) 120 0 0.01 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 10. 0.1 Hz to 10 Hz Voltage Noise Figure 13. Open-Loop Gain and Phase vs. Frequency Rev. C | Page 7 of 16 PHASE (Degrees) 0 10 05789-011 25 05789-008 INVERTING OR NONINVERTING INPUT BIAS CURRENT (mA) AD708 10M AD708 160 2mV/DIV 120 100 80 60 40 CH1 0 0.1 05789-014 20 1 10 100 1k 10k 100k 05789-017 COMMON-MODE REJECTION (dB) 140 TIME (2µs/DIV) 1M FREQUENCY (Hz) Figure 14. Common-Mode Rejection vs. Frequency 35 RL = 2kΩ 25°C VS = ±15V FMAX = 2.8kHz 30 2mV/DIV 25 20 15 10 CH1 05789-015 5 0 1k 10k 100k 05789-018 OUTPUT VOLTAGE (V p-p) Figure 17. Small Signal Transient Response; AV = +1, RL = 2 kΩ, CL = 50 pF TIME (2µs/DIV) 1M FREQUENCY (Hz) Figure 18. Small Signal Transient Response; AV = +1, RL = 2 kΩ, CL = 1000 pF Figure 15. Large Signal Frequency Response 160 120 100 80 60 40 20 0 0.001 05789-016 POWER SUPPLY REJECTION (dB) 140 0.01 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 16. Power Supply Rejection vs. Frequency Rev. C | Page 8 of 16 AD708 MATCHING CHARACTERISTICS 32 16 25°C 14 PERCENTAGE OF UNITS (%) 24 20 16 12 8 0 –50 –40 –30 –20 –10 0 10 20 30 40 10 8 6 4 2 05789-019 4 12 0 –1.0 50 05789-022 PERCENTAGE OF UNITS (%) 28 –0.8 –0.6 OFFSET VOLTAGE MATCH (µV) –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 OFFSET CURRENT MATCH (nA) Figure 19. Typical Distribution of Offset Voltage Match Figure 22. Typical Distribution of Input Offset Current Match 32 160 140 24 120 20 16 12 100 80 60 8 40 4 20 0 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0 –60 0.5 05789-023 PSRR MATCH (dB) 28 05789-020 PERCENTAGE OF UNITS (%) –55°C TO +125°C –40 –20 0 OFFSET DRIFT MATCH (µV/°C) 160 14 140 12 120 10 8 6 20 0 0.2 0.4 120 140 120 140 60 2 –0.2 100 80 40 –0.4 80 100 4 –0.6 60 0.6 0.8 0 –60 1.0 INPUT BIAS CURRENT MATCH (nA) 05789-024 CMRR MATCH (dB) 16 –0.8 40 Figure 23. PSRR Match vs. Temperature 05789-021 PERCENTAGE OF UNITS (%) Figure 20. Typical Distribution of Offset Voltage Drift Match 0 –1.0 20 TEMPERATURE (°C) –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 21. Typical Distribution of Input Bias Current Match Figure 24. CMRR Match vs. Temperature Rev. C | Page 9 of 16 AD708 THEORY OF OPERATION CROSSTALK PERFORMANCE Power = (30 V)(5 mA) = 150 mW Even this large change in power causes only an 8 μV (linear) change in the input offset voltage of Side B. VOUTA 2kΩ 10kΩ B 10Ω VOUTB 10Ω 2V VOUTA 05789-026 A VIN = ±10V A VIN = ±10V ΔVOSB = 1µV/DIV The AD708 exhibits very low crosstalk as shown in Figure 25, Figure 26, and Figure 27. Figure 25 shows the offset voltage induced on Side B of the AD708 when Side A output is moving slowly (0.2 Hz) from −10 V to +10 V under no load. This is the least stressful situation to the part because the overall power in the chip does not change. Only the location of the power in the output device changes. Figure 26 shows the input offset voltage change to Side B when Side A is driving a 2 kΩ load. Here the power changes in the chip with the maximum power change occurring at 7.5 V. Figure 27 shows crosstalk under the most severe conditions. Side A is connected as a follower with 0 V input, and is forced to sink and source ±5 mA of output current. VOUTA = 2V/DIV 10kΩ Figure 26. Crosstalk with 2 kΩ Load B 10Ω VOUTB 10Ω IIN = ±5mA A 2V 2kΩ VIN = ±10V 10kΩ ΔVOSB = 1µV/DIV B 10Ω VOUTB 10Ω ΔVOSB = 2µV/DIV 05789-025 2V VOUTA = 2V/DIV 05789-027 Figure 25. Crosstalk with No Load INA = 1mA/DIV Figure 27. Crosstalk Under Forced Source and Sink Conditions Rev. C | Page 10 of 16 AD708 1/2 OPERATION WITH A GAIN OF −100 VINA To show the outstanding dc precision of the AD708 in a real application, Table 3 shows an error budget calculation for a gain of −100. This configuration is shown in Figure 28. A0 AD708 OUT 1–4 10kΩ 10kΩ 10kΩ A1 S1 S2 9.9kΩ S3 Table 3. S4 9.9kΩ S7 S5 OUT 5–8 10 V/(5 × 106)/100 mV = 20 ppm = 4 ppm VOS Drift (0.3 mV/°C)/100 mV = 3 ppm/°C @ 25°C = 334 ppm > 11 bits −55°C to +125°C = 634 ppm > 10 bits @ 25°C = 34 ppm > 14 bits −55°C to +125°C = 334 ppm > 11 bits VINB RB 10kΩ 10kΩ 10kΩ 05789-029 = 10 ppm 0.35 mV/100 mV 1/2 AD708 Total Unadjusted Figure 29. Precision PGA With Offset 100kΩ +VS 0.1µF 1kΩ 2 – 1/2 6 AD708 3 + 4 1kΩ The gains of the circuit are controlled by the select lines, A0 and A1, of the AD7502 multiplexer, and are 1, 10, 100, and 1000 in this design. The input stage attains very high dc precision due to the 30 μV maximum offset voltage match of the AD708S and the 1 nA maximum input bias current match. The accuracy is maintained over temperature because of the ultralow drift performance of the AD708. To achieve 0.1% gain accuracy, along with high common-mode rejection, the circuit should be trimmed. 7 VOUT To maximize common-mode rejection 0.1µF –VS 05789-028 VIN AD707 10kΩ S6 Noise Calibrated Out 10kΩ S8 +VS Gain (2 kΩ Load) Error 1kΩ 26.1Ω (100 kΩ)(1 nA)/10 V 100Ω –VS 26.1Ω IOS 10kΩ AD7502 26.1Ω Error Sources VOS Maximum Error Contribution AV = 100 (S Grade) (Full Scale: VOUT = 10 V, VIN = 100 mV) 30 μV/100 mV = 300 ppm RA Figure 28. Gain of −100 Configuration This error budget assumes no error in the resistor ratio and no error from power supply variation (the 120 dB minimum PSRR of the AD708S makes this a good assumption). The external resistors can cause gain error from mismatch and drift over temperature. HIGH PRECISION PROGRAMMABLE GAIN AMPLIFIER The three op amp programmable gain amplifier shown in Figure 29 takes advantage of the outstanding matching characteristics of the AD708 to achieve high dc precision. 1. Set the select lines for gain = 1 and ground VINB. 2. Apply a precision dc voltage to VINA and trim RA until VO = −VINA to the required precision. 3. Connect VINB to VINA and apply an input voltage equal to the full-scale common mode expected. 4. Trim RB until VO = 0 V. B To minimize gain errors 1. Select gain = 10 with the control lines and apply a differential input voltage. 2. Adjust the 100 Ω potentiometer to VO = 10 VIN (adjust VIN magnitude as necessary). 3. Repeat Step 1 and Step 2 for gain = 100 and gain = 1000, adjusting the 1 kΩ and 10 kΩ potentiometers, respectively. The design shown in Figure 29 should allow for 0.1% gain accuracy and 0.1 μV/V common-mode rejection when ±1% resistors and ±5% potentiometers are used. Rev. C | Page 11 of 16 AD708 BRIDGE SIGNAL CONDITIONER The AD708 can be used in the circuit shown in Figure 30 to produce an accurate and inexpensive dynamic bridge conditioner. The low offset voltage match and low offset voltage drift match of the AD708 combine to achieve circuit performance better than all but the best instrumentation amplifiers. The outstanding specifications of the AD708, such as open-loop gain, input offset currents, and low input bias currents, do not limit circuit accuracy. As configured, the circuit only requires a gain resistor, RG, of suitable accuracy and a stable, accurate voltage reference. The transfer function is AD708 enables this circuit to accurately resolve the input signal. In addition, the tight offset voltage drift match maintains the resolution of the circuit over the full military temperature range. The high dc open-loop gain and exceptional gain linearity allows the circuit to perform well at both large and small signal levels. In this circuit, the only significant dc errors are due to the offset voltage of the two amplifiers, the input offset current match of the amplifiers, and the mismatch of the resistors. Errors associated with the AD708S contribute less than 0.001% error over −55°C to +125°C. Maximum error at 25°C 30 μV + (10 kΩ )(1 nA ) VO = VREF [ΔR/(R + ΔR)][RG/R] 10 V The only significant errors due to the AD708S are VOS_OUT = (VOS_MATCH)(2RG/R) = 30 mV Maximum error at +125°C or −55°C 50 μV + (2 nA )(10 kΩ ) VOS_OUT (T) = (VOS_DRIFT)(2RG/R) = 0.3 mV/°C To achieve high accuracy, Resistor RG should be 0.1% or better with a low drift coefficient. +15V AD580 RG 175kΩ 2.5V VREF R R = 350Ω 10 V = 7 ppm @ + 125 °C Figure 32 shows VOUT vs. VIN for this circuit with a ±3 mV input signal at 0.05 Hz. Note that the circuit exhibits very low offset at the zero crossing. This circuit can also produce VOUT = −|VIN| by reversing the polarity of the two diodes. 1/2 AD708 R = 40 μV/10 μV = 4 ppm 1mV 1mV VO R + ΔR VOUT = 1mV/DIV 1/2 AD708 05789-030 887Ω –15V Figure 30. Bridge Signal Conditioning Circuit 10kΩ IN459 1 10kΩ 10kΩ 5kΩ IN4591 3.75kΩ VIN 05789-032 10kΩ 1/2 VO = |VIN| VIN = 1mV/DIV AD708 Figure 32. Absolute Value Circuit Performance (Input Signal = 0.05 Hz) 1/2 AD708 NOTE 1LOW LEAKAGE DIODES SELECTION OF PASSIVE COMPONENTS 05789-031 5kΩ Figure 31. Precision Absolute Value Circuit PRECISION ABSOLUTE VALUE CIRCUIT The AD708 is ideally suited to the precision absolute value circuit shown in Figure 31. The low offset voltage match of the Use high quality passive components to take full advantage of the high precision and low drift characteristics of the AD708. Discrete resistors and resistor networks with temperature coefficients of less than 10 ppm/°C are available from Vishay, Caddock, Precision Replacement Parts (PRP), and others. Rev. C | Page 12 of 16 AD708 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.005 (0.13) MIN 0.055 (1.40) MAX 8 8 1 5 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.310 (7.87) 0.220 (5.59) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.060 (1.52) MAX 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.005 (0.13) MIN 1 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 4 0.100 (2.54) BSC 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 5 0.070 (1.78) 0.030 (0.76) SEATING PLANE 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) Figure 34. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model AD708JN AD708JNZ 1 AD708AQ AD708BQ AD708SQ/883B 1 Temperature Range 0°C to +70°C 0°C to +70°C −40°C to +85°C −40°C to +85°C −55°C to +125°C Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] Z = Pb-free part. Rev. C | Page 13 of 16 Package Option N-8 N-8 Q-8 Q-8 Q-8 AD708 NOTES Rev. C | Page 14 of 16 AD708 NOTES Rev. C | Page 15 of 16 AD708 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C05789-0-1/06(C) Rev. C | Page 16 of 16