Cypress CY7C64601 Ez-usb fx usb microcontroller data sheet Datasheet

4601/603/61
CY7C64601/603/613
CY7C64601/603/613
EZ-USB FX USB Microcontroller
Data Sheet
Cypress Semiconductor Corporation
Document #: 38-08005 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 21, 2001
CY7C64601/603/613
TABLE OF CONTENTS
1.0 FEATURES ...................................................................................................................................... 3
1.1 EZ-USB FX Features ....................................................................................................................... 3
1.2 Example Applications .................................................................................................................... 4
2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 4
2.1 Microprocessor ............................................................................................................................... 5
2.2 USB SIE ........................................................................................................................................... 5
2.3 Endpoints ........................................................................................................................................ 6
2.4 Default USB Machine ...................................................................................................................... 7
2.5 IBN (In-Bulk-NAK) Interrupts ......................................................................................................... 7
2.6 Slave FIFOs ..................................................................................................................................... 7
2.7 DMA .................................................................................................................................................. 8
2.8 GPIF (General Programmable Interface) ...................................................................................... 8
3.0 PIN ASSIGNMENTS ........................................................................................................................ 9
3.1 Pin Diagrams ................................................................................................................................... 9
3.2 CY7C646xx Pin Descriptions ....................................................................................................... 13
4.0 REGISTER SUMMARY .................................................................................................................. 22
5.0 INPUT/OUTPUT PIN SPECIAL CONSIDERATION ...................................................................... 29
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 29
7.0 OPERATING CONDITIONS ........................................................................................................... 29
8.0 DC CHARACTERISTICS ............................................................................................................... 29
9.0 AC ELECTRICAL CHARACTERISTICS ....................................................................................... 30
9.1 USB Transceiver ........................................................................................................................... 30
9.2 Program Memory Read ................................................................................................................ 30
9.3 Data Memory Read ....................................................................................................................... 31
9.4 Data Memory Write ....................................................................................................................... 32
9.5 DMA Read ...................................................................................................................................... 33
9.6 DMA Write ...................................................................................................................................... 34
9.7 Slave FIFOs—Output Enables ..................................................................................................... 34
9.8 Slave FIFOs—Synchronous Read ............................................................................................... 35
9.9 Slave FIFOs—Synchronous Write ............................................................................................... 35
9.10 Slave FIFOs—Asynchronous Read[9, 10] ....................................................................................................................................36
9.11 Slave FIFOs—Asynchronous Write[9, 10] ...................................................................................................................................36
9.12 GPIF Signals (Internally Clocked) ............................................................................................. 37
9.13 GPIF Signals (Externally Clocked) ............................................................................................ 37
10.0 ORDERING INFORMATION ........................................................................................................ 38
11.0 PACKAGE DIAGRAMS ............................................................................................................... 38
11.1 52 PQFP ....................................................................................................................................... 38
11.2 80 PQFP ....................................................................................................................................... 40
11.3 128 PQFP ..................................................................................................................................... 42
Document #: 38-08005 Rev. **
Page 2 of 42
CY7C64601/603/613
1.0
Features
The CY7C646xx (EZ-USB FX) is Cypress Semiconductor’s second-generation full-speed USB family. FX products offer higher
performance and a higher level of integration than first-generation EZ-USB products. The FX builds on the EZ-USB feature set,
including an intelligent USB core, enhanced 8051, 8-Kbyte RAM, and high-performance I/O. The CY7C646xx enhances the EZUSB family by providing faster operation and more ways to transfer data into and out of the chip at very high speed.
12 MHz
4-clock cycle
Enhanced
USB
SIE
4/8KB
RAM
SIO
Data Bus (8)
Transceiver
8051 Core
USB
GPIF
48 MHz,
X4
PLL
Data(8)
ADDR(16)
XTAL
2 KB
SIO
3 Timers
I/O Ports
4 x 64 bytes
FIFOs
8/16
bits
FIFO
(ISO)
DMA
CY7C64613-128
1.1
I2C
Engine
EZ-USB FX Features
• Single-chip integrated USB Transceiver, Serial Interface Engine (SIE), and Enhanced 8051 Microprocessor
• Soft: 8051 runs from internal RAM, which is:
— Downloaded via USB, or
— Loaded from EEPROM
• 14 Bulk/Interrupt endpoints, each with a maximum packet size of 64 bytes
• 16 Isochronous endpoints, with 2 KB of buffer space (1 KB, double buffered) which may be divided among the sixteen
isochronous endpoints
• Integrated, industry standard 8051 with enhanced features:
— Four clocks per cycle
— Two UARTS
— Three counter/timers
— Expanded interrupt system
•
•
•
•
•
•
•
— Two data pointers
3.3-volt operation
Smart Serial Interface Engine (SIE)
Vectored USB interrupts
Separate buffers for the SETUP and DATA portions of a CONTROL transfer
Integrated I2C™ controller
48-MHz or 24-MHz 8051 operation
Enhanced IO
— IO port registers mapped to SFRs
— Port bits can be controlled using 8051 bit addressing instructions
• Four integrated general purpose 8-bit FIFOs
— 64 bytes each
— Automatic conversion to and from 16-bit buses
Document #: 38-08005 Rev. **
Page 3 of 42
CY7C64601/603/613
— FIFOs can use externally supplied clock
— Easy interface to ASIC and DSP ICs
— Brings glue FIFOs inside for lower system cost
• DMA Controller
— Moves data between slave FIFOs, memory, and ports
— Very fast transfers—one clock (20.8 ns) per byte for internal transfers
— Can use external RAM as additional FIFO (addressed through A/D buses)
• Special Autovectors for DMA and FIFO interrupts
• 400-kHz or 100-kHz I2C operation
• General Programmable Interface (GPIF)
— Allows direct connection to most parallel interfaces: 8- and 16-bit
— Programmable Waveform Descriptors and Configuration Registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL) outputs
• Three package options - 128-pin PQFP, 80-pin PQFP, and 52-pin PQFP
1.2
•
•
•
•
•
•
•
•
•
•
Example Applications
DSL modems
ATAPI interface
Memory card readers
Legacy conversion devices
Cameras
Scanners
Home PNA
Wireless LAN
MP3 players
Networking
2.0
Functional Overview
The CY7C646xx enhances the line of Cypress EZ-USB chips while maintaining code compatibility. The CY7C646xx builds on the
feature set that has already made the EZ-USB family a popular choice for high-integration, high-speed USB applications:
• Soft operation. Program code can be downloaded into on-chip RAM via the USB cable, eliminating the need for external
program memory or mask ROM headaches.
• Enhanced 8051. A speedy four clocks per cycle, plus expanded features.
• Smart SIE. The USB Serial Interface Engine does much of the low-level USB overhead in logic, simplifying the 8051 code.
• DMA for very fast 8-bit or 16-bit transfers. In the fastest (synchronous byte) mode, one byte can be transferred per 48-MHz
clock, or every 20.8 nanoseconds.
• General Programmable Interface (GPIF). A reconfigurable 8- or 16-bit parallel interface allows the CY7C646xx to perform
local bus mastering, and can implement a wide variety of protocols such as ATAPI, printer parallel port, and Utopia.
• Abundant endpoints and buffers. 16x64 byte buffers for bulk/interrupt/control endpoints, 2x1024 byte FIFOs for up to 16
isochronous endpoints.
• Glueless memory expansion. The 8051 16-bit address bus and 8-bit data bus is available, along with strobes RD#, WR#,
OE# and CS#. The buses are brought out on separate pins (not multiplexed, as in the standard 8051), saving one clock per
external memory cycle.
• 48-MHz or 24-MHz 8051 selectable by EEPROM configuration byte.
• Five 8-bit IO ports.
• Optimum 8051 IO efficiency. IO pins can be addressed as external registers (as in EZ-USB) or through 8051 SFR (Special
Function Register) bits for faster operation.
• Four internal FIFOs for glueless interface to ASICs, DSPs, or external logic. These FIFOs can be clocked either by an
internal or external clock, and can operate either synchronously (using strobes and a clock) or asynchronously (using strobes
only). The FIFOs have 8-16 and 16-8 bit conversion modes that simplify interface to external data buses.
• The vectored interrupt system is expanded to accommodate the FIFO flags and DMA systems. Also, the 8051 can clear
the USB (INT2) or the FIFO/DMA (INT4) interrupt request bit for the interrupt currently being serviced by writing an SFR
location, saving time and code in the interrupt service routine.
• 400-kHz or 100-kHz I2C bus controller speed.
Document #: 38-08005 Rev. **
Page 4 of 42
CY7C64601/603/613
2.1
Microprocessor
The CY7C646xx uses a 12-MHz crystal for low EMI. An internal oscillator and PLL develops an internal 48-MHz clock for use by
the USB Serial Interface Engine and the 8051 microprocessor. The 8051 can run at either 24 MHz or 48 MHz, controlled by a
byte in the EEPROM attached to the I2C bus. The default rate (with no EEPROM connected) is 24 MHz.
The internal microprocessor is an enhanced version of the industry-standard 8051. Enhancements include 4 clock per cycle
operation, a second data pointer, and an enhanced interrupt system. The 8051 includes two UARTS, three counter-timers, and
256 bytes of register RAM.
The EZ-USB family implements IO differently than the standard 8051, by having its IO control registers in external memory space.
The CY7C646xx preserves this addressing for backward EZ-USB compatibility, and adds the ability to control IO registers using
8051 SFRs (Special Function Registers). This improves IO access time. For example, an IO pin may be toggled using one 8051
instruction, e.g., CPL (bit).
The 8051 program and data memory consists of an internal 8 KB RAM. This RAM is normally downloaded via the USB cable at
plug-in, followed by the 8051 starting up and executing the downloaded code. This gives the CY7C646xx family its ‘soft’ operation
feature, whereby permanent memory such as ROM or Flash memory is not required. Program code updates can easily be done
in the field since the code is loaded from the PC, not by physically changing or reprogramming a memory device. The 8051
program memory can also be loaded from the EEPROM connected to the I2C bus on reset for stand-alone use without the USB
connected.
The 128-pin version of the CY7C646xx brings out the full 8051 address and data buses, plus decoded control signals OE#, CS#,
RD#, PSEN, and WR# to allow glueless connection to external memory devices. The 80- and 52-pin packages allow smaller
footprints and more effective solutions for certain designs, but do not have external access to the 8051 buses.
2.2
USB SIE
The CY7C646xx uses the EZ-USB family enhanced SIE (Serial Interface Engine). This SIE has the intelligence to perform full
USB enumeration, creating a default USB device with predefined endpoints and alternate settings. This enhanced SIE is essential
in achieving the family’s soft operation, since it provides the mechanism to download firmware prior to the 8051 running.
Once the 8051 is in control, it can use advanced features of the SIE to simplify its USB firmware. Endpoint zero SETUP data is
placed in a separate 8-byte RAM space for easy access. GET_Descriptor requests are simplified by using a special Setup Data
Pointer. The 8051 simply loads a descriptor address into this 16-bit register, and the SIE takes care of the remaining overhead,
i.e., dividing the descriptor into packets, sending them via endpoint 0 in response to IN tokens, and providing the necessary
handshakes. The 8051 can do other chores while the SIE completes this USB transfer.
Document #: 38-08005 Rev. **
Page 5 of 42
CY7C64601/603/613
2.3
Endpoints
Endpoint
Type
Buffer Size
EP0-IN
EP0-OUT
Control
64
64
EP1-IN
Bulk/Interrupt
64
EP1-OUT
Bulk/Interrupt
64
EP2-IN
Bulk/Interrupt
64
EP2-OUT
Bulk/Interrupt
64
EP3-IN
Bulk/Interrupt
64
EP3-OUT
Bulk/Interrupt
64
EP4-IN
Bulk/Interrupt
64
EP4-OUT
Bulk/Interrupt
64
EP5-IN
Bulk/Interrupt
64
EP5-OUT
Bulk/Interrupt
64
EP6-IN
Bulk/Interrupt
64
EP6-OUT
Bulk/Interrupt
64
EP7-IN
Bulk/Interrupt
64
EP7-OUT
Bulk/Interrupt
64
EP8-IN
Isochronous
0–1023[1]
EP8-OUT
Isochronous
0–1023[1]
EP9-IN
Isochronous
0–1023[1]
EP9-OUT
Isochronous
0–1023[1]
EP10-IN
Isochronous
0–1023[1]
EP10-OUT
Isochronous
0–1023[1]
EP11-IN
Isochronous
0–1023[1]
EP11-OUT
Isochronous
0–1023[1]
EP12-IN
Isochronous
0–1023[1]
EP12-OUT
Isochronous
0–1023[1]
EP13-IN
Isochronous
0–1023[1]
EP13-OUT
Isochronous
0–1023[1]
EP14-IN
Isochronous
0–1023[1]
EP14-OUT
Isochronous
0–1023[1]
EP15-IN
Isochronous
0–1023[1]
EP15-OUT
Isochronous
0–1023[1]
Note:
1. 1023 FIFO bytes may be divided among all Isochronous endpoints.
The CY7C646xx has Control, Bulk, and Interrupt endpoints which each have 64-byte buffers to accommodate the maximum USB
specified packet size, giving the highest USB throughput. One endpoint pair is dedicated to endpoint zero, with separate EP0-IN
and EP0-OUT buffers to simplify programming. Fourteen additional 64-byte buffers may be used as Bulk or Interrupt endpoints.
These endpoints may also be double-buffered by using an endpoint paring mechanism. Double buffering allows the 8051 to
access a packet as another is being transmitted or received over USB. This technique is essential in high-bandwidth applications
where NAKs by the USB function would reduce performance.
The CY7C646xx also has sixteen Isochronous (ISO) endpoints which share 1024 bytes of double-buffered endpoint memory (2
KB total). The ISO buffer sizes are programmable within 16-byte increments. The Isochronous endpoint buffers are accessed as
FIFOs.
Document #: 38-08005 Rev. **
Page 6 of 42
CY7C64601/603/613
Endpoint data is serviced either directly by the 8051, or moved on or off-chip using the DMA system built into the CY7C646xx.
Bulk data is available in 64-byte random-access buffers that can also be addressed as a FIFO using the special AutoPointer
feature. Each endpoint has a unique interrupt vector. This allows ISRs (Interrupt Service Routines) automatically to be called with
minimum overhead and latency, simply by including the ISR address in an interrupt jump table.
2.4
Default USB Machine
When the CY7C64613 is plugged into USB with no EEPROM attached to its I2C port (but with the SCL and SDA pull-ups
installed), the intelligent SIE enumerates as a generic USB device with the following characteristics:
ID bytes (hex)
VID (Vendor ID)
0547
PID (Product ID)
2235
DID (Device ID)
0000
Default Endpoints
Endpoint
Type
Alternate Setting
0
1
2
Max Packet Size (bytes)
0
CTL
64
64
64
1 IN
INT
0
16
64
2 IN
BULK
0
64
64
2 OUT
BULK
0
64
64
4 IN
BULK
0
64
64
4 OUT
BULK
0
64
64
6 IN
BULK
0
64
64
6 OUT
BULK
0
64
64
8 IN
ISO
0
16
256
8 OUT
ISO
0
16
256
9 IN
ISO
0
16
16
9 OUT
ISO
0
16
16
10 IN
ISO
0
16
16
10 OUT
ISO
0
16
16
Powering up with default USB characteristics allows code to be written without initial consideration of the enumeration code that
establishes the default USB device, speeding the learning process.
2.5
IBN (In-Bulk-NAK) Interrupts
The CY7C646xx has an interrupt that indicates that an IN token has been received by an endpoint, and the SIE has NAK’d the
transfer due to no data being available in the endpoint buffer. Interrupt request bits are provided for endpoints EP1N through
EP7IN, and a previously reserved vector is added to the USB vectored interrupts.
2.6
Slave FIFOs
Many high-bandwidth USB designs use a FIFO between the USB interface chip and external logic to match data rates, or to
smooth the USB data delivery (which, being packet oriented, occurs in bursts). The CY7C646xx moves this glue logic into the
part by providing four 64-byte internal slave FIFOs. The FIFOs also provide two important interface functions, external clocking
and bus width conversion.
Using external clocking, external logic (such as a DSP or ASIC) can clock data into or out of the slave FIFOs under control of its
own clock, rather than synchronizing with the clock supplied by the CY7C646xx (24 or 48 MHz). The FIFOs can be controlled
Document #: 38-08005 Rev. **
Page 7 of 42
CY7C64601/603/613
either synchronously (using strobe signals and a clock) or asynchronously (using strobe signals only). The slave FIFO data is
available as two 8-bit buses, which may be used simultaneously to operate as a single 16-bit data bus. The 16-bit connection,
along with fast double-byte mode, combine to give fast conversion between 8 and 16 bit buses. A flexible set of FIFO flags (full,
empty, and programmable) provide FIFO flow control.
2.7
DMA
With many sources and destinations for USB data, such as endpoint buffers, slave FIFOs, and internal/external RAM buffers, it
is important to move blocks of data between them quickly. Using internal DMA, the 8051 sets up source, destination, and transfer
length registers, and then initiates a DMA transfer. The maximum DMA transfer rate occurs between internal resources, such as
endpoint buffers and slave FIFOs. This maximum rate is one byte per 48-MHz clock, or 48 Mbytes per second.
2.8
GPIF (General Programmable Interface)
The GPIF is a flexible 8 or 16-bit parallel interface driven by a user-programmable set of vectors that operate similarly to a finite
state machine. It allows the CY7C646xx to perform local bus mastering, and can implement a wide variety of protocols such as
ATAPI, printer parallel port, and Utopia.
The GPIF has six programmable Control Outputs (CTL), six Address Outputs (ADR), and six general purpose Ready Inputs
(RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, or determines what
state a ready input (or multiple inputs) must be before proceeding. A sequence of the GPIF vectors make up a single waveform
that will be executed to perform the desired data move between the CY7C646xx and the external design.
Document #: 38-08005 Rev. **
Page 8 of 42
CY7C64601/603/613
GND
PC7/RD#
PC6/W R#
PC5/T1
PC4/T0
GND
PC3/INT1#
PC2/INT0#
PC1/TxD0
PC0/RxD0
AOE
AINFLAG
VCC
52
51
50
49
48
47
46
45
44
43
42
41
40
Pin Diagrams
VCC
1
39
GND
SCL
2
38
XCLK
SDA
3
37
AOUTFLAG
WAKEUP#
4
36
PB7/T2OUT/AFI[7]
AVCC
5
35
PB6/INT6/AFI[6]
XIN
6
34
PB5/INT5#/AFI[5]
XOUT
7
33
PB4/INT4/AFI[4]
AGND
8
32
PB3/TxD2/AFI[3]
RESERVED
9
31
PB2/RxD2/AFI[2]
PA4/FWR#
10
30
PB1/T2EX/AFI[1]
PA5/FRD#
11
29
PB0/T2/AFI[0]
CLKOUT
12
28
RESET
GND
13
27
VCC
Document #: 38-08005 Rev. **
15
16
17
18
19
20
21
22
23
24
25
26
RESERVED
XCLKSEL
RESERVED
DISCO N#
RESERVED
RESERVED
G ND
RESERVED
RESERVED
USBD-
USBD+
G ND
52 PQFP
10 x 10 mm
14
3.1
Pin Assignments
VCC
3.0
Page 9 of 42
Vcc
Vcc
CTL0/AINFLAG
61
RDY0/ASEL
RDY1/BSEL
RDY2/AO E
NC
NC
PC0/RXD0/RDY0
PC1/TXD0/RDY1
PC2/INT0#
PC3/INT1#/RDY3
GND
PC4/T0/CTL1
PC5/T1/CTL3
PC6/WR#/CTL4
PC7/RD#/CTL5
NC
NC
NC
80
G ND
CY7C64601/603/613
1
60
GND
SCL
XCLK
SDA
CTL2/AOUTFLAG
WAKEUP#
CTL1/BINFLAG
AVCC
NC
XIN
NC
XOUT
PB7/T2OUT/D7/GDA7/AFI7
AGND
PB6/INT6/D6/GDA6/AFI6
80 PQFP
14 x 14 mm
RESERVED
GND
PA0/T0OUT
PA1/T1OUT
PB5/INT5#/D5/GDA5/AFI5
PB4/INT4/D4/GDA4/AFI4
PB3/TXD1/D3/GDA3/AFI3
PB2/RXD1/D2/GDA2/AFI2
PA2/OE#
PB1/T2EX/D1/GDA1/AFI1
PA3/CS#
PB0/T2/D0/GDA0/AFI0
PA4/FWR#/RDY4/SLWR
NC
PA5/FRD#/RDY5/SLRD
NC
PA6/RXD0OUT
NC
PA7/RXD1OUT
GND
CLKOUT
RESET#
20
GND
USBD+
USBD-
PD7/G DB7/BFI7
PD6/GDB7/BFI6
PD5/G DB5/BFI5
PD4/G DB4/BFI4
PD3/G DB3/BFI3
PD2/G DB2/BFI2
PD1/G DB1/BFI1
PD0/G DB0/BFI0
GND
DISCO N#
RDY5/SLRD
RDY4/SLWR
RDY3/BO E
RESERVED
XCLKSEL
RESERVED
Vcc
Document #: 38-08005 Rev. **
Vcc
40
41
21
GND
Page 10 of 42
A SEL
A INFLAG
V CC
GN D
X CLK
AOU TFLAG
B INFLAG
P E7
P E6
P E5
P E4/BOUTEMTY
P E3/AOUTE MTY
P E2/BIN FULL
P E1/AIN FULL
P E0/BOUTFLAG
GN D
PB 7/T2OU T/AFI[7]
P B6/IN T6/A FI[6]
P B5/IN T5#/AFI[5]
P B4/IN T4/A FI[4]
P B3/TxD1/A FI[3]
P B2/RxD 1/AFI[2]
P B1/T2E X/A FI[1]
P B0/T2/AFI[0]
GN D
R ESE RVE D
R ESE RVE D
VC C
R ESE RVE D
R ESE RVE D
GN D
R ESE RVE D
R ESE RVE D
R ESE T+
V CC
GN D
U SBD +
U SBD-
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CY7C64601/603/613
BSEL
103
64
PD7/BFI[7]
AOE
104
63
PD6/BFI[6]
A0
105
62
GND
A1
106
61
PD5/BFI[5]
A2
107
60
PD4/BFI[4]
A3
108
59
PD3/BFI[3]
VCC
109
58
PD2/BFI[2]
PC0/RxD0
110
57
PD1/BFI[1]
PC1/TxD0
111
56
PD0/BFI[0]
PC2/INT0#
112
55
VCC
PC3/INT1#
113
54
RESERVED
A4
114
53
RESERVED
A5
115
52
GND
A6
116
51
EA
A7
117
50
RESERVED
A8
118
49
RESERVED
GND
119
48
DISCON#
A9
120
47
GND
A10
121
46
SLRD
A11
122
45
SLWR
PC4/T0
123
44
BOE
PC5/T1
124
43
No Connect
PC6/WR#
125
42
No Connect
PC7/RD#
126
41
BKPT
A12
127
40
GND
A13
128
39
RESERVED
3.2
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GND
D4
D5
D6
D7
VC C
AV CC
XIN
XOU T
AGND
RES ERV ED
GND
N o Connect
ADR5
PA0/T0out
PA1/T1out
P A2/OE#
PA3/C S#
PA 4/FW R #
P A5/FRD #
PA6/R XD0out
PA7/RX D1out
PSEN #
C LKOU T
GND
V CC
RE SER VED
XCLKS EL
8
D0
D3
7
W A KEU P#
10
6
SDA
D2
5
SC L
9
4
V CC
D1
3
2
A15
GND
1
A14
128 PQFP
14 x 20 mm
CY7C646xx Pin Descriptions
128
80
52
18
5
5
21
8
48
28
Name
Type
Default
AVCC
Power
N/A
Analog VCC. This signal provides power to the analog section of
the chip.
8
AGND
Power
N/A
Analog Ground. Connect to ground with as short a path as possible.
18
DISCON#
O/Z
H
Disconnect. This pin can drive HIGH, LOW, or float. DISCON# pin
floats when the register bit USBCS.2 is LOW, and drives when it is
HIGH. The drive level of the DISCON# pin is the invert of register
bit USBCS.3.
The DISCON# pin is normally connected to the USB D+ line through
a 1500Ω resistor. The CY7C646xx signals a USB connection by
setting USBCS.3=0 (drive 3.3V) and USBCS.2=1 (output enable).
The CY7C646xx signals a USB disconnect by setting USBCS.2=0
which floats the pin and disconnects the 1500Ω resistor from D+.
Document #: 38-08005 Rev. **
Description
Page 11 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
52
65
38
24
USBD–
Name
66
39
25
USBD+
Type
Default
Description
I/O/Z
Z
USB D– Signal. Connect to the USB D– signal through a 24Ω resistor.
I/O/Z
Z
USB D+ Signal. Connect to the USB D+ pin through a 24Ω resistor.
105
A0
Output
L
106
A1
Output
L
107
A2
Output
L
108
A3
Output
L
8051 Address Bus. This bus is driven at all times. When the 8051
is addressing internal RAM it reflects the internal address.
During DMA transfers that use the RD# and WR# strobes, the address bus contains the incrementing DMA source or destination
address for data transferred over D[7..0].
114
A4
Output
L
115
A5
Output
L
116
A6
Output
L
117
A7
Output
L
118
A8
Output
L
120
A9
Output
L
121
A10
Output
L
122
A11
Output
L
127
A12
Output
L
128
A13
Output
L
1
A14
Output
L
2
A15
Output
L
8
D0
I/O/Z
Z
9
D1
I/O/Z
Z
10
D2
I/O/Z
Z
11
D3
I/O/Z
Z
13
D4
I/O/Z
Z
14
D5
I/O/Z
Z
15
D6
I/O/Z
Z
8051 Data Bus. This bidirectional bus is high-impedance when inactive, input for bus reads, and output for bus writes. The data bus
is used for external 8051 program and data memory. The data bus
is also used for DMA transfers that use the RD#/FRD#, WR#,FWR#
pins as strobes. The data bus is active only for external bus accesses, and is driven LOW in suspend.
16
D7
I/O/Z
Z
33
PSEN#
Output
H
Program Store Enable. This active-LOW signal indicates an 8051
code fetch from external memory. It is active for program memory
fetches from 0x1B40-0xFFFF when the EA pin is LOW, or from
0x0000-0xFFFF when the EA pin is HIGH.
41
BKPT
Output
L
Breakpoint. This pin goes active (HIGH) when the 8051 address
bus matches the BPADDRH/L registers and breakpoints are enabled in the USBBAV register (BPEN=1). If the BPPULSE bit in the
USBBAV register is HIGH, this signal pulses HIGH for eight 24-/48MHz clocks. If the BPPULSE bit is LOW, the signal remains HIGH
until the 8051 clears the BREAK bit (by writing 1 to it) in the USBBAV
register.
RESET#
Input
N/A
Active LOW Reset. Resets the entire chip. This pin is normally tied
to VCC through a 10K resistor, and to GND through a 1-µF capacitor.
Hysteresis input.
EA
Input
N/A
External Access. This pin determines where the 8051 fetches code
between addresses 0x0000 and 0x1B3F. If EA=0 the 8051 fetches
this code from its internal RAM. IF EA=1 the 8051 fetches this code
from external memory.
69
51
42
28
Document #: 38-08005 Rev. **
Page 12 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
52
19
6
6
XIN
Name
Type
Default
Input
N/A
Crystal Input. Connect this signal to a 12-MHz series-resonant,
fundamental mode crystal and 22–33 pF capacitor to GND. Also
connect a 1-MΩ resistor between XIN and XOUT.
20
7
7
XOUT
34
19
12
Description
Output
N/A
Crystal Output. Connect this signal to a 12-MHz series-resonant,
fundamental mode crystal and 22–33 pF capacitor to GND. Also
connect a 1-MΩ resistor between XIN and XOUT.
CLKOUT
O/Z
24 MHz
24- or 48-MHz clock, phase locked to the 12-MHz input clock. Output frequency is set by an external EEPROM bit (Config0.2). If no
EEPROM is connected to the I2C port (but the required pull-up resistors are present), the 8051 defaults to 24-MHz operation. The
8051 may three-state this output by setting CPUCS.1=1. The CLKOUT pin may be inverted by setting the boot EEPROM bit
CONFIG0.1=1.
Port A
25
11
PA0 or
T0OUT
I/O/Z
I
(PA0)
Multiplexed pin whose function is selected by two bits:
PORTACFG.0 and IFCONFIG.3.
PA0 is a bidirectional IO port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT
outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in mode 3 (two separate timer/counters),
T0OUT is active when the low byte timer/counter overflows.
26
12
PA1 or
T1OUT
I/O/Z
I
(PA1)
Multiplexed pin whose function is selected by two bits:
PORTACFG.1 and IFCONFIG.3.
PA1 is a bidirectional IO port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT
outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in mode 3 (two separate timer/counters),
T1OUT is active when the low byte timer/counter overflows.
27
13
PA2 or
OE# or
I/O/Z
I
(PA2)
Multiplexed pin whose function is selected by two bits:
PORTACFG.2 and IFCONFIG.3.
PA2 is a bidirectional IO port pin.
OE# is an active-LOW output enable for external memory. If the OE#
pin is used, it should be externally pulled up to VCC to ensure that
the write strobe is inactive (high) at power-on.
28
14
PA3 or
CS#
I/O/Z
I
(PA3)
Multiplexed pin whose function is selected by the PORTACFG.3 bit.
PA3 is a bidirectional I/O port pin.
CS# is an active-LOW chip select for external memory. If the CS#
pin is used, it should be externally pulled up to VCC to ensure that
the write strobe is inactive (HIGH) at power-on.
29
15
PA4 or
FWR# or
RDY4 or
SLWR
I/O/Z
I
(PA4)
Multiplexed pin whose function is selected by the following bits:
PORTACFG.4, PORTACF2.4, and IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FWR# is the write strobe output for an external FIFO connected to
the data bus D[7..0]. If the FWR# pin is used, it should be externally
pulled up to VCC to ensure that the write strobe is inactive at poweron.
RDY4 is a GPIF input signal.
SLWR is the write strobe input for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
10
Document #: 38-08005 Rev. **
Page 13 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
52
30
16
11
Type
Default
Description
PA5 or
FRD# or
RDY5 or
SLRD
31
32
Name
I/O/Z
I
(PA5)
Multiplexed pin whose function is selected by the following bits:
PORTACFG.5, PORTACF2.5, and IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FRD# is the write strobe output for an external FIFO connected to
the data bus D[7..0]. If the FRD# pin is used, it should be externally
pulled up to VCC to ensure that the read strobe is inactive at poweron.
RDY5 is a GPIF input signal.
SLRD is the read strobe input for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
17
PA6 or
RXD0OUT
I/O/Z
I
(PA6)
Multiplexed pin whose function is selected by the PORTACFG.6 bit.
PA6 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in mode 0, this pin provides
the output data for UART0 only when it is in sync mode. Otherwise
it is a 1.
18
PA7 or
RXD1OUT
I/O/Z
I
(PA7)
Multiplexed pin whose function is selected by the PORTACFG.7 bit.
PA7 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In modes
1, 2, and 3, this pin is HIGH.
Port B
The following descriptions apply to the PORT B pins:
D[7..0] is the 8051 data bus. This bus is optionally available on
PORT B pins to provide access to the 8051 data bus in smaller EZUSB II packages that do not bring out the 8051 address and data
buses.
GDA[7..0] is the GPIF A data bus.
AFI[7..0] is the bidirectional A-FIFO data bus.
79
47
29
PB0 or
T2 or
D[0] or
GDA[0] or
AFI [0]
I/O/Z
I
(PB0)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.0 and IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does
not use this pin.
AFI [0] is the bidirectional A-FIFO data bus.
80
48
30
PB1 or
T2EX or
D[1] or
GDA[1] or
AFI [1]
I/O/Z
I
(PB1)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.1 and IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2
bit is set in T2CON.
AFI [1] is the bidirectional A-FIFO data bus.
81
49
31
PB2 or
RXD1 or
D[2] or
GDA[2] or
AFI [2]
I/O/Z
I
(PB2)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.2 and IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
RXD1is an active-HIGH input signal for 8051 UART1, which provides data to the UART in all modes.
AFI [2] is the bidirectional A-FIFO data bus.
Document #: 38-08005 Rev. **
Page 14 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
52
Name
Type
Default
Description
82
50
32
PB3 or
TXD1 or
D[3] or
GDA[3] or
AFI [3]
I/O/Z
I
(PB3)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.3 and IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async
mode.
AFI [3] is the bidirectional A-FIFO data bus.
83
51
33
PB4 or
INT4 or
D[4] or
GDA[4] or
AFI [4]
I/O/Z
I
(PB4)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.4 and IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin
is edge-sensitive, active HIGH.
AFI [4] is the bidirectional A-FIFO data bus.
84
52
34
PB5 or
INT5# or
D[5] or
GDA[5] or
AFI [5]
I/O/Z
I
(PB5)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.5 and IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin
is edge-sensitive, active LOW.
AFI [5] is the bidirectional A-FIFO data bus.
85
53
35
PB6 or
INT6 or
D[6] or
GDA[6] or
AFI [6]
I/O/Z
I
(PB6)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.6 and IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin
is edge-sensitive, active HIGH.
AFI [6] is the bidirectional A-FIFO data bus.
86
54
36
PB7 or
T2OUT or
D[7] or
GDA[7] or
AFI [7]
I/O/Z
I
(PB7)
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.7 and IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT
is active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
AFI [7] is the bidirectional A-FIFO data bus.
110
68
43
PC0 or
RXD0 or
RDY0
I/O/Z
I
(PC0)
Multiplexed pin whose function is selected by the PORTCCFG.0 and
PORTCGPIF.0 bits.
PC0 is a bidirectional I/O port pin.
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes.
RDY0 is a GPIF input signal.
111
69
44
PC1 or
TXD0 or
RDY1
I/O/Z
I
(PC1)
Multiplexed pin whose function is selected by the PORTCCFG.1 and
PORTCGPIF.1 bits.
PC1 is a bidirectional I/O port pin.
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in async
mode.
RDY1 is a GPIF input signal.
112
70
45
PC2 or
INT0#
I/O/Z
I
(PC2)
Multiplexed pin whose function is selected by the PORTCCFG.2 bit.
PC2 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
113
71
46
PC3 or
INT1# or
RDY3
I/O/Z
I
(PC3)
Multiplexed pin whose function is selected by the: PORTCCFG.3
and PORTCGPIF.3 bits.
PC3 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
RDY3 is a GPIF input signal.
Port C
Document #: 38-08005 Rev. **
Page 15 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
52
Type
Default
Description
123
73
48
PC4 or
T0 or
CTL1
Name
I/O/Z
I
(PC4)
Multiplexed pin whose function is selected by the PORTCCFG.4
and PORTCGPIF.4 bits.
PC4 is a bidirectional I/O port pin.
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the
input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not
use this bit.
CTL1 is a GPIF output signal.
124
74
49
PC5 or
T1 or
CTL3
I/O/Z
I
(PC5)
Multiplexed pin whose function is selected by the PORTCCFG.5
and PORTCGPIF.5 bits.
PC5 is a bidirectional I/O port pin.
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the
input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not
use this bit.
CTL3 is a GPIF output signal.
125
75
50
PC6 or
WR# or
CTL4
I/O/Z
I
(PC6)
Multiplexed pin whose function is selected by the PORTCCFG.6
and PORTCGPIF.6 bits.
PC6 is a bidirectional I/O port pin.
WR# is the active-LOW write strobe output for external memory. If
the WR# signal is used, it should be externally pulled up to VCC to
ensure that the write strobe is inactive at power-on.
CTL4 is a GPIF output signal.
126
76
51
PC7 or
RD# or
CTL5
I/O/Z
I
(PC7)
Multiplexed pin whose function is selected by the PORTCCFG.7
and PORTCGPIF.7 bits.
PC7 is a bidirectional I/O port pin.
RD# is the active-LOW read strobe output for external memory. If
the RD# signal is used, it should be externally pulled up to VCC to
ensure that the write strobe is inactive at power-on.
CTL5 is a GPIF output signal.
Port D
Port D is multiplexed between three sources:
PD0–PD7 are bidirectional I/O port pins.
GDB[7..0] is the GPIF B data bus.
BFI[7..0] is the bidirectional B-FIFO data bus.
56
30
PD0 or
GDB[0] or
BFI [0]
I/O/Z
I
(PD0)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [0] is the bidirectional B-FIFO data bus.
57
31
PD1 or
GDB[1] or
BFI [1]
I/O/Z
I
(PD1)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [1] is the bidirectional B-FIFO data bus.
58
32
PD2 or
GDB[2] or
BFI [2]
I/O/Z
I
(PD2)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [2] is the bidirectional B-FIFO data bus.
59
33
PD3 or
GDB[3] or
BFI [3]
I/O/Z
I
(PD3)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [3] is the bidirectional B-FIFO data bus.
60
34
PD4 or
GDB[4] or
BFI [4]
I/O/Z
I
(PD4)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [4] is the bidirectional B-FIFO data bus.
61
35
PD5 or
GDB[5] or
BFI [5]
I/O/Z
I
(PD5)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [5] is the bidirectional B-FIFO data bus.
63
36
PD6 or
GDB[6] or
BFI [6]
I/O/Z
I
(PD6)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [6] is the bidirectional B-FIFO data bus.
Document #: 38-08005 Rev. **
Page 16 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
64
37
52
Name
Type
Default
Description
PD7 or
GDB[7] or
BFI [7]
I/O/Z
I
(PD7)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
BFI [7] is the bidirectional B-FIFO data bus.
88
PE0 or
ADR0 or
BOUTFLAG
I/O/Z
I
(PE0)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
PE0 is a bidirectional I/O port pin.
ADR0 is a GPIF address output pin.
BOUTFLAG is the B-OUT FIFO flag output, which indicates a programmable level of FIFO fullness.
89
PE1 or
ADR1 or
AINFULL
I/O/Z
I
(PE1)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
PE1 is a bidirectional I/O port pin.
ADR1 is a GPIF address output pin.
AINFULL is the A-IN FIFO flag output, which indicates FIFO full.
90
PE2 or
ADR2 or
BINFULL
I/O/Z
I
(PE2)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
PE2 is a bidirectional I/O port pin.
ADR2 is a GPIF address output pin.
BINFULL is the B-IN FIFO flag output, which indicates FIFO full.
91
PE3 or
ADR3 or
AOUTEMTY
I/O/Z
I
(PE3)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
PE3 is a bidirectional I/O port pin.
ADR3 is a GPIF address output pin.
AOUTEMTY is the A-OUT FIFO flag output, which indicates FIFO
empty.
92
PE4 or
ADR4 or
BOUTEMTY
I/O/Z
I
(PE4)
Multiplexed pin whose function is selected by the IFCONFIG[2..0]
bits.
PE4 is a bidirectional I/O port pin.
ADR4 is a GPIF address output pin.
BOUTEMTY is the B-OUT FIFO flag output, which indicates FIFO
empty.
93
PE5 or
CTL3
I/O/Z
I
(PE5)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PE5 is a bidirectional I/O port pin.
CTL3 is a GPIF output signal.
94
PE6 or
CTL4
I/O/Z
I
(PE6)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PE6 is a bidirectional I/O port pin.
CTL4 is a GPIF output signal.
95
PE7 or
CTL5
I/O/Z
I
(PE7)
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PE7 is a bidirectional I/O port pin.
CTL5 is a GPIF output signal.
24
ADR5
O
X
ADR5 is a GPIF address output pin.
Port E
102
63
RDY0 or
ASEL
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
ASEL is the select input for the A-IN and A-OUT FIFOs.
103
64
RDY1 or
BSEL
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
BSEL is the select input for the B-IN and B-OUT FIFOs.
Document #: 38-08005 Rev. **
Page 17 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
52
104
65
42
Type
Default
RDY2 or
AOE
44
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY2 is a GPIF input signal.
AOE is the output enable input for the A-OUT FIFO.
25
RDY3 or
BOE
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY3 is a GPIF input signal.
BOE is the output enable input for the B-OUT FIFO.
45
26
RDY4 or
SLWR
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY4 is a GPIF input signal.
SLWR is the input-only write strobe for the slave FIFOs connected
to AFI[7..0] and/or BFI[7..0].
46
27
RDY5 or
SLRD
Input
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY5 is a GPIF input signal.
SLRD is the input-only read strobe for the slave FIFOs connected
to AFI[7..0] and/or BFI[7..0].
101
62
CTL0 or
AINFLAG
Output
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
AINFLAG is the A-IN FIFO flag output which indicates a programmable level of FIFO fullness.
96
57
CTL1 or
BINFLAG
Output
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
BINFLAG is the B-IN FIFO flag output which indicates a programmable level of FIFO fullness.
97
58
37
CTL2 or
AOUTFLAG
Output
X
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
AOUTFLAG is the A-OUT FIFO flag output which indicates a programmable level of FIFO fullness.
98
59
38
XCLK
Input
N/A
External clock input, used for synchronously clocking data into the
slave FIFOs. XCLK also serves as a timing reference for all slave
FIFO control signals and GPIF.
53
22
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
54
23
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
70
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
71
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
73
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
74
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
76
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
41
77
Name
Description
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
50
20
Reserved
Rsrvd
N/A
Reserved. Leave open.
49
19
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
Input
N/A
USB Wakeup. If the 8051 is in suspend, a HIGH-to-LOW edge on
this pin starts up the oscillator and interrupts the 8051 to allow it to
exit the suspend mode. Holding WAKEUP# LOW inhibits the EZUSB chip from suspending.
OD
Z
I2C Clock. Connect to VCC with a 1K resistor, even if no I2C peripheral is attached.
7
4
4
WAKEUP#
5
2
2
SCL
Document #: 38-08005 Rev. **
Page 18 of 42
CY7C64601/603/613
3.2
CY7C646xx Pin Descriptions (continued)
128
80
52
6
3
3
SDA
Type
Default
Description
OD
Z
I2C Data. Connect to VCC with a 1K resistor, even if no I2C peripheral is attached.
38
23
16
XCLKSEL
Input
N/A
HIGH: Use XCLK pin for GPIF and slave FIFOs.
LOW: Use internal 48-MHz clock for GPIF and slave FIFOs.
39
24
17
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
37
22
22
15
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
9
9
Reserved
Rsrvd
N/A
Reserved. Connect to Ground.
4
1
1
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
21
14
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
VCC
Power
N/A
VCC. Connect to 3.3 V power source.
17
36
55
68
41
27
61
40
75
100
109
3
80
52
Name
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
40
GND
Ground
N/A
Ground.
47
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
GND
Ground
N/A
Ground.
78
GND
Ground
N/A
Ground.
87
GND
Ground
N/A
Ground.
12
23
10
35
20
52
29
13
21
62
67
40
72
43
26
99
60
39
GND
Ground
N/A
Ground.
119
72
47
GND
Ground
N/A
Ground.
42
79
NC
N/A
N/A
No-connect. This pin must be left open.
43
44
NC
N/A
N/A
No-connect. This pin must be left open.
45
NC
N/A
N/A
No-connect. This pin must be left open.
46
NC
N/A
N/A
No-connect. This pin must be left open.
55
NC
N/A
N/A
No-connect. This pin must be left open.
56
NC
N/A
N/A
No-connect. This pin must be left open.
66
NC
N/A
N/A
No-connect. This pin must be left open.
67
NC
N/A
N/A
No-connect. This pin must be left open.
77
NC
N/A
N/A
No-connect. This pin must be left open.
78
NC
N/A
N/A
No-connect. This pin must be left open.
Document #: 38-08005 Rev. **
Page 19 of 42
CY7C64601/603/613
t
4.0
Addr
Register Summary
Name
Description
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
FIFO A-IN
7800 AINDATA
Read Data from FIFO A
7801 AINBC
Input FIFO A Byte Count
0
D6
D5
D4
D3
D2
D1
D0
7802 AINPF
FIFO A-IN Prog. Flag
(internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7803 AINPFPIN
FIFO A-IN Prog. Flag
(external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
7804 (reserved)
FIFO B-IN
7805 BINDATA
Read Data from FIFO B
7806 BINBC
Input FIFO B Byte Count
0
D6
D5
D4
D3
D2
D1
D0
7807 BINPF
FIFO B-IN Prog. Flag
(internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7808 BINPFPIN
FIFO B-IN Prog. Flag
(external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
INTOG
INSEL
AINPF
AINEF
AINFF
BINPF
BINEF
BINFF
7809 (reserved)
FIFO A/B-IN Control
780A ABINTF
Input FIFOs Toggle control
and flags
780B ABINIE
Input FIFO Interrupt
Enables
0
0
AINPFIE
AINEFIE
AINFFIE
BINPFIE
BINEFIE
BINFFIE
780C ABINIRQ
Input FIFO Interrupt
Requests
0
0
AINPFIR
AINEFIR
AINFFIR
BINPFIR
BINEFIR
BINFFIR
780E AOUTDATA
Load Output FIFO A
D7
D6
D5
D4
D3
D2
D1
D0
780F AOUTBC
Output FIFO A Byte Count
0
D6
D5
D4
D3
D2
D1
D0
7810 AOUTPF
FIFO A-OUT Prog. Flag (internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7811
FIFO A-OUT Programmable Flag (external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
780D (reserved)
FIFO A-OUT
AOUTPFPIN
7812 (reserved)
FIFO B-OUT
7813 BOUTDATA
Load Output FIFO B
7814 BOUTBC
Output FIFO B Byte Count
D7
D6
D5
D4
D3
D2
D1
D0
0
D6
D5
D4
D3
D2
D1
D0
7815 BOUTPF
FIFO B-OUT Prog.
(internal bit)
LTGT
D6
D5
D4
D3
D2
D1
D0
7816 BOUTPFPIN
FIFO B-OUT Prog. Flag
(external pin)
LTGT
D6
D5
D4
D3
D2
D1
D0
7817 (reserved)
FIFO A/B OUT Control
7818 ABOUTTF
Output FIFOs Toggle
control and flags
OUTTOG
OUTSEL
AOUTPF
AOUTEF
AOUTFF
BOUTPF
BOUTEF
BOUTFF
7819 ABOUTIE
Output FIFO Interrupt
Enables
0
0
AOUTPFIE
AOUTEFIE
AOUTFFIE
BOUTPFIE
BOUTEFIE
BOUTFFIE
781A ABOUTIRQ
Output FIFO Interrupt
Requests
0
0
AOUTPFIR
AOUTEFIR
AOUTFFIR
BOUTPFIR
BOUTEFIR
BOUTFFIR
0
0
ASYNC
DBLIN
0
OUTDLY
0
DBLOUT
781B (reserved)
FIFO A/B Global Control
781C ABSETUP
FIFO Setup
Document #: 38-08005 Rev. **
Page 20 of 42
CY7C64601/603/613
4.0
Addr
Register Summary (continued)
D7
D6
D5
D4
D3
D2
D1
D0
781D ABPOLAR
Name
FIFO Control Signals
Polarity
Description
0
0
BOE
AOE
SLRD
SLWR
ASEL
BSEL
781E ABFLUSH
Write (data=x) to reset all
flags
*
*
*
*
*
*
*
*
781F-7823 (reserved)
7824 WFSELECT
Waveform Selector
7825 IDLE_CS
GPIF IDLE State control
7826 IDLECTLOUT
7827 CTLOUTCFG
SINGLEWR
SINGLERD
FIFOWR
FIFORD
DONE
0
0
0
0
0
0
IDLEDRV
GPIF IDLE CTL states
IOE3
IOE2
IOE1/
CTL5
IOE0/
CTL4
CTL3
CTL2
CTL1
CTL0
GPIF CTL Drive mode
TRICTL
0
CTL5
CTL4
CTL3
CTL2
CTL1
CTL0
*
*
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
*
*
*
7828-7829 (reserved)
782A GPIFADRL
GPIF Address
782B (reserved)
782C AINTC
FIFO A In Transfer Count
FITC
782D AOUTTC
FIFO A Out Transfer Count
FITC
782E ATRIG
Trigger a FIFO A RD/WR
*
7830 BINTC
FIFO B In Transfer Count
FITC
7831 BOUTTC
FIFO B Out Transfer Count
FITC
7832 BTRIG
Trigger a FIFO B RD/WR
Transfer Count
Transfer Count
*
*
*
*
782F (reserved)
Transfer Count
Transfer Count
*
*
*
*
*
*
*
*
D15
D14
D13
D12
D11
D10
D9
D8
7833 (reserved)
7834 SGLDATH
GPIF Data High
7835 SGLDATLTRIG GPIF Data Low and Trigger
D7
D6
D5
D4
D3
D2
D1
D0
7836 SGLDATLNTRIG
D7
D6
D5
D4
D3
D2
D1
D0
INTRDY
SAS
RDY5
RDY4
RDY3
RDY2
RDY1
RDY0
GPIF Data Low and No
Trigger
7837(reserved)
7838 READY
GPIF Ready flags
7839 ABORT
Abort current GPIF cycle
*
*
*
*
*
*
*
*
783B GENIE
GPIF/DMA Interrupt Enable
0
0
0
0
0
DMADN
GPWR
GPDONE
783C GENIRQ
GPIF/DMA Interrupt
Request
0
0
0
0
0
DMADN
GPWR
GPDONE
783A (reserved)
783D-7840 (reserved)
IO Ports D, E
7841 OUTD
Output Port D
OUTD7
OUTD6
OUTD5
OUTD4
OUTD3
OUTD2
OUTD1
OUTD0
7842 PINSD
Input Port D pins
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
7843 OED
Port D Output Enable
0ED7
0ED6
0ED5
0ED4
0ED3
0ED2
0ED1
0ED0
7844 (reserved)
7845 OUTE
Output Port E
OUTE7
OUTE6
OUTE5
OUTE4
OUTE3
OUTE2
OUTE1
OUTE0
7846 PINSE
Input Port E pins
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
7847 OEE
Port E Output Enable
OEE7
OEE6
OEE5
OEE4
OEE3
OEE2
OEE1
OEE0
7849 PORTSETUP
Timer0 Clock source,
Port-to-SFR mapping
0
0
0
0
0
0
T0CLK
SFRPORT
784A IFCONFIG
Select 8/16 bit data bus,
configure buses (IF)
52ONE
0
0
0
GSTATE
BUS16
IF1
IF0
784B PORTACF2
Port A Configuration #2
0
0
SLRD
SLWR
0
0
0
0
7848 (reserved)
Document #: 38-08005 Rev. **
Page 21 of 42
CY7C64601/603/613
4.0
Addr
Register Summary (continued)
Name
784C PORTCCF2
Description
Port C Configuration #2
D7
D6
D5
D4
D3
D2
D1
D0
CTL5
CTL4
CTL3
CTL1
RDY3
0
RDY1
RDY0
784D-784E (reserved)
DMA Control
784F DMASRCH
DMA Source H
A15
A14
A13
A12
A11
A10
A9
A8
7850 DMASRCL
DMA Source L
A7
A6
A5
A4
A3
A2
A1
A0
7851 DMADESTH
DMA Destination H
A15
A14
A13
A12
A11
A10
A9
A8
7852 DMADESTL
DMA Destination L
A7
A6
A5
A4
A3
A2
A1
A0
7854 DMALEN
DMA Transfer Length
D7
D6
D5
D4
D3
D2
D1
D0
7855 DMAGO
Start DMA Transfer
DONE
*
*
*
*
*
*
*
7853 (reserved)
7856 (reserved)
7857 DMABURST
DMA Burst control
7858 DMAEXTFIFO
Dummy data reg for using
RAM as external FIFO
*
*
*
DSTR2
DSTR1
DSTR0
RB
WB
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
7859 - 785C (reserved)
785D INT4IVEC
Interrupt 4 Vector
0
1
I4V3
I4V2
I4V1
I4V0
0
0
785E INT4SETUP
Interrupt 4 Set-up
0
0
0
0
0
INT4SFC
INTERNAL
AV4EN
d7
d6
d5
d4
d3
d2
d1
d0
785F-78FF (reserved)
7900- WFDESC
797F
GPIF Waveform
Descriptors
7980-7B3F (reserved)
Endpoint 0–7 Data Buffers
7B40 OUT7BUF
(64 bytes)
7B80 IN7BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7BC0 OUT6BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7C00 IN6BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7C40 OUT5BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7C80 IN5BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7CC0 OUT4BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7D00 IN4BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7D40 OUT3BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7D80 IN3BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7DC0 OUT2BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7E00 IN2BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7E40 OUT1BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7E80 IN1BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7EC0 OUT0BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
7F00 IN0BUF
(64 bytes)
d7
d6
d5
d4
d3
d2
d1
d0
d7
d6
d5
d4
d3
d2
d1
d0
7F40-7F5F (reserved)
Isochronous Data
7F60 OUT8DATA
Endpoint 8 OUT Data
7F61 OUT9DATA
Endpoint 9 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F62 OUT10DATA
Endpoint 10 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F63 OUT11DATA
Endpoint 11 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F64 OUT12DATA
Endpoint 12 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
Document #: 38-08005 Rev. **
Page 22 of 42
CY7C64601/603/613
4.0
Addr
Register Summary (continued)
D7
D6
D5
D4
D3
D2
D1
D0
7F65 OUT13DATA
Name
Endpoint 13 OUT Data
Description
d7
d6
d5
d4
d3
d2
d1
d0
7F66 OUT14DATA
Endpoint 14 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F67 OUT15DATA
Endpoint 15 OUT Data
d7
d6
d5
d4
d3
d2
d1
d0
7F68 IN8DATA
Endpoint 8 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F69 IN9DATA
Endpoint 9 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6A IN10DATA
Endpoint 10 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6B IN11DATA
Endpoint 11 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6C IN12DATA
Endpoint 12 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6D IN13DATA
Endpoint 13 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6E IN14DATA
Endpoint 14 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
7F6F IN15DATA
Endpoint 15 IN Data
d7
d6
d5
d4
d3
d2
d1
d0
EP8 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F71 OUT8BCL
EP8 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F72 OUT9BCH
EP9 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F73 OUT9BCL
EP9 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F74 OUT10BCH
EP10 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F75 OUT10BCL
EP10 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F76 OUT11BCH
EP11 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F77 OUT11BCL
EP11 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F78 OUT12BCH
EP12 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F79 OUT12BCL
EP12 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F7A OUT13BCH
EP13 Out Byte Count H
0
0
0
0
0
0
d9
d8
Isochronous Byte Counts
7F70 OUT8BCH
7F7B OUT13BCL
EP13 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F7C OUT14BCH
EP14 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F7D OUT14BCL
EP14 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F7E OUT15BCH
EP15 Out Byte Count H
0
0
0
0
0
0
d9
d8
7F7F OUT15BCL
EP15 Out Byte Count L
d7
d6
d5
d4
d3
d2
d1
d0
7F92 CPUCS
Control & Status
rv3
rv2
rv1
rv0
24/48
CLKINV
CLKOUT
OE
8051RES
7F93 PORTACFG
Port A Configuration
RxD1out
RxD0out
FRD
FWR
CS
OE
T1out
T0out
7F94 PORTBCFG
Port B Configuration
T2OUT
INT6
INT5
INT4
TxD1
RxD1
T2EX
T2
7F95 PORTCCFG
Port C Configuration
RD
WR
T1
T0
INT1
INT0
TxD0
RxD0
OUTA7
OUTA6
OUTA5
OUTA4
OUTA3
OUTA2
OUTA1
OUTA0
7F80-7F91 (reserved)
CPU Registers
Input-Output Port Registers
7F96 OUTA
Output Register A
7F97 OUTB
Output Register B
OUTB7
OUTB6
OUTB5
OUTB4
OUTB3
OUTB2
OUTB1
OUTB0
7F98 OUTC
Output Register C
OUTC7
OUTC6
OUTC5
OUTC4
OUTC3
OUTC2
OUTC1
OUTC0
7F99 PINSA
Port Pins A
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
7F9A PINSB
Port Pins B
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
7F9B PINSC
Port Pins C
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
7F9C OEA
Output Enable A
OEA7
OEA6
OEA5
OEA4
OEA3
OEA2
OEA1
OEA0
7F9D OEB
Output Enable B
OEB7
OEB6
OEB5
OEB4
OEB3
OEB2
OEB1
OEB0
Document #: 38-08005 Rev. **
Page 23 of 42
CY7C64601/603/613
4.0
Addr
Register Summary (continued)
Name
7F9E OEC
7F9F
UART230
Description
Output Enable C
230k Baud Configuration
D7
D6
D5
D4
D3
D2
D1
D0
OEC7
OEC6
OEC5
OEC4
OEC3
OEC2
OEC1
OEC0
0
0
0
0
0
0
UART1
UART0
ISO15
ERR
ISO14
ERR
ISO13
ERR
ISO12
ERR
ISO11
ERR
ISO10
ERR
ISO9
ERR
ISO8
ERR
Isochronous Control/Status Registers
7FA0 ISOERR
ISO OUT Endpoint Error
7FA1 ISOCTL
Isochronous Control
*
*
*
*
PPSTAT
0
0
ISODISAB
7FA2 ZBCOUT
Zero Byte Count bits
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
START
STOP
LASTRD
ID1
ID0
BERR
ACK
DONE
7FA3 (reserved)
7FA4 (reserved)
I2C Registers
7FA5 I2CS
Control & Status
7FA6 I2DAT
Data
d7
d6
d5
d4
d3
d2
d1
d0
7FA7 I2CMODE
STOP Int Enable, I2C bus
speed
0
0
0
0
0
0
STOPIE
400KHZ
7FA8 IVEC
Interrupt Vector
0
IV4
IV3
IV2
IV1
IV0
0
0
7FA9 IN07IRQ
EPIN Interrupt Request
7FAA OUT07IRQ
EPOUT Interrupt Request
Interrupts
IN7IR
IN6IR
IN5IR
IN4IR
IN3IR
IN2IR
IN1IR
IN0IR
OUT7IR
OUT6IR
OUT5IR
OUT4IR
OUT3IR
OUT2IR
OUT1IR
OUT0IR
7FAB USBIRQ
USB Interrupt Request
7FAC IN07IEN
EP0–7IN Int Enables
0
0
IBNIR
URESIR
SUSPIR
SUTOKIR
SOFIR
SUDAVIR
IN7IEN
IN6IEN
IN5IEN
IN4IEN
IN3IEN
IN2IEN
IN1IEN
IN0IEN
7FAD OUT07IEN
EP0–7OUT Int Enables
7FAE USBIEN
USB Int Enables
OUT7IEN
OUT6IEN
OUT5IEN
OUT4IEN
OUT3IEN
OUT2IEN
OUT1IEN
OUT0IEN
0
0
IBNIE
URESIE
SUSPIE
SUTOKIE
SOFIE
SUDAVIE
7FAF USBBAV
Breakpoint & Autovector
*
7FB0 IBNID
IN-Bulk-NAK ID
EP7IN
*
*
INT2SFC
BREAK
BPPULSE
BPEN
AVEN
EP6IN
EP5IN
EP4IN
EP3IN
EP2IN
EP1IN
EP0IN
7FB1 IBNMASK
IN-Bulk-NAK Intr. mask
EP7IN
7FB2 BPADDRH
Breakpoint Address H
A15
EP6IN
EP5IN
EP4IN
EP3IN
EP2IN
EP1IN
EP0IN
A14
A13
A12
A11
A10
A9
A8
7FB3 BPADDRL
Breakpoint Address L
A7
A6
A5
A4
A3
A2
A1
A0
Bulk Endpoints 0–7
7FB4 EP0CS
Control & Status
*
*
*
*
OUTBSY
INBSY
HSNAK
EP0STALL
7FB5 IN0BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FB6 IN1CS
Control & Status
*
*
*
*
*
*
in1bsy
in1stl
7FB7 IN1BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FB8 IN2CS
Control & Status
*
*
*
*
*
*
in2bsy
in2stl
7FB9 IN2BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FBA IN3CS
Control & Status
*
*
*
*
*
*
in3bsy
in3stl
7FBB IN3BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FBC IN4CS
Control & Status
*
*
*
*
*
*
in4bsy
in4stl
7FBD IN4BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FBE IN5CS
Control & Status
*
*
*
*
*
*
in5bsy
in5stl
7FBF IN5BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC0 IN6CS
Control & Status
*
*
*
*
*
*
in6bsy
in6stl
7FC1 IN6BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC2 IN7CS
Control & Status
*
*
*
*
*
*
in7bsy
in7stl
7FC3 IN7BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC4 (reserved)
Document #: 38-08005 Rev. **
Page 24 of 42
CY7C64601/603/613
4.0
Addr
Register Summary (continued)
Name
Description
D7
D6
D5
D4
D3
D2
D1
D0
*
d6
d5
d4
d3
d2
d1
d0
*
*
out1bsy
out1stl
d3
d2
d1
d0
*
*
out2bsy
out2stl
d3
d2
d1
d0
*
*
out3bsy
out3stl
d3
d2
d1
d0
7FC5 OUT0BC
Byte Count
7FC6 OUT1CS
Control & Status
*
*
*
*
7FC7 OUT1BC
Byte Count
*
d6
d5
d4
7FC8 OUT2CS
Control & Status
*
*
*
*
7FC9 OUT2BC
Byte Count
*
d6
d5
d4
7FCA OUT3CS
Control & Status
*
*
*
*
7FCB OUT3BC
Byte Count
*
d6
d5
d4
7FCC OUT4CS
Control & Status
*
*
*
*
*
*
out4bsy
out4stl
7FCD OUt4BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FCE OUT5CS
Control & Status
*
*
*
*
*
*
out5bsy
out5stl
7FCF OUT5BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FD0 OUT6CS
Control & Status
*
*
*
*
*
*
out6bsy
out6stl
7FD1 OUT6BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FD2 OUT7CS
Control & Status
*
*
*
*
*
*
out7bsy
out7stl
7FD3 OUT7BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC5 OUT0BC
Byte Count
*
d6
d5
d4
d3
d2
d1
d0
7FC6 OUT1CS
Control & Status
*
*
*
*
*
*
out1bsy
out1stl
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
WakeSRC
*
*
*
DisCon
DiscOE
ReNum
SIGRSUME
Global USB Registers
7FD4 SUDPTRH
Setup Data Ptr H
7FD5 SUDPTRL
Setup Data Ptr L
7FD6 USBCS
USB Control & Status
7FD7 TOGCTL
Toggle Control
Q
S
R
IO
0
EP2
EP1
EP0
7FD8 USBFRAMEL
Frame Number L
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
7FD9 USBFRAMEH
Frame Number H
0
0
0
0
0
FC10
FC9
FC8
Function Address
0
FA6
FA5
FA4
FA3
FA2
FA1
FA0
7FDD USBPAIR
Endpoint Control
ISOsend0
*
PR6OUT
PR4OUT
PR2OUT
PR6IN
PR4IN
PR2IN
7FDE IN07VAL
Input Endpoint 0–7 valid
IN7VAL
IN6VAL
IN5VAL
IN4VAL
IN3VAL
IN2VAL
IN1VAL
1
7FDF OUT07VAL
Output Endpoint 0–7 valid
OUT7VAL
OUT6VAL
OUT5VAL
OUT4VAL
OUT3VAL
OUT2VAL
OUT1VAL
1
7FE0 INISOVAL
Input EP 8–15 valid
IN15VAL
IN14VAL
IN13VAL
IN12VAL
IN11VAL
IN10VAL
IN9VAL
IN8VAL
7FE1 OUTISOVAL
Output EP 8–15 valid
OUT15VAL
OUT14VAL
OUT13VAL
OUT12VAL
OUT11VAL
OUT10VAL
OUT9VAL
OUT8VAL
7FE2 FASTXFR
Fast Transfer Mode
FISO
FBLK
RPOL
RMOD1
RMOD0
WPOL
WMOD1
WMOD0
7FE3 AUTOPTRH
Auto-Pointer H
A15
A14
A13
A12
A11
A10
A9
A8
7FE4 AUTOPTRL
Auto-Pointer L
A7
A6
A5
A4
A3
A2
A1
A0
7FE5 AUTODATA
Auto Pointer Data
D7
D6
D5
D4
D3
D2
D1
D0
8 bytes of SETUP data
d7
d6
d5
d4
d3
d2
d1
d0
A9
A8
A7
A6
A5
A4
0
0
7FDA (reserved)
7FDB FNADDR
7FDC (reserved)
7FE6-7FE7 (reserved)
Setup Data
7FE8 SETUPDAT
Isochronous FIFO Sizes
7FF0 OUT8ADDR
Endpt 8 OUT Start Addr
7FF1 OUT9ADDR
Endpt 9 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF2 OUT10ADDR
Endpt 10 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
Document #: 38-08005 Rev. **
Page 25 of 42
CY7C64601/603/613
4.0
Addr
Register Summary (continued)
D7
D6
D5
D4
D3
D2
D1
D0
7FF3 OUT11ADDR
Name
Endpt 11 OUT Start Addr
Description
A9
A8
A7
A6
A5
A4
0
0
7FF4 OUT12ADDR
Endpt 12 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF5 OUT13ADDR
Endpt 13 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF6 OUT14ADDR
Endpt 14 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF7 OUT15ADDR
Endpt 15 OUT Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF8 IN8ADDR
Endpt 8 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FF9 IN9ADDR
Endpt 9 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFA IN19ADDR
Endpt 10 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFB IN11ADDR
Endpt 11 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFC IN12ADDR
Endpt 12 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFD IN13ADDR
Endpt 13 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFE IN14ADDR
Endpt 14 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
7FFF IN15ADDR
Endpt 15 IN Start Addr
A9
A8
A7
A6
A5
A4
0
0
* - register bit is not used and undefined if read.
5.0
Input/Output Pin Special Consideration
The EZ-USB FX has a weak internal pull-up resistor that is present on the inputs and outputs when the external signal level is a
high (above 1.3V). The weak internal pull-up is not present in the circuit when the voltage level of the external signal is low. Since
the weak pull-up is only in the circuit when the external signal level is high, this means that if the last voltage level driven on the
pin was a high, the pull-up resistor will keep it high. However, if the last voltage level driven on the pin was a low then the pull-up
is turned off and the pad can float until it gets to a high logic level. This situation affects both inputs as well as outputs that are
three-stated. Use a 25-KΩ or lower pull-down resistor to bring a pin to a low level if needed.
6.0
Absolute Maximum Ratings
Storage Temperature ..........................................................................................................................................–65°C to +150°C
Ambient Temperature with Power Supplied ...............................................................................................................0°C to +70°C
Supply Voltage on VCC relative to VSS.................................................................................................................... –0.5V to +4.0V
DC Input Voltage............................................................................................................................................. –0.5V to VCC+0.5V
DC Voltage Applied to Outputs in High Z State ............................................................................................... –0.5V to VCC+0.5V
Power Dissipation ..............................................................................................................................................................500 mW
Static Discharge Voltage................................................................................................................ >1000V (per JEDEC standard)
Latch-up Current .............................................................................................................................................................. >200 mA
Max Output Sink Current ..................................................................................................................................................... 10 mA
7.0
Operating Conditions
TA (Ambient Temperature Under Bias) ......................................................................................................................0°C to +70°C
Supply Voltage ........................................................................................................................................................ +3.0V to +3.6V
Ground Voltage .......................................................................................................................................................................... 0V
FOSC (Oscillator or Crystal Frequency) ................................................................................................................ 12 MHz ± 0.25%
Document #: 38-08005 Rev. **
Page 26 of 42
CY7C64601/603/613
8.0
DC Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
3.0
3.6
V
VIH
Input High Voltage
2
5.25
V
VIL
Input Low Voltage
–0.5
0.8
V
II
Input Leakage Current
0< VIN < VCC
±10
µA
VOH
Output Voltage High
IOUT = 1.6 mA
VOL
Output Low Voltage
IOUT = –1.6 mA
CIN
Input Pin Capacitance
ISUSP
Suspend Current
ICC
Supply Current
2.4
8051 running, connected to USB
V
0.8
V
10
pF
[2]
µA
120
275
50
TBD
mA
USB Transceiver
VOH
Output Voltage High
IOUT = 1.6 mA
2.8
3.6
V
VOL
Output Low Voltage
IOUT = –1.6 mA
0.0
0.3
V
RpH
Output Impedance (HIGH state)
Includes external 24Ω ±1% resistor
28
44
Ω
RpL
Output Impedance (LOW state)
Includes external 24Ω ±1% resistor
28
44
Ω
Ii
Input Leakage Current
VCC = 3.6V; VI = 5.5V or GND; not for
IO pins
±5
µA
Ioz
Three-State Output OFF-State
Current
VI = VIH or VIL;
VO = VCC or GND
±10
µA
±0.1
Note:
2. Maximum suspend current is not guaranteed.
Document #: 38-08005 Rev. **
Page 27 of 42
CY7C64601/603/613
9.0
AC Electrical Characteristics
9.1
USB Transceiver
Specified Conditions: Per Table 7-6 of Revision 1.1 of USB specification
Parameter
Min.
Max.
Unit
4
20
ns
Tfall
Rise and Fall Times
Full Speed
4
20
ns
tRFM
Rise/Fall Time Matching
90
110
%
Vcr
Crossover Point
1.3
2.0
V
Trise
9.2
Description
Condition
Program Memory Read
tCL
CLKOUT
Note 3
tAV
tAV
A[15..0]
tSTBL
tSTBH
PSEN#
[4]
tACC1
D[7..0]
tDSU
tDH
data in
f1_8051_pgmemrd.vsd
Parameter
tCL
Description
Min.
1/CLKOUT Frequency
Typ.
Max.
Unit
Notes
41.66
ns
24 MHz
20.83
ns
48 MHz
tAV
Delay from Clock to Valid Address
0
10
ns
tSTBL
Clock to PSEN Low
0
8
ns
tSTBH
Clock to PSEN High
0
8
ns
tDSU
Data Set-up to Clock
10
ns
Data Hold Time
tDH
Notes:
3. CLKOUT is shown with positive polarity.
4. tACC1 is computed from the above parameters as follows:
tACC1(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC1(48 Mhz) = 3*tCL – tAV – tDSU = 44 ns
Document #: 38-08005 Rev. **
0
ns
Page 28 of 42
CY7C64601/603/613
9.3
Data Memory Read
Stretch=0
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
RD#
tACC2
[5]
tDSU
D[7..0]
tDH
data in
Stretch=1
tCL
CLKOUT
tAV
A[15..0]
RD#
tACC3
[5]
tDSU
D[7..0]
tDH
data in
f2_8051_datamemrd.vsd
Parameter
Description
Min.
1/CLKOUT Frequency
tCL
Typ.
Max.
Notes
ns
24 MHz
20.83
ns
48 MHz
tAV
Delay from Clock to Valid Address
tSTBL
Clock to RD Low
0
8
ns
tSTBH
Clock to RD High
0
8
ns
tDSU
Data Set-up to Clock
10
ns
Data Hold Time
tDH
Note:
5. tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 Mhz) = 3*tCL – tAV – tDSU = 44 ns
0
Unit
41.66
0
10
ns
ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 188 ns
tACC3(48 Mhz) = 5*tCL – tAV – tDSU = 85 ns
Document #: 38-08005 Rev. **
Page 29 of 42
CY7C64601/603/613
9.4
Data Memory Write
Stretch=0
tCL
CLKOUT
tAV
tSTBH
tSTBL
tAV
A[15..8]
WR#
tON1
tOFF1
D[7..0]
data out
Stretch=1
tCL
CLKOUT
tAV
tAV
A[15..8]
WR#
tOFF1
tON1
data out
D[7..0]
data_memory_write.vsd
Parameter
Description
Min.
Max.
Unit
tAV
Delay from Clock to Valid Address
0
10
ns
tSTBL
Clock to WR Pulse Low
0
8
ns
tSTBH
Clock to WR Pulse High
0
8
ns
tON1
Clock to Data Turn-on
0
7
ns
tOFF1
Clock to Data Hold Time
–2
7
ns
Document #: 38-08005 Rev. **
Notes
Page 30 of 42
CY7C64601/603/613
9.5
DMA Read
non-burst
tCL
CLKOUT
tAV
A[15..0]
Note 6
tSTBL
RD#/FRD#
CS#, OE#
Note 7
tDSU
D[7..0]
tSTBH
tDH
in
in
in
burst
tCL
CLKOUT
tAV
A[15..0]
Note 6
RD#/FRD#
CS#, OE#
tSTBL
tSTBH
tDSU
D[7..0]
tDH
in
in
in
in
in
f4_dmard.vsd
Parameter
Description
Min.
Max.
Unit
0
10
ns
Notes
tAV
Delay from Clock to Valid Address
tSTBL
Clock to Strobe Low
0
8
ns
Non-burst
tSTBH
Clock to Strobe High
0
8
ns
Non-burst
tDSU
Data to Clock Set-up
10
ns
Clock to Data Hold
tDH
Notes:
6. The address bus is not used in external FIFO transfers that use FRD#.
7. This is the maximum data rate. The strobes are programmable for longer access times.
Document #: 38-08005 Rev. **
0
ns
Page 31 of 42
CY7C64601/603/613
9.6
DMA Write
Non-Burst
tCL
CLKOUT
tAV
A[15..0]
Note 8
tSTBL
WR#/FWR#
CS#, OE#
Note 9
tON1
tSTBH
tDA
tOFF1
D[7..0]
Burst
tCL
CLKOUT
tAV
A[15..0]
Note 8
WR#/FWR#
CS#, OE#
tSTBL
tSTBH
tDA
D[7..0]
f5_dmawr.vsd
Min.
Max.
Unit
tAV
Parameter
Clock to Address Valid
Description
0
10
ns
tSTBL
Clock to Strobe Low
0
8
ns
Non-burst
tSTBH
Clock to Strobe High
0
8
ns
Non-burst
tDA
Clock to Valid Data
12
ns
tON1
Clock to Data Turn-on
7
ns
7
ns
0
Clock to Data Hold Time
–2
tOFF1
Notes:
8. The address bus in not used in external FIFO transfers (FWR# strobe).
9. This is the maximum data rate. The WR/FWR pulses are programmable for longer access times.
9.7
Notes
Slave FIFOs—Output Enables
AOE
BOE
tON
AFI [7..0]
BFI [7..0]
tOFF
f6_fifo_sync_oe.vsd
Parameter
Description
Min.
Max.
Unit
tON
FIFO Data Bus Turn-on Time
0
10
ns
tOFF
FIFO Data Bus Turn-off Time
0
10
ns
Document #: 38-08005 Rev. **
Page 32 of 42
CY7C64601/603/613
9.8
Slave FIFOs—Synchronous Read
tCL
XCLK
tSUX
tXH
ASEL/BSEL
SLRD
tXDA
AFI/BFI [7..0]
tXFLAG
FLAGS
f7_fifo_sync_read.vsd
Parameter
Description
tSUX
Strobe & Sel to External Clock Set-up Time
tXH
External Clock to Strobe & Sel Hold Time
tXDA
Clock to A/B FIFO data
tXFLAG
Clock to FIFO flag
9.9
Min.
Max.
Unit
9
ns
6
ns
13
ns
2tCL+11
ns
Slave FIFOs—Synchronous Write
tCL
XCLK
tSUX
tXH
ASEL/BSEL
SLWR
valid
AFI/BFI [7..0]
tXFLAG
FLAGS
f8_fifo_sync_write.vsd
Parameter
tCL
Description
Min.
CLKOUT Period
tSUX
Sel, Strobe & Data Set-up to External Clock
tXH
External Clock to Sel, Strobe & Data Hold Time
tXFLAG
External Clock to FIFO Flag
Document #: 38-08005 Rev. **
Typ.
Max.
Unit
41.66
ns
20.83
ns
9
ns
2tCL+11
ns
2
ns
Page 33 of 42
CY7C64601/603/613
9.10
Slave FIFOs—Asynchronous Read[10, 11]
Note 12
ASEL/BSEL
tRDL
tRDH
SLRD
tACCA
AFI/BFI [7..0]
tAFLAG
FLAGS
f9_fifo_async_read.vs
Parameter
Description
tRDL
SLRD strobe active
tRDH
SLRD strobe inactive
Min.
Max.
Unit
30
70
ns
90
ns
tACCA
Read active to FIFO data valid
40
ns
tAFLAG
SLRD inactive to FIFO flag
95
ns
9.11
Notes
ns
double byte mode
Slave FIFOs—Asynchronous Write[10, 11]
Note 12
ASEL/BSEL
tWRL
tWRH
SLWR
tSUA
tHA
AFI/BFI [7..0]
tAFLAG
FLAGS
f10_fifo_async_write.vsd
Parameter
Description
Min.
Max.
Unit
tWRL
Slave Write Strobe Active
30
ns
tWRH
Slave Write Strobe Inactive
70
ns
tSUA
Async Data Set-up Time to Write Strobe Inactive
10
ns
tHA
Async Data Hold Time to Write Strobe Inactive
5
tAFLAG
Async Write Strobe Inactive to FIFO Flag Valid
ns
95
ns
Notes:
10. The timing diagram assumes OEA/OEB is active.
11. The read operation begins when both A/BSEL and SLRD are active, and ends when either is inactive.
12. The polarities of ASEL/BSEL and SLRD are programmable. Active-LOW is shown.
Document #: 38-08005 Rev. **
Page 34 of 42
CY7C64601/603/613
9.12
GPIF Signals (Internally Clocked)
tCL
XCLK
(output)
tSRY
tRYH
RDYn
valid
GD[15..0] (input)
tXGD
CTLn and
GD[15..0] (output)
Parameter
Description
tSRY
RDYn and GPIF Data to External Clock Set-up Time
tRYH
External Clock to RDYn and GPIF Data Hold Time
tXGD
Clock to GPIF Data and CTLn output
9.13
Min.
Max.
9
2
Unit
ns
ns
13
ns
Max.
Unit
9
ns
13
ns
GPIF Signals (Externally Clocked)
tCL
XCLK
(input)
tSRX
tRYX
RDYn
GD[15..0] (input)
valid
tXGX
CTLn and
GD[15..0] (output)
Parameter
Description
tSRX
RDYn and GPIF Data to External Clock Set-up Time
tRYX
External Clock to RDYn and GPIF Data Hold Time
tXGX
Clock to GPIF Data and CTLn output
Min.
2
ns
Note:
13. tcl for an XCLK input must be greater than 20.83 ns.
Document #: 38-08005 Rev. **
Page 35 of 42
CY7C64601/603/613
10.0
Ordering Information
Part
Number
Package
Type
RAM
Size
Burst I/O Rate
(Bytes/sec)
# Prog
I/Os
Dataport
Isochronous
Support
CY7C64601-52NC
52 PQFP
4K
48 Mbytes
16
8-bit
No
CY7C64603-52NC
52 PQFP
8K
48 Mbytes
16
8-bit
No
CY7C64613-52NC
52 PQFP
8K
48 Mbytes
16
8-bit
Yes
CY7C64603-80NC
80 PQFP
8K
96 Mbytes
32
16-bit
No
CY7C64613-80NC
80 PQFP
8K
96 Mbytes
32
16-bit
Yes
CY7C64603-128NC
128 PQFP
8K
96 Mbytes
40
16-bit + Addr
No
CY7C64613-128NC
128 PQFP
8K
96 Mbytes
40
16-bit + Addr
Yes
EZ-USB FX Xcelerator
Development Kit
11.0
11.1
CY3671
Package Diagrams
52 PQFP
13.20 BSC
10.0 BSC
SQ.
7.8 REF.
1.1 REF.
52
40
39
1
0.65 BSC
52 PQFP
27
13
14
Document #: 38-08005 Rev. **
26
Page 36 of 42
CY7C64601/603/613
8 Places
12/16o
2.35 MAX
See Lead Detail
0.22/0.33
With Lead Finish
0.13/0.23
~
0.13/0.17
Base Metal
0.22/0.38
2.10
1.95
0o MIN
0.13
R. MIN.
0.13/
0.30 R.
0 .2 5 G a ge P lane
0.40 MIN
Base Plane
Seating Plane
0.10
0.25
0.73
1.03
0 - 7o
1.60 REF
52-Pin Lead Detail
Document #: 38-08005 Rev. **
Page 37 of 42
CY7C64601/603/613
11.2
80 PQFP
17.20 BSC.
14.00 BSC.
12.00 BSC.
61
80
1.00 Ref.
1
60
0.65 BSC.
80 PQFP
20
40
21
41
See Lead Detail
3.00 MAX
0.22/0.33
With Lead Finish
0.13/0.23
~
0.13/0.17
Base Metal
0.22/0.38
Document #: 38-08005 Rev. **
Page 38 of 42
CY7C64601/603/613
0.40 MIN.
0D MIN.
2.55
2.75
0.13/0.30 R.
0.13
R. MIN.
GAGE PLANE
Base
Plane
0.25
Seating
Plane
0.10
0.25
0.73
1.03
1.60 REF.
0-7D
80-Pin Lead Detail
Document #: 38-08005 Rev. **
Page 39 of 42
CY7C64601/603/613
11.3
128 PQFP
23.2 BSC.
20.0 BSC.
18.5 REF
0.75 REF.
102
65
64
0.50 BSC.
12.5 R E F
14.0 B S C .
17.20 B S C.
103
14.0
BASIC
128 PQFP
39
128
38
0.75 R E F.
1
8 Places
12/16o
See
Lead
Detail
3.40 MAX
0.13/0.28
With Lead Finish
0.11/0.23
~
0.11/0.19
Base Metal
0.13/0.25
Document #: 38-08005 Rev. **
Page 40 of 42
CY7C64601/603/613
2 .87
2 .57
0o MIN
0.13
R. MIN.
0.13/
0.30 R.
0.2 5 G ag e P lane
0.40 MIN
Base Plane
Seating Plane
0.25
0.50
0.73
1.03
0 - 7o
1.60 REF
128-Pin Lead Detail
Document #: 38-08005 Rev. **
Page 41 of 42
CY7C64601/603/613
Document Title: CY7C64601/CY7C64603/CY7C64613 EZ USB FX USB Microcontroller
Document Number: 38-08005
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
110206
11/11/01
SZV
Document #: 38-08005 Rev. **
Description of Change
Change from Spec number: 38-00903 to 38-08005
Page 42 of 42
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.