ASAHI KASEI [AK93C85A/95A/10A] AK93C85A / 95A / 10A 16K / 32K / 64Kbit Serial CMOS EEPROM Features ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION Vcc = 1.8V 5.5V AK93C85A 16384 bits, 1024 16 organization AK93C95A 32768 bits, 2048 16 organization 65536 bits, 4096 16 organization AK93C10A SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors LOW POWER CONSUMPTION - 0.4mA max. Read Operation - 0.8A Max. Standby HIGH RELIABILITY -Endurance : 100K cycles -Data Retention : 10 years Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE (Max. 8ms : VCC=4.5V 5.5V) Busy/Ready status signal Software controlled write protection IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package Block Diagram DAM02E-01 1999/10 -1- ASAHI KASEI [AK93C85A/95A/10A] General Description The AK93C85A/95A/10A is a 16384/32768/65536-bit serial CMOS EEPROM divided into 1024/2048/4096 registers of 16 bits each. The AK93C85A/95A/10A has 4 instructions such as READ, WRITE, EWEN and EWDS. Those instructions control the AK93C85A/95A/10A. The AK93C85A/95A/10A can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C85A/95A/10A, consisting of chip select (CS), serial clock (SK), data-in (DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C85A/95A/10A takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C85A/95A/10A takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output. Software controlled write protection When Vcc is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or Vcc is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. Busy/Ready status signal After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part. Type of Products Model AK93C85AF AK93C85AM AK93C95AF AK93C10AF Memory size 16Kbits 32Kbits 64Kbits Temp.Range -40C85C -40C85C -40C85C -40C85C DAM02E-01 Vcc 1.8V5.5V 1.8V5.5V 1.8V5.5V 1.8V5.5V Package 8pin Plastic SOP 8pin Plastic SSOP 8pin Plastic SOP 8pin Plastic SOP 1999/10 -2- ASAHI KASEI [AK93C85A/95A/10A] Pin arrangement Pin Name CS SK DI DO GND Vcc NC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Not Connected DAM02E-01 1999/10 -3- ASAHI KASEI [AK93C85A/95A/10A] Functional Description The AK93C85A/95A/10A has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address location. The CS pin must be brought low for a minimum of 250ns (Tcs) between each instruction when the instruction is continuously executed. Instruction READ WRITE EWEN EWDS WRAL Start Bit 1 1 1 1 1 Op Address Data Comments Code 10 A9-A0 D15-D0 Reads data stored in memory, at specified address. 01 A9-A0 D15-D0 Writes register. 00 11XXXXXXXX Write enable must precede all programming modes. 00 00XXXXXXXX Disables all programming instructions. 00 01XXXXXXXX D15-D0 Writes all registers. table1. Instruction Set for the AK93C85A Instruction READ WRITE EWEN EWDS WRAL Start Bit 1 1 1 1 1 Op Address Data Comments Code 10 A10-A0 D15-D0 Reads data stored in memory, at specified address. 01 A10-A0 D15-D0 Writes register. 00 11XXXXXXXXX Write enable must precede all programming modes. 00 00XXXXXXXXX Disables all programming instructions. 00 01XXXXXXXXX D15-D0 Writes all registers. table2. Instruction Set for the AK93C95A Instruction READ WRITE EWEN EWDS WRAL Start Bit 1 1 1 1 1 Op Address Data Comments Code 10 A11-A0 D15-D0 Reads data stored in memory, at specified address. 01 A11-A0 D15-D0 Writes register. 00 11XXXXXXXXXX Write enable must precede all programming modes. 00 00XXXXXXXXXX Disables all programming instructions. 00 01XXXXXXXXXX D15-D0 Writes all registers. table3. Instruction Set for the AK93C10A (Note) The WRAL instruction are used for factory function test only. User can't use the WRAL instruction. The AK93C85A/95A/10A perceives the start bit in the logic"1" and also "01". DAM02E-01 1999/10 -4- ASAHI KASEI [AK93C85A/95A/10A] Write The write instruction is followed by 16 bits of data to be written into the specified address. AK93C85A : After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). AK93C95A/10A : The self-timed programming cycle is initiated on the rising edge of the SK clock as the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the selftimed programming cycle is initiated. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. DAM02E-01 1999/10 -5- ASAHI KASEI [AK93C85A/95A/10A] Read The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. AK93C85A When the highest address is reached ($3FF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. AK93C95A When the highest address is reached ($7FF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. AK93C10A When the highest address is reached ($FFF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. DAM02E-01 1999/10 -6- ASAHI KASEI [AK93C85A/95A/10A] EWEN / EWDS When Vcc is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or Vcc is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. DAM02E-01 1999/10 -7- ASAHI KASEI [AK93C85A/95A/10A] Absolute Maximum Ratings Parameter Power Supply All Input Voltages with Respect to Ground Ambient storage temperature Symbol Min Max Unit VCC VIO -0.6 -0.6 +7.0 VCC+0.6 V V Tst -65 +150 C Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Recommended Operating Condition Parameter Symbol Min Max Unit Power Supply VCC 1.8 5.5 V Ambient Operating Temperature Ta -40 +85 C DAM02E-01 1999/10 -8- ASAHI KASEI [AK93C85A/95A/10A] Electrical Characteristics (1) D.C. ELECTRICAL CHARACTERISTICS ( 1.8VVcc5.5V, -40CTa85C, unless otherwise specified ) Parameter Symbol Current Dissipation ICC1 (WRITE) ICC2 Current Dissipation ICC3 (READ,EWEN,EWDS) ICC4 Current Dissipation ICCSB (Standby) Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH1 VOH2 Output Low Voltage VOL1 VOL2 Input Leakage ILI Output Leakage ILO Condition VCC=5.5V, tSKP=1us, VCC=1.8V, tSKP=4us, VCC=5.5V, tSKP=1us, VCC=1.8V, tSKP=4us, VCC=5.5V 2.5VVCC5.5V IOH=-0.1mA 1.8VVCC<2.5V IOH=-0.1mA 2.5VVCC5.5V IOL=1.0mA 1.8VVCC<2.5V IOL=0.1mA VCC=5.5V,VIN=5.5V VCC=5.5V VOUT=5.5V,CS=GND Min. *1 *1 *1 *1 *2 0.8 VCC -0.1 0.8 VCC Max. Unit 5.5 3.0 0.4 0.1 0.8 mA mA mA mA uA VCC+0.5 0.2 VCC V V V 0.8 VCC V 0.4 V 0.4 V 1.0 uA 1.0 uA *1:VIN=VIH/VIL,DO=Open *2:VIN=VCC/GND,CS=GND,DO=Open DAM02E-01 1999/10 -9- ASAHI KASEI [AK93C85A/95A/10A] (2) A.C. ELECTRICAL CHARACTERISTICS ( 1.8VVcc5.5V, -40CTa85C, unless otherwise specified ) Parameter SK Cycle Time Symbol tSKP1 tSKP2 tSKP3 SK Pulse Width tSKW1 tSKW2 tSKW3 CS Setup Time tCSS CS Hold Time tCSH Data Setup Time tDIS Data Hold Time tDIH Output delay tPD1 tPD2 tPD3 Selftimed Programming tE/W1 Time tE/W2 Min CS Low Time tCS CS to Status Valid1 tSV CS to Status Valid2 tSVV CS to Output High-Z tOZ1 tOZ2 Condition 4.5VVCC5.5V 2.0VVCC<4.5V 1.8VVCC<2.0V 4.5VVCC5.5V 2.0VVCC<4.5V 1.8VVCC<2.0V Min. Max. 1.0 2.0 4.0 500 1.0 2.0 100 0 200 200 4.5VVCC5.5V, *3 2.0VVCC<4.5V, *3 1.8VVCC<2.0V. *3 4.5VVCC5.5V 1.8VVCC<4.5V 500 1.0 2.0 8 10 250 CL=100pF CL=100pF 2.0VVCC5.5V 1.8VVCC<2.0V 500 1000 100 250 Unit us us us ns us us ns ns ns ns ns us us ms ms ns ns ns ns ns *3:CL=100pF DAM02E-01 1999/10 - 10 - ASAHI KASEI [AK93C85A/95A/10A] Synchronous Data timing The Start of Instruction The End of Instruction DAM02E-01 1999/10 - 11 - ASAHI KASEI [AK93C85A/95A/10A] Busy/Ready Signal Output (AK93C85A) Busy/Ready Signal Output (AK93C95A/10A) DAM02E-01 1999/10 - 12 - IMPORTANT NOTICE zThese products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. 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