Cypress CY7C185D-10PXC 64k (8k x 8) static ram Datasheet

PRELIMINARY
CY7C185D
64K (8K x 8) Static RAM
Functional Description[1]
Features
• Pin- and function-compatible with CY7C185
The CY7C185D is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and three-state drivers. This device has an automatic
power-down feature (CE1 or CE2), reducing the power
consumption when deselected.
• High speed
— tAA = 10 ns
• Low active power
— ICC = 60 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 3 mA
• CMOS for optimum speed/power
• Data Retention at 2.0V
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Lead (Pb)-Free Packages
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.The CY7C185D is in a standard 28-pin
300-mil-wide DIP, SOJ, or SOIC Pb-Free package.
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
I/O0
INPUT BUFFER
SENSE AMPS
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O1
256 x 32 x 8
ARRAY
I/O2
I/O3
I/O4
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O5
I/O6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
I/O7
A12
A11
A10
A0
A9
OE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05466 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 10, 2005
CY7C185D
PRELIMINARY
Selection Guide
CY7C185D-10
CY7C185D-12
CY7C185D-15
Unit
Maximum Access Time
10
12
15
ns
Maximum Operating Current
60
50
40
mA
Maximum Standby Current
3
3
3
mA
Document #: 38-05466 Rev. *C
Page 2 of 10
CY7C185D
PRELIMINARY
DC Input Voltage[2].................................... −0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[2] ....................................... −0.5V to VCC + 0.5V
Range
Ambient Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Commercial
Industrial
Electrical Characteristics Over the Operating Range
7C185D-10
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
Voltage[2]
Min.
7C185D-12
Max.
Min.
2.4
Max.
2.4
0.4
Unit
V
0.4
V
2.0
VCC + 0.3V
2.0
VCC + 0.3V
V
–0.5
0.8
–0.5
0.8
V
VIL
Input LOW
IIX
Input Load Current
GND ≤ VI ≤ VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage Current
GND ≤ VI ≤ VCC, Output Disabled
–1
+1
–1
+1
µA
–300
mA
IOS
Output Short Circuit
Current[3]
VCC = Max., VOUT = GND
–300
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA
60
50
mA
ISB1
Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL
Min. Duty Cycle = 100%
10
10
mA
ISB2
Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
3.0
3.0
mA
7C185D-15
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
Min.
2.4
Voltage[2]
VIL
Input LOW
IIX
Input Load Current
IOZ
Output Leakage Current
Current[3]
Max.
Unit
V
0.4
V
2.0
VCC + 0.3V
V
–0.5
0.8
V
GND ≤ VI ≤ VCC
–1
+1
µA
GND ≤ VI ≤ VCC, Output Disabled
–1
+1
µA
IOS
Output Short Circuit
–300
mA
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA
40
mA
ISB1
Automatic Power-down Current Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL
Min. Duty Cycle = 100%
10
mA
ISB2
Automatic Power-down Current Max. VCC, CE1 ≥ VCC – 0.3V or CE2 ≤ 0.3V
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
3.0
mA
VCC = Max., VOUT = GND
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
7
pF
7
pF
Notes:
2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05466 Rev. *C
Page 3 of 10
CY7C185D
PRELIMINARY
Thermal Resistance[4]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance
(Junction to Ambient)[4]
ΘJC
Thermal Resistance
(Junction to Case)[4]
All-Packages
Unit
TBD
°C/W
TBD
°C/W
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
AC Test Loads and Waveforms
10-ns Device
ALL INPUT PULSES
Z = 50Ω
3.0V
OUTPUT
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(a)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
30 pF*
GND
≤ 3 ns
≤ 3 ns
12, 15-ns Devices
R1 481 Ω
5V
OUTPUT
1.5V
30 pF
1.73V
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
High-Z characteristics:
5V
OUTPUT
R2
255Ω
R1 481 Ω
5 pF
INCLUDING
JIGAND
SCOPE
(b)
R2
255Ω
(c)
Switching Characteristics Over the Operating Range [6]
7C185D-10
Parameter
Description
Min.
Max.
7C185D-12
Min.
Max.
7C185D-15
Min.
Max.
Unit
Read Cycle
tpower[5]
VCC(typical) to the first access
100
100
100
µs
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
10
12
15
ns
tACE2
CE2 HIGH to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7]
tLZCE1
CE1 LOW to Low
Z[8]
tLZCE2
CE2 HIGH to Low Z
tHZCE
CE1 HIGH to High Z[7, 8]
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
CE2 to HIGH to Power-Up
tPD
CE1 HIGH to Power-Down
CE2 LOW to Power-Down
10
3
12
3
5
3
6
3
5
3
ns
7
0
12
ns
ns
3
0
10
7
6
ns
ns
3
3
5
0
8
6
ns
ns
3
3
3
15
3
ns
ns
15
ns
Notes:
5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.
Document #: 38-05466 Rev. *C
Page 4 of 10
CY7C185D
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[6]
7C185D-10
Parameter
Write Cycle
Description
Min.
Max.
7C185D-12
Min.
7C185D-15
Max.
Min.
Max.
Unit
[9]
tWC
Write Cycle Time
10
12
15
ns
tSCE1
CE1 LOW to Write End
8
10
12
ns
tSCE2
CE2 HIGH to Write End
8
10
12
ns
tAW
Address Set-up to Write End
7
10
12
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
10
12
ns
tSD
Data Set-up to Write End
6
7
8
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High Z[7]
tLZWE
WE HIGH to Low Z
6
3
6
7
3
3
ns
ns
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current Non-L, Com’l / Ind’l
tCDR
tR[10]
Max.
2.0
L-Version Only
Chip Deselect to Data Retention Time
[4]
Min.
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
Operation Recovery Time
Unit
V
3
mA
1.2
mA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
4.5V
VCC
VDR > 2V
4.5V
tR
tCDR
CE
Switching Waveforms
Read Cycle No.1[11,12]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes:
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
11. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
12. WE is HIGH for read cycle.
Document #: 38-05466 Rev. *C
Page 5 of 10
CY7C185D
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No.2[13,14]
tRC
CE1
CE2
tACE
OE
OE
DATA OUT
tHZOE
tDOE
tLZOE
HIGH IMPEDANCE
tHZCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[12,14]
tWC
ADDRESS
tSCEI
CE1
tAW
tHA
tSCE2
CE
CE
2
tSA
WE
tPWE
OE
tSD
DATA I/O
tHD
DATA IN VALID
NOTE 15
tHZOE
Write Cycle No. 2 (CE Controlled)[14,15,16]
tWC
ADDRESS
tSCE1
CE1
tSA
tSCE2
CE2
tAW
tHA
WE
tSD
DATA I/O
tHD
DATA IN VALID
Notes:
13. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.
14. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH to
initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
15. During this period, the I/Os are in the output state and input signals should not be applied.
16. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05466 Rev. *C
Page 6 of 10
CY7C185D
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14,15,16,17]
tWC
ADDRESS
CE1
tSCE1
CE2
tSCE2
tAW
tHA
tSA
WE
tSD
DATA I/O
NOTE 15
tHD
DATA IN VALID
tLZWE
tHZWE
Truth Table
CE1
CE2
WE
OE
Input/Output
Mode
H
X
X
X
High Z
Deselect/Power-down
X
L
X
X
High Z
Deselect/Power-down
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
High Z
Deselect
Ordering Information
Speed
(ns)
10
12
15
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C185D-10PXC
P21
28-Lead (300-Mil) Molded DIP (Pb-Free)
Commercial
CY7C185D-10SXC
S21
28-Lead Molded SOIC (Pb-Free)
CY7C185D-10VXC
V21
28-Lead Molded SOJ (Pb-Free)
CY7C185D-10VXI
V21
28-Lead Molded SOJ (Pb-Free)
Industrial
CY7C185D-12PXC
P21
28-Lead (300-Mil) Molded DIP (Pb-Free)
Commercial
CY7C185D-12SXC
S21
28-Lead Molded SOIC (Pb-Free)
CY7C185D-12VXC
V21
28-Lead Molded SOJ (Pb-Free)
CY7C185D-12VXI
V21
28-Lead Molded SOJ (Pb-Free)
Industrial
CY7C185D-15PXC
P21
28-Lead (300-Mil) Molded DIP (Pb-Free)
Commercial
CY7C185D-15SXC
S21
28-Lead Molded SOIC (Pb-Free)
CY7C185D-15VXC
V21
28-Lead Molded SOJ (Pb-Free)
CY7C185D-15VXI
V21
28-Lead Molded SOJ (Pb-Free)
Industrial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Note:
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05466 Rev. *C
Page 7 of 10
CY7C185D
PRELIMINARY
Package Diagrams
28-Lead (300-Mil) PDIP P21
SEE LEAD END OPTION
14
1
DIMENSIONS IN INCHES [MM] MIN.
MAX.
REFERENCE JEDEC MO-095
0.260[6.60]
0.295[7.49]
15
PACKAGE WEIGHT: 2.15 gms
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.115[2.92]
0.160[4.06]
0.015[0.38]
0.060[1.52]
0.009[0.23]
0.012[0.30]
0.055[1.39]
0.065[1.65]
0.090[2.28]
0.110[2.79]
3° MIN.
0.310[7.87]
0.385[9.78]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
51-85014-*D
LEAD END OPTION
(LEAD #1, 14, 15 & 28)
28-Lead (300-Mil) Molded SOIC S21
PIN 1 ID
14
1
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.394[10.01]
*
0.419[10.64]
0.291[7.39]
PACKAGE WEIGHT 0.85gms
0.300[7.62]
15
28
REFERENCE JEDEC MO-119
PART #
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
0.026[0.66]
0.032[0.81]
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
0.004[0.10]
0.050[1.27]
TYP.
0.013[0.33]
0.004[0.10]
0.019[0.48]
0.0118[0.30]
*
0.015[0.38]
0.050[1.27]
0.0091[0.23]
0.0125[3.17]
*
51-85026-*C
Document #: 38-05466 Rev. *C
Page 8 of 10
PRELIMINARY
CY7C185D
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
51-85031-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05466 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C185D
Document History Page
Document Title: CY7C185D 64K (8K x 8) Static RAM (Preliminary)
Document Number: 38-05466
REV.
ECN NO.
Orig. of
Issue Date Change
Description of Change
**
201560
See ECN
SWI
Advance Datasheet for C9 IPP
*A
233715
See ECN
RKF
DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in Ordering Information
*B
262950
See ECN
RKF
Added Tpower Spec in Switching Characteristics table
Added Data Retention Characteristics table and waveforms
Shaded Ordering Information
*C
307593
See ECN
RKF
1) Reduced Speed bins to -10, -12 and -15 ns
2) Added ‘Industrial’ grade parts to the Ordering Info on Page #6
Document #: 38-05466 Rev. *C
Page 10 of 10