AMD AM79C984AJC Enhanced integrated multiport repeater (eimrâ ¢) Datasheet

PRELIMINARY
Am79C984A
enhanced Integrated Multiport Repeater (eIMR™)
DISTINCTIVE CHARACTERISTICS
■ Repeater functions comply with IEEE 802.3
Repeater Unit specifications
■ Full LED support for individual port status LEDs
and network utilization LEDs
■ Four integral 10BASE-T transceivers with onchip filtering that eliminate the need for external
filter modules on the 10BASE-T transmit-data
(TXD) and receive-data (RXD) lines
■ Programmable extended distance mode on the
RXD lines, allowing connection to cables longer
than 100 meters
■ One Reversible Attachment Unit Interface
(RAUI™) port that can be used either as a
standard IEEE-compliant AUI port for
connection to a Medium Attachment Unit (MAU),
or as a reversed port for direct connection to a
Media Access Controller (MAC)
■ Low cost suitable for non-managed multiport
repeater designs
■ Expandable to increase number of repeater
ports with support for up to seven eIMR devices
without the need for an external arbiter
■ Twisted Pair Link Test capability conforming to
the 10BASE-T standard. The Link Test function
and the transmission of Link Test pulses can be
optionally disabled through the control port to
allow devices that do not implement the Link Test
function to work with the eIMR device.
■ Programmable option of automatic polarity
detection and correction permits automatic
recovery due to wiring errors
■ Full amplitude and timing regeneration for
retransmitted waveforms
■ CMOS device with a single +5-V supply
■ All ports can be individually isolated
(partitioned) in response to excessive collision
conditions or fault conditions.
GENERAL DESCRIPTION
The enhanced Integrated Multiport Repeater (eIMR)
device is a VLSI integrated circuit that provides a system-level solution to designing non-managed multiport
repeaters. The device integrates the repeater functions
specified in Section 9 of the IEEE 802.3 standard and
Twisted Pair Transceiver functions complying with the
10BASE-T standard.
The eIMR device provides four Twisted Pair (TP) ports
and one RAUI port for direct connection to a MAC. The
total number of ports per repeater unit can be increased by connecting multiple eIMR devices through
their expansion ports, hence, minimizing the total cost
per repeater port.
The device is fabricated in CMOS technology and
requires a single +5-V supply.
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
Publication# 20650 Rev: B Amendment/0
Issue Date: January 1998
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am79C984A
J
C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
TEMPERATURE RANGE
C = Commercial (0˚C to +70˚C)
PACKAGE TYPE
J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
K = 100-Pin Plastic Quad Flat Pack (PQR100)
SPEED OPTION
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C984A
enhanced Integrated Multiport Repeater (eIMR)
Valid Combinations
Am79C984A
2
JC, KC\W
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.
Am79C984A
Am79C984A
Reset
Clock
Gen
CLK
TP
Port
3
TP
Port
0
AUI
Port
RST
TXD±
RXD±
TXD±
RXD±
DO±
CI±
DI±
RX
MUX
Timers
Partitioning
Link Test
eIMR Chip
Control
Manchester
Encoder
Phase
Lock
Loop
Manchester
Decoder
FIFO
CONTROL
FIFO
Test
and
Control
Port
LED
Interface
Expansion Port
Jam Sequence
Preamble
SI
SO
SCLK
AMODE
LDA[4:0], LDB[4:0]
LDGA, LDGB
LDC[2:0]
ACT[7:0]
SELI[1:0]
SELO
ACK
COL
DAT
JAM
20650B-1
20650A-1
TX
MUX
P R E L I M I N A R Y
BLOCK DIAGRAM
3
P R E L I M I N A R Y
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Hardware Implemented Management Information Base (HIMIB™)
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Am79C900
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Am79C940
Media Access Controller for Ethernet (MACE™)
Am79C960
PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961
PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)
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PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965
PCnet™-32 Single-Chip 32-Bit Ethernet Controller
Am79C970
PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C970A
PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
Am79C974
PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C983
Integrated Multiport Repeater 2 (IMR2™)
Am79C985
enhanced Integrated Multiport Repeater Plus (eIMR+™)
4
Am79C984A
P R E L I M I N A R Y
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
STANDARD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
RELATED AMD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32
CONNECTION DIAGRAM (PL 084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
CONNECTION DIAGRAM (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
LOGIC SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
LOGIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
PIN DESIGNATIONS (PL 084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
PIN DESIGNATIONS (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Twisted Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Basic Repeater Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Repeater Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Signal Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Jabber Lockup Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Fragment Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Auto Partitioning/Reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Detailed Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
TP Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Twisted Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44
Link Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Visual Status Monitoring (LED) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Network Activity Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48
Internal Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48
IMR+ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48
Control Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49
Command/Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50
Control Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50
SET (Write Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Chip Programmable Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Alternate AUI Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Alternate TP Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
AUI Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
AUI Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
TP Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
TP Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Disable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Enable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Disable Link Pulse (Per TP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Am79C984A
5
P R E L I M I N A R Y
Enable Link Pulse (Per TP Port). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52
Disable Automatic Receiver Polarity Reversal (Per TP Port) . . . . . . . . . . . . . . . . . 1-53
Enable Automatic Receiver Polarity Reversal (Per TP Port) . . . . . . . . . . . . . . . . . 1-53
Disable Receiver Extended Distance Mode (Per TP Port) . . . . . . . . . . . . . . . . . . . 1-53
Enable Receiver Extended Distance Mode (Per TP Port) . . . . . . . . . . . . . . . . . . . 1-53
Disable Software Override of LEDs 5
(Per Port - AUI and TP, Global) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53
Enable Software Override of Bank A LEDs (Per Port - AUI and TP, Global) . . . . . 1-53
Enable Software Override of Bank B LEDs (Per Port - AUI and TP, Global) . . . . . 1-54
Software Override of LED Blink Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54
GET (Read Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54
AUI Port(s) Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54
Alternate AUI Port(s) Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54
TP Port Partitioning Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54
Bit Rate Error Status of TP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54
Link Test Status of TP ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
Receive Polarity Status of TP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
MJLP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
SYSTEMS APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
eIMR to TP Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
Twisted Pair Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55
MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57
Internal Arbitration Mode Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57
IMR+ Mode External Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57
Visual Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-59
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60
DC CHARACTERISTICS over operating ranges unless otherwise specified . . . . . . . . . . . . . . . . . 1-60
SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62
KEY TO SWITCHING WAVEFORMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64
SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64
SWITCHING TEST CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-69
6
Am79C984A
P R E L I M I N A R Y
TXD0–
TXD0+
VDD
LDC2
LDC1
LDC0
VDD
LDGB
LDGA
LDB4
DVSS
LDA4
LDB3
LDA3
DVSS
LDB2
LDA2
VDD
LDB1
LDA1
DVSS
LDB0
LDA0
ACT7
SCLK
VDD
ACT0
ACT1
ACT2
DVSS
ACT3
ACT4
ACT5
ACT6
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
13
73
72
14
71
15
70
16
17
69
68
18
67
19
66
20
21
65
eIMR
64
22
Am79C984A
63
23
62
24
61
25
60
26
27
59
58
28
57
29
56
30
55
31
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
SELO
COL
DVSS
ACK
DAT
VDD
JAM
NC
DVSS
SI
SO
REXT
AVSS
DI+
DI–
VDD
CI+
CI–
AVSS
DO+
DO–
AMODE
VDD
DVSS
VDD
VDD
VDD
RST
CLK
DVSS
SELI_0
SELI_1
TXD1–
TXD1+
AVSS
RXD3–
RXD3+
RXD2–
RXD2+
RXD1–
RXD1+
RXD0–
RXD0+
VDD
TXD3–
TXD3+
AVSS
TXD2–
TXD2+
VDD
CONNECTION DIAGRAM (PL 084)
20650A-2
20650B-2
Am79C984A
7
P R E L I M I N A R Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
eIMR
Am79C984A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
NC
NC
NC
LDC2
LDC1
LDC0
VDD
LDGB
LDGA
LDB4
DVSS
LDA4
LDB3
LDA3
DVSS
LDB2
LDA2
VDD
LDB1
LDA1
NC
DVSS
LDB0
LDA0
ACT7
NC
NC
NC
ACT6
COL
DVSS
NC
ACK
DAT
VDD
JAM
NC
DVSS
SI
SO
SCLK
VDD
ACT0
ACT1
ACT2
DVSS
ACT3
ACT4
ACT5
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RXD3–
NC
NC
NC
REXT
AVSS
DI+
DI–
VDD
CI+
CI–
AVSS
DO+
DO–
AMODE
VDD
DVSS
VDD
VDD
VDD
RST
NC
CLK
DVSS
SELI_0
SELI_1
NC
NC
NC
SELO
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
RXD3+
RXD2–
NC
RXD2+
RXD1–
RXD1+
RXD0–
RXD0+
VDD
TXD3–
TXD3+
AVSS
TXD2–
TXD2+
VDD
TXD1–
TXD1+
AVSS
TXD0–
TXD0+
CONNECTION DIAGRAM (PQR100)
20650B-3
8
Am79C984A
P R E L I M I N A R Y
LOGIC SYMBOL
V DD
TXD+
TXD–
RXD+
RXD–
DAT
JAM
ACK
COL
SELO
SELI[1:0]
Expansion
Port
DO+
DO–
DI+
DI–
CI+
CI–
SI
Am79C984
SO
SCLK
AMODE
LDA[4:0], LDB[4:0]
LDGA, LDGB
LDC[2:0]
ACT[7:0]
CLK
Test and
Control
Port
Twisted Pair
Ports
(4 Ports)
AUI
LED
Interface
RST
DVSS
AVSS
20650A-4
20650B-4
LOGIC DIAGRAM
AUI
LED
Port
Control
Port
Repeater
State
Machine
Twisted Pair
Port 0
Expansion
Port
Twisted Pair
Port 3
20650A-5
20650B-5
Am79C984A
9
P R E L I M I N A R Y
PIN DESIGNATIONS (PL 084)
Listed by Pin Number
10
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
TXD3+
22
AMODE
43
SO
64
LDA3
2
TXD3-
23
VDD
44
SCLK
65
LDB3
3
VDD
24
DVSS
45
VDD
66
LDA4
4
RXD0+
25
VDD
46
ACT0
67
DVSS
5
RXD0-
26
VDD
47
ACT1
68
LDB4
6
RXD1+
27
VDD
48
ACT2
69
LDGA
7
RXD1-
28
RST
49
DVSS
70
LDGB
8
RXD2+
29
CLK
50
ACT3
71
VDD
9
RXD2-
30
DVSS
51
ACT4
72
LDC0
10
RXD3+
31
SELI_0
52
ACT5
73
LDC1
11
RXD3-
32
SELI_1
53
ACT6
74
LDC2
12
REXT
33
SELO
54
ACT7
75
VDD
13
AVSS
34
COL
55
LDA0
76
TXD0+
14
DI+
35
DVSS
56
LDB0
77
TXD0-
15
DI-
36
ACK
57
DVSS
78
AVSS
16
VDD
37
DAT
58
LDA1
79
TXD1+
17
CI+
38
VDD
59
LDB1
80
TXD1-
18
CI-
39
JAM
60
VDD
81
VDD
19
AVSS
40
NC
61
LDA2
82
TXD2+
20
DO+
41
DVSS
62
LDB2
83
TXD2-
21
DO-
42
SI
63
DVSS
84
AVSS
Am79C984A
P R E L I M I N A R Y
PIN DESIGNATIONS (PQR100)
Listed by Pin Number
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
RXD3-
26
SELI_1
51
ACT6
76
LDC2
2
NC
27
NC
52
NC
77
NC
3
NC
28
NC
53
NC
78
NC
4
NC
29
NC
54
NC
79
NC
5
REXT
30
SELO
55
ACT7
80
VDD
6
AVSS
31
COL
56
LDA0
81
TXD0+
7
DI+
32
DVSS
57
LDB0
82
TXD0-
8
DI-
33
NC
58
DVSS
83
AVSS
9
VDD
34
ACK
59
NC
84
TXD1+
10
CI+
35
DAT
60
LDA1
85
TXD1-
11
CI-
36
VDD
61
LDB1
86
VDD
12
AVSS
37
JAM
62
VDD
87
TXD2+
13
DO+
38
NC
63
LDA2
88
TXD2-
14
DO-
39
DVSS
64
LDB2
89
AVSS
15
AMODE
40
SI
65
DVSS
90
TXD3+
16
VDD
41
SO
66
LDA3
91
TXD3-
17
DVSS
42
SCLK
67
LDB3
92
VDD
18
VDD
43
VDD
68
LDA4
93
RXD0+
19
VDD
44
ACT0
69
DVSS
94
RXD0-
20
VDD
45
ACT1
70
LDB4
95
RXD1+
21
RST
46
ACT2
71
LDGA
96
RXD1-
22
NC
47
DVSS
72
LDGB
97
RXD2+
23
CLK
48
ACT3
73
VDD
98
NC
24
DVSS
49
ACT4
74
LDC0
99
RXD2-
25
SELI_0
50
ACT5
75
LDC1
100
RXD3+
Notes:
1. Pin 40 has a bonding option depending on internal device name.
2. NC = No Connection.
Am79C984A
11
P R E L I M I N A R Y
PIN DESCRIPTION
AUI Port
state of the DAT pin is used in conjunction with JAM to
indicate a single port (DAT =1) or multiport (DAT=0) collision. JAM is in the high-impedance state if neither the
SEL nor ACK signal is asserted. It is recommended that
JAM be pulled up or down via a high value resistor.
DI+, DI–
Data In
Differential Input
DI± are differential, Manchester receiver pins. The signals comply with IEEE 802.3, Section 7.
SELI0-1
Select In
Input, Active LOW
DO+, DO–
Data Out
Differential Output
DO± are differential, Manchester output driver pins. The
signals comply with IEEE 802.3, Section 7.
When the expansion bus is configured for Internal Arbitration mode, these signals indicate that another eIMR
device is active; SELI0 or SELI1 is driven by SELO from
the upstream device. At reset, SELI0 selects between
the Internal Arbitration mode and the IMR+ mode of the
expansion bus; a HIGH selects the Internal Arbitration
mode and a LOW selects the IMR+ mode.
CI+, CI–
Collision Input
Differential Input/Output
CI± are differential, Manchester I/O signals. As an input,
CI is a collision-receive indicator. As an output, CI generates a 10-MHz signal if the eIMR device senses a
collision.
Twisted Pair Ports
TXD+0-3, TXD–0-3
Transmit Data
Differential Output
TXD± are 10BASE-T port differential drivers (4 ports).
RXD+0-3, RXD–0-3
Receive Data
Differential Input
RXD± are 10BASE-T port differential receive inputs
(4 ports).
Expansion Bus
DAT
Data
Input/Output/3-State
If the SELO and ACK pins are asserted during noncollision conditions, the eIMR device drives NRZ data
onto the DAT line, regenerating the preamble if necessary. During a collision, when JAM is HIGH, DAT is used
to differentiate between single-port (DAT=1) and multiport (DAT=0) collisions. DAT is an output when ACK is
asserted and the eIMR device’s ports are active; DAT
is an input when ACK is asserted and the ports are
inactive. If ACK is not asserted, DAT is in the high-impedance state. It is recommended that DAT be pulled
up or down via a high value resistor.
JAM
Jam
Input/Output/3-State
The active eIMR device drives JAM HIGH, if it detects
a collision condition on one or more of its ports. The
12
Arbitration
Mode
SELI_1
SELI_0
X
1
Internal
X
0
IMR+
SELO
Select Out
Output, Active LOW
If the expansion bus is configured for Internal Arbitration
mode, an eIMR device drives this pin LOW when it is
active or when either of its SELI0-1 pins is LOW. An
active eIMR device is defined as having one or more
ports receiving or colliding and/or is still transmitting
data from the internal FIFO, or extending a packet to the
minimum of 96 bit times. When the expansion bus is
configured for IMR+ mode, SELO is active when the
eIMR device is active (acquiring the functionality of the
REQ pin on the Am79C971 IMR+ device).
ACK
Acknowledge
Input/Output, Active LOW, Open Drain
This signal is asserted to indicate that an eIMR device
is active. It also signals to the other eIMR devices the
presence of a valid collision status on the JAM line and
valid data on the DAT line. When the eIMR device is
configured for Internal Arbitration mode, ACK is an I/O,
and must be pulled to VDD via a minimum equivalent
resistance of 1 kΩ. When the eIMR device is configured
for IMR+ mode, ACK is an input driven by an external
arbiter.
COL
Collision
Input/Output, Active LOW, Open Drain
When asserted, COL indicates that more than one eIMR
device is active. Each eIMR device generates the Collision Jam sequence independently. When the eIMR device is configured for Internal Arbitration mode, COL is
Am79C984A
P R E L I M I N A R Y
an I/O and must be pulled to VDD via a minimum equivalent resistance of 1 kΩ. When the eIMR device expansion port is configured for IMR+ mode, COL is an input
driven by an external arbiter.
Control Port
AMODE
AUI Mode
Input
At reset, this pin sets the AUI port to either normal or
reversed mode. If AMODE is LOW at the rising edge of
RST, the AUI port is set to the normal mode; if AMODE
is HIGH, the AUI port is set to the reversed mode.
SCLK
Serial Clock In
Input
Serial data (input or output) is clocked (in or out) on the
rising edge of the signal on this pin. SCLK is asynchronous to CLK and can operate at frequencies up to 10
MHz.
SI
Serial In
Input
The SI pin is used as a test/control serial input port.
Control commands are clocked in on this pin synchronous to SCLK input.
multiple-eIMR configuration, LDGA from each of the
eIMR devices can be tied together to drive a single global LED in Bank A.
LDGB
Global LED Driver, Bank B
Output, Open Drain
LDGB is the Global LED driver for LED Bank B. The
signal represents global CRS or JAB conditions. In a
multiple eIMR configuration, LDGB from each of the
eIMR devices can be tied together to drive a single global LED in Bank B.
LDC0-2
LED Control
Input
These pins select the attributes that will be displayed
on LDA0-4, LDB0-4, LDGA, and LDGB. If an LED is programmed to display two attributes, the attribute associated with the periodic blink takes precedence.
ACT0-7
Activity Display
Output
These signals drive the activity LEDs, which indicate
the percentage of network utilization. The display is updated every 250 ms.
Miscellaneous Pins
At reset, SI sets the state of the Automatic Polarity Reversal function. If SI is HIGH at the rising edge of RST,
Automatic Polarity Reversal is disabled. If SI is LOW at
the rising edge of RST, Automatic Polarity Reversal is
enabled.
SO
Serial Out
Output
The SO pin is used as a control command serial output
port. Responses to control commands are clocked out
on this pin synchronous to the SCLK input.
LED Interface
LDA0-4, LDB0-4
LED Drivers
Output, Open Drain
LDA0-4 and LDB0-4 drive LED Bank A and LED Bank B,
respectively. LDA0 and LDB0 indicate the status of the
AUI port; LDA1-4 and LDB1-4 indicate the status of the
four TP ports. The port attributes monitored by LDA0-4
and LDB0-4 are programmed by three pins, LDC0-2.
LDGA
Global LED Driver, Bank A
Output, Open Drain
LDGA is the Global LED driver for LED Bank A. The
signal represents global CRS or COL conditions. In a
RST
Reset
Input, Active LOW
When RST is LOW, the eIMR device resets to its default
state. On the rising (trailing) edge of RST, the eIMR also
monitors the state of the SELI0-1, SI, and AMODE pins,
to configure the operating mode of the device. In multiple eIMR systems, the falling (leading) edge of the RST
signal must be synchronized to CLK.
CLK
Master Clock In
Input
This pin is a 20-MHz clock input.
REXT
External Reference
Input
This pin is used for an internal current reference. It must
be tied to VDD via a 13-kΩ resistor with 1% tolerance.
VDD
Power
Power Pin
This pin supplies power to the device.
Am79C984A
13
P R E L I M I N A R Y
AVSS
Analog Ground
Ground Pin
DVSS
Digital Ground
Ground Pin
This pin is the ground reference for the differential
receivers and drivers.
This pin is the ground reference for all the digital logic
in the eIMR device.
14
Am79C984A
P R E L I M I N A R Y
FUNCTIONAL DESCRIPTION
The Am79C984A eIMR device is a single-chip implementation of an IEEE 802.3/Ethernet repeater (or hub).
It is offered with four integral 10BASE-T ports plus one
RAUI port comprising the basic repeater. The eIMR device is also expandable, enabling the implementation of
high port count repeaters based on several eIMR devices.
The eIMR chip complies with the full set of repeater
basic functions as defined in Section 9 of ISO 8802.3
(ANSI/IEEE 802.3c). The basic repeaters functions are
summarized in the paragraphs below.
Basic Repeater Functions
The Am79C984A chip implements the basic repeater
functions as defined by Section 9.5 of the ANSI/IEEE
802.3 specification.
Repeater Function
If any single network port senses the start of a valid
packet on its receive lines, the eIMR device will retransmit the received data to all other enabled network ports
(except when contention exists among any of the ports
or when the receive port is partitioned). To allow multiple eIMR device configurations, the data will also be repeated on the expansion bus data line (DAT).
Signal Regeneration
When retransmitting a packet, the eIMR device ensures that the outgoing packet complies with the IEEE
802.3 specification in terms of preamble structure and
timing characteristics. Specifically, data packets repeated by the eIMR device will contain a minimum of 56
preamble bits before the Start-of-Frame Delimiter. In
addition, the eIMR restores the voltage amplitude of
the repeated waveform to levels specified in the IEEE
802.3 specification. Finally, the eIMR device restores
signal symmetry to repeated data packets, removing jitter and distortion caused by the network cabling. Jitter
present at the output of the AUI port will be better than
0.5 ns; jitter at the TP outputs will be better than 1.5 ns.
The start-of-packet propagation delay for a repeater set
is the time delay between the first edge transition of a
data packet on its input port to the first edge transition
of the repeated packet on its output ports. The start-ofpacket propagation delay for the eIMR is within the
specification given in Section 9.5.5.1 of the IEEE 802.3
standard.
Jabber Lockup Protection
The eIMR device implements a built-in jabber protection scheme to ensure that the network is not disabled
by the transmission of excessively long data packets.
This protection scheme causes the eIMR device to interrupt transmission for 96 bit-times if the device has
been transmitting continuously for more than 65,536 bit
times. This is referred to as MAU Jabber Lockup Protection (MJLP). The MJLP status for the eIMR device
can be read through the Control Port, using the Get
MJLP Status command.
Collision Handling
The eIMR device will detect and respond to collision
conditions as specified in the IEEE 802.3 specification.
Repeater configurations consisting of multiple eIMR
devices also comply with the IEEE 802.3 specification,
using status signals provided by the expansion bus. In
particular, a repeater based on one or more eIMR devices will handle the transmit collision and one-port-left
collision conditions correctly, as specified in Section 9
of the IEEE 802.3 specification.
Fragment Extension
If the total packet length received is less than 96 bits,
including preamble, the eIMR device will extend the repeated packet length to 96 bits by appending a Jam sequence to the original fragment.
Auto Partitioning/Reconnection
Any of the TP ports or the AUI port can be partitioned if
the duration or frequency of collisions becomes excessive. The eIMR device will continue to transmit data
packets to a partitioned port, but will not respond, as a
repeater, to activity on the partitioned port’s receiver.
The eIMR device will monitor the port and reconnect it
once certain criteria are met. The criteria for reconnection are specified by the IEEE 802.3 standard. In addition to the standard reconnection algorithm, the eIMR
device implements an alternative reconnection algorithm, which provides a more robust partitioning function for the TP ports and/or AUI port. The eIMR device
partitions each TP port and the AUI port separately and
independently of other network ports.
The eIMR device will partition an enabled network port
if either of the following conditions occurs at that port:
a. A collision condition exists continuously for more
than 2048 bit times. (AUI port—SQE signal active;
TP port—simultaneous transmit and receive).
b. A collision condition occurs during each of 32 consecutive attempts to transmit to that port.
In the AUI port, a collision condition is indicated by an
active SQE signal. In a TP port, a collision condition is
indicated when the port is simultaneously attempting to
transmit and receive.
Once a network port is partitioned, the eIMR device will
reconnect that port, according to the selected reconnection algorithm, as follows:
a. Standard reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted or
received by the partitioned port without a collision.
Am79C984A
15
P R E L I M I N A R Y
b. Alternative reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted by
the partitioned port without a collision.
A partitioned port can also be reconnected by disabling
and re-enabling the port.
All TP ports use the same reconnection algorithm; either they must all use the standard algorithm, or they
must all use the alternative reconnection algorithm.
However, the reconnection algorithm for the AUI port is
programmed independently from that of the TP ports.
Detailed Functions
power is maintained to the eIMR device, a reset duration of only 4 µs is required. This allows the eIMR device to reset its internal logic. During reset, the eIMR
registers are set to their default values. Also during reset, the eIMR device sets the output signals to their inactive state; that is, all analog outputs are placed in
their idle state, no bidirectional signals are driven, all
active-HIGH signals are driven LOW and all activeLOW signals are driven HIGH. In a multiple eIMR system, the reset signal must be synchronized to CLK.
See Figure 10 in the Systems Applications section.
The eIMR device also monitors the state of the SELI0-1,
SI, and AMODE pins on the rising (trailing) edge of
RST to configure the operating mode of the device.
Reset
The eIMR device enters the reset state when the reset
(RST) pin is driven LOW. After the initial application of
power, the RST pin must be held LOW for a minimum
of 150 µs. If the RST pin is subsequently asserted while
Table 1 summarizes the state of the eIMR chip following
reset.
Table 1. eIMR States after Reset
Function
State after Reset
Active-LOW Outputs
HIGH
No
Active-HIGH Outputs
LOW
No
SO Output
HIGH
DAT, JAM
HIGH IMPEDANCE
Transmitters (TP and AUI)
IDLE
Receivers (TP and AUI)
ENABLED
AUI Partitioning/Reconnection Algorithm
STANDARD ALGORITHM
N/A
TP Partitioning/Reconnection Algorithm
STANDARD ALGORITHM
N/A
Link Test Functions for TP Ports
ENABLED, TP PORTS IN LINK FAIL
N/A
Automatic Receiver Polarity Reversal Function
DISABLED IF SI PIN IS HIGH
ENABLED IF SI PIN IS LOW
N/A
No
Terminated
TP Port Interface
The AUI Port is fully compatible with the IEEE 802.3,
Section 7 requirement for an AUI port. It has the signals
associated with an AUI port: DO, DI, and CI.
Twisted Pair Transmitters
The eIMR device can be connected directly to a MAC
through the AUI port. This requires that the AUI port be
configured for reverse operation. Refer to the Systems
Applications section for more details.
16
Either
No
AUI Port
The AUI port has two modes of operation: normal and
reverse. When configured for normal operation, the
functionality is that of an AUI port on a MAC (CI is an
input). When configured for reverse operation, the functionality is that of an AUI on a MAU (CI is an output).
The mode of the AUI port is set during the trailing (rising) edge of the reset pulse, by the state of the AMODE
pin. A LOW sets the AUI port to its normal mode (CI Input) and a HIGH sets the AUI port to its reversed (CI
Output) mode.
Pull Up/Pull Down
TXD is a differential twisted-pair driver. When properly
terminated, TXD will meet the electrical requirements
for 10BASE-T transmitters as specified in IEEE 802.3,
Section 14.3.1.2.
The TXD signal is filtered on the chip to reduce harmonic content per IEEE 802.3, Section 14.3.2.1
(10BASE-T). Since filtering is performed in silicon, TXD
can connect directly to a standard transformer, thereby,
eliminating the need for external filtering modules.
Proper termination is shown in the Systems Applications section.
Twisted Pair Receivers
RXD is a differential twisted-pair receiver. When properly terminated, RXD will meet the electrical requirements for 10BASE-T receivers as specified in IEEE
802.3, Section 14.3.1.3. The receivers do not require
Am79C984A
P R E L I M I N A R Y
external filter modules. Proper termination is shown in
the Systems Applications section.
The receiver’s threshold voltage can be programmed to
an extended-distance mode. In this mode, the differential receiver’s threshold is reduced to allow a longer
cable than the 100 meters specified in the IEEE 802.3
standard. For programming details, refer to the Control
Commands section.
Link Test
The integrated TP ports implement the Link Test function, as specified in the IEEE 802.3 10BASE-T standard. The eIMR device will transmit Link Test pulses to
any TP port after that port’s transmitter has been inactive for more than 8 ms to 17 ms. Conversely, if a TP
port does not receive any data packets or Link Test
pulses for more than 65 ms to 132 ms and the Link Test
function is enabled for that port, then that port will enter
the link-fail state. The eIMR device will disable a port in
link-fail state (i.e., disable repeater transmit and receive
functions) until it receives either four consecutive Link
Test pulses or a data packet.
The Link Test function can be disabled via the eIMR
control port on a port-by-port basis, to allow the eIMR
device to operate with pre-10BASE-T networks that do
not implement the Link Test function. When the Link
Test function is disabled, the eIMR device will not allow
the TP port to enter link-fail state, even if no Link Test
pulses or data packets are being received. Note, however, that the eIMR device will always transmit Link Test
pulses to all TP ports, regardless of whether or not the
port is enabled, partitioned, in link-fail state, or has its
Link Test function disabled. Separate control commands exist for enabling and disabling the transmission
of Link Test pulses on a port-by-port basis.
Polarity Reversal
The TP ports can be programmed to receive data if a
wiring error results in a data packet being received at a
TP port with reversed polarity. This function will be enabled upon reception of a negative End Transmit Delimiter (ETD) or negative pulses and allows subsequent
packets to be received with the correct polarity. The polarity-reversal function is executed once following reset
or link-fail and can be programmed via the control port
to be enabled or disabled on a port-by-port basis. The
function may be enabled or disabled, following a reset,
depending on the level of the SI signal on the rising
edge of the RST pulse.
Visual Status Monitoring (LED) Support
The eIMR status port can be connected to LEDs to facilitate the visual monitoring of repeater port status.
The status port has twelve output signals, LDA0-4, and
LDB0-4, LDGA, and LDGB. LDA0-4 and LDB0-4 represent the four TP ports and AUI port. LDGA and LDGB
are global indicators. Attributes that may be monitored
are Carrier Sense (CRS), Collision (COL), Partition
(PAR), Link Status (LINK), Loopback (LB), Port Disabled (DIS), and Jabber (JAB). Three control bits,
LDC0-2, select the particular attributes to be displayed
on the LEDs. Table 2 shows how the programming
combinations for LDC0-2 control the attributes that will
be monitored.
Each LED drive pin (LDGA, LDGB, LDA0-4, and LDB0-4)
has two states: Off and LOW. When none of the selected attributes are true, the driver is off and the diode
is unlit. When an attribute is true, the driver is LOW, and
the corresponding LEDs in Bank A or Bank B will be lit.
Some of the settings (LDC2 = 1) include a blink function. This allows two attributes to be selected for a given
state on the pin. As an example when LDC0-2 = 110,
the LDA outputs relating to TP ports will be solidly lit
when there is a link established at that port. However,
whenever there is activity on a port, the corresponding
LDA pin will switch on (LOW) and off at a period of 130
ms. Note that a partition on that port will also cause the
pin to go LOW.
On LDC settings that have two attributes for a state on
a pin (blink or solid-on), the attribute causing the output
to blink has priority. (Those attributes are shown in
Table 2 with a blink period specified next to it.) If an attribute has no blink period specified, the LED indicates
the attribute by being solidly lit.
The LEDs can also be controlled via the control port.
The Enable Software Override commands turn the
LEDs on regardless of the attributes selected for display through the LDC setting. Enable Software Override of Bank A LEDs causes the LDA0-4 and LDGA pins
to be driven LOW, and Enable Software Override of
Bank B LEDs causes the LDB0-4 and LDGB pins to be
driven LOW. The blink rate is set by the Software Override LED Blink Rate command. The periods are off,
512 ms, 1560 ms, or solid on.
Am79C984A
17
P R E L I M I N A R Y
Table 2. LED Attribute-Monitoring Program Options
LED Control
LDC2
LDC1
LDC0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Global LEDs
LDGA
LDGB
CRS
COL
CRS
COL
1
0
1
CRS 260-ms blk
COL
1
1
0
CRS
1
1
1
CRS
COL 260-ms blk
JAB
COL
COL
TP LEDs
LDA1-4
LDB1-4
LINK (Note 2)
PAR
LINK
CRS
Reserved (Note 5)
Reserved (Note 5)
LINK
PAR
CRS 260-ms blk COL 260-ms blk
LINK (Note 3)
PAR (Note 3)
CRS 512-ms blk
LINK
PAR or DIS
CRS 130-ms blk
LINK (Note 4)
PAR 1.56-s blk
COL (Note 4)
AUI LEDs
LDA0
LB
LB
LDB0
PAR
CRS
PAR
COL 260-ms blk
PAR (Note 3)
CRS 260-ms blk
(Note 3)
CRS 512-ms blk
PAR or DIS
CRS 130-ms blk
(Note 4)
PAR 1.56-s blk
PAR (Note 4)
Notes:
1. CRS = Carrier Sense, COL = Collision, JAB = Jabber, LINK = Link, LB = Loop Back, PAR = Partition, DIS = Port Disabled,
blk = Blink (Number = period of Blink).
2. For the LDC0-2 setting of 000: If the port is partitioned, the LINK LED is off.
3. All LEDs blink 16 times at 260 ms per blink after reset.
4. All LEDs are on for approximately 4 seconds after reset.
5. LDC0-2 = ‘010’ and ‘011’ are undefined.
LED software override is executed in two stages, by
first issuing the blink rate (Software Override of LED
Blink Rate) and then issuing the command to enable
the particular port LEDs (Enable Software Override of
Bank A/B LEDs). All port combinations selected for
software override control will reference the blink rate
last issued by the Software Override of the LED Blink
Rate command.
Figure 1 shows the recommended connection of LEDs.
When LDA0-4, LDB0-4, LDGA, or LDGB are LOW, the
LED lights.
VDD
eIMR
LED
Interface
LDA0-4, LDB0-4, LDGA, and LDGB are open drain output drivers that sink 12 mA of current to turn on the
LEDs. In a multiple eIMR configuration, the outputs
from the global LED drivers (LDGA and LDGB) of each
chip can be tied together to drive a single pair of global
status LEDs.
CRS and COL are extended to make it easier for visual
recognition; that is, they will remain active for some
time even if the corresponding condition has expired.
Once carrier sense is active, CRS will remain active for
a minimum of 4 ms. Once a collision is detected, COL
is active for at least 4 ms. The exception to this rule is
for selection LDC0-2 = 111. For this selection, COL is
stretched to 100 µs.
When LDC0-2 = 000 or LDC0-2 = 001, the loopback attribute (LB) for the AUI port is displayed on LDA0. LB is
true when DO on the MAU is successfully looped back
to DI on the AUI port. LB is false (off) if a loopback error
is detected, or if the AUI port is disabled or in the reverse mode. Transmit carrier sense is sampled at the
end of packet to determine the state of LB. The state of
LB remains latched until carrier sense is sampled again
for the next packet. The default/power-up state for LB is
false (off).
18
R
LDA[4:0]
LDB[4:0]
LDGA
LDGB
Typical
20650B-6
20650A-6
Figure 1. Visual Monitoring Application—Direct
LED Drive
Network Activity Display
The eIMR status port can drive up to eight LEDs to indicate the network-utilization level as a percentage of
bandwidth. The status port uses eight dedicated outputs (ACT0-7) to drive a series of LEDs. The number of
LEDs in the series that will be lit increases as the
amount of network activity increases. ACT0 represents
the lowest level of activity; ACT7 represents the highest. ACT0-7 are open-drain outputs that typically sink
12 mA of current to turn on the LEDs. See Figure 2.
Am79C984A
P R E L I M I N A R Y
VDD
eIMR
LED
Interface
ACT[0]
ACT[1]
ACT[2]
ACT[3]
ACT[4]
ACT[5]
ACT[6]
ACT[7]
20650A-7
Figure 2. Network Activity Display
Table 3 shows ACT0-7 as a function of the percentage
of network utilization. The table uses a scale that is
more sensitive at low utilization levels. 100% utilization
represents the maximum number of events that could
occur in a given window of time.
Table 3. Network Utilization
Number of LEDs
Lit by ACT7-0
8
7
6
5
4
3
2
1
The update rate and corresponding internal sampling
window for ACT[7:0] is 250 ms. During this sampling
window, a counter is used to count the number of times
repeater transmit activity is TRUE. The counter uses a
free-running clock which has the granularity to detect
the minimum packet size of 96 bit times.
Figure 3 shows the timing relationship between the
sampling window, counting clock, and transmit activity.
Percentage Utilization
>80%
>64%
>32%
>16%
>8%
>4%
>2%
>1%
latch data;
update display;
clear counter
counter is active
next counting cycle
Sampling
Window
Counting
Clock
Xmit
Activity
20650B-8
Figure 3. Activity Sampling
Am79C984A
19
P R E L I M I N A R Y
Expansion Bus Interface
The eIMR device expansion bus allows multiple eIMR
devices to be interconnected.
The expansion bus supports two modes of operation:
internal arbitration mode and IMR+ mode. The internal
arbitration mode uses a modified daisy-chain scheme
to eliminate the need for any external arbitration circuitry. The IMR+ mode maintains the full functionality of
the IMR+ (Am79C981) expansion bus and benefits
from minimum delays. In this mode, the eIMR device
requires external circuitry to handle arbitration for control of the bus.
The eIMR arbitration mode is determined at reset. This
occurs on the trailing edge of RST according to the
state of SELI0-1, as illustrated in Figure 4.
Internal Arbitration Mode
The internal arbitration mode uses a daisy-chain (cascade) configuration. SELI0-1 are arbitration inputs and
SELO is the arbitration output. SELO goes LOW when
there is activity on one or more of the eIMR ports, or a
SELI input is LOW. The SEL lines are connected as
shown in Figure 5. This technique allows activity indication to propagate down the chain to the end device. All
unused SELI inputs must be tied to VDD.
ACK and COL are global activity I/O pins. When the
eIMR device senses activity, it drives ACK LOW.
DAT and JAM are synchronized to CLK. DAT is the repetition of data from any connected port (either TP or
AUI port) encoded in NRZ format. JAM is an internal
collision indicator. If JAM is HIGH, the active eIMR device has detected an internal collision across one or
more of its ports. When this occurs, the DAT signal distinguishes between single-port collisions and multiport
collisions. DAT = 1 indicates a single port collision;
DAT = 0 indicates a multiport collision.
The drive capabilities of the I/O signals on the expansion bus (DAT, JAM, ACK, and COL) are sufficient to
allow seven eIMR devices to be connected together
without the use of external transceivers or buffers.
The maximum number of eIMR devices that can be
daisy chained is limited by the propagation delay of the
eIMR devices. In practice, the depth of the cascade is
limited to three eIMR devices, thus allowing a maximum of seven eIMR devices connected together via
this expansion bus as shown in Figure 5.
The active device will not drive the data line, DAT,
until one bit time (100 ns) after SELO goes LOW. This
is to avoid a situation where two devices drive DAT
simultaneously.
IMR+ Mode
In IMR+ mode, the expansion bus requires an external
arbiter. The arbiter allows only one eIMR device to control the expansion bus. If more than one device attempts to take control, the arbiter terminates all access
and signals a collision condition.
.
RST
SELI_0
ACK and COL are mutually exclusive. If an eIMR driving ACK senses COL LOW, the device will deassert
ACK.
Mode Selection
Arbitration
Mode
SELI_1
SELI_0
X
1
Internal
X
0
IMR+
20650B-9
Figure 4. Expansion Bus Mode Selection
An eIMR device drives COL LOW when it senses more
than one device is active; that is, if the device has an
active port AND a SELI input is LOW, OR both SELI inputs are LOW. In Boolean notation, the formula for COL
is:
COL = (Active port & (SELI1 + SELI0))+
(SELI1 & SELI0)
In IMR+ mode, DAT and JAM retain the same functionality as in internal arbitration mode, but ACK and COL
are inputs to the eIMR device, driven by the external arbiter. The arbiter should drive ACK LOW when exactly
one eIMR device is active. It should drive COL when
more than one eIMR device is active. SELO is an output from the eIMR device. It indicates that the eIMR device has an active port and is requesting access to the
bus.
When ACK is HIGH, DAT and JAM are in the highimpedance state. DAT and JAM go active when ACK
goes LOW. Refer to the Systems Applications section
(Figure 13) for the configuration of IMR+ mode of
operation.
Note: The IMR+ mode is recommended when arbitrating
between multiple boards.
.
where
& represents the Boolean AND operation
+ represents the Boolean OR operation
20
Am79C984A
P R E L I M I N A R Y
VDD
1kΩ
SELI_0
SELO
SELI_0
COL
SELI_0
SELO
COL
ACK
SELI_1
DAT
JAM
ACK
SELO
SELI_0
COL
SELI_0
COL
SELO
SELI_0
COL
SELI_0
SELO
COL
ACK
SELI_1
DAT
JAM
ACK
SELI_1
DAT
JAM
SELO
SELI_1
DAT
JAM
ACK
DAT
JAM
SELI_1
ACK
DAT
JAM
SELI_1
SELO
COL
ACK
DAT
JAM
SELI_1
20650A-10
20650B-10
Figure 5. Internal Arbitration—eIMR Devices in Cascade
Control Functions
The eIMR device receives control commands in the
form of byte-length data on the serial input pin, SI. If the
eIMR device is expected to provide data in response to
the command, it will send byte-length data to the serialoutput pin, SO. Both the input and output data streams
are clocked with the rising edge of the SCLK signal.
The byte-length data is in RS232 serial-data format;
that is, one start bit followed by eight data bits. The externally generated clock at the SCLK pin may be either
a free-running clock synchronized to the input bit patterns, or a series of individual transitions meeting the
setup-and-hold times with respect to the input bit pattern. If the latter method is used, 20 SCLK clock transitions are required for control commands that produce
SO data, and 14 SCLK clock transitions are required
for control commands that do not produce SO data.
Am79C984A
21
P R E L I M I N A R Y
Command/Response Timing
Figure 6 shows the command/response timing. At the
end of a GET command, the eIMR device waits two
SCLK cycles and then transmits the response on SO.
.
SCLK
SI
ST D0 D1 D2 D3 D4 D5 D6 D7
SO
ST D0 D1 D2 D3 D4 D5 D6 D7
20650A-11
20650B-11
Figure 6. Control Get Command/Response
Control Commands
The following section details the operation of each control commands available in the eIMR device. In all
cases, the individual bits in each command are shown
with the most-significant bit (bit 7) on the left and the
least-significant bit (bit 0) on the right. Table 4 and Table
5 show a summary of default states and a summary of
control commands, respectively.
Note: Data is transmitted and received on the serial
data lines least-significant bit first and most-significant
bit last.
22
Table 4. Summary of Default States after Reset
eIMR Programmable Option—S
AUI Partitioning Algorithm
TP Partitioning Algorithm
AUI/TP Port
Link Test
Link Pulse
Automatic Receiver Polarity
Reversal
Extended Distance Mode
Blink Rate
Software Override of LEDs
Am79C984A
Off
Normal
Normal
Enabled
Enabled
Enabled
State of SI at reset
Disabled
Off
Disabled
P R E L I M I N A R Y
Table 5. Control Port Command Summary
SI Data
Commands
Set (Write Commands)
eIMR Chip Programmable Options
Alternate AUI Partitioning Algorithm
Alternate TP Partitioning Algorithm
AUI Port Disable
AUI Port Enable
TP Port Disable
TP Port Enable
Disable Link Test Function (per TP port)
Enable Link Test Function (per TP port)
Disable Link Pulse (per TP port)
Enable Link Pulse (per TP port)
Disable Automatic Receiver Polarity Reversal
(per TP port)
Enable Automatic Receiver Polarity Reversal
(per TP port)
Disable Receiver Extended Distance Mode
(per TP port)
Enable Receiver Extended Distance Mode
(per TP port)
Disable Software Override of LEDs
(per Port - AUI & TP)
Enable Software Override of Bank A LEDs
(per Port - AUI & TP, Global)
Enable Software Override of Bank B LEDs
(per Port - AUI & TP, Global)
Software Override LED Blink Rate
Get (Read Commands)
AUI Port Status (B, S, and L Cleared)
AUI Port Status (B Cleared)
AUI Port Status (S, L, Cleared)
AUI Port status (None Cleared)
TP Port Partitioning Status
Bit Rate Error Status of TP Ports
Link Test Status of TP Ports
Receive Polarity Status of TP Ports
MJLP Status
Version
SO Data
0000 10S0
0001 1111
0001 0000
0010 1111
0011 1111
0010 00##
0011 00##
0100 00##
0101 00##
0100 10##
0101 10##
0110 00##
0111 00##
0110 10##
0111 10##
1001 ####
1011 ####
1100 ####
1110 1###
1000 1111
1000 1101
1000 1011
1000 1001
1000 0000
1010 0000
1101 0000
1110 0000
1111 0000
1111 1111
Am79C984A
PBSL 0000
PBSL 0000
PBSL 0000
PBSL 0000
0000 C3..C0
0000 E3..E0
0000 L3..L0
0000 P3..P0
M000 0000
0000 0011
23
P R E L I M I N A R Y
SET (Write Commands)
AUI Port Enable
Chip Programmable Option
SI
SO Data
SI Data
SO Data
0000 10S0
None
This command enables the AUI port.
The eIMR chip programmable option can be enabled
(or disabled) by setting (or resetting) the S bit in the
command string.
S
AUI SQE Test Mask
Setting this bit allows the eIMR chip to ignore activity on
the CI signal pair, during the SQE test window, following
a transmission on the AUI port. Enabling this function
does not prevent the reporting of this condition by the
eIMR device. The two functions operate independently.
The SQE Test Window, as defined in IEEE 802.3 (Section 7.2.2.2.4) is from 6 bit times to 34 bit times (0.6 µs
to 3.4 µs). This includes the delay introduced by a 50meter AUI. CI activity that occurs outside this window is
not ignored and is treated as a true collision.
Alternate AUI Partitioning Algorithm
SI Data
SO Data
SI Data
SO Data
0010 00##
None
This command disables the TP port designated by the
two least-significant bits of the command byte. Subsequently, the eIMR chip will ignore all inputs to the designated port and will not transmit a DAT or JAM pattern
on that port. Disabling the TP port also sets the partitioning state machine of that port to the idle state. Therefore, a partitioned port can be reconnected by first
disabling the port and then enabling it.
TP Port Enable
SI Data
SO Data
0011 00##
None
Disable Link Test Function (Per TP port)
Alternate TP Partitioning Algorithm
0001 0000
None
SI Data
SO Data
0100 00##
None
This command disables the Link Test function of the TP
port designated by the two least-significant bits of the
command data. As a consequence of this, the port will
no longer be disconnected if it fails the Link Test. If a
port has the Link Test disabled, reading the Link Test
Status indicates a ‘Link Pass’.
Enable Link Test Function (Per TP port)
Invoking this command sets the partition/reconnection
scheme for the TP ports to the alternate (transmit-only)
reconnection algorithm. To return the TP ports to the
standard (transmit or receive) reconnection algorithm,
it is necessary to reset the eIMR device. The standard
partitioning algorithm is selected on reset.
AUI Port Disable
SI
SO Data
TP Port Disable
This command enables the TP port designated by the
two least-significant bits of the command byte.
0001 1111
None
Invoking this command sets the partition/reconnection
scheme for the AUI port to the alternate (transmit-only)
reconnection algorithm. To return the AUI port to the
standard (transmit or receive) reconnection algorithm,
it is necessary to reset the eIMR device. The standard
partitioning algorithm is selected on reset.
SI Data
SO Data
0011 1111
None
SI Data
SO Data
0101 00##
None
This command enables the Link Test function of the TP
port designated by the two least-significant bits of the
command data. As a consequence of this, the port is
disconnected if it fails the Link Test.
Disable Link Pulse (Per TP Port)
0010 1111
None
This command disables the AUI port. Subsequently, the
eIMR chip will ignore all inputs to this port and will not
transmit a DAT or JAM pattern on the AUI port. Disabling
the AUI port also sets the partitioning state machine of
the AUI port to the idle state. Therefore, a partitioned
port can be reconnected by first disabling the AUI port
and then enabling the AUI port.
SI Data
SO Data
0100 10##
None
This command disables the transmission of the Link
pulse on the TP port designated by the two leastsignificant bits of the command byte.
Enable Link Pulse (Per TP Port)
SI Data
SO Data
0101 10##
None
This command enables the transmission of the Link
pulse on the TP port designated by the two leastsignificant bits of the command byte.
24
Am79C984A
P R E L I M I N A R Y
Disable Automatic Receiver Polarity Reversal (Per TP
Port)
Disable Software Override of LEDs
(Per Port - AUI and TP, Global)
SI Data
SO Data
SI Data
SO Data
0110 00##
None
This command disables the Automatic Receiver Polarity
Reversal function for the TP port designated by the two
least-significant bits in the command byte. If this function is disabled on a TP port receiving with reversed
polarity (due to a wiring error), the TP port will fail the
Link Test due to the incorrect polarity of the received
Link pulses.
This command disables Software Override of the Port
LEDs.
Individual LEDs and combinations of LEDs can be
selected via the lower four bits of the command byte as
follows:
####
0000-0011
0100-0111
1000
1001
1010
1011
1100
1101
1110
1111
The state of Automatic Polarity Reversal function is set
by SI on reset. If SI is HIGH at the rising edge of RST,
the eIMR device disables Automatic Polarity Reversal.
If SI is LOW at the rising edge of RST, the eIMR device
enables Automatic Polarity Reversal.
Enable Automatic Receiver Polarity Reversal (Per TP
Port)
SI Data
SO Data
0111 00##
None
This command enables the Automatic Receiver Polarity
Reversal function for the TP port designated by the two
least-significant bits in the command byte. If enabled in
a TP port, the eIMR chip will automatically invert the
polarity of that port’s receiver circuitry if the TP port is
detected as having reversed polarity (due to wiring error). After reversing the receiver polarity, the TP port
could then receive subsequent (reverse polarity)
packets correctly.
Disable Receiver Extended Distance Mode (Per TP
Port)
SI Data
SO Data
Enable Software Override of Bank A LEDs (Per Port AUI and TP, Global)
SI Data
SO Data
1011 ####
None
This command forces the LEDs in Bank A to blink. Individual LEDs and combinations of LEDs can be selected via the lower four bits of the command byte as follows:
####
0000-0011
0100-0111
1000
1001
1010
1011
1100
1101
1110
1111
0110 10##
None
Enable Receiver Extended Distance Mode (Per TP Port)
0111 10##
None
This command modifies the RXD circuit of the transceiver for the TP port driver designated by the two leastsignificant bits of the command data. The RXD squelchthreshold value is lowered to accommodate signal attenuation associated with lines longer than 100 meters.
At reset, Receiver Extended Distance Mode is disabled
and the RXD circuit defaults to normal squelch-threshold values.
Port(s) affected
TP0 - TP3
Reserved
AUI port
Reserved
Reserved
All TP ports
All ports
Global
Reserved
Reserved
Following command execution, the attributes displayed
on the LEDs will be determined by LDC0-2. Software
Override of LEDs is disabled after reset.
This command disables the Receiver Extended
Distance Mode and restores the RXD circuit of the transceiver to normal squelch levels for the TP port driver
designated by the two least-significant bits of the command data.
SI Data
SO Data
1001 ####
None
Port(s) affected
TP0 - TP3
Reserved
AUI port
Reserved
Reserved
All TP ports
All ports
Global
Reserved
Reserved
The designated LED driver(s) will switch between LOW
and ‘off’ at the rate set by the Software Override Blink
Rate command. Enable Software Override of Bank A
LEDs references the blink rate last issued and overrides
any other attribute specified by LDC0-2. Software Override of LEDs is disabled after reset.
Am79C984A
25
P R E L I M I N A R Y
Enable Software Override of Bank B LEDs (Per Port AUI and TP, Global)
SI Data
SO Data
1100 ####
None
This command forces the LEDs in Bank B to blink. Individual LEDs and combinations of LEDs can be selected via the lower four bits of the command byte as follows:
####
0000-0011
0100-0111
1000
1001
1010
1011
1100
1101
1110
1111
Port(s) affected
TP0 - TP3
Reserved
AUI port
Reserved
Reserved
All TP ports
All ports
Global
Reserved
Reserved
This bit is set to ‘1’ if the SQE test error is detected by
the eIMR chip. The bit is cleared when the status is read.
1110 1###
None
Alternate 1: B is not cleared, S and L are Cleared
SI Data
SO Data
1000 1011
PBSL 0000
Alternate 2: S and L are not cleared, B is Cleared
SI Data
SO Data
1000 1101
PBSL 0000
Alternate 3: None of S, B, and L are Cleared
SI Data
SO Data
1000 1001
PBSL 0000
TP Port Partitioning Status
SI Data
SO Data
Blink Period
Off
512 ms
1560 ms
Solid On
1000 0000
0000 P3..P0
Pn = 0
TP Port Partitioned
TP port Connected
Pn = 1
where n is a port number in the range 0–3.
The response to this command gives the partitioning
status of all four TP ports. If a port is disabled, reading
its partitioning status will indicate that it is connected.
Bit Rate Error Status of TP Ports
SI Data
SO Data
GET (Read Commands)
AUI Port(s) Status
1010 0000
0000 E3..E0
En = 0
No Error
En = 1
FIFO Overflow
where n is a port number in the range 0–3.
1000 1111
PBSL 0000
The combined AUI status of the eIMR device allows a
single instruction to be used to monitor the AUI port.
The four local status bits are:
Partitioning Status
The response to this command gives the bit-rate-overflow or underflow (data rate mismatch) condition of all
the TP ports. A 1 indicates that the FIFO has overflowed
or underflowed due to the amount of data received by
the corresponding port.
This bit is ‘0’ if the AUI port is partitioned and ‘1’ if the
AUI port is connected.
26
Loopback Error
There are three further variations of the AUI Port Status
Command allowing selective clearing of a combination
of B,S, and L bits. These are the following:
These settings apply to the blink rate for both Bank A
and Bank B. This command must precede the Enable
Software Override of Bank A/B LEDs command. All LED
combinations selected for Software Override will reference the blink rate last issued.
P
SQE Test Status
Alternate AUI Port(s) Status
This command sets the blink period of the LEDs with
Software Override enabled. The duty cycle is 50%. This
command defaults to ‘off’ at reset.
SI Data
SO Data
S
The MAU attached to the AUI port is required to loopback data transmitted to DO onto the DI circuit. If the
loopback carrier is not detected by the eIMR device, this
bit is set to ‘1’. This bit is cleared when the status is read.
Software Override of LED Blink Rate
Setting
1110 1000
1110 1001
1110 1010
1110 1011
Bit Rate Error
This bit is set to ‘1’ if there is an instance of FIFO overflow
or underflow. The bit is cleared when the eIMR device
is read.
L
The designated LED driver(s) will switch between LOW
and ‘off’ at the rate set by the Software Override of LED
Blink Rate command. Enable Software Override of
Bank B LEDs references the blink rate last issued and
overrides any other attribute specified by LDC0-2. Software Override of LEDs is disabled after reset.
SI Data
SO Data
B
Am79C984A
P R E L I M I N A R Y
Link Test Status of TP ports
SI Data
SO Data
SYSTEMS APPLICATIONS
eIMR to TP Port Connection
1101 0000
0000 L3..L0
Ln = 0
TP Port n in Link Test Failed
Ln = 1
TP port n in Link Test Passed
where n is a port number in the range 0–3.
The response to this command gives the Link Test status of all the TP ports. A disabled port continues to report
Link Test status. Re-enabling the port causes the port
to be placed in the Link Test Fail state.
Receive Polarity Status of TP Ports
SI Data
SO Data
1110 0000
0000 P3......P0
Pn = 0
TP Port n Polarity Correct
Pn = 1
TP port n Polarity Reversed
where n is a port number in the range 0–3.
The response to this command gives the Received Polarity status of all the TP ports. If the polarity is detected
as reversed for a TP port, then the eIMR device will set
the appropriate bit in this command’s result only if the
Polarity Reversal Function is enabled for that port.
The eIMR device provides a system solution to designing
non-managed multiport repeaters. The eIMR device connects directly to AC coupling modules for a 10BASE-T
hub. Figure 7 shows the simplified connection.
Twisted Pair Transmitters
TXD signals need to be properly terminated to meet the
electrical requirement for 10BASE-T transmitters. Proper termination is shown in Figure 8 which consists of a
110-Ω resistor and a 1:1 transformer. The load is a twistedpair cable that meets IEEE 802.3, Section 14.4 specifications. The cable is terminated at the opposite end by
100 Ω.
Twisted Pair Receivers
RXD signals need to be properly terminated to meet the
electrical requirements for 10BASE-T receivers. Proper
termination is shown in Figure 9. Note that the receivers
do not require external filter modules.
MJLP Status
SI Data
SO Data
1111 0000
M000 0000
Each eIMR device contains an independent MAU Jabber Lock Up Protection timer. The timer is designed to
inhibit the transmit function of the eIMR device if it has
been transmitting continuously for more than 65536 bit
times. This bit remains set and is only cleared when the
MJLP status is read using this command.
Version
SI Data
SO Data
1111 1111
0000 0011
The response to this command gives the version of the
eIMR device. 0011 was chosen to help distinguish the
eIMR device from the IMR (Am79C980) and the IMR+
(Am79C981) devices.
Am79C984A
27
P R E L I M I N A R Y
eIMR
TP Connector
TXD0+
TXD0–
110 Ω
RXD0+
RXD0–
100 Ω
1:1
1:1
TP Connector
TXD1+
TXD1–
110 Ω
RXD1+
RXD1–
100 Ω
1:1
1:1
TP Connector
TXD2+
TXD2–
110 Ω
RXD2+
RXD2–
100 Ω
1:1
1:1
TP Connector
RST
TXD3+
TXD3–
110 Ω
RXD3+
RXD3–
100 Ω
1:1
1:1
CLK
20650A-12
Figure 7. Simplified 10BASE-T Connection
1:1
TXD+
Twisted Pair
100Ω
110Ω
TXD-
20650A-13
20650B-13
Figure 8. TXD Termination
RXD+
1:1
Twisted Pair
100Ω
100Ω
RXD–
20650A-14
20650A-14
20650B-14
Figure 9. RXD Termination
28
Am79C984A
P R E L I M I N A R Y
MAC Interface
of the MAC and DO is connected to DI of the MAC,
because the reverse configuration only affects CI.
Where CI is an input in the normal mode, in the reverse
mode, CI is an output. Figure 10b shows the normal AUI
configuration for reference.
The eIMR device can be connected directly to a MAC
through the AUI port. This requires that the AUI port be
configured in the reverse mode and connected as
shown in Figure 10a. Notice that DI is connected to DO
Am79C940
eIMR
Am7996
DO+
DI+
DI+
DO–
DI–
DI–
40 Ω
DO+
DI–
DO–
DO–
40 Ω
CI+
CI+
CI–
CI–
CI–
0.1 µF
DO+
DO–
0.1 µF
40 Ω
1:1
CI+
CI–
40 Ω
40 Ω
39 – 150 Ω
0.1 µF
40 Ω
1:1
40 Ω
CI+
DI+
DI–
40 Ω
DO+
40 Ω
1:1
40 Ω
DI+
40 Ω
eIMR
0.1 µF
40 Ω
0.1 µF
–9 V
a) Reverse Mode (with MAC)
b) Normal Mode (with MAU)
20650B-15
20650A-16
Figure 10. AUI Port Interconnections
Internal Arbitration Mode Connection
IMR+ Mode External Arbitration
The internal arbitration mode uses a modified daisychain scheme to eliminate the need for any external
arbiter. In this mode, ACK and COL need to be pulled
up through a minimum resistance of 1 kΩ. The DAT and
JAM pins also need to be pulled down via a high value
resistor. Refer to Figure 11.
The IMR+ mode maintains the full functionality of AMD’s
IMR+ (Am79C981) device’s expansion bus. In this
mode, the eIMR device requires external circuitry to
handle arbitration for control of the bus. Figure 12 shows
the configuration for the IMR+ mode of operation.
Am79C984A
29
P R E L I M I N A R Y
VDD
eIMR
SELI_0
SELI_1
RST
CLK
COL
SELO
ACK
DAT
Q
P C
SELO
JAM
Q
COL
Q
P C
D
ACK
Q
DAT
D
JAM
74LS74
RST
eIMR
SELI_0
SELI_1
RST
CLK
(Note: In a multiple eIMR system, the reset
signal must be synchronized to CLK.)
VDD
20 MHz
OSC
~1 kΩ
eIMR
1 kΩ
VDD
~1 kΩ
COL
SELO
ACK
JAM
DAT
SELI_0
SELI_1
RST
CLK
20650B-16
Figure 11. eIMR Internal Arbitration Mode Connection
eIMR
eIMR
SELI_0
eIMR
SELI_0
SELO
SELI_0
SELO
SELO
SELI_1
SELI_1
SELI_1
DAT JAM ACK COL
DAT JAM ACK COL
DAT JAM ACK COL
1 kΩ
COL ACK SEL1 SEL2 SEL3
GCOL
Arbiter
20650B-17
Figure 12. IMR+ Mode External Arbitration
30
Am79C984A
P R E L I M I N A R Y
Visual Status Display
LDA/B[4:0] and LDGA/B provide visual status indicators
for the eIMR. LDA/B[4:0] displays Link, Carrier Sense,
Collision, and Partition information for the TP and AUI
ports. LDGA/B display global Carrier Sense, Collision,
and Jabber information.
In a multiple eIMR configuration, the global LED drivers
(LDGA/B) from each chip can be tied together to drive
a single pair of global status LEDs. The open drain output of these drivers facilitate this configuration. Refer to
Figure 13.
VDD
LDA[4:0]
LDB[4:0]
LDGA
LDGB
LDA[4:0]
LDB[4:0]
LDGA
LDGB
20650B-18
20650A-19
Figure 13. Visual Status Display Connection
Am79C984A
31
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . –65° C to +150° C
Ambient Temperature Under Bias . . . . 0° C to +70° C
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . . . . . 0° C to +70° C
Supply Voltage referenced to
Supply Voltages (VDD) . . . . . . . . . . . . . . . . . +5 V ±5%
AVSS or DVSS (AVDD, DVDD) . . . . . . . –0.3 V to +6.0 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect reliability. Programming conditions may
differ.
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Digital I/O
VIL
Input LOW Voltage
VSS = 0.0 V
–0.5
0.8
V
VIH
Input HIGH Voltage
VSS = 0.0 V
2.0
0.5 + VDD
V
VOL
Output LOW Voltage
IOL = 4.0 mA
–
0.4
V
VOH
Output HIGH Voltage
IOH = –0.4 mA
2.4
–
V
Input Leakage Current
VSS<VIN<VDD
–
10
µA
IILSTR
Input Leakage Current for STR pin
VSS<VIN<VDD
–
50
µA
VOLOD
Open Drain Output LOW Voltage (LED pins)
IOLOD = 12 mA
–
0.4
V
VSS<VIN<VDD
–500
500
µA
IIN = 0
VDD – 3.0
VDD – 1.0
V
VDD = 5.0 V
–2.5
+2.5
V
–
–275
–160
mV
IIL
AUI Ports
IIAXD
Input Current at DI± and CI± Pairs
VAICM
DI±, CI± Open Circuit Input Voltage Range
VAIDV
Differential Mode Input Voltage Range
(DI, CI)
VASQ
DI, CI Squelch Threshold
VATH
DI Switching Threshold
(Note 1)
-35
+35
mV
VAOD
Differential Output Voltage (DO+) – (DO)
RL = 78 Ω
620
1100
mV
VAOC
Differential Output Voltage (CI+) – (CI–)
(Reverse Mode)
RL = 78 Ω
620
1100
mV
VAODI
DO Differential Output Voltage Imbalance
RL = 78 Ω
–25
+25
mV
VAODOFF
DO Differential Idle Output Voltage
RL = 78 Ω
–40
+40
mV
IAODOFF
DO Differential Idle Output Current
RL = 78 Ω (Note 1)
–1.0
+1.0
mA
RL = 78 Ω
2.5
VDD
V
–500
500
µA
VAOCM
DO+, DO- Common Mode Output Voltage
Twisted Pair Ports
32
IIRXD
Input Current at RXD±
and CI± Pairs
AVSS<VIN<VDD
(Note 1)
RRXD
RXD Differential Input
VTIVB
RXD+, RXD– Open Circuit
Input Voltage (bias)
VTID
Differential Mode Input
Range (RXD)
VDD = 5.0 V
Am79C984A
10
–
kΩ
VDD – 3.0
VDD – 1.5
V
–3.1
+3.1
V
P R E L I M I N A R Y
DC CHARACTERISTICS (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Twisted Pair Ports (Continued)
VTSQ+
RXD Positive Squelch Threshold
(peak)
Sinusoid
5 MHz<f<10 MHz
300
520
mV
VTSQ–
RXD Negative Squelch Threshold
(peak)
Sinusoid
5 MHz<f<10 MHz
–520
–300
mV
VTHS+
RXD Post-Squelch Positive
Threshold (peak)
Sinusoid
5 MHz<f<10 MHz
150
293
mV
VTHS–
RXD Post-Squelch Negative
Threshold (peak)
Sinusoid
5 MHz<f<10 MHz
–293
–150
mV
VLTSQ+
RXD Positive Squelch Threshold
(peak) - Extended Distance Mode
Sinusoid
5 MHz<f<10 MHz
180
365
mV
VLTSQ–
RXD Negative Squelch Threshold
(peak) - Extended Distance Mode
Sinusoid
5 MHz<f<10 MHz
–365
–180
mV
VLTHS+
RXD Post-Squelch Positive
Threshold - Extended Distance Mode
Sinusoid
5 MHz<f<10 MHz
90
175
mV
VLTHS–
RXD Post-Squelch Negative
Threshold - Extended Distance Mode
Sinusoid
5 MHz<f<10 MHz
–175
–90
mV
VRXDTH
RXD Switching Threshold
(Note 1)
–60
60
mV
Power Supply Current
(Idle) (Note 2)
CLK = 20 MHz
VDD = +5.25V
–
100
mA
Power Supply Current
(Transmitting)
CLK = 20 MHz
VDD = +5.25V
–
350
mA
Power Supply Current
IDD
Notes:
1. Parameter not tested.
2. LED current not included. Maximum current rating on LED drivers is 12 mA.
Am79C984A
33
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Clock and Reset Timing
tCLK
CLK Clock Period
49.995
50.005
ns
tCLKH
CLK Clock High
20
30
ns
tCLKL
CLK Clock Low
20
30
ns
tCLKR
CLK Rise Time
–
10
ns
tCLKF
CLK Fall Time
–
10
ns
tPRST
Reset Pulse Width after Power On
150
–
µs
tRST
Reset Pulse Width
4
–
µs
Reset HIGH Setup Time with respect to
CLK
15
–
ns
tRSTSET
tRSTHLD
Reset LOW Hold Time
0
–
ns
tXRS
AMODE, SELI0, and SI_D Setup Time
to Rising Edge of RST
0
–
ns
tXRH
AMODE,SELI0, and SI_D Hold Time
from Rising Edge of RST
400
–
ns
AUI Port Timing
tDOTD
CLK Rising Edge to DO Toggle
–
30
ns
tDOTR
DO+, DO– Rise Time (10% to 90%)
–
7.0
ns
tDOTF
DO+, DO– Fall Time (90% to 10%)
–
7.0
ns
tDORM
DO+, DO– Rise and Fall Time Mismatch
–
1.0
ns
tDOETD
DO± End of Transmission
275
375
ns
tPWODI
DI Pulse Width Accept/Reject Threshold
|VIN|>|VASQ| (Note 2)
15
45
ns
tPWKDI
DI Pulse Width Not to Turn-off Internal
Carrier Sense
|VIN|>|VASQ| (Note 3)
136
200
ns
tPWOCI
CI Pulse Width Accept/Reject Threshold
|VIN|>|VASQ| (Note 4)
10
26
ns
tPWKCI
CI Pulse Width Not to Turn-off Threshold
|VIN|>|VASQ| (Note 5)
75
160
ns
tCITR
CI Rise Time (In Reverse Mode)
–
7.0
ns
tCITF
CI Fall Time (In Reverse Mode)
–
7.0
ns
tCIRM
CI+, CI– Rise and Fall Time Mismatch
(AUI in Reverse Mode)
–
1.0
ns
Expansion Bus Timing
tCLKHRL
CLK HIGH to SELO Driven LOW
CL = 50 pF
15
30
ns
tCLKHRH
CLK HIGH to SELO Driven HIGH
CL = 50 pF
15
30
ns
tCLKHDR
CLK HIGH to DAT/JAM Driven
CL = 100 pF
14
30
ns
tCLKHDZ
CLK HIGH to DAT/JAM Not Driven
CL = 100 pF
14
30
ns
DAT/JAM Setup Time to CLK
10
–
ns
tDJHOLD
tDJSET
DAT/JAM Hold Time from CLK
9
–
ns
tCASET
COL/ACK Setup Time to CLK
10
–
ns
tCAHLD
COL/ACK Hold Time from CLK
9
–
ns
SI, SCLK Hold Time
50
–
ns
tSCLKHLD
34
Am79C984A
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Twisted Pair Port Timing
tTXTD
CLK Rising Edge to TXD± Transition Delay
tTETD
Transmit End of Transmission
|VIN|>|VTHS| (Note 6)
–
50
ns
250
375
ns
136
200
ns
tPWKRD
RXD Pulse Width Maintain/Turn-off
Threshold
tPERLP
Idle Signal Period
8
24
ms
tPWLP
Idle Link Test Pulse Width
75
120
ns
Control Port Timing
tSCLK
SCLK Clock Period
100
–
ns
tSCLKH
SCLK Clock HIGH
30
–
ns
tSCLKL
SCLK Clock LOW
30
–
ns
tSCLKR
SCLK Clock Rise Time
–
10
ns
tSCLKF
SCLK Clock Fall Time
–
10
ns
tSISET
SI Input Setup Time to SCLK Rising Edge
10
–
ns
tSIHLD
SI Input Hold Time from SCLK Rising Edge
10
–
ns
tSODLY
SO Output Delay from SCLK Rising Edge
–
40
ns
CL = 100 pF
Notes:
1. Parameter not tested.
2. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.
3. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier on; pulses wider than tPWKDI (max) will turn internal DI
carrier sense off.
4. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.
5. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier on; pulses wider than tPWKCI (max) will turn internal CI
carrier sense off.
6. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; a pulse wider than tPWKRD (max) will turn
RXD carrier sense off.
Am79C984A
35
P R E L I M I N A R Y
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING WAVEFORMS
t CLK
t CLKH
t CLKL
CLK
t CLKR
t CLKF
20650A-20
20650B-19
Figure 14. Clock Timing
36
Am79C984A
P R E L I M I N A R Y
SWITCHING WAVEFORMS (continued)
t SCLKR
t SCLK
tSCLKF
SCLK
tSCLKH
t SCLKL
SI
t SISET
tSODLY
tSIHLD
SO
20650B-20
20650A-21
Figure 15. Control Port Timing
CLK
tRSTSET
tRSTHLD
RST
tRST
or tPRST
TCLK
Note: TCLK represents internal eIMR timing
20650B-21
20650A-22
Figure 16. Reset Timing
AMODE, SELI_0
tXRS
tXRH
RST
20650B-22
Figure 17. Mode Initialization
Am79C984A
37
P R E L I M I N A R Y
SWITCHING WAVEFORMS (continued)
CLK
TCLK
SELO
ACK
COL
tDJSET
DAT/JAM
tDJHOLD
IN
Note: TCLK represents internal eIMR timing
20650B-23
Figure 18. Expansion Bus Input Timing
CLK
TCLK
tCLKHRL
tCLKHRH
SELO
tCASET
tCASET
ACK
tCAHLD
COL
tCLKHDZ
tCLKHDR
DAT/JAM
OUT
Note: TCLK represents internal eIMR timing
Figure 19. Expansion Bus Output Timing
38
Am79C984A
20650B-24
P R E L I M I N A R Y
SWITCHING WAVEFORMS (continued)
CLK
TCLK
tCLKHRH
SELO
tCASET
tCLKHRL
ACK
tCASET
COL
tCAHLD
IN
DAT/JAM
IN
20650B-25
Note: TCLK represents internal eIMR timing
20650A-26
Figure 20. Expansion Bus Collision Timing
CLK
tDOTD
tDOETD
tDOTR
DO+
tDOTF
DO –
20650B-26
Figure 21. AUI Timing Diagram
tPWKDI
tPWKDI
(tPWKCI)
DI+
(CI±)
(tPWKCI)
VASQ
tPWODI
(tPWOCI)
20650A-28
20650B-27
Figure 22. AUI Receive Diagram
Am79C984A
39
P R E L I M I N A R Y
SWITCHING WAVEFORMS (continued)
1
0
1
0
1
1
1
0
1
0
ETD
CLK
tTXETD
tTXETD
TXD+
TXD–
20650A-29
20650B-28
Figure 23. TP Ports Output Timing Diagram
tPWLP
tPERLP
Figure 24. TP Idle Link Test Pulse
tPWKRD
VTSQ+
VTHS+
VTHS–
RXD+/–
VTSQ–
tPWKRD
tPWKRD
Figure 25. TP Receive Timing Diagram
40
Am79C984A
P R E L I M I N A R Y
SWITCHING TEST CIRCUIT
VDD
Pin
Test Point
VSS
20650A-32
20650B-31
Figure 26. Switching Test Circuit
Am79C984A
41
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
PL 084
84-Pin Plastic LCC (measured in inches)
1.185
1.195
1.150
1.156
.042
.056
.062
.083
1.090
1.130
1.000
REF
Pin 1 I.D.
1.185
1.195
1.150
1.156
.013
.021
.026
.032
.050 REF
.007
.013
TOP VIEW
42
.090
.130
.165
.180
SEATING PLANE
SIDE VIEW
Am79C984A
16-038-SQ
PL 084
DF79
8-1-95 ae
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
PQR100
100-Pin Plastic Quad Flat Pack
Pin 100
12.35
REF
13.90
14.10
17.00
17.40
Pin 80
Pin 1 I.D.
18.85
REF
19.90
20.10
23.00
23.40
Pin 30
Pin 50
2.70
2.90
0.65 BASIC
0.25
MIN
3.35
MAX
SEATING PLANE
16-038-PQR-2
PQR100
DA92
8-2-94 ae
Am79C984A
43
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am186, Am386, Am486, Am29000, bIMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet,
PCnet-FAST, PCnet-FAST+, PCnet-Mobile, QFEX, QFEXr, QuASI, QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced
Micro Devices, Inc.
Microsoft is a registered trademark of Microsoft Corporation.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.