AD ADP3020 High-efficiency notebook computer power supply controller Datasheet

a
High-Efficiency Notebook Computer
Power Supply Controller
ADP3020
FEATURES
Wide Input Voltage Range: 4.5 V to 25 V
High Conversion Efficiency > 96%
Integrated Current Sense—No External Resistor Required
Low Shutdown Current: 7 ␮A (Typical)
Dual Synchronous Buck Controllers with Selectable
PWM/Power-Saving Mode Operation
Built-In Gate Drive Boost Circuit for Driving External
N-Channel MOSFETs
Two Independently Programmable Output Voltages
Fixed 3.3 V or Adjustable (1.25 V to VIN–0.5 V)
Fixed 5 V or Adjustable (1.25 V to VIN–0.5 V)
Programmable PWM Frequency
Integrated Linear Regulator Controller
Extensive Circuit Protection Functions
38-Lead TSSOP Package
APPLICATIONS
Notebook Computers and PDAs
Portable Instruments
General Purpose DC-DC Converters
GENERAL DESCRIPTION
The ADP3020 is a highly efficient dual synchronous buck switching regulator controller optimized for converting the battery or
adapter input into the system supply voltages required in notebook computers. The ADP3020 uses a dual-mode PWM/Power
Saving Mode architecture to maintain efficiency over a wide
load range. The oscillator frequency can be programmed for
200 kHz, 300 kHz, or 400 kHz operation, or it can be synchronized to an external clock signal of up to 600 kHz.
The ADP3020 provides accurate and reliable short circuit protection using an internal current sense circuit, which reduces
cost and increases overall efficiency. Other protection features
include programmable soft-start, UVLO, and integrated output
undervoltage/overvoltage protection. The ADP3020 contains a
linear regulator controller that is designed to drive an external
P-channel MOSFET or PNP transistor. The linear regulator
output is adjustable, and can be used to generate the auxiliary
voltages required in many laptop designs.
FUNCTIONAL BLOCK DIAGRAM
VIN
5.5V TO 25V
PFO
ADP3020
5V LINEAR
1.20V
REF
Q1
Q3
L2
L1
5V
3.3V
5V
SMPS
Q4
3.3V
SMPS
Q2
SS3
SS5
Q5
PWRGD
LINEAR
CONTROLLER
POWER-ON
RESET
2.5V
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
(@ T = –40ⴗC to +85ⴗC, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA,
ADP3020–SPECIFICATIONS
REF Load = 0 mA, MODE = 0 V, SYNC = 0 V, SD = 5 V, unless otherwise noted.)
A
Parameter
Symbol
INTERNAL 5 V REGULATOR
Input Voltage Range
5 V Voltage
Line Regulation
Total Variation
Switchover Voltage
Switchover Hysteresis
Undervoltage Lockout
Threshold Voltage
Undervoltage Lockout
Hysteresis
INTVCC
REFERENCE
Output Voltage2
SUPPLY CURRENT
Shutdown Current
Standby Current
TA = 25°C
5.5 V ≤ VIN ≤ 25 V
Line, Temp
AUXVCC from Low to High
AUXVCC from High to Low
INTVCC Falling
REF
IQ
Quiescent Current
(Power-Saving Mode)
fOSC
SYNC Input
Frequency Range
Input Low Voltage3
Input High Voltage3
Input Current
POWER GOOD
Output Voltage In Regulation
Output Voltage Out of Regulation
MAIN SMPS CONTROLLERS
Fixed 5 V Output Voltage
PWM Mode
Power-Saving Mode
Fixed 3.3 V Output Voltage
PWM Mode
Power-Saving Mode
5.5 V ≤ VIN ≤ 25 V
5.5
4.95
4.8
4.65
3.6
1.185
SD = 0 V
SS3 = SS5 = SD2 = 0 V
SD = 5 V
No Loads, MODE = 5 V
SS3 = SS5 = SD2 = 5 V
FB5 = FB3 = FB2 = 1.25 V,
ADJ/FX5 = ADJ/FX3 = 5 V
No Loads, MODE = 0 V
SS3 = SS5 = SD2 = 5 V
FB5 = FB3 = FB2 = 1.25 V,
ADJ/FX5 = ADJ/FX3 = 5 V
SYNC = AGND
SYNC = REF
SYNC = INTVCC
Typ
5.025
0.3
4.75
100
3.8
Max
Unit
25
5.15
V
V
mV/V
V
V
mV
V
5.2
4.85
4.2
mV
1.197
1.209
V
7
250
15
400
µA
µA
0.95
1.8
mA
µA
650
176
264
352
200
300
400
230
tF ≤ 200 ns
tR ≤ 200 ns
SYNC = REF
224
336
448
kHz
kHz
kHz
600
0.4
kHz
V
V
µA
4.6
1.2
PWRGD
10 kΩ Pull-Up to 5 V
10 kΩ Pull-Up to 5 V
FB5 < 90% of Nominal
Output Value
FB5 Rising
FB5 Falling
CPOR = 1.2 V
PWRGD Trip Threshold
PWRGD Hysteresis
CPOR Pull-Up Current
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Input Leakage Current
Min
120
Quiescent Current
(PWM Mode)
OSCILLATOR
Frequency
Conditions
GBW
IEAN
4.8
0.4
–8
–4
4
2.5
–2
67
10
ADJ/FX5 = ADJ/FX3 = 5 V
V
V
%
%
µA
200
dB
MHz
nA
FB5
5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = 0 V
5.5 V ≤ VIN ≤ 25 V, ADJ/FX5 = 0 V
4.90
4.925
5.0
5.025
5.10
5.125
V
V
5.5 V ≤ VIN ≤ 25 V, ADJ/FX3 = 0 V
5.5 V ≤ VIN ≤ 25 V, ADJ/FX3 = 0 V
3.234
3.250
3.3
3.316
3.366
3.382
V
V
FB3
–2–
REV. 0
ADP3020
Parameter
Adjustable Output Voltage
PWM Mode
Power-Saving Mode
Symbol
Conditions
Min
Typ
EAN5,
EAN3
FB5, FB3
5.5 V ≤ VIN ≤ 25 V,
ADJ/FX5 = ADJ/FX3 = 5 V
5.5 V ≤ VIN ≤ 25 V,
ADJ/FX5 = ADJ/FX3 = 5 V
ADJ/FX5 = ADJ/FX3 = 5 V
1.173
1.197 1.221
V
1.179
1.203 1.227
V
1.25
5.5 V ≤ VIN ≤ 25 V, TA = 25°C
5.5 V ≤ VIN ≤ 25 V, TA = 25°C
54
115
72
144
0.7
16
35
28
4
1.2
94
99
Output Voltage Adjustment Range3
Current Limit Threshold (PWM Mode)
CLSET5 = CLSET3 = Floating
CLSET5 = CLSET3 = 0 V
Current Limit Threshold
(Power-Saving Mode)
CLSET5 = CLSET3 = Floating
CLSET5 = CLSET3 = 0 V
Power-Saving Mode Trip Threshold
Soft-Start Current
Soft-Start Turn-On Threshold
Feedback Input Leakage Current
FB5, FB3
Maximum Duty Cycle3
Transition Time (DRVH/DRVL)
Rise
Fall
Logic Input Low Voltage
Logic Input High Voltage
DMAX
LINEAR REGULATOR CONTROLLER
Feedback Threshold
SD2 Pull-Up Current
SD2 Threshold
Current Sinking Capability
FB2 Input Leakage Current
POWER-FAIL COMPARATOR
PFI Input Threshold
PFI Input Hysteresis
PFI Input Current
PFO High Voltage
PFO Low Voltage
FAULT PROTECTION
Output Overvoltage Trip Threshold
Output Undervoltage Lockout Threshold
5.5 V ≤ VIN ≤ 25 V, TA = 25°C
5.5 V ≤ VIN ≤ 25 V, TA = 25°C
CLSET5 = CLSET3 = 0 V, TA = 25°C
SS3 = SS5 = 3 V
SS5, SS3
IFB
tR
tF
ADJ/FX5 = ADJ/FX3 = 5 V,
FB = 1.2 V
VIN = 5.5 V, SYNC = AGND
CLOAD = 3000 pF, 10%–90%
CLOAD = 3000 pF, 90%–10%
MODE, SD, ADJ/FX3, ADJ/FX5
MODE, SD, ADJ/FX3, ADJ/FX5
FB2
SD2
SD2 = 1.2 V
DRV2
IFB
DRV2 = 2 V, FB2 = 1 V, SD2 = 5 V
FB2 = 1.2 V
0.7
20
PFO from High to Low
1.176
10 kΩ Pull-Up to 5 V
10 kΩ Pull-Up to 5 V
4.8
With Respect to Nominal Output
With Respect to Nominal Output
115
75
90
173
mV
mV
1.8
200
mV
mV
mV
µA
V
nA
%
40
40
70
70
0.6
ns
ns
V
V
1.20
4
1.2
45
50
1.224
V
µA
V
mA
nA
1.20
24
1.8
1.224
0.4
V
mV
nA
V
V
125
85
%
%
200
Specifications subject to change without notice.
–3–
Unit
VIN–0.5 V
2.4
1.176
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
The reference’s line-regulation error is insignificant. The reference cannot be used for external load.
3
Guaranteed by design, not tested in production.
REV. 0
Max
120
80
ADP3020
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
CS5
2
FB5
3
EAN5
4
5
EAO5
ADJ/FX5
6
7
SS5
CLSET5
8
REF
9
10
AGND
CLSET3
11
MODE
12
SYNC
13
14
SS3
ADJ/FX3
15
16
EAO3
EAN3
17
FB3
18
CS3
19
PFI
20
PFO
21
PWRGD
22
CPOR
23
24
25
26
27
28
29
30
SD2
FB2
DRV2
BST3
DRVH3
SW3
DRVL3
VIN
Current Sense Input for top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of
the top N-channel MOSFET.
Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode.
Connect to an external resistor divider in adjustable output mode.
Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation
only in fixed output mode. In adjustable output mode, connect to an external resistor divider.
Error Amplifier Output for the 5 V Buck Converter.
TTL Logic Input. When ADJ/FX5 = 0 V, fixed output mode, connect FB5 to the output sense point.
When ADJ/FX5 = 5 V, adjustable output mode, connect FB5 to the external resistor divider.
Soft Start for the 5 V Buck Converter. Also used as an ON/OFF Pin.
Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current
limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND.
1.2 V Bandgap Reference. Bypass it with a capacitor (1 nF typical) to AGND. REF cannot be used
directly with an external load.
Analog Signal Ground.
Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current
limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND.
TTL Logic Input. MODE = 5 V, always in constant frequency PWM mode; MODE = 0 V, PWM
mode at moderate and heavy loads, and Power Saving (PSV) Mode at light load.
Oscillator Synchronization and Frequency Select. fOSC = 200 kHz, when SYNC = 0 V; fOSC = 300 kHz, if
SYNC is tied to the REF Pin; fOSC = 400 kHz, when SYNC = 5 V. Oscillator can be synchronized with an
external source through the SYNC Pin.
Soft Start for the 3.3 V Buck Converter. Also used as an ON/OFF Pin
TTL Logic Input. When ADJ/FX3 = 0 V, fixed output mode, connect FB3 to the output sense point.
When ADJ/FX3 = 5 V, adjustable output mode, connect FB3 to external resistor divider.
Error Amplifier Output for the 3.3 V Buck Converter.
Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation only in
fixed output mode. In adjustable output mode, connect to an external resistor divider.
Feedback Input for the 3.3 V Buck Converter. Connect to output sense point in fixed output mode.
Connect to an external resistor divider in adjustable output mode.
Current Sense Input for Top N-Channel MOSFET of the 3.3 V Buck Converter. It should be connected to the drain of the N-channel MOSFET.
The (–) Input of a comparator that can be used as a power fail detector. The positive input is connected
to the 1.20 V reference. There is a 24 mV hysteresis for this comparator.
Open Drain Output. This pin will sink current when the PFI pin is lower than 1.20 V. Otherwise, PFO
is floating.
Power Good Output. PWRGD goes low with no delay, whenever the 5 V output drops 8% below its
nominal value. When the 5 V output is within –4% of its nominal value, PWRGD will be released after a
time delay determined by the timing capacitor on the CPOR pin.
Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 2.5 µA
pull-up current is used to charge the capacitor. A manual reset (MR) function can also be implemented
by grounding this pin.
Shutdown input for the Linear Regulator Controller.
Feedback for the Linear Regulator Controller.
Open Collector Output for the Linear Regulator Controller.
Boost Capacitor Connection for High Side Gate Driver of the 3.3 V Buck Converter.
High Side Gate Driver for 3.3 V Buck Converter.
Switching Node (Inductor) Connection of the 3.3 V Buck Converter.
Low Side Gate Driver of 3.3 V Buck Converter.
Main Supply Input (4.5 V to 25 V).
–4–
REV. 0
ADP3020
PIN FUNCTION DESCRIPTIONS (Continued)
Pin No.
Mnemonic
Function
31
32
INTVCC
AUXVCC
33
SD
34
35
36
37
38
PGND
DRVL5
SW5
DRVH5
BST5
Linear Regulator Bypass for the internal 5 V LDO. Bypass this pin with a 4.7 µF capacitor to AGND.
Supply Switch Over. When AUXVCC > 4.75 V, and both of the switchers are in Power Saving mode,
the internal 5 V LDO is turned off. The chip is powered by AUXVCC pin. There is a 2% hysteresis for
this pin.
Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown with very low quiescent current. For automatic start-up, connect SD to VIN directly.
Power Ground.
Low Side Driver for 5 V Buck Converter.
Switching Node (Inductor) Connection for 5 V Buck Converter.
High Side Gate Driver for 5 V Buck Converter.
Boost Capacitor Connection for High Side Gate Driver of the 5 V Buck Converter.
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS*
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +27 V
AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
INTVCC . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +6 V
BST5, BST3 to PGND . . . . . . . . . . . . . . . . . –0.3 V to +32 V
BST5 to SW5 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
BST3 to SW3 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
CS5, CS3 . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to VIN
SW3, SW5 to PGND . . . . . . . . . . . . . . –0.3 V to VIN + 0.3 V
SD . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +27 V
DRVL5/3 to PGND . . . . . . . . . –0.3 V to (INTVCC + 0.3 V)
DRVH5/3 to SW5/3 . . . . . . . . . –0.3 V to (INTVCC + 0.3 V)
All Other Inputs and Outputs
. . . . . . . . . . . . . . . . . . AGND – 0.3 V to INTVCC + 0.3 V
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Operating Ambient Temperature Range . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –40°C to +150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
CS5 1
38 BST5
FB5 2
37 DRVH5
EAN5 3
36 SW5
EAO5 4
35 DRVL5
34 PGND
ADJ/FX5 5
33 SD
SS5 6
CLSET5 7
ADP3020
32 AUXVCC
31 INTVCC
TOP VIEW
AGND 9 (Not to Scale) 30 VIN
REF 8
29 DRVL3
CLSET3 10
28 SW3
MODE 11
27 DRVH3
SYNC 12
SS3 13
26 BST3
ADJ/FX3 14
25 DRV2
EAO3 15
24 FB2
EAN3 16
23 SD2
22 CPOR
FB3 17
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
CS3 18
21 PWRGD
20 PFO
PFI 19
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADP3020ARU
–40°C to +85°C
Thin Shrink Small Outline
RU-38
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3020 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
ADP3020
INPUT
VIN
AUXVCC
32
30
ADP3020
+
–
+
72mV
– +
CS5
1
–
4.7V
SD 33
INTVCC
5V
14mV
– +
+5V
LINEAR REG
31
+
–
REF
8
1.2V
AGND
CLSET5
7
1.2V
REF
ULVO
9
PFO 20
PFI
38
–
19
37
+
1.20V
36
MODE 11
200kHz/
300kHz/
400kHz
OSC
PWRGD 21
CPOR
DRVH5
SW5
INTVCC
SYNC 12
3.3V
BST5
POWER–
ON
RESET
CONTROL
LOGIC
35
34
VOUT5
5V
DRVL5
PGND
FB5
+
–
–3mV
FB5
22
+
+2%
–
2
1.22V
DRV2
25
+
0%
–
2.5V
1.2V
+
–
24
+
–2% 1.18V
–
4␮A
SD2 23
+
–
1.2V
EA
–
+
FB2
1.2V
3
4
SHUTDOWN
+
+20%
–
+
–20%
–
S
EAN5
1.2V
EAO5
1.44V
5 ADJ/FX5
0.7␮A
0.96V
OC
Q
R
2.5V
–
+
4␮A
SS5
6
+
ON5
–
1.2V
DUPLICATE FOR SECOND CONTROLLER
Figure 1. Block Diagram (All Switches and Components Are Shown for Fixed Output Operation)
–6–
REV. 0
Typical Performance Characteristics– ADP3020
100
100
VIN = 6V
90
90
VIN = 15V
EFFICIENCY – %
EFFICIENCY – %
VIN = 6V
80
70
VIN = 15V
70
60
60
50
0.01
80
0.1
1
OUTPUT CURRENT – A
50
0.01
10
Figure 2. Efficiency vs. 5 V Output Current
0.1
1
OUTPUT CURRENT – A
10
Figure 5. Efficiency, 1.5 V Output Current
1200
100
VIN = 6V
90
+85ⴗC
CURRENT – ␮A
EFFICIENCY – %
VIN = 15V
80
70
1000
+25ⴗC
–40ⴗC
800
60
50
0.01
600
0.1
1
OUTPUT CURRENT – A
5
10
10
15
20
25
INPUT VOLTAGE – V
Figure 3. Efficiency vs. 3.3 V Output Current
Figure 6. PWM Mode Input Current vs. Input Voltage
100
900
90
800
CURRENT – ␮A
EFFICIENCY – %
VIN = 6V
80
70
VIN = 15V
60
50
0.01
+25ⴗC
–40ⴗC
600
500
0.1
1
OUTPUT CURRENT – A
400
10
5
10
15
20
25
INPUT VOLTAGE – V
Figure 4. Efficiency vs. 2.5 V Output Current
REV. 0
+85ⴗC
700
Figure 7. PSV Mode Input Current vs. Input Voltage
–7–
ADP3020
250
300
CURRENT LIMIT THRESHOLD – mV
+85ⴗC
+25ⴗC
CURRENT – ␮A
250
–40ⴗC
200
150
10
15
20
150
VIN = 5.5V TO 25V
100
50
0
–40 –30 –20 –10
100
5
CLSET = GND
200
25
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE – ⴗC
INPUT VOLTAGE – V
Figure 8. Input Standby Current vs. Input Voltage
Figure 11. Current Limit Threshold vs. Temperature
1.210
10
9
1.205
8
REFERENCE OUTPUT – V
+85ⴗC
CURRENT – ␮A
7
+25ⴗC
6
5
–40ⴗC
4
3
2
1.200
1.195
1.190
VIN = 5.5V TO 25V
1.185
1
0
5
10
15
20
1.180
–40 –30 –20 –10
25
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE – ⴗC
INPUT VOLTAGE – V
Figure 9. Input Shutdown Current vs. Input Voltage
Figure 12. Reference Output vs. Temperature
TEK STOP: SINGLE SEQ 250 S/s
[ T
315
]
SYNC = REF
FREQUENCY – kHz
310
CH1 = 3.3V
OUTPUT
VIN = 25
305
VIN = 12
CH2 = 2.5V
OUTPUT
300
VIN = 7.5
295
CH3 = SS3
VIN = 5.5
VIN = 12V
290
–40
CH4 = SS5
–10
20
50
AMBIENT TEMPERATURE – ⴗC
CH1
CH3
80
2.00V
1.00V
CH2
CH4
1.00V
1.00V
M 200MS CH4
740mV
Figure 13. Soft-Start Sequencing
Figure 10. PWM Mode Oscillator Frequency vs.
Temperature
–8–
REV. 0
ADP3020
STOP
T
[
CH1 = 5V
OUTPUT
T
[
STOP
]
]
CH1 = 5V
OUTPUT
CH2 = I OUT =
10mA TO 3A
CH2 = I OUT =
10mA TO 3A
CH1 200mV
CH2
2.00V
M 200␮s
CH2
CH1 200mV
1.88V
Figure 14. Power-Saving Mode, Transient Response
STOP
T
[
CH2
2.00V
M 200␮s
CH2
1.88V
Figure 16. PWM Mode, Transient Response
TEK STOP: SINGLE SEQ 250 S/s
[ T
]
]
CH1 = 5V
OUTPUT
(IOUT = 20mA)
CH1
CH2
CH2 = SW5
CH1 200mV
CH2
5.00V
M 400␮s
CH2
CH1
1.90V
Figure 15. Power-Saving Mode, Waveforms
REV. 0
10.0V
CH2
200mV
M 5.00ms CH1
10.8V
Figure 17. VIN = 7.5 V to 22 V Transient, 2.5 V Output,
CH1 – Input Voltage, CH2 – Output Voltage
–9–
ADP3020
THEORY OF OPERATION
The ADP3020 is a dual-mode, step-down power supply controller
for notebook computers or similar battery-powered applications.
The device contains two synchronous step-down buck controllers and a linear regulator controller. The buck controllers in the
ADP3020 have the ability to provide either fixed 3.3 V and 5 V
outputs or independently adjustable (1.25 V to VIN–0.5 V) outputs. High efficiency over a broad load range is achieved by using a
proprietary dual-mode PWM/power-saving (PSV) mode architecture. Efficiency is further improved by deleting the external current
sense resistor, which is the main contributor to loss during high
current, low output voltage conditions.
CIRCUIT DESCRIPTION
Dual-Mode Architecture
The ADP3020 contains two independent dual-mode, synchronous buck controllers. Traditional constant frequency PWM
buck converters suffer from relatively low efficiency under light
load conditions. In order to maintain high efficiency over a wide
load range, the ADP3020 uses a proprietary dual-mode architecture. At moderate to heavy loads, the buck converter operates
in the traditional Pulsewidth Modulation (PWM) mode. At light
loads, PSV mode is used to increase system efficiency. A proprietary detection scheme is used for transition from one mode to the
other. Input current to the high-side MOSFET is detected when
going from PWM mode to PSV mode, and output voltage information is used when changing from PSV mode to PWM mode.
When the high-side N-channel MOSFET is turned on, the current
going through the N-channel MOSFET is measured as a voltage
between CS and SW. If the peak current through the MOSFET
is less than 20% of the current limit value set by CLSET, an
internal counter that is based on the oscillator frequency will be
started. If the current stays below this threshold for 16 PWM
cycles, the buck converter will enter power-saving mode. The
counter will automatically reset if the peak current is higher than
20% of the current limit value any time prior to when the counter
reaches 16.
In PSV mode, the buck converter works like a window regulator. If the output voltage drops below the PWM mode nominal
output voltage, the high-side MOSFET will be turned on. It will
remain on until the output capacitors are charged up to 2%
above the PWM mode nominal output voltage. The high-side
MOSFET will then be latched off until the output capacitors are
discharged to the lower threshold. The discharge rate is dependent on the output capacitor value and load current.
It is important to note that the current limit threshold when in
PSV mode is approximately 1/4 of the current limit threshold
when in PWM mode. If a large load is applied to the converter
when in PSV mode (for example, larger than the current limit in
PSV mode), the output will continue to drop due to the lower
current limit threshold of PSV mode. When the output voltage
drops to 2% below the PWM mode nominal voltage, the converter
will automatically return to PWM mode. Once in PWM mode,
the current limit is quadrupled, and the output will be charged
up to the nominal level, as long as the load does not exceed the
higher PWM current limit.
MODE can be driven by an external TTL logic signal. When
MODE is pulled HIGH, PSV mode operation is disabled, and
the system is always in constant frequency PWM mode. In order
to enable PSV mode at light loads, the MODE pin needs to be
pulled LOW.
Table I. PWM Mode and PSV Mode
Mode
Load
Current
Operating
Mode
High
Low
Low
Low
X
Heavy
Moderate
Light
PWM
PWM
PWM
PSV
Description
Constant-Frequency PWM
Constant-Frequency PWM
Constant-Frequency PWM
Variable-Frequency, Burst
Mode
X = Don’t Care.
Forcing the ADP3020 to always remain in constant frequency
PWM mode can be used to reduce interference, as this allows
filtering of the fixed fundamental frequency and its harmonics.
The operating frequency should be carefully chosen so that both
the fundamental and harmonic frequencies are not within sensitive
audio or IF bands. This is particularly important in noise-sensitive
applications such as multimedia systems, cellular phones, computers with built-in RF communications, and PDAs. If two or
more switching regulators are used in a system, it is best to synchronize all the switching regulators to a single master regulator
or an external clock signal.
Internal 5 V Supply (INTVCC)
An internal low dropout regulator (LDO) generates a 5 V supply
(INTVCC) that powers all of the functional blocks within the
IC. The total current rating of this LDO is 50 mA. However,
this current is used for supplying gate-drive power, and it is not
recommended that current be drawn from this pin for other
purposes. Bypass INTVCC to AGND with a 4.7 µF capacitor.
A UVLO circuit is also included in the regulator. When INTVCC
< 3.8 V, the two switching regulators and the linear regulator
controller are shut down. The UVLO hysteresis voltage is about
120 mV. The internal LDO has a built-in fold-back current
limit, so that it will be protected if a short circuit is applied to
the 5 V output.
If AUXVCC is higher than 4.75 V, and both the 5 V and 3.3 V
switching regulators are in PSV mode, an internal switch will
connect INTVCC to AUXVCC, while simultaneously turning
off the internal LDO. AUXVCC can be tied to either the 5 V
switching regulator output or a separate 5 V voltage source. By
doing this, the power loss across the internal LDO is eliminated,
and the total efficiency in PSV mode is improved.
When AUXVCC = GND, this automatic power switchover feature will be disabled.
Internal Reference (REF)
The ADP3020 contains a precision 1.2 V bandgap reference.
Bypass REF to AGND with a 1 nF ceramic capacitor. The reference is intended for internal use only. An external voltage
buffer is needed if the reference is used for another purpose.
Boost High Side Gate Drive Supply (BST)
PWM/PSV Operation (MODE)
Table I shows the summary of the operating modes of the synchronous buck controllers. The MODE pin determines whether or not
the controllers remain in PWM mode under all load conditions.
The gate drive voltage for the high-side N-channel MOSFETs is
generated by a flying-capacitor boost circuit. The boost capacitor
connected between BST and SW is charged from the INTVCC
supply. Use only small-signal diodes for the boost circuit.
–10–
REV. 0
ADP3020
Synchronous Rectifier (DRVL)
coefficient of RDS(ON) of the N-channel MOSFET is canceled by
the internal current limit circuitry, so that an accurate current
limit value can be obtained over a wide temperature range. In
PSV mode, the current limit value is reduced to about 1/4 of
the value in PWM mode to reduce the interference noise to other
components on the PC board.
Synchronous rectification is used to reduce conduction losses
and to ensure proper start-up of the boost gate driver circuit.
Antishoot-through protection has been included to prevent cross
conduction during switch transitions. The low side driver must
be turned off before the high side driver is turned on. For typical N-channel MOSFETs, the dead time is about 50 ns. On the
other edge, a dead time of about 50 ns is achieved by an internal
delay circuit. The synchronous rectifier is turned off when the
current flowing through the low-side MOSFET falls to zero when
in Discontinuous Conduction (DCM) PWM mode and PSV mode.
In Continuous Conduction (CCM) PWM mode, the current
flowing through the low-side MOSFET never reaches zero, so the
synchronous rectifier is turned off by the next clock cycle.
Each switching controller has an undervoltage protection circuit.
When the current flowing through the high-side MOSFET
reaches the current limit continuously for eight clock cycles,
and the output voltage is below 20% of the nominal output
voltage, both controllers will be latched off and will not restart
until SD or SS3/SS5 is toggled, or until VIN is cycled below 4 V.
This feature is disabled during soft start.
Oscillator Frequency and Synchronization (SYNC)
Output Overvoltage Protection
The SYNC pin controls the oscillator frequency. When SYNC
= 0 V, fOSC = 200 kHz ; when SYNC = REF, fOSC = 300 kHz;
when SYNC = 5 V, fOSC = 400 kHz. 400 kHz operation will
minimize external component size and cost while 200 kHz operation provides better efficiency and lower dropout. The SYNC
pin can also be used to synchronize the oscillator with an external 5 V clock signal. A low-to-high transition on SYNC initiates
a new cycle. Synchronization range is 230 kHz to 600 kHz.
Output Undervoltage Protection
Both converter outputs are continuously monitored for overvoltage. If either output voltage is higher than the nominal output
voltage by more than 20%, both converter’s high-side gate drivers
(DRVH5/3) will be latched off, and the low-side gate drivers
will be latched on, and will not restart until SD or SS5/SS3 are
toggled, or until VIN is cycled below 4 V. The low-side gate
driver (DRVL) is kept high when the controller is in off-state
and the output voltage is less than 93% of the nominal output
voltage. Discharging the output capacitors through the main
inductor and low-side N-channel MOSFET will cause the output to ring. This will make the output momentarily go below
GND. To prevent damage to the circuit, use a reverse-biased
1 A Schottky diode across the output capacitors to clamp the
negative surge.
Shutdown (SD)
Holding SD = GND low will put the ADP3020 into ultralow
current shutdown mode. For automatic start-up, SD can be tied
directly to VIN.
Soft-Start and Power-Up Sequencing (SS)
SS3 and SS5 are soft start pins for the two controllers. A 4 µA
pull-up current is used to charge an external soft start capacitor.
Power-up sequencing can be easily done by choosing different
size external capacitors. When SS3/SS5 < 1.2 V, the two switching regulators are turned off. When 1.2 V < SS5/SS3 < 2.6 V,
the regulators start working in soft start mode. When SS3/SS5 >
2.6 V, the regulators are in normal operating mode. The controllers are forced to stay in PWM mode during the soft-start
period. The minimum soft-start time (~20 µs) is set by an internal capacitor. Table II shows the ADP3020 operating modes.
Power Good Output (PWRGD)
The ADP3020 also provides a PWRGD signal for the microprocessor. During start-up, the PWRGD pin is held low until 5 V
output is within –4% of its preset voltage. Then, after a time
delay determined by an external timing capacitor connected from
CPOR to GND, PWRGD will be actively pulled up to INTVCC
by an external pull-up resistor. CPOR can also be used as a
manual reset (MR) function. When the 5 V output is lower than
the preset voltage by more than 8%, PWRGD is immediately
pulled low.
Current Limiting (CLSET)
A cycle-by-cycle current limiting scheme is used by monitoring
current through the top N-channel MOSFET when it is turned
on. By measuring the voltage drop across the high-side MOSFET
VDS(ON), the external sense resistor can be deleted. The current
limit value can be set by CLSET. When CLSET = Floating, the
maximum VDS(ON) = 72 mV at room temperature; when CLSET
= 0 V, the maximum VDS(ON) = 144 mV at room temperature. An
external resistor can be connected between CLSET and AGND
to choose a value between 72 mV and 144 mV. The temperature
Linear Regulator Controller
The ADP3020 includes an onboard linear regulator controller.
An external PNP transistor can be used for operation up to 1 A.
For higher output current applications, a low threshold PMOS
can be used as the pass transistor. The output voltage can be set
by a resistor divider. The minimum output voltage of the LDO
is 1.25 V, while the maximum output voltage depends on where
the LDO input is connected and the dropout voltage of the
external pass transistor.
Table II. Operating Modes
SD
SS5
SS3
Mode
Description
Low
High
High
High
High
High
X
SS5 < 1.2 V
1.2 V < SS5 < 2.6 V
2.6 V < SS5
X
X
X
SS3 < 1.2 V
X
X
1.2 V < SS3 < 2.6 V
2.6 V < SS3
Shutdown
Standby
Run
Run
Run
Run
All Circuits Turned Off
5 V and 3.3 V Off; INTVCC = 5 V, REF = 1.2 V
5 V in Soft Start
5 V in Normal Operation
3.3 V in Soft Start
3.3 V in Normal Operation
REV. 0
–11–
ADP3020
Output Voltage Adjustment
Input Voltage Range
Fixed output voltages (5 V and 3.3 V) are selected when
ADJ/FX5 = ADJ/FX3 = 0 V. The output voltage of each controller can also be set by an external feedback resistor network
when ADJ/FX5 = ADJ/FX3 = 5 V as shown in Figure 18. There
should be two external feedback resistor dividers for each controller, one for the voltage feedback loop, and one for output
voltage monitor. Both resistor dividers need to be identical. The
minimum output voltage is 1.25 V. The maximum output voltage is limited only by the minimum supply voltage. Remote
output voltage sensing can be done for both fixed and adjustable
output voltage modes.
The input voltage range of the ADP3020 is 5.5 V to 25 V when
5 V output is desired, and 4.5 V to 25 V when neither switcher
output is >4.0 V. This converter design is optimized to deliver
the best performance within a 7.5 V to 18 V range, which is the
nominal voltage for three to four cell Li-Ion battery stacks. Voltages above 18 V may occur under light loads and when the
system is powered from an ac adapter with no battery installed.
The output voltage can be calculated using the following formula:

R1
VOUT = REF × 1 + 
R2

(1)
where REF = 1.2 V, and R1/R2 = R3/R4.
VIN
DRVH
Maximum Output Current and MOSFET Selection
The maximum output current for each switching regulator is limited by sensing the voltage drop between the drain and source of
the high-side MOSFET when it is turned on. A current sense
comparator senses voltage drop between CS5 and SW5 for the
5 V converter and between CS3 and SW3 for the 3.3 V converter.
The sense comparator threshold is 72 mV when the programming pin, CLSET, is floating, and is 144 mV when CLSET is
connected to ground. Current-limiting is based on sensing the
peak current. Peak current varies with input voltage and depends
on the inductor value. The higher the ripple current or input
voltage, the lower the converter maximum output current at the
set current sense amplifier threshold. The relation between peak
and dc output current is given by:
VOUT
 VIN( MAX ) – VOUT 
I PEAK = IOUT + VOUT × 

 2 × f × L × VIN( MAX ) 
DRVL
ADP3020
R3
R1
R4
R2
At a given current comparator threshold VTH and MOSFET
RDS(ON), the maximum inductor peak current is:
FB
I PEAK =
EAN
5V
VTH
RDS(ON )
(3)
Rearranging Equation 2 to solve for IOUT(MAX) gives:
ADJ/FX
IOUT( MAX ) =
Figure 18. Adjustable Output Mode
If the loop is carefully compensated, R3 and R4 can be, removed,
and FB and EAN can be tied together.
APPLICATION INFORMATION
A typical notebook PC application circuit using the ADP3020 is
shown in Figure 19. Although the component values given in
Figure 19 are based on a 5 V @ 4 A /3.3 V @ 4 A/2.5 V @ 1.5 A
design, the ADP3020 output drivers are capable of handling output currents anywhere from <1 A to over 10 A. Throughout this
section, design examples and component values will be given for
three different power levels. For simplicity, these levels will be
referred to as low power, basic, and extended power. Table
III shows the input/output specifications for these three levels.
Table III. Typical Power Level Examples
Input Voltage
Range
Switching
Output 1
Switching
Output 2
Linear Output
(2)
 VIN( MAX ) – VOUT 
VTH
– VOUT × 
 (4)
RDS(ON )
 2 × f × L × VIN( MAX ) 
Normally, VTH should be set to its maximum value of 144 mV.
For example, in the circuit of Figure 19, an Si4410, which has
an RDS(ON) of 13.5 mΩ would have a maximum peak current
limit of around 10 A. A less efficient way to achieve maximum
power from the converter is to design the inductor with a larger
inductance, (i.e., a lower ripple current). This helps reduce
the peak-to-dc current ratio and increases maximum converter
output, but may also increase the inductor value and its size.
It is important to remember that this current limit circuit is
designed to protect against high current or short circuit conditions only. This will protect the IC and MOSFETs long enough
to allow the output undervoltage protection circuitry to latch off
the supply.
Extended
Power
Low Power
Basic
5.5 V to 25 V
5.5 V to 25 V 5.5 V to 25 V
3.3 V/2 A
3.3 V/4 A
3.3 V/10 A
5 V/2 A
2.5 V/1 A
5 V/4 A
2.5 V/1.5 A
5 V/10 A
2.5 V/2 A
–12–
REV. 0
ADP3020
VIN
5.5V-25V
C22
4.7␮F
C18
150pF
R10
10k⍀
R2
130k⍀
C1
68pF
C2
330pF
R2
47k⍀
C4
1␮F
C5
1nF
R3
47k⍀
U1
ADP3020
C14A
10␮F
1
CS5
2
FB5
3
EAN5
SW5 36
4
EAO5
DRVL5 35
5
ADJ/FX5
6
SS5
7
CLSET5
8
REF
9
AGND
BST5 38
DRVH5 37
PGND 34
SD 33
AUXVCC 32
INTVCC 31
VIN 30
C17
100nF
D6
1N4148
C8
470pF
C9
68pF
C19
330pF
R11
6.2k⍀
11 MODE
SW3 28
12 SYNC
DRVH3 27
13 SS3
BST3 26
14 ADJ/FX3
DRV2 25
15 EAO3
FB2 24
16 EAN3
SD2 23
17 FB3
CPOR 22
18 CS3
PWRGD 21
19 PFI
R26
60.4k⍀
L2
6.8␮H
Q5
SI4410
D2
10BQ040
+
C27A
68␮F
+
+
C24A
68␮F
+
C27B
68␮F
VOUT5
5V, 4A
C16
1␮F
R6
10⍀
R5
10⍀
C15
4.7␮F
C13
1␮F
PFO 20
C20A
10␮F
C20B
10␮F
D5
1N4148
Q2
C12 SI4410
Q5
SI4410
L1
6.8␮H
D1
10BQ040
D3
10BQ040
(OPTIONAL)
C26
4.7␮F
R12
10k⍀
R17
1k⍀
R9
47k⍀
C24B
68␮F
Q1
IRF7404
C28
1␮F
PFO
R24
210k⍀
–13–
VOUT33
3.3V, 4A
VOUT25
2.5V, 1.5A
R8
13k⍀
C11
33␮F
PWRGD
R13
10k⍀
Figure 19. 45 W, Triple Output DC-DC Converter
REV. 0
D4
10BQ040
(OPTIONAL)
Q4
SI4410
100nF
R4
75k⍀
C14B
10␮F
DRVL3 29
10 CLSET3
C6
1␮F
R14
4.7⍀
R7
12k⍀
ADP3020
Nominal Inductor Value
Standard Inductors
The inductor design is based on the assumption that the inductor ripple current is 30% of the maximum output dc current at
nominal 12 V input voltage. The inductor ripple current and
inductance value are not critical, but this choice is quite important in analyzing the trade-offs between cost, size, efficiency,
and volume. The higher the ripple current, the lower the inductor size and volume. However, this will lead to higher ac losses
in the windings. Conversely, a higher inductor value means
lower ripple current and smaller output filter capacitors, but
transient response will be slower.
Buying a standard inductor will provide the fastest, easiest solution, and many companies offer suitable power inductor solutions.
A list of power inductor manufacturers is given in Table V.
DESIGNING THE INDUCTOR IN-HOUSE
Core Material Concerns
The design of the inductor should be based on the maximum
output current plus 15% (1/2 of the 30% ripple allowance) at
the nominal input voltage:
(
)
L ≥ 3 × VIN( NOM) – VOUT ×
VOUT
VIN( NOM) × IOUT × f
(5)
Optimum standard inductor values for the three power levels are
shown in Table IV.
Table IV. Standard Inductor Values
Freq.
3.3 V/2 A 3.3 V/4 A 3.3 V/10 A 5 V/2 A 5 V/4 A 5 V/10 A
200 kHz 20 µH
300 kHz 12 µH
400 kHz 10 µH
8.2 µH
6.8 µH
4.7 µH
3.3 µH
2.2 µH
1.5 µH
22 µH
15 µH
10 µH
10 µH
8.2 µH
6.8 µH
4.7 µH
3.3 µH
2.2 µH
Inductor Selection
Once the value for the inductor is known, there are two ways to
proceed; either to design the inductor in-house or to buy the
closest inductor that meets the overall design goals.
There are several good choices for low core loss materials at
high frequency. Two examples are distributed gap Kool Mu
powdered cores from Magnetics and soft ferrite cores, material
3F3, 3F4, 3D3, or 4C4, from Philips. To minimize the ac core
loss, especially when the inductor value is relatively low and
ripple current is high, the use of low frequency powdered iron
cores and low frequency ferrite cores (specified for frequency up
to 100 kHz) should be avoided. The ripple current is a key factor for optimization of the converter design and determines core
losses to a large extent. Selecting a high ripple current means
a relatively low inductor value. This, for a given core size,
reflects a lower number of turns and higher core loss.
Core Geometry
There are two main categories of ferromagnetic cores that could
be used in this type of application. Open magnetic loop types
such as beads, beads on leads, rods, and slugs provide the lowest cost, but do not have focused magnetic fields in the core.
The radiated EMI distributed around the magnetic field may
create problems with noise interference in electronic circuits
surrounding the choke. Other types are cores with closed magnetic paths, such as pot cores, PQ, U, and E cores, toroids, etc.
The cost of these cores is higher, but EMI and RFI performance
is better. A good compromise between price and performance
are cores with a toroidal shape, used primarily in through-hole
printing board designs. A very cost-effective solution based, not
on closed-loop core, but on good shielded open-loop core, are
surface-mount power inductors, DO, DT, and DS Series from
Coilcraft.
Table V. Recommended Inductor Manufacturers
Coilcraft
Coiltronics
Murata Electronics
North America Inc.
Phone: 847/639-6400
Fax: 847/639-1469
Web: www.coilcraft.com
Phone: 561/241-7876
Fax: 561/241-9339
Web: www.coiltronics.com
Phone: 770/436-1300
Fax: 770/436-3030
Web: www.murata.com
SMT Power Inductors,
Series 1608, 3308, 3316, 5022, 5022HC,
DO3340, Low Cost Solution
SMT Shielded Power Inductors,
Series DS5022, DS3316, DT3316,
Best for Low EMI/RFI
SMT Power Inductors,
Series UNI-PAC2, UNI-PAC3 and UNI-PAC4,
Low Cost Solution
SMT Power Inductors,
Series, ECONO-PAC, VERSA-PAC,
Best for Low Profile or Flexible Design.
SMT Power Inductors,
Series LQT2535
Best for Low EMI/RFI
Power Inductors and Chokes,
Series DC1012, PCV-0, PCV-1, PCV-2,
PCH-27, PCH-45, Low Cost
Power Inductors CTX Series,
Low EMI/RFI, Low Cost Toroidal Inductors
but Not Miniature.
Chip Inductors
LQN6C, LQS66C
–14–
REV. 0
ADP3020
The Design
The details of designing the power inductor are covered in many
reference texts, and will not be covered here. Examples of software and reference books that can be used for quick design of
the power inductor are given below:
Software—Magnetic Designer from Intusoft, www.intusoft.com
“Designing Magnetic Components for High Frequency
DC-DC Converters,” McLyman, Kg Magnetics Inc.,
ISBN 1-883107-00-08 (for advanced users)
“Power Supply Cookbook,” Marty Brown, EDN Series for
Design Engineers, ISBN 0-7506-9442-4 (for beginners and
intermediate users)
CIN and COUT Selection
In continuous conduction mode, the source current of the upper
MOSFET is approximately a square wave of duty cycle VOUT/VIN.
To prevent large voltage transients, a low ESR input capacitor
sized for the maximum rms current must be used. The maximum
rms capacitor current is given by:
(
)
I RMS ≈ VOUT × VIN – VOUT ×
I MAX
VIN
(6)
This formula has a maximum at VIN = 2 × VOUT, where IRMS =
IOUT/2. Note that the capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor, or to choose a capacitor
rated at a higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements in the
design. If electrolytic or tantalum capacitors are used, an additional 0.1 µF–1 µF ceramic bypass capacitor should be placed in
parallel with CIN.
The selection of COUT is driven by the required effective series
resistance (ESR) and the desired output ripple. A good rule of
thumb is to limit the ripple voltage to 1% of the nominal output
voltage. It is assumed that the total ripple is caused by two factors:
25% comes from the COUT bulk capacitance value, and 75%
comes from the capacitor ESR. The value of COUT can be determined by:
COUT
I RIPPLE
=
2 × f × VRIPPLE
where IRIPPLE = 0.3 × IOUT and VRIPPLE = 0.01 × VOUT. The
maximum acceptable ESR of COUT can then be found using:
ESR ≤ 0.75 ×
V RIPPLE
I RIPPLE
(8)
Manufacturers such as Vishay, AVX, Elna, WIMA and Sanyo
provide good high-performance capacitors. Sanyo’s OSCON
semiconductor dielectric capacitors have lower ESR for a given
size, at a somewhat higher price. Choosing sufficient capacitors
to meet the ESR requirement for COUT will normally exceed
the amount of capacitance needed to meet the ripple current
requirement.
In surface-mount applications, multiple capacitors may have to
be paralleled to meet the capacitance, ESR, or RMS current
handling requirements. Aluminum electrolytic and dry tantalum
capacitors are available in surface-mount configurations. In the
case of tantalum, it is critical that capacitors are surge tested for
use in switching power supplies. Recommendations for output
capacitors are shown in Table VI.
Power MOSFET Selection
N-channel power MOSFETs must be selected for use with the
ADP3020 for both the main and synchronous switch. The main
selection parameters for the power MOSFETs are the threshold
voltage (VGS(TH)) and ON-resistance (RDS(ON)). An internal LDO
generates a 5 V supply that is boosted above the input voltage
using a bootstrap circuit. This floating 5 V supply is used for the
upper MOSFET gate drive. Logic-level threshold MOSFETs
must be used for both the main and synchronous switches.
Maximum output current (IMAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3020 is
operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting the
load current. The duty cycles for the MOSFETs are given by:
VOUT
VIN
(9)
VIN – VOUT
VIN
(10)
Upper MOSFET Duty Cycle =
Lower MOSFET Duty Cycle =
(7)
Table VI. Recommended Capacitor Manufacturers
Maximum Output
Current
Input Capacitors
Output Capacitors
+3.3 V Output
Output Capacitors
+5 V Output
REV. 0
2A
4A
10 A
TOKIN Multilayer
Ceramic Caps, 22 µF/25 V
P/N: C55Y5U1E226Z
TAIYO YUDEN INC.
Ceramic Caps, Y5V Series
10 µF/25 V
P/N: TMK432BJ106KM
SANYO POSCAP TPC
Series, 68 µF/10 V
SANYO POSCAP TPC
Series, 68 µF/10 V
TOKIN Multilayer
Ceramic Caps, 2 × 22 µF/25 V
P/N: C55Y5U1E226Z
TAIYO YUDEN INC.
Ceramic Caps, Y5V Series
2 ×10 µF/25 V
P/N: TMK432BJ106KM
SANYO POSCAP TPC
Series, 2 × 68 µF/10 V
SANYO POSCAP TPC
Series, 2 × 68 µF/10 V
TOKIN Multilayer
Ceramic Caps, 2 × 22 µF/25 V
P/N: C55Y5U1E226Z
VISHEY Ceramic Caps,
Z5U Series, 2 × 15 µF/25 V
–15–
SANYO POSCAP TPB
Series, 2 × 220 µF/4.0 V
SANYO POSCAP TPB
Series, 2 × 330 µF/6.3 V
ADP3020
From the duty cycle, the required minimum RDS(ON) for each
MOSFET can be derived by the following equations:
Table VII. Recommended MOSFETs
Upper MOSFET:
R DS (ON ) (Upper ) =
V IN × PD
2
(
VOUT × I MAX × 1 + α∆T
)
(11)
Lower MOSFET:
RDS(ON ) (Lower ) =
(V
IN
VIN × PD
)
2
(
– VOUT × I MAX × 1 + α∆T
)
Maximum
Output
2A
4A
10 A
Vishay/
Siliconix
Si4412DY,
28 mΩ
Si4410DY,
13.5 mΩ
Si4874DY,
7.5 mΩ
International
Rectifier
IRF7805,
11 mΩ
IRF7811,
8.9 mΩ
IRF7805,
11 mΩ
IRFBA3803,
5.5 mΩ
IRF7809,
7.5 mΩ
(12)
Soft Start
where PD is the allowable power dissipation and α is the temperature dependency of RDS(ON). PD will be determined by efficiency
and/or thermal requirements (see Efficiency ). (1 + α∆T) is generally given for a MOSFET in the form of a normalized RDS(ON)
vs. temperature curve, but α = 0.007/°C can be used as an
approximation for low voltage MOSFETs.
The soft-start time of each of switching regulator can be programmed by connecting a soft-start capacitor to the corresponding
soft-start pin (SS3 or SS5). The time it takes each regulator to
ramp up to its full duty ratio depends proportionally on the
values of the soft-start capacitors. The charging current is 4 µA
± 20%. The capacitor value to set a given soft-start time, tSS, is
given by:
Maximum MOSFET power dissipation occurs at maximum
output current, and can be calculated as follows:
C SS ≅ 4 µA ×
Upper MOSFET:
PD (Upper ) =
2
VOUT
× I MAX × RDS (ON ) × (1 + α∆T )
VIN
SS
(15)
Fixed or Adjustable Output Voltage
(13)
Lower MOSFET:
PD ( Lower ) =
(t ) ( pF )
2.6 V
2
VIN – VOUT
× I MAX × RDS (ON ) × (1 + α∆T ) (14)
VIN
The Schottky diode, D1 shown in Figure 19, conducts only during
the dead time between conduction of the two power MOSFETs.
D1’s purpose is to prevent the body-diode of the lower N-channel
MOSFET from turning on and storing charge during the dead
time, which could cost as much as 1% in efficiency. D1 should
be selected for forward voltage of less than 0.5 V when conducting
IMAX. Recommended transistors for upper and lower MOSFET’s
are given in Table VII.
Each switching controller of the ADP3020 can be programmed
to operate with a fixed or adjustable output voltage. As shown
by the general application schematic in Figure 19, putting the
ADP3020 into fixed mode gives a nominal output of 3.3 V and
5 V for the two switching buck converters. By using two identical resistor dividers per converter, any output voltage between
1.25 V and VIN–0.5 V can be set. The center point of one divider
is connected to the feedback pin, FB, and the center point of the
other identical divider is connected to EAN. It is important to use
1% resistors. A good value for the lower leg resistors is 10 kΩ,
1%, then the upper leg resistors for a given output voltage can
be determined by:
RUPPER =
VOUT – 1.2 V
( kΩ)
0.12
(16)
Table VIII shows the resistor values for the most common output voltages.
Table VIII. Typical Feedback Resistor Values
VOUT
1.25 V
1.3 V
1.5 V
1.8 V
2.0 V
2.5 V
3.0 V
3.3 V
5.0 V
RUPPER
RLOWER
412 Ω
10 kΩ
825 Ω
10 kΩ
2.49 kΩ
10 kΩ
4.99 kΩ
10 kΩ
6.65 kΩ
10 kΩ
10.7 kΩ
10 kΩ
15.0 kΩ
10 kΩ
17.4 kΩ
10 kΩ
31.6 kΩ
10 kΩ
–16–
REV. 0
ADP3020
PWM Mode/Power-Saving (PSV) Mode Operation
Transient Response Considerations
The mode of operation for both switching regulators can be preset
using the MODE pin. When MODE is HIGH, or connected to
INTVCC, both converters work only in PWM mode, regardless
of output current. MODE connected to GND makes both converters operate in a dual PWM/PSV mode of operation. In dual
mode, each converter has its own boundary output current when
the converter switches from PSV mode to PWM mode and vice
versa. There is an output current hysteresis for each mode transition to avoid improper operation.
Both stability and regulator loop response can be checked by
looking at the load transient response. Switching regulators take
several cycles to respond to a step in output load current. When
a load step occurs, output voltage shifts by an amount equal to
the current step multiplied by the total ESR of the summed output
capacitor array. Output overshoot or ringing during the recovery
time (in both directions of the current step change) indicates a
stability problem. The external feedback compensation components shown in Figure 18 should provide adequate
compensation for most applications.
There are several design recommendations regarding dual mode
operation. The trip output current level for switching between
PWM mode and PSV mode is a percentage of the peak current
sensed via the internal current sense comparator. However,
the value of that current depends on the RDS(ON) of the upper
MOSFET. For example, if the design uses an Si4420 versus an
Si4410 power MOSFET (9 mΩ vs. 13.5 mΩ) the maximum
output power of the converter and the mode trip output current
will both be 50% higher.
Efficiency Enhancement
The efficiency of each switching regulator is inversely proportional to the losses during the switching conversion. The main
factors to consider when attempting to maximize efficiency are:
Feedback Loop Compensation
The ADP3020 uses Voltage Mode control to stabilize the switching controller outputs. Figure 20 shows the voltage mode control
loop for one of the buck switching regulators. The internal reference voltage VREF is applied to the positive input of the internal
error amplifier. The other input of the error amplifier is EAN,
and is internally connected to the feedback sensing pin FB via an
internal resistor. The error amplifier creates the closed-loop
voltage level for the pulsewidth modulator that drives the external
power MOSFETs. The output LC filter smooths the pulsewidth modulated input voltage to a dc output voltage.
ADP3020
1. Resistive losses, which include the RDS(ON) of upper and
lower MOSFETs, trace resistances and output choke wire
resistance.
PWM
COMPARATOR
VIN
DRVH
L1
VRAMP
These losses contribute a major part of the overall power loss
in low voltage battery-powered applications. However, trying
to reduce these resistive losses by using multiple MOSFETs
and thick traces may tend to lead to lower efficiency and higher
price. This is due to the trade-off between reduced resistive
loss and increased gate drive loss that must be considered
when optimizing efficiency.
VOUT
COUT
DRVL
C2
PARASITIC
ESR
EAO
C1 R2
C3
EAN
2. Switching losses due to the limited time of switching transitions.
This occurs due to gate drive losses of both upper and lower
MOSFETs, and switching node capacitive losses, as well as
through hysteresis and eddy-current losses in power choke.
Input and output capacitor ripple current losses should also
be considered as switching losses. These losses are inputvoltage-dependent and can be estimated as follows:
PSWLOSS = 2.5 × VIN
1.85
× I MAX × C SN × f
(17)
where CSN is the overall capacitance of the switching node
related to loss.
R3
REF
Figure 20. Buck Regulator Voltage Control Loop
The pulsewidth modulator transfer function is VOUT/VEAOUT,
where VEAOUT is the output voltage of the error amplifier. That
function is dominated by the impedance of the output filter with
its double-pole resonance frequency (fLC) and a single zero at
output capacitor (fESR) and the dc gain of the modulator, equal
to the input voltage divided by the peak ramp height (VRAMP),
which is equal to VREF (1.2 V):
3. Supply current of the switching controller (independent of
the input current redirected to supply the MOSFETs’ gates).
f LC =
This is a very small portion of the overall loss, but it does
increase with input voltage.
FESR =
REV. 0
R1
FB
–17–
1
2π ×
L F × COUT
1
2 π × ESR × COUT
(18)
(19)
ADP3020
The compensation network consists of the internal error amplifier and two external impedance networks ZIN and ZFB. Once the
application and the output filter capacitance and ESR are chosen,
the specific component values of the external impedance networks ZIN and ZFB can be determined. There are two design
criteria for achieving stable switching regulator behavior within
the line and load range. One is the maximum bandwidth of the
loop, which affects fast transient response, if needed, and the
other is the minimum accepted by the design phase margin.
Compensation Loop Design and Test Method
1. Choose the gain (R2/R1) for the desired bandwidth.
2. Place fZ1 20%–30% below fLC.
3. Place fZ2 20%–30% above fLC.
4. Place fP1 at fESR, check the output capacitor for worst-case ESR
tolerances.
5. Place fP2 at 40%–60% of oscillator frequency.
6. Estimate phase margins in full frequency range (zero frequency
to zero gain crossing frequency).
The phase margin is the difference between the closed-loop phase
and 180 degrees. Recommended phase margin is 45 to 60 degrees
for most applications.
The equations for calculating the compensation Poles and Zeros
are:
1
f P1 =
2 π × R2 ×
f P2
(20)
1
=
2 π × R3 × C 3
(21)
1
2 π × R2 × C1
(22)
1
2 π × (R1 + R 3) × C 3
(23)
f Z1 =
f Z2 =
C1 × C 2
C1 + C 2
7. Apply the designed compensation and test the transient
response under a moderate step load change (30%–60%) and
various input voltages. Monitor the output voltage via
oscilloscope. The voltage overshoot or undershoot should be
within 1%–3% of the nominal output, without ringing and
abnormal oscillation.
Additional Application Circuits
The multiple outputs and wide input voltage range of the ADP3020
make it a very flexible IC for use in a wide variety of applications.
For example, the ADP3020 can be used to generate low voltage
(<4.0 V) outputs from a 5 V supply. The circuit shown in Figure 21 converts the 5 V input into a 3.3 V and a 2.5 V output.
The circuit of Figure 22 uses a secondary winding on the 5 V
output to generate an unregulated 15 V rail which is then regulated to 12 V by the LDO output of the ADP3020.
The value of the internal resistor R1 is 71 kΩ for the 3.3 V
switching regulator, and 128 kΩ for the 5 V switching regulator.
–18–
REV. 0
ADP3020
VIN
4.5V-5.5V
C22
4.7␮F
C18
2.2nF
R15
10.7k⍀
R10
2.2k⍀
R16
10k⍀
R1
6.9k⍀
C1
150pF
C2
6.8nF
R2
47k⍀
C4
1␮F
C5
1nF
R3
47k⍀
U1
ADP3020
C6
1␮F
R4
75k⍀
C8
470pF
C9
68pF
R11
6.2k⍀
C14A
10␮F
1
CS5
2
FB5
3
EAN5
SW5 36
4
EAO5
DRVL5 35
5
ADJ/FX5
6
SS5
7
CLSET5
8
REF
9
AGND
10 CLSET3
C19
330pF
R14
4.7⍀
BST5 38
DRVH5 37
PGND 34
SD 33
AUXVCC 32
INTVCC 31
VIN 30
SW3 28
12 SYNC
DRVH3 27
14 ADJ/FX3
L2
4.7␮H
Q5
SI4410
D2
10BQ040
D4
10BQ040
(OPTIONAL)
+
C27A
68␮F
+
+
C24A
68␮F
+
C27B
68␮F
C16
1␮F
R13
4.7⍀
R6
10⍀
R5
10⍀
C15
4.7␮F
C13
1␮F
Q2
SI4410
C12
100nF
DRV2 25
FB2 24
16 EAN3
SD2 23
17 FB3
CPOR 22
18 CS3
PWRGD 21
PFO 20
C20A
10␮F
C20B
10␮F
D5
1N4148
Q5
SI4410
L1
4.7␮H
D1
10BQ040
D3
10BQ040
(OPTIONAL)
C26
4.7␮F
R12
10k⍀
R17
100⍀
R9
4.7k⍀
C24B
68␮F
Q1
NDS8434
C28
1␮F
C11
33␮F
PWRGD
Figure 21. 5 V to 2.5 V/3.3 V DC-DC Converter
–19–
VOUT33
3.3V, 4A
VOUT15
1.5V, 1.5A
R8
3.16k⍀
R7
12k⍀
REV. 0
VOUT25
2.5V, 3A
Q4
SI4410
BST3 26
15 EAO3
19 PFI
D6
1N4148
DRVL3 29
11 MODE
13 SS3
C17
100nF
C14B
10␮F
ADP3020
VIN
5.5V-25V
C22
4.7␮F
R14
4.7⍀
C14B
10␮F
C14A
10␮F
C18
150pF
R10
10k⍀
R1
130k⍀
C1
68pF
C2
330pF
R2
47k⍀
C4
1␮F
C5
1nF
R3
47k⍀
U1
ADP3020
1
CS5
2
FB5
3
EAN5
SW5 36
4
EAO5
DRVL5 35
5
ADJ/FX5
6
SS5
7
CLSET5
8
REF
9
AGND
BST5 38
DRVH5 37
PGND 34
SD 33
AUXVCC 32
INTVCC 31
VIN 30
R4
75k⍀
11 MODE
SW3 28
12 SYNC
DRVH3 27
13 SS3
C8
470pF
C9
68pF
C19
330pF
R11
6.2k⍀
Q5
SI4410
L2*
• N2
N1
D2
10BQ040
•
+
C27A
68␮F
+
+
C24A
68␮F
+
C27B
68␮F
VOUT5
5V, 4A
Q4
SI4410
C16
1␮F
R6
10⍀
R5
10⍀
C15
4.7␮F
C13
1␮F
Q2
SI4410
C12
100nF
DRV2 25
15 EAO3
FB2 24
16 EAN3
SD2 23
17 FB3
CPOR 22
18 CS3
PWRGD 21
19 PFI
PFO 20
C14A
10␮F
C14B
10␮F
D5
1N4148
BST3 26
14 ADJ/FX3
R26
60.4k⍀
D6
1N4148
DRVL3 29
10 CLSET3
C6
1␮F
*L2
4.7␮H
N2/N1 =2:1
C17
100nF
Q3
SI4410
L1
6.8␮H
D1
10BQ040
D11
1N4148
C31
4.7␮F
R12
10k⍀
R17
1k⍀
R9
4.7k⍀
C28
1␮F
C24B
68␮F
Q1
2N3906
VOUT33
3.3V, 4A
VOUT12
12V, 100mA
R8
9.09k⍀
C32
4.7␮F
PWRGD
R13
10k⍀
R7
1k⍀
PFO
R24
210k⍀
Figure 22. Using a Secondary Winding and an LDO Post Regulator to Generate 12 V
Layout Considerations
2.
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.
3.
The power and ground planes should overlap each other as
little as possible. It is generally easiest (although not necessary) to have the power and signal ground planes on the same
PCB layer. The planes should be connected nearest to the
first input capacitor where the input ground current flows
from the converter back to the battery.
The following guidelines are recommended for optimal performance of a switching regulator in a portable PC system:
General Recommendations
1.
For best results, a four-layer (minimum) PCB is recommended. This should allow the needed versatility for control
circuitry interconnections with optimal placement, a signal
ground plane, power planes for both power ground and
the input power, and wide interconnection traces in the
rest of the power delivery current paths. Each square unit of 1
ounce copper trace has a resistance of ~ 0.53 mΩ at room
temperature.
–20–
REV. 0
ADP3020
4.
If critical signal lines (including the voltage and current sense
lines of the ADP3020) must cross through power circuitry,
it is best if a signal ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier.
5.
The PGND pin of the ADP3020 should connect first to a
ceramic bypass capacitor on the VIN pin, and then into the
power ground plane using the shortest possible trace. However, the power ground plane should not extend under other
signal components, including the ADP3020 itself. If necessary, follow the preceding guideline to use the signal plane as
a shield between the power ground plane and the signal
circuitry.
6.
The AGND pin of the ADP3020 should connect first to the
REF capacitor, and then into the signal ground plane. In cases
where no signal ground plane can be used, short interconnections to other signal ground circuitry in the power converter
should be used.
7.
The output capacitors of the power converter should be
connected to the signal ground plane even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections
(e.g., the signal circuitry of the power converter) in the signal
ground plane between the input and output capacitors. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
8.
The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the power.
If the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends
to be more dynamic.
9.
Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
Power Circuitry
10. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FETs (and the power Schottky
diode if used), including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces
is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause
high-energy ringing, and it accommodates the high current
demand with minimal voltage loss.
REV. 0
11. A power Schottky diode (1 ~ 2 A dc rating) placed from the
lower FET’s source (anode) to drain (cathode) will help to
minimize switching power dissipation in the upper FET. In
the absence of an effective Schottky diode, this dissipation
occurs through the following sequence of switching events.
The lower FET turns off in advance of the upper FET turning
on (necessary to prevent cross-conduction). The circulating
current in the power converter, no longer finding a path for
current through the channel of the lower FET, draws current through the inherent body-drain diode of the FET.
The upper FET turns on, and the reverse recovery characteristic of the lower FET’s body-drain diode prevents the
drain voltage from being pulled high quickly.
The upper FET then conducts very large current while it
momentarily has a high voltage forced across it, which translates into added power dissipation in the upper FET. The
Schottky diode minimizes this problem by carrying a majority
of the circulating current when the lower FET is turned off,
and by virtue of its essentially nonexistent reverse recovery time.
12. Whenever a power-dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for
this are: improved current rating through the vias (if it is
a current path), and improved thermal performance, especially if the vias are extended to the opposite side of the
PCB where a plane can more readily transfer the heat to
the air.
13. The output power path, though not as critical as the switching power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the output capacitors, and back to the
input capacitors.
14. For best EMI containment, the power ground plane should
extend fully under all the power components except the
output capacitors. These are: the input capacitors, the power
MOSFETs and Schottky diode, the inductor, and any snubbing elements that might be added to dampen ringing. Avoid
extending the power ground under any other circuitry or
signal lines, including the voltage and current sense lines.
Signal Circuitry
15. The CS and SW traces should be Kelvin-connected to the
upper MOSFET drain and source so that the additional
voltage drop due to current flow on the PCB at the current
sense comparator connections does not affect the sensed
voltage. It is desirable to have the ADP3020 close to the output capacitor bank and not in the output power path, so that
any voltage drop between the output capacitors and the
AGND pin is minimized, and voltage regulation is not
compromised.
–21–
ADP3020
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3773–5–4/00 (rev. 0)
38-Lead TSSOP
(RU-38)
0.386 (9.80)
0.378 (9.60)
20
38
0.177 (4.50)
0.169 (4.30)
0.252 (6.40) BSC
1
19
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0200 (0.50)
BSC
0.0106 (0.27)
0.0067 (0.17)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
SEATING
PLANE
0.0433 (1.10)
MAX
–22–
REV. 0