Datasheet
Serial EEPROM series Standard EEPROM
I2C BUS EEPROM (2-Wire)
BR24G01-3A
●General Description
2
BR24G01-3A is a serial EEPROM of I C BUS interface method
●Packages W(Typ.) x D(Typ.)x H(Max.)
●Features
All controls available by 2 ports of serial clock(SCL) and
serial data(SDA)
Other devices than EEPROM can be connected to the
same port, saving microcontroller port
1.6V to 5.5V single power source action most suitable
for battery use
1MHz action is possible (1.7V to 5.5V)
Up to 8 bytes in page write mode
Self-timed programming cycle
Low current consumption
Prevention of write mistake
¾
Write (write protect) function added
¾
Prevention of write mistake at low voltage
More than 1 million write cycles
More than 40 years data retention
Noise filter built in SCL / SDA terminal
Initial delivery state FFh
DIP-T8
TSSOP-B8J
9.30mm x 6.50mm x 7.10mm
3.00mm x 4.90mm x 1.10mm
MSOP8
SOP8
5.00mm x 6.20mm x 1.71mm
2.90mm x 4.00mm x 0.90mm
SOP-J8
VSON008X2030
4.90mm x 6.00mm x 1.65mm
2.00mm x 3.00mm x 0.60mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
Figure 1.
●BR24G01-3A
Capacity
1Kbit
Bit Format
128×8
Type
Power Source
Voltage
Package
BR24G01-3A
DIP-T8
BR24G01F-3A
SOP8
BR24G01FJ-3A
SOP-J8
BR24G01FVT-3A
1.6V to 5.5V
TSSOP-B8
BR24G01FVJ-3A
TSSOP-B8J
BR24G01FVM-3A
MSOP8
BR24G01NUX-3A
VSON008X2030
○Product structure：Silicon monolithic integrated circuit
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○This product is not designed protection against radioactive rays
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BR24G01-3A
Datasheet
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Supply voltage
Power Dissipation
Symbol
Ratings
Unit
VCC
-0.3 to +6.5
V
Pd
Remarks
450 (SOP8)
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
450 (SOP-J8)
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
330 (TSSOP-B8)
When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
310 (TSSOP-B8J)
mW
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
310 (MSOP8)
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
300 (VSON008X2030)
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
800 (DIP-T8)
When using at Ta=25℃ or higher 8.0mW to be reduced per 1℃.
Storage Temperature
Tstg
－65 to +150
℃
Operation Temperature
Topr
－40 to +85
℃
‐
-0.3 to Vcc+1.0
V
The Max value of input voltage / output voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of input voltage
/ output voltage is not under -0.8V.
Junction Temperature
Tjmax
150
℃
Junction temperature at the storage condition
Electrostatic discharge
voltage
(human body model)
VESD
-4000 to +4000
V
Input Voltage /
Output Voltage
●Memory Cell Characteristics (Ta=25℃, Vcc=1.6V to 5.5V)
Limits
Parameter
Min.
Typ.
1,000,000
－
Write cycles *1
40
－
Data retention *1
Max
－
－
Unit
Times
Years
*1Not 100% TESTED
●Recommended Operating Ratings
Parameter
Symbol
Supply voltage
Vcc
Input voltage
VIN
Ratings
1.6 to 5.5
0 to Vcc
Unit
V
●DC Characteristics (Unless otherwise specified, Ta=-40 to +85℃, Vcc =1.6 to 5.5V)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
Input High Voltage1
VIH1
Input Low Voltage1
VIL1
Input High Voltage2
VIH2
Input Low Voltage2
VIL2
Output Low Voltage1
VOL1
Output Low Voltage2
VOL2
Input Leakage Current
Output Leakage Current
Supply Current (Write)
Supply Current (Read)
0.7Vcc
－
Vcc+1.0
V
1.7V≦Vcc≦5.5V
－
0.3Vcc
V
1.7V≦Vcc≦5.5V
－
Vcc+1.0
V
1.6V≦Vcc＜1.7V
－
0.2Vcc
V
1.6V≦Vcc＜1.7V
－
－
0.4
V
IOL=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
－
－
0.2
V
IOL=0.7mA, 1.6V≦Vcc＜2.5V (SDA)
ILI
－1
－
1
μA
VIN=0 to Vcc
ILO
－1
－
1
μA
VOUT=0 to Vcc (SDA)
ICC1
－
－
2.0
ICC2
-
-
2.0
ISB
－
－
2.0
－0.3*1
0.8Vcc
－0.3*1
mA
Standby Current
Conditions
μA
Vcc=5.5V, fSCL=1MHz, tWR=5ms,
Byte write, Page write
Vcc=5.5V, fSCL=1MHz
Random read, current read,
sequential read
Vcc=5.5V, SDA, SCL=Vcc
A0, A1, A2=GND,WP=GND
*1 When the pulse width is 50ns or less, it is -0.8V.
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Datasheet
●AC Characteristics (Unless otherwise specified, Ta=－40 to +85℃)
Parameter
Symbol
Limits
(1.6V≦Vcc＜1.7V)
Min.
Typ.
Max.
Clock Frequency
fSCL
Data Clock “HIGH“ Period
tHIGH
0.6
tLOW
Data Clock “LOW“ Period
SDA, SCL (INPUT) Rise Time
*1
SDA, SCL (INPUT) Fall Time *1
SDA (OUTPUT) Fall Time
*1
Limits
(1.7V≦Vcc≦5.5V)
Min.
Typ.
Max.
Unit
400
－
－
1000
kHz
-
-
0.3
－
－
µs
1.2
-
-
0.5
－
－
µs
-
-
tR
-
-
1
－
－
0.12
µs
tF1
-
-
1
－
－
0.12
µs
tF2
-
-
0.12
－
－
0.12
µs
－
－
µs
－
－
µs
Start Condition Hold Time
tHD:STA
0.6
-
-
0.25
Start Condition Setup Time
tSU:STA
0.6
-
-
0.25
Input Data Hold Time
tHD:DAT
0
-
-
0
－
－
ns
Input Data Setup Time
tSU:DAT
100
-
-
50
－
－
ns
Output Data Delay Time
tPD
0.1
-
0.9
0.05
－
0.45
µs
Output Data Hold Time
tDH
0.1
-
-
0.05
－
－
µs
tSU:STO
0.6
-
-
0.25
－
－
µs
Bus Free Time
tBUF
1.2
-
-
0.5
－
－
µs
Write Cycle Time
tWR
-
-
5
－
－
5
ms
tI
-
-
0.05
－
－
0.05
µs
－
－
µs
Stop Condition Setup Time
Noise Spike Width (SDA, SCL)
WP Hold Time
tHD:WP
1.0
-
-
1.0
WP Setup Time
tSU:WP
0.1
-
-
0.1
－
－
µs
WP High Period
tHIGH:WP
1.0
-
-
1.0
－
－
µs
*1 Not 100% tested
●AC Characteristics Condition
Parameter
Symbol
Condition
Unit
Load Capacitance
CL
100
pF
SDA, SCL (INPUT) Rise Time
tR
20
ns
SDA, SCL (INPUT) Fall Time
Input Data Level
Input/Output Data Timing Reference Level
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tF1
20
ns
VIL1/VIH1
0.2Vcc/0.8Vcc
V
-
0.3Vcc/0.7Vcc
V
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Datasheet
●Serial Input / Output timing
tR
SCL
tF1
70%
70% 70%
70%
30%
30%
tHD:DAT
tSU:DAT
70%
70%
30%
30%
tLOW
tHD:STA
70%
tHIGH
70%
70%
30%
30%
SDA
(入力)
(INPUT)
tDH
tPD
tBUF
70%
70%
SDA
30%
(出力)
(OUTPUT)
30%
30%
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tF2
Figure 2-(a). Serial input / output timing
70%
70%
70%
tSU:STA
tHD:STA
tSU:STO
70%
30%
30%
STOP CONDITION
START CONDITION
Figure 2-(b). Start-stop bit timing
D0
70%
70%
ACK
tWR
write data
(n-th address)
STOP CONDITION
START CONDITION
Figure 2-(c). Write cycle timing
70%
DATA(n)
DATA(1)
D0
D1
70%
ACK
ACK
tWR
30%
30%
tSU:WP
tHD:WP
STOP CONDITION
Figure 2-(d). WP timing at write execution
DATA(n)
DATA(1)
D1
D0
ACK
ACK
tWR
tHIGH:WP
70%
70%
70%
Figure 2-(e). WP timing at write cancel
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Datasheet
●Block Diagram
A0 1
1Kbit
EEPROM
array
8
Vcc
7
WP
6
SCL
5
SDA
8bit
A1 2
Address
decoder
Word
address register
7bit
START
A2 3
Data
register
STOP
Control circuit
ACK
GND 4
Power source
voltage detection
High voltage
generating circuit
Figure 3. Block diagram
●Pin Configuration
A0
1
A1
2
8 Vcc
7 WP
BR24G01-3A
A2
3
6 SCL
GND
4
5 SDA
●Pin Descriptions
Terminal
Name
Input/
Output
Function
A0
Input
Slave address setting*
A1
Input
Slave address setting*
A2
Input
Slave address setting*
GND
－
Reference voltage of all input / output, 0V
SDA
Input/
output
Serial data input serial data output
SCL
Input
Serial clock input
WP
Input
Write protect terminal
Vcc
－
Connect the power source.
*A0, A1 and A2 are not allowed to use as open.
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Datasheet
●Typical Performance Curves
(The following values are Typ. ones)
6
5
5
Ta=-40℃
Ta= 25℃
Ta= 85℃
4
INPUT LOW VOLTAGE: VIL1(V)
INPUT HIGH VOLTAGE: VIH1(V)
6
3
SPEC
2
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
4
3
2
1
SPEC
0
0
0
1
2
3
4
5
0
6
1
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 4. Input High Voltage1,2 VIH1,2
(A0, A1, A2, SCL, SDA, WP)
Figure 5. Input Low Voltage1,2 VIL1,2
(A0, A1, A2, SCL, SDA, WP)
1
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.8
OUTPUT LOW VOLTAGE: VOL2(V)
OUTPUT LOW VOLTAGE: VOL1(V)
2
0.6
SPEC
0.4
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.8
0.6
0.4
SPEC
0.2
0
0
0
1
2
3
4
5
0
6
1
2
3
4
5
L OUTPUT CURRENT: IOL(mA)
L OUTPUT CURRENT: IOL(mA)
Figure 6. Output Low Voltage1 VOL1
(Vcc=2.5V)
Figure 7. Output Low Voltage2 VOL2
(Vcc=1.6V)
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Datasheet
●Typical Performance Curves‐Continued
1.2
OUTPUT LEAKAGE CURRENT: ILO(µA)
INPUT LEAKAGE CURRENT: ILI (µA)
1.2
SPEC
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.8
0.6
0.4
0.2
0
SPEC
1
0.8
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.6
0.4
0.2
0
0
1
2
3
4
5
6
0
1
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 8. Input Leakage Current ILI
(A0, A1, A2, SCL, WP)
Figure 9. Output Leakage Current ILO (SDA)
2.5
SUPPLY CURRENT (READ) : Icc2(mA)
2.5
SUPPLY CURRENT (WRITE) : Icc1(mA)
2
SPEC
2
1.5
Ta=-40℃
Ta= 25℃
Ta= 85℃
1
0.5
SPEC
2
Ta=-40℃
Ta= 25℃
Ta= 85℃
1.5
1
0.5
0
0
0
1
2
3
4
5
0
6
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 10. Supply Current (WRITE) ICC1
(fscl=1MHz)
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1
Figure 11. Supply Current (READ) ICC2
(fscl=1MHz)
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Datasheet
●Typical Performance Curves‐Continued
10000
SPEC
STANDBY CURRENT: I
SCL FREQUENCY: fscl(kHz)
2
SB
(µA)
2.5
Ta=-40℃
Ta= 25℃
Ta= 85℃
1.5
1
0.5
1000
SPEC
100
Ta=-40℃
Ta= 25℃
Ta= 85℃
10
1
0.1
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 12. Standby Current ISB
Figure 13. Clock Frequency fSCL
0.6
0.4
SPEC
0.5
LOW (µs)
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
DATA CLK L TIME : t
DATA CLK H TIME : t
HIGH (µs)
SPEC
0.3
0.1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.4
0.3
0.2
0.1
0
0
0
1
2
3
4
5
6
0
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 15. Data Clock Low Period tLOW
Figure 14. Data Clock High Period tHIGH
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Datasheet
●Typical Performance Curves‐Continued
0.3
HD:STA (µs)
SPEC
0.12
0.1
START CONDITION HOLD TIME: t
SDA (OUTPUT) FALL TIME: t
F2 (µs)
0.14
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.08
0.06
0.04
0.02
0
0
1
2
3
4
5
SPEC
0.25
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.15
0.1
0.05
0
6
0
1
SUPPLY VOLTAGE: Vcc(v)
4
5
6
Figure 17. Start Condition Hold Time tHD:STA
0.3
50
SPEC
HD:DAT
(ns)
0.25
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.15
INPUT DATA HOLD TIME: t
SU:STA (µs)
3
SUPPLY VOLTAGE: Vcc(v)
Figure 16. SDA (OUTPUT) Fall Time tF2
START CONDITION SETUP TIME: t
2
0.1
0.05
0
SPEC
0
-50
Ta=-40℃
Ta= 25℃
Ta= 85℃
-100
-150
-0.05
0
1
2
3
4
5
0
6
SUPPLY VOLTAGE: Vcc(v)
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
Figure 19. Input Data Hold Time tHD:DAT(HIGH)
Figure 18. Start Condition Setup Time tSU:STA
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Datasheet
●Typical Performance Curves‐Continued
60
SU:DAT (ns)
SPEC
0
INPUT DATA SET UP TIME: t
INPUT DATA HOLD TIME: t
HD:DAT (ns)
50
-50
Ta=-40℃
Ta= 25℃
Ta= 85℃
-100
-150
SPEC
50
Ta=-40℃
Ta= 25℃
Ta= 85℃
40
30
20
10
0
0
1
2
3
4
5
6
0
1
SUPPLY VOLTAGE: Vcc(v)
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
Figure 20. Input Data Hold Time tHD:DAT(LOW)
Figure 21. Input Data Setup Time tSU:DAT(HIGH)
0.5
60
PD (µs)
50
OUTPUT DATA DELAY TIME: t
INPUT DATA SET UP TIME: t
SU:DAT
(ns)
SPEC
SPEC
40
Ta=-40℃
Ta= 25℃
Ta= 85℃
30
20
10
0.4
0.3
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.1
SPEC
0
0
0
1
2
3
4
5
6
0
SUPPLY VOLTAGE: Vcc(v)
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
Figure 22. Input Data Setup Time tSU:DAT(LOW)
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Figure 23. ‘L’ Output Data Delay Time tPD0
TSZ02201-0R2R0G100580-1-2
31.May.2013 REV.002
BR24G01-3A
Datasheet
●Typical Performance Curves‐Continued
0.5
0.3
SU:STO (µs)
0.4
STOP CONDITION SET UP TIME: t
OUTPUT DATA DELAY TIME: t
PD (µs)
SPEC
0.3
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.1
SPEC
0
0
1
2
3
4
5
SPEC
0.25
0.2
0.15
0.1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.05
0
0
6
1
5
6
6
SPEC
SPEC
5
INTERNAL WRITING
CYCLE TIME: t W R(ms)
BUF (µs)
0.6
BUS OPEN TIME
BEFORE TRANSMISSION: t
4
Figure 25. Stop Condition Setup Time tSU:STO
Figure 24. ‘H’ Output Data Delay Time tPD1
0.4
3
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
0.5
2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.3
0.2
4
3
2
0.1
1
0
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 26. BUS Free Time tBUF
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Ta=-40℃
Ta= 25℃
Ta= 85℃
Figure 27. Write Cycle Time tWR
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Datasheet
0.3
0.3
0.25
0.25
NOISE REDUCTION
EFECTIVE TIME: t I(SCL L)(µs)
NOISE REDUCTION
EFECTIVE TIME: t I(SCL H)(µs)
●Typical Performance Curves‐Continued
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.15
0.1
0.05
SPEC
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.15
0.1
0.05
SPEC
0
0
0
1
2
3
4
5
0
6
1
SUPPLY VOLTAGE: Vcc(v)
4
5
6
Figure 29. Noise Spike Width tI (SCL L)
0.3
0.3
0.25
0.25
NOISE REDUCTION
EFECTIVE TIME: t I(SDA L)(µs)
NOISE REDUCTION
EFECTIVE TIME: t I(SDA H)(µs)
3
SUPPLY VOLTAGE: Vcc(v)
Figure 28. Noise Spike Width tI (SCL H)
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
2
0.15
0.1
0.05
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.15
0.1
0.05
SPEC
SPEC
0
0
0
1
2
3
4
5
0
6
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 31. Noise Spike Width tI (SDA L)
Figure 30. Noise Spike Width tI (SDA H)
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●Typical Performance Curves‐Continued
0.2
SU:W P (µs)
SPEC
1
0.8
WP DATA SET UP TIME: t
WP DATA HOLD TIME: t
HD:W P(µs)
1.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.6
0.4
0.2
0
SPEC
0.1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0
-0.1
-0.2
-0.3
0
1
2
3
4
5
6
0
1
2
3
4
5
SUPPLY VOLTAGE: Vcc(v)
SUPPLY VOLTAGE: Vcc(v)
Figure 32. WP Hold Time tHD:WP
Figure 33. WP Setup Time tSU:WP
6
1.2
WP EFECTIVE TIME: t
HIGH:W P
( µs)
SPEC
1
0.8
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.6
0.4
0.2
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE: Vcc(v)
Figure 34. WP High Time tHIGH:WP
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●Timing Chart
○I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
2
acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices connected by 2
communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during data
communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
SCL
1-7
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
8
1-7
9
DATA
ACK
8
DATA
9
ACK
Figure 35. Data transfer timing
P
STOP
condition
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge
signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC continues data
output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop cindition
(stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as
shown below.
Setting R /
Setting R /
――
W
W
――
to 0 ------- write (setting 0 to word address setting of random read)
to 1 ------- read
Type
BR24G01-3A
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1
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1 0
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A0
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●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. Up to 8 arbitrary bytes can be written.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 A2 A1 A0
WORD
ADDRESS
WA
* 6
DATA
* Don’t Care bit
WA
0
D7
D0
A
C
K
R A
/ C
W K
S
T
O
P
A
C
K
Figure 36. Byte write cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS(n)
*
1 0 1 0 A2 A1A0
R A
/ C
W K
WA
6
DATA(n)
WA
0
D7
A
C
K
S
T
O
P
DATA(n+7)
D0
* Don’t Care bit
D0
A
C
K
A
C
K
Figure 37. Page write cycle
・During internal write execution, all input commands are ignored, therefore ACK is not sent back.
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, data up to 8 bytes can be written in bulk.
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment")
・As for page write cycle of BR24G01-3A after the significant 4 bits are designated arbitrarily, by continuing data input of 2
bytes or more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be written.
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○Notes on write cycle continuous input
The maximum page numbers of BR24G01-3A are 8 bytes. Any bytes below these can be written.
1 page=8bytes, but the page write cycle time is 5ms at maximum for 8byte bulk write.
It does not stand 5ms at maximum × 8byte=40ms(Max.)
○Internal address increment
Page write mode
06h
0
0
0
WA7
WA4
WA3
WA2
WA1
WA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
Increment
For example, when it is started from address 06h,
therefore, increment is made as below,
06h→07h→00h→01h･･･ which please note.
※06h･･･06 in hexadecimal, therefore, 00000110 becomes a
binary number.
Significant bit is fixed.
No digit up
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not
use it open.
In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
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●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S
T
A
R
T
SDA
LIN E
W
R
I
T
E
SLAVE
ADDRESS
S
T
A
R
T
W ORD
A D D R E S S (n)
WA
* 6
1 0 1 0 A 2A 1A 0
WA
0
R A
/ C
W K
R
E
A
D
S LA V E
ADDRESS
1 0 1 0 A 2 A 1A 0
S
T
O
P
D A TA (n)
D7
A
C
K
R A
/ C
W K
A
C
K
* Don’t Care bit
D0
Figure 38. Random read cycle
S
T
A
R
T
SDA
LINE
S LAV E
AD DRES S
R
E
A
D
S
T
O
P
DA TA (n)
1 0 1 0 A 2A 1A 0
D7
D0
A
C
K
R A
/ C
W K
Figure 39. Current read cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 A1A0
R A
/ C
W K
DATA(n+x)
DATA(n)
D7
S
T
O
P
D0
D7
A
C
K
A
C
K
D0
A
C
K
Figure 40. Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal
'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
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●Software Reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 41-(a), Figure 41-(b), Figure 41-(c))
In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both
'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow,
leading to instantaneous power failure of system power source or influence upon devices.
Dummy clock x 14
SCL
1
2
Start x 2
13
Normal command
14
SDA
Normal command
Figure 41-(a). Dummy clock x 14 + START + START + command input
SCL
Start
Dummy clock x 9
Start
1
2
8
Normal command
9
SDA
Normal command
Figure 41-(b). START + dummy clock x 9 + START + command input
Start x 9
SCL
1
2
3
7
8
Normal command
9
SDA
Normal command
Figure 41-(c). START x 9 + command input
※Start command from START input.
●Acknowledge Polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
Write command
S
T
O
P
S
T Slave
A
R address
T
A
C
K
H
tWR
S
T Slave
A
R address
T
A
C
K
H
…
Second write command
…
S
T Slave
A
R address
T
tWR
A
C
K
H
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
After completion of internal write,
ACK=LOW is sent back, so input
next word address and data in
succession.
Figure 42. Case to continuously write by acknowledge polling
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●WP Valid Timing (Write Cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel
valid area. And, after execution of forced end by WP, standby status gets in.
・Rise of SDA
・Rise of D0 taken clock
SCL
SDA
SCL
D1
D0
ACK
SDA
S
T Slave
A
R address
T
A
C Word
K address
L
ACK
Enlarged view
Enlarged view
SDA
D0
A
C D7 D6 D5 D4 D3 D2 D1 D0
K
L
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
WP cancel valid area
tWR
WP cancel invalid area
WP
Data is not written.
Figure 43. WP valid timing
●Command Cancel by Start Condition and Stop Condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure 44)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Figure 44. Case of cancel by start, stop condition during slave address input
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●I/O Peripheral Circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the supply current.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
①SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of 'H' to
SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including
recommended noise margin 0.2Vcc.
VCC－ILRPU－0.2 VCC ≧ VIH
0.8VCC－VIH
IL
IL=10μA VIH=0.7 VCC
Microcontroller
RPU ≦
∴
Ex.) VCC =3V
from②
RPU ≦
EEPROM
RPU
SDA terminal
A
0.8×3－0.7×3
-6
10×10
IL
IL
Bus line
capacity
≦ 30 ［kΩ］
CBUS
Figure 45. I/O circuit diagram
○ Minimum value of RPU
The minimum value of RPU is determined by the following factors.
When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCC－VOL
≦ IOL
RPU
∴ RPU ≧
VCC－VOL
IOL
②VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended
noise margin 0.1Vcc.
VOLMAX ≦ VIL－0.1 VCC
Ex.) VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from①
RPU
≧
3－0.4
3×10 -3
≧ 867 ［Ω］
And
VOL=0.4［V］
VIL=0.3×3
=0.9［V］
Therefore, the condition ② is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ to several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
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●Cautions on Microcontroller Connection
○RS
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
ACK
SCL
RPU
RS
SDA
'H' output of microcontroller
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
EEPROM
Microcontroller
'L' output of EEPROM
Figure 46. I/O circuit diagram
Figure 47. Input / output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
①SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
(VCC－VOL)×RS
RPU+RS
VCC
RPU
RS
A
VOL
∴
RS
VIL－VOL－0.1VCC
1.1VCC-VIL
≦
IOL
×
RPU
Ex.）VCC=3V VIL=0.3VCC VOL=0.4V RPU=20kΩ
Bus line
capacity
CBUS
VIL
+ VOL+0.1VCC≦VIL
RS
EEPROM
Micro controller
Figure 48. I/O Circuit Diagram
≦
0.3×3－0.4－0.1×3
1.1×3－0.3×3
×
20×10
3
≦ 1.67［kΩ］
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
VCC
≦
RS
RPU
'L'output
RS
∴ RS ≧
Over current I
I
VCC
I
Ex.) VCC=3V, I=10mA
'H' output
RS
Microcontroller
EEPROM
≧
3
-3
10×10
≧ 300［Ω］
Figure 49. I/O circuit diagram
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●I/O Equivalence Circuit
○Input (A2,A1,A0,SCL, WP)
○Input / output (SDA)
Figure 51. Input / output pin circuit diagram
Figure 50. Input pin circuit diagram
●Power-up / Down Conditions
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H’
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
tOFF
Recommended conditions of tR, tOFF,Vbot
tR
tOFF
Vbot
10ms or below 10ms or larger 0.3V or below
Vbot
100 or below 10ms or larger 0.2V or below
0
Figure 52. Rise waveform diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Figure 53. When SCL= 'H' and SDA= 'L'
tSU:DAT
Figure 54. When SCL='L' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P18).
ｃ) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low Voltage Malfunction Prevention Function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●Noise Countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended
to attach a by pass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
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●Operational Notes
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions
exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing
to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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TSZ22111・15・001
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BR24G01-3A
Datasheet
●Part Numbering
B
R
2
4
G
0
1
x
x
x
-
3
A
x
x
BUS type
2
24 : I C
Operating temperature/
Operating Voltage
-40℃ to +85℃ / 1.6V to 5.5V
Capacity
01=01K
Package
Blank : DIP-T8
: SOP-J8
FJ
FVJ : TSSOP-B8J
NUX : VSON008X2030
: SOP8
F
FVT : TSSOP-B8
FVM : MSOP8
Process code
Revision
Packaging and forming specification
E2
: Embossed tape and reel
(SOP8, SOP-J8, TSSOP-B8, TSSOP-B8J)
TR
: Embossed tape and reel
(MSOP8, VSON008X2030)
None : Tube
(DIP-T8)
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TSZ22111・15・001
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BR24G01-3A
Datasheet
●Physical Dimensions Tape and Reel Information
DIP-T8
9.3±0.3
5
1
4
3.2±0.2 3.4±0.3
0.51Min.
6.5±0.3
8
7.62
0.3±0.1
0°−15°
2.54
0.5±0.1
(Unit : mm)
<Tape and Reel information>
Container
Tube
Quantity
2000pcs
Direction of feed
Direction of products is fixed in a container tube
∗ Order quantity needs to be multiple of the minimum quantity.
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TSZ22111・15・001
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BR24G01-3A
Datasheet
SOP8
6
5
1 2
3
4
0.3MIN
7
4.4±0.2
6.2±0.3
8
+6°
4° −4°
0.9±0.15
5.0±0.2
(MAX 5.35 include BURR)
0.595
1.5±0.1
+0.1
0.17 -0.05
S
S
0.11
0.1
1.27
0.42±0.1
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
)
∗ Order quantity needs to be multiple of the minimum quantity.
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Datasheet
SOP-J8
4.9±0.2
(MAX 5.25 include BURR)
7
6
5
1
2
3
4
0.45MIN
8
3.9±0.2
6.0±0.3
+6°
4° −4°
0.545
0.2±0.1
1.375±0.1
S
0.175
1.27
0.42±0.1
0.1 S
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.co
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
)
∗ Order quantity needs to be multiple of the minimum quantity.
27/33
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31.May.2013 REV.002
BR24G01-3A
Datasheet
TSSOP-B8
3.0 ± 0.1
(MAX 3.35 include BURR)
7
6
5
1
2
3
4
4±4
1.0±0.2
0.5±0.15
1PIN MARK
0.525
+0.05
0.145 −0.03
S
0.1±0.05
1.2MAX
1.0±0.05
6.4±0.2
4.4±0.1
8
0.08 S
+0.05
0.245 −0.04
0.08
M
0.65
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.co
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
)
∗ Order quantity needs to be multiple of the minimum quantity.
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BR24G01-3A
Datasheet
TSSOP-B8J
3.0 ± 0.1
(MAX 3.35 include BURR)
5
1
2
3
4
4±4
0.45±0.15
1PIN MARK
0.95±0.2
6
3.0±0.1
7
+0.05
0.145 −0.03
0.525
S
0.1±0.05
4.9±0.2
0.85±0.05
1.1MAX
8
0.08 S
+0.05
0.32 −0.04
0.08
M
0.65
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
www.rohm.co
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
)
∗ Order quantity needs to be multiple of the minimum quantity.
29/33
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BR24G01-3A
Datasheet
MSOP8
4.0±0.2
2.8±0.1
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
1 2 3 4
1PIN MARK
+0.05
0.145 −0.03
0.475
0.08±0.05
0.75±0.05
0.9MAX
S
+0.05
0.22 −0.04
0.08 S
0.65
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1pin
Direction of feed
Reel
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
∗ Order quantity needs to be multiple of the minimum quantity.
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BR24G01-3A
Datasheet
VSON008X2030
3.0±0.1
2.0±0.1
0.6MAX
1PIN MARK
1.5±0.1
0.5
1
4
8
5
0.25
1.4±0.1
0.3±0.1
C0.25
(0.12)
0.08 S
+0.03
0.02 −0.02
S
+0.05
0.25 −0.04
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
4000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
1pin
Reel
www.rohm.co
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
31/33
TSZ02201-0R2R0G100580-1-2
31.May.2013 REV.002
BR24G01-3A
Datasheet
●Marking Diagrams (TOP VIEW)
SOP8(TOP VIEW)
DIP-T8 (TOP VIEW)
Part Number Marking
BR24G01A
Part Number Marking
4 G 0 1 A
LOT Number
LOT Number
1PIN MARK
SOP-J8(TOP VIEW)
TSSOP-B8(TOP VIEW)
Part Number Marking
4 G 0 1 A
4G01A
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
MSOP8(TOP VIEW)
TSSOP-B8J(TOP VIEW)
Part Number Marking
4 G 0
4
LOT Number
A
1 A 3
G
A
Part Number Marking
LOT Number
1PIN MARK
1PIN MARK
VSON008X2030 (TOP VIEW)
Part Number Marking
4 G 0
LOT Number
1 A 3
1PIN MARK
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© 2013 ROHM Co., Ltd. All rights reserved.
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BR24G01-3A
Datasheet
●Revision History
Date
Revision
26.Dec.2012
001
31.May.2013
002
Changes
New Release
P1 Change format of package line-up table and change title.
P.2 Add VESD in Absolute Maximum Ratings
P.5 Add directions in Pin Descriptions
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Datasheet
Notice
●General Precaution
1) Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2) All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
●Precaution on using ROHM Products
1) Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment, transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
2)
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3)
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4)
The Products are not subject to radiation-proof design.
5)
Please verify and confirm characteristics of the final or mounted products in using the Products.
6)
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7)
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8)
Confirm that operation temperature is within the specified range described in the product specification.
9)
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
Datasheet
●Precaution for Mounting / Circuit board design
1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2)
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
●Precautions Regarding Application Examples and External Circuits
1) If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2)
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
●Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
●Precaution for Storage / Transportation
1) Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2)
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3)
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4)
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
●Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
●Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
●Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
●Precaution Regarding Intellectual Property Rights
1) All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2)
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
Datasheet
●Other Precaution
1) The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
2)
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
3)
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
4)
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
5)
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.