Anpec APA0710K-TR 1.1w mono low-voltage audio power amplifier Datasheet

APA0710/0711
1.1W Mono Low-Voltage Audio Power Amplifier
Features
•
Operating Voltage : 2.6V-5.5V
•
APA0710 Compatible with TPA711
General Description
The APA0710 is a bridged-tied load (BTL) or singledended (SE) audio power amplifier developed especially
for low-voltage applications where internal speakers
and external earphone operation are required. The
APA0711 is a only BTL audio power amplifier developed
especially for low-voltage applications where internal
speakers are required. Operating with a 5V supply,
the APA0710/1 can deliver 1.1W of continuous power
into a BTL 8Ω load at 10% THD+N throughout voice
band frequencies. Although this device is characterized
out to 20kHz,its operation is optimized for narrow band
applications such as wireless communications. The
BTL configuration eliminates the need for external
coupling capacitors on the output in most applications,
which is particularly important for small battery-powered
equipment. A unique feature of the APA0710 is that it
allows the amplifier to switch from BTL to SE on the
fly when an earphone drive is required. This eliminates
complicated mechanical switching or auxiliary devices
just to drive the external load. This device features a
shutdown mode for power-sensitive applications with
special depop circuitry to eliminate speaker noise when
exiting shutdown mode. The APA0710/1 are available
in an 8-pin SOP and 8-pin MSOP-P with enhanced
thermal pad.
APA0711 Compatible with TPA751
•
Bridge-Tied Load (BTL) or Single-Ended (SE)
Modes Operation (for APA0710 only)
•
Supply Current
– IDD=1.3mA at VDD=5V ,BTL mode
•
•
– IDD=0.9mA at VDD=3.3V ,BTL mode
Low Shutdown Current
– IDD=0.1µA
Low Distortion
– 630mW, at VDD=5V, BTL, RL=8Ω
THD+N=0.15%
– 280mW, at VDD=3.3V, BTL, RL=8Ω
THD+N=0.15%
•
Output Power
at 1% THD+N
– 900mW, at VDD=5V, BTL, RL=8Ω
– 400mW, at VDD=3.3V, BTL, RL=8Ω
at 10% THD+N
–1.1W at VDD=5V, BTL, RL=8Ω
–480mW at VDD=3.3V, BTL, RL=8Ω
•
•
Depop Circuitry Integrated
Applications
Thermal Shutdown Protection and
Over Current Protection Circuitry
•
•
•
•
•
•
High supply voltage ripple rejection
Surface-Mount Packaging
– 8 pin MSOP-P (with enhanced thermal pad)
power package available
Mobil Phones
PDAs
Digital Camera
Portable Electronic Devices
– SOP-8 package
•
Lead Free Available (RoHS Compliant)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
1
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APA0710/0711
Pin Description
APA0710
APA0711
Shutdown
1
8
VO-
Shutdown
1
8
VO-
Bypass
2
7
GND
Bypass
2
7
GND
SE/BTL
3
6
VDD
IN+
3
6
VDD
IN
4
5
VO+
IN-
4
5
VO+
SOP-8
SOP-8
APA0710
APA0711
Shutdown
1
8
VO-
Bypass
2
7
GND
VDD
IN+
3
6
VDD
VO+
IN-
4
5
VO+
Shutdown
1
8
VO-
Bypass
2
7
GND
SE/BTL
3
6
IN
4
5
MSOP-8-P
MSOP-8-P
NC = No internal connection
= Thermal Pad
(connected to GND plane for better heat dissipation)
Ordering and Marking Information
Package Code
K : SOP-8
XA : MSOP-8-P
Temp. Range
I : -40 to 85 ° C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
APA0710/1
Lead Free Code
Handling Code
Temp. Range
Package Code
APA0710/1 K :
APA0710/1
XXXXX
XXXXX - Date Code
APA0710/1 XA :
A0710/1
XXX
XX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
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APA0710/0711
Block Diagram
RF
V DD
Audio
Input
V DD
6
V DD /2
RI
4
IN
2
Bypass
Cs
_
Vo+
CI
5
+
CC
CB
_
Vo-
8
+
From System Control
1
Shutdown
From HP Jack
3
SE/BTL
Bias
Control
GND
7
APA0710
RF
VDD
Au d i o
In p u t
6
VDD /2
RI
CI
4
IN -
3
IN +
2
Bypass
VDD
Cs
_
Vo+
5
Vo-
8
+
CB
_
+
From S ys te m C o n t r o l
1
Shutdown
Bias
C o n trol
GND
7
APA0711
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
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APA0710/0711
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol
Parameter
Rating
Unit
-0.3 to 6
V
V
VDD
Supply Voltage
VIN
Input Voltage Range, Shutdown, SE/BTL
-0.3 to VDD+0.3
TA
Operating Ambient Temperature Range
-40 to 85
TJ
Maximum Junction Temperature
TSTG
Internally Limited*
°C
-65 to +150
°C
Storage Temperature Range
TS
Soldering Temperature, 10 seconds
VESD
°C
260
2
Electrostatic Discharge
PD
°C
1
Power Dissipation
-2000 to 2000*
V
Internally Limited
W
Note:
1.APA0710/1 integrated internal thermal shutdown protection when junction temperature ramp up to 170°C
2.Human body model: C=100pF, R=1500Ω, 3 positives pulses plus 3 negative pulses
3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Recommended Operating Conditions
Symbol
Parameter
VDD
Supply Voltage
VIH
High-Level Voltage
Test Conditions
Shutdown, Shutdown
Low-Level Voltage
Max.
Unit
2.6
5.5
V
2.2
V
0.9VDD
SE/BTL
VIL
Min.
0.4
Shutdown, Shutdown
V
0.9VDD-1
SE/BTL
Thermal Characteristics
Symbol
Parameter
Value
Unit
RTHJA
Thermal Resistance from Junction to Ambient in Free Air
MSOP-8-P*
50
°C/W
SOP-8
160
* 3.42in 2 printed circuit board with 20z trace and copper through 6 vias of 12mil diameter vias.
The thermal pad on the MSOP-8-P package with solder on the printed circuit board.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
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APA0710/0711
Electrical Characteristics
Electrical Characteristics at Specified Free - Air Temperature
VDD = 3.3V, TA = 25°C (unless otherwise noted)
Symbol
Parameter
VOO
Output Offset Voltage
IDD
Supply Current
IDD(SD)
Supply Current,
Shutdown Mode
|IH|
|IL|
Test Conditions
APA0710/1
Min.
Typ.
Max.
20
RL = 8Ω, R F = 10kΩ
BTL mode, RF = 10kΩ
0.9
1.8
SE mode, RF = 10kΩ
0.55
1.1
RF = 10kΩ
0.1
2
Shutdown, VI = V DD
1
Shutdown, VI = V DD
1
SE/BTL, VI = VDD
1
Shutdown, VI = 0V
1
Shutdown, VI = 0V
1
SE/BTL, VI = 0V
1
Unit
mV
mA
µA
µA
µA
Operating characteristic, VDD = 3.3V, T A = 25°C, RL = 8Ω
PO
THD+N
Bom
B1
Output Power (Note 1)
THD = 1%, BTL mode, RL = 8Ω
400
THD = 1%, SE mode, RL = 32Ω
40
Total Harmonic Distortion
PO = 280mW, BTL mode, R L = 8Ω
Plus Noise (Note 1)
Maximum Output Power
Gain = 2, THD+N = 2%
Bandwidth
Unity-Gain Bandwidth
Open Loop
mW
0.15
%
20
kHz
2
MHz
Power Supply Rejection
Ratio (Note1)
CB = 1µF, BTL mode, RL = 8Ω
74
CB = 1µF, SE mode, RL = 8Ω
61
Vn
Noise Output Voltage
Gain = 1, CB = 0.1µF
28
µV(rms)
T WU
Wake-up time
CB = 1µF
380
ms
PSRR
dB
VDD= 5V, TA = 25°C (unless otherwise noted)
Symbol
Parameter
VOO
Output Offset Voltage
IDD
Supply Current
IDD(SD)
Supply Current ,
Shutdown Mode
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
Test Conditions
APA0710/1
Min.
Typ.
Max.
20
RL = 8Ω, R F = 10kΩ
BTL mode, RF = 10kΩ
1.3
2.6
SE mode, RF = 10kΩ
0.75
1.5
RF = 10kΩ
0.1
2
5
Unit
mV
mA
µA
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APA0710/0711
Electrical Characteristics(Cont.)
Electrical Characteristics at Specified Free - Air Temperature (Cont.)
VDD= 5V, TA= 25°C (unless otherwise noted)
Symbol
Parameter
|IH|
|IL|
Test Conditions
APA0710/1
Min.
Typ.
Max.
Shutdown, VI = VDD
1
Shutdown, VI = VDD
1
SE/BTL, VI = VDD
1
Shutdown, VI = 0V
1
Shutdown, VI = 0V
1
SE/BTL, VI = 0V
1
Unit
µA
µA
Operating characteristic, VDD = 5V, TA = 25°C, RL = 8Ω
THD = 1%, BTL mode, RL = 8Ω
900
THD = 1%, SE mode, RL = 32Ω
Total Harmonic Distortion PO = 630mW, BTL mode,
THD+N
(Note 1)
Plus Noise
RL = 8Ω
Maximum Output Power
Bom
Gain = 2, THD+N = 2%
Bandwidth
B1
Unity-Gain Bandwidth
Open Loop
94
(Note 1)
Output Power
PO
PSRR
Vn
Twu
mW
0.15
%
20
kHz
2
MHz
Power Supply Rejection
(Note1)
Ratio
CB = 1µF, BTL mode, RL = 8Ω
74
CB = 1µF, SE mode, RL = 8Ω
61
Noise Output Voltage
Gain = 1, CB = 0.1µF
28
µV(rms)
Wake-up time
CB = 1µF
400
ms
dB
Note1 : Output power is measured at the output terminals of device at f=1KHz.
Pin Description
APA0710
Pin
I/O
Description
1
I
Shutdown mode control signal input, place entire IC in shutdown mode
when held high.
Bypass
2
I
Bypass pin
SE/BTL
3
I
When SE/BTL is held low, the APA0710 is in BTL mode. When SE/BTL is
held high, the APA0710 is in SE mode
IN
4
I
In is the audio input terminal
VO+
5
O VO+ is the positive output for BTL and SE modes
VDD
6
Supply voltage input pin
GND
7
Ground connection for circuitry
VO-
8
Name
No
Shutdown
O
VO- is the negative output in BTL mode and a high-impedance output in SE
mode
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
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APA0710/0711
Pin Description
APA0711
Pin
I/O
Description
1
I
Shutdown mode control signal input, place entire IC in shutdown mode
when held low.
Bypass
2
I
Bypass pin
IN+
3
I
IN+ is the non-inverting input. IN+ is typically tied to the Bypass terminal.
IN-
4
I
IN- is the inverting input. IN- is typically used as the audio input terminal.
VO+
5
O VO+ is the positive BTL output.
VDD
6
Supply voltage input pin.
GND
7
Ground connection for circuitry.
VO-
8
O VO- is the negative BTL output.
Name
No
Shutdown
Typical Application Circuit
for APA0710 Application
RF
1 0kΩ
Audio
Input
V DD
RI
10k Ω
V DD /2
4
Vo+
CI
0.47 µ F
2
CC
330 µ F
_
IN
Bypass
V DD
6
Cs
1µ F
5
+
1kΩ
CB
1µF
_
Vo-
From System Control
1
3
0.1 µ F
+
Shutdown
SE/BTL
8
7
Bias
Control
GND
100k Ω
V DD
100k Ω
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
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APA0710/0711
Typical Application Circuit (Cont.)
for APA0711 Application
RF
1 0 kΩ
Audio
Input
VD D
RI
6
VDD/2
1 0k Ω
CI
0.47 µ F
4
IN-
3
IN+
2
Byp a s s
VD D
Cs
_
1µ F
Vo+
5
Vo-
8
+
CB
1µ F
_
+
From S ystem Control
1
Shutdown
7
Bias
Control
GND
for APA0711 Differential Input Application
RF
1 0 kΩ
Audio C I
RI
Input- 0.47 µ F 1 0k Ω
VD D
6
VDD/2
4
3
IN+
2
Bypass
Cs
1µ F
_
IN-
VD D
Vo+
5
Vo-
8
+
RI
10k Ω R F
Audio
Input+
1 0 kΩ
CI
0.47 µ F
CB
1µ F
_
+
From S ys tem Control
1
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
Shutdown
Bias
Control
8
7
GND
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APA0710/0711
Typical Characteristics
PSRR vs. Frequency
PSRR vs. Frequency
+0
No-Capacitor
Ripple Rejection Ration (dB)
Ripple Rejection Ration (dB)
+0
-20
-40
CB=0.1µF
CB=1µF
-60
CB=2.2µF
-80
VDD=3.3V
RL=8Ω
SE
-100
20
100
1k
No-Capacitor
-20
-40
-60
CB=2.2µF
-80
VDD=5V
RL=8Ω
SE
-100
20
10k 20k
100
Frequency (Hz)
1600
RF=10kΩ
CB=1µF
BTL
1400
Supply Current (µA)
Ripple Rejection Ration (dB)
10k 20k
Supply Current vs. Supply Voltage
TRL=8Ω
-20
1k
Frequency (Hz)
PSRR vs. Frequency
+0
CB=0.1µF
CB=1µF
-40
-60
VDD=3.3V
1200
BTL(SE/BTL=0.1VDD)
1000
800
600
400
SE(SE/BTL=0.9VDD)
-80
VDD=5V
-100
20
200
0
100
1k
2.5
10k 20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
3
3.5
4
4.5
5
5.5
Supply Voltage(V)
9
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APA0710/0711
Typical Characteristics (Cont.)
Output Power vs. Supply Voltage
Supply Current vs. Supply Voltage
0.12
1200
RF=10kΩ
Output Power (mW)
Supply Current (uA)
1000
0.11
0.1
0.09
THD+N=1%
f=1kHz
BTL
800
600
RL=8Ω
400
200
0.08
2.5
3
3.5
4
4.5
5
RL=32Ω
0
2.5
5.5
3
3.5
5
5.5
Output Power vs. Load Resistance
Output Power vs. Supply Voltage
1000
400
THD+N=1%
f=1kHz
SE
800
300
250
RL=8Ω
200
150
RL=32Ω
100
50
0
2.5
THD+N=1%
f=1kHz
BTL
900
Output Power (mW)
Output Power (mW)
4.5
Supply Voltage(V)
Supply Voltage(V)
350
4
700
600
500
VDD=5V
400
300
200
VDD=3.3V
100
0
3
3.5
4
4.5
5
8
5.5
Rev. A.5 - Oct., 2005
24
32
40
48
56
64
Load Resistance(Ω)
Supply Voltage(V)
Copyright  ANPEC Electronics Corp.
16
10
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APA0710/0711
Typical Characteristics (Cont.)
Output Power vs. Load Resistance
THD+N vs. Frequency
350
10
THD+N=1%
f=1kHz
SE
1
200
150
VDD=5V
AV=-10V/V
AV=-2V/V
0.1
100
50
VDD=3.3V
0
8
16
24
32
40
48
56
0.01
20
64
100
THD+N vs. Output Power
THD+N vs. Frequency
10
VDD=3.3V
f=1kHz
AV=-2V/V
BTL
VDD=3.3V
RL=8Ω
AV=-2V/V
BTL
Po=50mW
1
1
THD+N (%)
10
Po=125mW
Po=250mW
0.1
0.01
20
10k 20k
1k
Frequency (Hz)
Load Resistance(Ω)
THD+N (%)
AV=-20V/V
250
THD+N (%)
Output Power (mW)
300
VDD=3.3V
Po=250mW
RL=8Ω
BTL
RL=8Ω
0.1
0.01
100
1k
10k
0
20k
Rev. A.5 - Oct., 2005
0.2
0.3
0.4
0.5
0.6
Output Power (W)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
0.1
11
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
f=10kHz
AV=-20V/V
f=20kHz
1
THD+N (%)
1
THD+N (%)
VDD=5V
Po=700mW
RL=8Ω
BTL
f=1kHz
0.1
f=20Hz
0.01
0.01
VDD=3.3V
RL=8Ω
CB=1µF
AV=-2V/V
BTL
AV=-10V/V
0.1
AV=-2V/V
0.01
0.1
20
1
100
Output Power (W)
10k
20k
THD+N vs. Output Power
THD+N vs. Frequency
10 R R
10
VDD=5V
RL=8Ω
AV=-2V/V
BTL
VDD=5V
f=1kHz
AV=-2V/V
BTL
1
1
Po=50mW
THD+N (%)
THD+N (%)
1k
Frequency (Hz)
Po=700mW
0.1
Po=350mW
0.01
RL=8Ω
0.1
0.01
20
100
1k
10k 20k
0.1
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
0.3
0.5
0.7
0.9
1.1 1.2
Output Power (W)
12
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
1
f=10kHz
AV=-10V/V
f=20kHz
THD+N (%)
THD+N (%)
1
f=1kHz
0.1
f=20Hz
VDD=5V
RL=8Ω
CB=1µF
AV =2V/V
BTL
0.1
0.001
20
1
1k
10k 20k
Frequency (Hz)
THD+N vs. Frequency
THD+N vs. Output Power
10
VDD=3.3V
f=1kHz
RL=32Ω
AV=-1V/V
1 SE
RL=32Ω
AV=-1V/V
SE
THD+N (%)
1
THD+N (%)
100
Output Power (W)
10 R
VDD=3.3V
Po=10mW
0.1
Po=15mW
0.01
100
1k
10k
0.001
0.02
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
0.1
0.01
Po=30mW
20
AV=-5V/V
0.1
AV=-1V/V
0.01
0.01
0.001
VDD=3.3V
Po=30mW
RL=32Ω
SE
0.025
0.03
0.035
0.04
0.045
0.05
Output Power (W)
13
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Frequency
10
10 T T TTTTTTTTT T TTTTTTTTTTTTTTTTTTTTTTTTTTTT
VDD=3.3V
RL=32Ω
AV=-1V/V
SE
1
VDD =5V
Po=60mW
RL=32Ω
SE
1
AV=-10V/V
THD+N (%)
THD+N (%)
f=20Hz
0.1
f=20kHz
f=10kHz
f=1kHz
0.01
0.001
0.002
AV=-5V/V
0.1
AV=-1V/V
0.01
0.001
20
0.1
0.01
100
10k
1k
Output Power (W)
Frequency (Hz)
THD+N vs. Frequency
THD+N vs. Output Power
10 R R R R
20k
10
VDD=5V
RL=32Ω
AV=-1V/V
SE
VDD=5V
f=1kHz
RL=32Ω
AV=-1V/V
SE
1
THD+N (%)
THD+N (%)
1
Po=15mW
0.1
Po=30mW
0.1
0.01
Po=60mW
0.01
0.001
20
100
1k
10k
20k
0.02
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
0.04
0.06
0.08
0.1
0.12
0.14
Output Power (W)
14
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Output Power
10
VDD=3.3V
Po=0.1mW
RL=10kΩ
SE
1
1
f=20kHz
THD+N (%)
THD+N (%)
10
T
VDD=5V
RL=32Ω
AV=-1V/V
SE
f=20Hz
0.1
AV=-2V/V
0.1
AV=-1V/V
0.01
f=10kHz
AV=-5V/V
f=1kHz
0.01
0.002
0.01
0.1
100
20
0.2
Output Power (W)
10
THD+N (%)
VDD=3.3V
RL=10kΩ
AV=-1V/V
SE
THD+N (%)
1
Po=0.1mW
Po=0.13mW
100
1
0.01
1k
10k
20k
50
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
VDD=3.3V
f=1kHz
RL=10kΩ
AV=-1V/V
SE
0.1
Po=0.05mW
20
20k
THD+N vs. Output Power
THD+N vs. Frequency
0.01
10k
Frequency (Hz)
10
0.1
1k
75
100
125
150
175
200
Output Power (µW)
15
www.anpec.com.tw
APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Frequency
10 T T T T
T
VDD=5V
Po=0.3mW
RL=10kΩ
SE
VDD=3.3V
RL=10kΩ
AV=-1V/V
SE
1
THD+N (%)
THD+N (%)
1
f=20Hz
f=20kHz
0.1
0.1
AV=-5V/V
AV=-1V/V
0.01
AV=-2V/V
f=10kHz
f=1kHz
0.01
50
200
100
300
0.001
20
400 500
THD+N vs. Frequency
20k
THD+N vs. Output Power
10
VDD=5V
RL=10kΩ
AV=-1V/V
SE
1
1
THD+N (%)
THD+N (%)
10k
Frequency (Hz)
Output Power (µW)
10
1k
100
0.1
Po=0.2mW
Po=0.1mW
VDD=5V
f=1kHz
RL=10kΩ
AV=-1V/V
SE
0.1
0.01
0.01
Po=0.3mW
0.001
50
0.001
20
100
1k
10k
20k
Rev. A.5 - Oct., 2005
150
200
250
300
350
400
450
500
Output Power (µW)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
100
16
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APA0710/0711
Typical Characteristics (Cont.)
Close Loop Gain and Phase vs. Frequency
THD+N vs. Output Power
10
VDD=5V
RL=10kΩ
AV=-1V/V
SE
+28
f=20Hz
0.1
f=20kHz
f=10kHz
0.01
+180
Phase
+20
+140
+16
+12
+100
Gain
+8
VDD=3.3V
RL=8Ω
AV=-4V/V
Po=250mW
BTL
+4
f=1kHz
-0
0.001
10
100
10
500
100
Output Power (µW)
1k
10k
Phase(°)
Close Loop Gain (dB)
1
THD+N (%)
+220
+24
+60
+20
100k
Frequency (Hz)
Close Loop Gain and Phase vs. Frequency
Close Loop Gain and Phase vs. Frequency
+300
+10
+28
+220
+8
+260
Gain
+12
+100
Gain
+8
VDD=5V
RL=8Ω
AV=-4V/V
Po=700mW
BTL
+4
-0
+60
+220
+4
+2
+180
Phase
+0
+140
-2
+100
-4
VDD=3.3V
RL=32Ω
AV=-2V/V
Po=30mW
SE
-6
-8
+20
Phase(°)
+140
+16
Close Loop Gain (dB)
Phase
+20
+6
+180
Phase(°)
Close Loop Gain (dB)
+24
+60
+20
-10
10
100
1k
10k
100k
10
Rev. A.5 - Oct., 2005
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
100
17
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APA0710/0711
Typical Characteristics (Cont.)
Close Loop Gain and Phase vs. Frequency
+10
+8
+260
Gain
+6
RL= 8Ω, BTL
+2
Noise Floor (µVrms)
+220
+4
+180
Phase
+0
+140
-2
+100
-4
VDD=5V
RL=32Ω
AV=-2V/V
Po=60mW
SE
-6
-8
Phase(°)
Close Loop Gain (dB)
Noise Floor vs. Frequency
100
+300
10
RL= 32Ω, SE
+60
VDD=3.3V
BW=22Hz to 22kHz
AV=-1V/V
+20
1
-10
10
100
1k
10k
100k
20
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Power Dissipation vs. Output Power
Noise Floor vs. Frequency
100
Power Dissipation (mW)
350
RL= 8Ω, BTL
Noise Floor (µVrms)
100
10
RL= 32Ω, SE
VDD =5V
BW=22Hz to 22kHz
AV=-1V/V
300
RL=8Ω
250
200
150
100
RL=32Ω
50
VDD=3.3V
BTL
0
1
20
100
1k
0
10k 20k
Rev. A.5 - Oct., 2005
400
600
Output Power (mW)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
200
18
www.anpec.com.tw
APA0710/0711
Typical Characteristics (Cont.)
Power Dissipation vs. Output Power
Power Dissipation vs. Output Power
100
800
700
80
Power Dissipation (mW)
Power Dissipation (mW)
90
RL=8Ω
70
60
50
40
30
20
RL=32Ω
VDD=3.3V
SE
10
RL=8Ω
600
500
400
300
200
RL=32Ω
VDD=5V
BTL
100
0
0
0
50
100
150
0
Output Power (mW)
200
400
600
800
1000
Output Power (mW)
Power Dissipation vs. Output Power
200
Power Dissipation (mW)
180
RL=8Ω
160
140
120
100
80
60
RL=32Ω
VDD=5V
SE
40
20
0
0
50
100
150
200
250
300
Output Power (mW)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
19
www.anpec.com.tw
APA0710/0711
Application Descriptions
supply, no need DC voltage exists across the load.
This eliminates the need for an output coupling
capacitor which is required in a single supply, SE
configuration.
BTL Operation
Vo+
Single-Ended Operation
OP1
Consider the single-supply SE configuration shown
Application Circuit. A coupling capacitor is required to
block the DC offset voltage from reaching the load.
These capacitors can be quite large (approximately
33µF to 1000µF) so they tend to be expensive, occupy
valuable PCB area, and have the additional drawback
of limiting low-frequency performance of the system
(refer to the Output Coupling Capacitor).
RL
Vo-
Vbias
OP2
Figure1:
APA0710/1 power amplifier internal configuration
The power amplifier OP1 gain is setting by external
gain setting, while the second amplifier OP2 is
internally fixed in a unity-gain, inverting configuration.
Figure 1 shows that the output of OP1 is connected
to the input to OP2, which results in the output
signals of with both amplifiers with identical in
magnitude, but out of phase 180°. Consequently, the
differential gain for each channel is 2X (Gain of SE
mode).
The rules described still hold with the addition of the
following relationship :
1
1
1
≤
<<
(1)
Cbypass× 80kO (RI + RF) × CI
RLCC
Output SE/BTL Operation (for APA0710 only)
The ability of the APA0710 to easily switch between
BTL and SE modes is one of its most important costs
saving features. This feature eliminates the requirement
for an additional headphone amplifier in applications
where internal speakers are driven in BTL mode but
By driving the load differentially through outputs Vo+
and Vo-, an amplifier configuration commonly referred
to as bridged mode is established. BTL mode operation
is different from the classical single-ended SE amplifier
configuration where one side of its load is connected
to ground.
external headphone or speakers must be accommodated.
Internal to the APA0710, two separate amplifiers drive
Vo+ and Vo- (see Figure 2). The SE/BTL input controls
the operation of the follower amplifier that drives Vo-.
A BTL amplifier design has a few distinct advantages
over the SE configuration, as it provides differential
drive to the load, thus doubling the output swing for a
specified supply voltage.
• When SE/BTL is held low, the OP2 is turn on and
the APA0710 is in the BTL mode.
• When SE/BTL is held high, the OP2 is in a high
output impedance state, which configures the
APA0710 as SE driver from Vo+. IDD is reduced by
Four times the output power is possible as compared
to a SE amplifier under the same conditions. A BTL
configuration, such as the one used in APA0710, also
creates a second advantage over SE amplifiers. Since
the differential outputs, Vo+, Vo- are biased at halfCopyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
approximately one-half in SE mode.
Control of the SE/BTL input can be a logic-level TTL
20
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APA0710/0711
Application Descriptions (Cont.)
Output SE/BTL Operation (for APA0710 only)
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit.
Consider the example where Ri is 100kΩ and the
specification calls for a flat bass response down to
40Hz. Equation is reconfigured as follow :
source or a resistor divider network or the mono headphone jack with switch pin as shown in Application
Circuit.
vo +
Ci=
1kΩ
V DD
100k Ω
1
2πRif C
(3)
Consider to input resistance variation, the Ci is 0.04µF
so one would likely choose a value in the range of
Control
Pin
0.1µF to 1.0µF.
SE/BTL
100k Ω
A further consideration for this capacitor is the leakage
path from the input source through the input network
(Ri+Rf, Ci) to the load.
Headphone
Jack
Figure 2: SE/BTL input selection by phonejack plug
In Figure 2, input SE/BTL operates as follows :
This leakage current creates a DC offset voltage at the
input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason a
low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the
positive side of the capacitor should face the amplifier
input in most applications as the DC level there is held
at VDD/2, which is likely higher that the source DC
level. Please note that it is important to confirm the
capacitor polarity in the application.
When the phonejack plug is inserted, the 1kΩ resistor
is disconnected and the SE/BTL input is pulled high
and enables the SE mode.
When this input goes high level, the Vo- amplifier is
shutdown causing the speaker to mute. The Vo+
amplifier then drives through the output capacitor (CC)
into the headphone jack.
When there is no headphone plugged into the system,
the contact pin of the headphone jack is connected
from the signal pin, the voltage divider set up by
resistors 100kΩ and 1kΩ. Resistor 1kΩ then pulls
low the SE/BTL pin, enabling the BTL function.
Effective Bypass Capacitor, Cbypass
As other power amplifiers, proper supply bypassing is
critical for low noise performance and high power
supply rejection.
Input Capacitor, Ci
The capacitors located on the bypass and power
supply pins should be as close to the device as
In the typical application an input capacitor, Ci, is
required to allow the amplifier to bias the input signal
to the proper DC level for optimum operation. In this
case, Ci and the minimum input impedance Ri form a
high-pass filter with the corner frequency determined
in the follow equation :
1
(2)
FC(highpass)=
2πRiCi
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
possible. The effect of a larger half supply bypass
capacitor will improve PSRR due to increased halfsupply stability. Typical application employ a 5V
regulator with 1.0µF and a 0.1µF bypass as supply
filtering. This does not eliminate the need for bypassing
the supply nodes of the APA0710/1. The selection of
21
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APA0710/0711
Application Descriptions (Cont.)
Effective Bypass Capacitor, Cbypass (Cont.)
Power Supply Decoupling, Cs
bypass capacitors, especially Cbypass, is thus
dependent upon desired PSRR requirements, click
and pop performance.
The APA0710/1 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic
distortion (THD) is as low as possible. Power supply
decoupling also prevents the oscillations causing by
long lead length between the amplifier and the speaker.
The optimum decoupling is achieved by using two
different type capacitors that target on different type
of noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good
low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1µF placed as close as possible
to the device VDD lead works best. For filtering lowerfrequency noise signals, a large aluminum electrolytic
capacitor of 10µF or greater placed near the audio
power amplifier is recommended.
To avoid start-up pop noise occurred, the bypass
voltage should rise slower than the input bias voltage
and the relationship shown in equation (4) should be
1
maintained.1
<<
(4)
(R I + R F) × C I
Cbypass × 80kO
The bypass capacitor is fed from a 80kΩ resistor
inside the amplifier. Bypass capacitor, Cbypass, values
of 0.1µF to 2.2µF ceramic or tantalum low-ESR
capacitors are recommended for the best THD and
noise performance.
The bypass capacitance also effects to the start up
time. It is determined in the following equation :
Tstart up = 5 x (Cbypass x 80kΩ)
(5)
Optimizing Depop Circuitry
Output Coupling Capacitor, Cc (for APA0710 only)
Circuitry has been included in the APA0710/1 to
minimize the amount of popping noise at power-up
and when coming out of shutdown mode. Popping
occurs whenever a voltage step is applied to the
speaker. In order to eliminate clicks and pops, all
capacitors must be fully discharged before turn-on.
Rapid on/off switching of the device or the shutdown
function will cause the click and pop circuitry. The
value of Ci will also affect turn-on pops (refer to Effective
Bypass Capacitance). The bypass voltage rise up
should be slower than input bias voltage.
In the typical single-supply (SE) configuration on a
APA0710, an output coupling capacitor (Cc) is required
to block the DC bias at the output of the amplifier thus
preventing DC currents in the load. As with the input
coupling capacitor, the output coupling capacitor and
impedance of the load form a high-pass filter governed
by equation.
FC(highpass)=
1
2πRLCC
(6)
For example, a 330µF capacitor with an 8Ω speaker
would attenuate low frequencies below 60.6Hz. The
main disadvantage, from a performance standpoint, is
the load impedance is typically small, which drives
the low-frequency corner higher degrading the bass
response. Large values of CC are required to pass low
frequencies into the load.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
Although the bypass pin current source cannot be
modified, the size of Cbypass can be changed to alter
the device turn-on time and the amount of clicks and
pops. By increasing the value of Cbypass, turn-on pop
can be reduced. However, the tradeoff for using a larger
bypass capacitor is to increase the turn-on time for
this device. There is a linear relationship between the
22
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APA0710/0711
Application Descriptions (Cont.)
supply to the power delivered to the load. The following
equations are the basis for calculating amplifier
efficiency.
Optimizing Depop Circuitry (Cont.)
size of Cbypass and the turn-on time.
In a SE configuration, the output coupling capacitor,
CC, is of particular concern. This capacitor discharges
through the internal 10kΩ resistors. Depending on the
size of CC, the time constant can be relatively large.
Efficiency =
PO
PSUP
(7)
Where :
VO,RMS x VO,RMS
RL
= VPxVP
2RL
In the most cases, choosing a small value of Ci in the
range of 0.33µF to 1µF, Cbypass being equal to 1µF
should produce a virtually clickless and popless turn-on.
PO =
VP
√2
(8)
A high gain amplifier intensifies the problem as the
small delta in voltage is multiplied by the gain. So it is
advantageous to use low-gain configurations.
PSUP = VDD x IDD,AVG = VDDx 2VP
πRL
(9)
VO,RMS =
Efficiency of a BTL configuration :
Shutdown Function
In order to reduce power consumption while not in use,
the APA0710/1 contains a shutdown function to
externally turn off the amplifier bias circuitry. This
shutdown feature turns the amplifier off when a logic
high is placed on the Shutdown pin for APA0710 and a
logic low on the Shutdown pin for APA0711.
The trigger point between a logic high and logic low
level is typically 0.4VDD. It is best to switch between
ground and the supply voltage VDD to provide maximum
device performance.
Po (W)
Efficiency (%)
VP(V)
PD (W)
0.125
33.6
1.41
0.26
0.25
47.6
2.00
0.29
0.375
58.3
2.45*
0.28
Table 1. Efficiency Vs Output Power in 3.3V/8Ω BTL
Systems.
Table 1 employs equation10 to calculate efficiencies
for three different output power levels when load is 8Ω.
The efficiency of the amplifier is quite low for lower
power levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less than
in the half power range. Calculating the efficiency for a
specific system is the key to proper power supply
design. For a mono 900mW audio system with 8Ω
loads and a 5V supply, the maximum draw on the
BTL Amplifier Efficiency
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the power
Rev. A.5 - Oct., 2005
(10)
*High peak voltages cause the THD to increase.
By switching the Shutdown/Shutdown pin to high level/
low level, the amplifier enters a low-current state, IDD
for APA0710/1. APA0710/1 are in shutdown mode. On
normal operating, APA0710’s Shutdown pin pull to low
level and APA0711’s Shutdown pin should pull to high
level to keeping the IC out of the shutdown mode. The
Shutdown/Shutdown pin should be tied to a definite
voltage to avoid unwanted state changes.
Copyright  ANPEC Electronics Corp.
PO
VPxVP ) / (VDD x2VP ) = πV P
=(
4VDD
PSUP
πRL
2RL
23
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APA0710/0711
Application Descriptions (Cont.)
BTL Amplifier Efficiency (Cont.)
thermal pad, the thermal resistance (θJA) is equal to
50οC/W and 160οC/W, respectively.
power supply is almost 1.5W.
Since the maximum junction temperature (TJ,MAX) of
APA0710/1 are 170οC and the ambient temperature
(T A) is defined by the power system design, the
maximum power dissipation which the IC package is
able to handle can be obtained from equation13. Once
the power dissipation is greater than the maximum
limit (PD,MAX), either the supply voltage (VDD) must be
decreased, the load impedance (RL) must be increased
or the ambient temperature should be reduced.
A final point to remember about linear amplifiers (either
SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when
possible. Note that in equation10, V DD is in the
denominator.
This indicates that as VDD goes down, efficiency goes
up. In other words, use the efficiency analysis to choose
the correct supply voltage and speaker impedance for
the application.
Thermal Pad Considerations
Power Dissipation
The thermal pad must be connected to ground. The
package with thermal pad of the APA0710/1 requires
special attention on thermal design. If the thermal
design issues are not properly addressed, the
APA0710/1 8Ω will go into thermal shutdown when
driving a 8Ω load.
Whether the power amplifier is operated in BTL or SE
modes, power dissipation is a major concern. In
equation11 states the maximum power dissipation
point for a SE mode operating at a given supply
voltage and driving a specified load.
VDD 2
SE mode : PD,MAX=
(11)
2π2RL
The thermal pad on the bottom of the APA0710/1
should be soldered down to a copper pad on the
circuit board. Heat can be conducted away from the
thermal pad through the copper plane to ambient. If
the copper plane is not on the top surface of the circuit
board, 6 to 10 vias of 12 mil or smaller in diameter
should be used to thermally couple the thermal pad to
the bottom plane. For good thermal conduction, the
vias must be plated through and solder filled. The
copper plane used to conduct heat away from the
thermal pad should be as large as practical.
In BTL mode operation, the output voltage swing is
doubled as in SE mode. Thus the maximum power
dissipation point for a BTL mode operating at the same
given conditions is 4 times as in SE mode.
2
BTL mode : PD,MAX= 4V2DD
2π RL
(12)
Since the APA0710/1 is a mono channel power
amplifier, the maximum internal power dissipation is
equal to the both of equations depending on the mode
of operation. Even with this substantial increase in
power dissipation, the APA0710/1 does not require
If the ambient temperature is higher than 25°C, a larger
copper plane or forced-air cooling will be required to
keep the APA0710/1 junction temperature below the
thermal shutdown temperature (170°C).
extra heatsink. The power dissipation from equation12,
assuming a 5V-power supply and an 8Ω load, must
not be greater than the power dissipation that results
from the equation13 :
TJ,MAX - TA
(13)
PD,MAX=
θJA
In higher ambient temperature, higher airflow rate
and/or larger copper area will be required to keep the
IC out of thermal shutdown.
For MSOP-8-P package with and SOP-8 without
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
24
www.anpec.com.tw
APA0710/0711
Packaging Information
E
e1
0.015X45
SOP-8 pin ( Reference JEDEC Registration MS-012)
H
e2
D
A1
1
L
0.004max.
Dim
A
Millimeters
Inches
Min.
Max.
Min.
Max.
A
1.35
1.75
0.053
0.069
A1
D
0.10
4.80
0.25
5.00
0.004
0.189
0.010
0.197
E
H
3.80
5.80
4.00
6.20
0.150
0.228
0.157
0.244
L
e1
0.40
0.33
1.27
0.51
0.016
0.013
0.050
0.020
e2
φ1
1.27BSC
0°
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
0.50BSC
8°
25
0°
8°
www.anpec.com.tw
APA0710/0711
Packaging Information
MSOP-8-P
e1
E
E1
H1
GAUGE
PLANE
D1
L
C
e
0.25
L1
A2
A1
A3
Dim
A1
A2
A3
C
e
e1
E
E1
D1
H1
L
L1
φ
Millimeters
Min.
0.06
Max.
0.15
Min.
0.002
0.86 TYP
0.25
0.13
0.4
0.23
0.01
0.005
3.1
5.0
3.1
0.114
0.189
0.114
0.0126
0.009
0.0256 TYP
2.146 REF
1.740 REF
0.9
0.45
Max.
0.006
0.34 TYP
0.65 TYP
2.90
4.8
2.90
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
Inches
0.122
0.197
0.122
0.0845 REF
0.0685 REF
1.0
0.65
0.036
0.018
6°
0.039
0.026
6°
26
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APA0710/0711
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Time
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
27
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APA0710/0711
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s
Package Thickness
Volume mm 3
Volume mm 3
<350
≥350
<2.5 mm
240 +0/-5°C
225 +0/-5°C
≥2.5 mm
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm 3
Volume mm 3
Volume mm 3
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
D1
28
www.anpec.com.tw
APA0710/0711
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
A
B
330±1
62 ± 1.5
F
D
M/SOP-8
5.5 ± 0.1
C
12.75 +
0.1 5
D1
J
T1
T2
2 + 0.5
12.4 +0.2
2± 0.2
Po
P1
Ao
W
12 + 0.3
- 0.1
Bo
2.0 ± 0.1
6.4 ± 0.1
5.2± 0.1
1.55±0.1 1.55+ 0.25 4.0 ± 0.1
P
E
8± 0.1
1.75± 0.1
Ko
t
2.1± 0.1 0.3±0.013
(mm)
Cover Tape Dimensions
Application
SOP- 8
MSOP- 8
Carrier Width
12
12
Cover Tape Width
9.3
9.3
Devices Per Reel
2500
3000
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
29
www.anpec.com.tw