CY7C1020CV33 32K x 16 Static RAM Features (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). • Pin- and function-compatible with CY7C1020V33 • High speed — tAA = 10, 12, 15 ns • CMOS for optimum speed/power • Low active power — 360 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 44-pin TSOP II Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. Functional Description The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV33 is available in standard 44-pin TSOP Type II packages. Logic Block Diagram Pin Configuration TSOP II Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K × 16 RAM Array I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 BHE WE CE OE BLE NC A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A4 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Selection Guide 1020CV33-10 1020CV33-12 1020CV33-15 Maximum Access Time 10 12 15 ns Maximum Operating Current 90 85 80 mA Maximum CMOS Standby Current 5 5 5 mA Cypress Semiconductor Corporation Document #: 38-05133 Rev. *B • 3901 North First Street • San Jose • Unit CA 95134 • 408-943-2600 Revised August 13, 2002 CY7C1020CV33 DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Ambient Temperature 0°C to +70°C 3.3V ± 10% –40°C to +85°C 3.3V ± 10% Commercial Industrial VCC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 1020CV33-10 1020CV33-12 1020CV33-15 Min. Min. Min. Max. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 VIL Input LOW Voltage[1] −0.3 0.8 –0.3 IIX Input Load Current GND < VI < VCC −1 +1 IOZ Output Leakage Current GND < VI < VCC, Output Disabled −1 +1 IOS[2] Output Short Circuit Current VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 ISB2 2.4 Max. 2.4 0.4 Unit V 0.4 V 2.0 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA 0.4 −300 –300 –300 mA 90 85 80 mA Automatic CE Max. VCC, Power-down Current CE > VIH VIN > VIH or —TTL Inputs VIN < VIL, f = fMAX 15 15 15 mA Automatic CE Max. VCC, Power-down Current CE > VCC – 0.3V, VIN > —CMOS Inputs VCC – 0.3V, or VIN < 0.3V, f = 0 5 5 5 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05133 Rev. *B Page 2 of 8 CY7C1020CV33 AC Test Loads and Waveforms[4] R 317Ω High-Z characteristics: 3.3V R 317Ω 3.3V OUTPUT R2 351Ω 30 pF OUTPUT R2 351Ω 5 pF (a) ALL INPUT PULSES 3.0V 90% GND 10% 10% (b) Rise Time: 1 V/ns Switching Characteristics Over the Operating Range Parameter Description (c) 90% Fall Time: 1 V/ns [4] 1020CV33-10 1020CV33-12 1020CV33-15 Min. Min. Min. Max. Max. Max. Unit Read Cycle tRC Read Cycle Time 10 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 5 6 7 ns Low-Z[5] tLZOE OE LOW to tHZOE OE HIGH to High-Z[5, 6] [5] tLZCE CE LOW to Low-Z tHZCE CE HIGH to High-Z[5, 6] tPU[7] tPD[7] CE LOW to Power-up tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z 12 10 3 12 3 0 3 ns 0 6 0 5 ns 7 12 5 0 ns 3 0 10 ns 7 6 ns 15 ns 7 ns 0 6 ns ns 0 3 0 15 6 5 ns 3 0 5 CE HIGH to Power-down 15 ns 7 ns Write Cycle[8] tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 9 10 ns tAW Address Set-up to Write End 7 8 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 10 ns tSD Data Set-up to Write End 5 6 8 ns tHD Data Hold from Write End 0 0 0 ns [5] tLZWE WE HIGH to Low-Z tHZWE WE LOW to High-Z[5, 6] tBW Byte Enable to End of Write 3 3 5 7 3 6 8 ns 7 9 ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05133 Rev. *B Page 3 of 8 CY7C1020CV33 Switching Waveforms Read Cycle No. 1 [9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for Read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05133 Rev. *B Page 4 of 8 CY7C1020CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [12, 13] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05133 Rev. *B Page 5 of 8 CY7C1020CV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read—All bits Active (ICC) L H Data Out High-Z Read—Lower bits only Active (ICC) L X L BLE BHE I/O1–I/O8 I/O9–I/O16 Mode Power H L High-Z Data Out Read—Upper bits only Active (ICC) L L Data In Data In Write—All bits Active (ICC) L H Data In High-Z Write—Lower bits only Active (ICC) H L High-Z Data In Write—Upper bits only Active (ICC) L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) L X X H H High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 10 CY7C1020CV33-10ZC Z44 44-lead TSOP Type II Commercial CY7C1020CV33-10ZI Z44 44-lead TSOP Type II Industrial 12 CY7C1020CV33-12ZC Z44 44-lead TSOP Type II Commercial CY7C1020CV33-12ZI Z44 44-lead TSOP Type II Industrial CY7C1020CV33-15ZC Z44 44-lead TSOP Type II Commercial CY7C1020CV33-15ZI Z44 44-lead TSOP Type II Industrial 15 Document #: 38-05133 Rev. *B Page 6 of 8 CY7C1020CV33 Package Diagrams 44-Pin TSOP II Z44 51-85087-A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05133 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1020CV33 Document Title: CY7C1020CV33 32K x 16 Static RAM Document Number: 38-05133 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109428 12/16/01 HGK New Data Sheet *A 115045 05/30/02 HGK ICC and ISB1 data modified *B 117615 08/14/02 DFP Pin 1= NC Pin 18 = A4; remove SOJ package option; remove 8ns option. Document #: 38-05133 Rev. *B Page 8 of 8