Cypress CY62137FV18 2-mbit (128k x 16) static ram Datasheet

CY62137FV18 MoBL®
2-Mbit (128K x 16) Static RAM
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both the Byte High
Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),
or during an active write operation (CE LOW and WE LOW).
Features
■
Very high speed: 55 ns
■
Wide voltage range: 1.65 V – 2.25 V
■
Pin compatible with CY62137CV18
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A
■
Ultra low active power
❐ Typical active current: 1.6 mA @ f = 1 MHz
■
Ultra low standby power
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Byte power-down feature
■
Available in a Pb-free 48-Ball Very fine ball grid package
(VFBGA) package
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from the memory
appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a
complete description of read and write modes.
Functional Description
The CY62137FV18 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
Logic Block Diagram
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
128K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Cypress Semiconductor Corporation
Document #: 001-08030 Rev. *H
•
BHE
WE
CE
OE
BLE
A16
A15
A14
A13
BHE
BLE
A11
CE
A12
POWER DOWN
CIRCUIT
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 15, 2010
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CY62137FV18 MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Document #: 001-08030 Rev. *H
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definition ........................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY62137FV18 MoBL®
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62137FV18LL
Min
Typ [1]
Max
1.65
1.8
2.25
55
Standby ISB2 (A)
f = fmax
Typ[1]
Max
Typ[1]
Max
Typ[1]
Max
1.6
2.5
13
18
1
5
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [2, 3]
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS I/O11
NC
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
Document #: 001-08030 Rev. *H
Page 3 of 16
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CY62137FV18 MoBL®
DC Input Voltage [4, 5] ...................................–0.2 V to 2.45 V
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage ........................................ > 2001 V
(MIL-STD-883, Method 3015)
Storage temperature ............................... –65 °C to + 150 °C
Latch up Current .................................................... > 200 mA
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Operating Range
Supply voltage to ground
potential ....................................................–0.2 V to + 2.45 V
Device
DC voltage applied to outputs
in High Z State [4, 5] .......................................–0.2 V to 2.45 V
CY62137FV18
Range
Ambient
Temperature
VCC [6]
Industrial –40 °C to +85 °C 1.65 V to 2.25 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
55 ns
Unit
Min
Typ[7]
Max
1.4
–
–
V
–
0.2
V
VOH
Output high voltage
IOH = –0.1 mA
VOL
Output low voltage
IOL = 0.1 mA
VIH
Input high voltage
VCC =1.65 V to 2.25 V
1.4
–
VCC + 0.2 V
V
VIL
Input low voltage
VCC =1.65 V to 2.25 V
–0.2
–
0.4
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
A
ICC
VCC operating supply
current
f = fmax = 1/tRC
VCC(max) = 2.25 V
IOUT = 0 mA
CMOS levels
–
13
18
mA
f = 1 MHz
VCC(max) = 2.25 V
–
1.6
2.5
mA
[8]
Automatic power down
current–CMOS inputs
CE > VCC0.2 V, or (BHE and BLE) VCC(max) = 2.25 V
> VCC0.2V, VIN > VCC – 0.2 V, VIN
< 0.2 V, f = fmax (address and data
only), f = 0 (OE, WE)
–
1
5
A
ISB2 [8]
Automatic power down
current–CMOS inputs
CE > VCC– 0.2 V, or (BHE and BLE) VCC(max) = 2.25 V
> VCC0.2V, VIN > VCC – 0.2 V, or
VIN < 0.2 V, f = 0
–
1
5
A
ISB1
Capacitance
Parameter[9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max)=VCC+0.5 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
8. Chip enable (CE) and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating
9. Tested initially and after any design or process changes that may affect these parameters
Document #: 001-08030 Rev. *H
Page 4 of 16
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CY62137FV18 MoBL®
Thermal Resistance
Parameter[10]
Description
JA
Thermal resistance
(Junction to Ambient)
Thermal resistance
JC
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
VFBGA
75
Unit
C / W
10
C / W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
INCLUDING
JIG AND
SCOPE
Parameters
R1
R2
RTH
VTH
R2
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
1.80 V
13500
10800
6000
0.80
Unit



V
Note
10. Tested initially and after any design or process changes that may affect these parameters
Document #: 001-08030 Rev. *H
Page 5 of 16
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CY62137FV18 MoBL®
Data Retention Characteristics
Over the Operating Range
Min
Typ[11]
Max
Unit
1.0
–
–
V
–
1
4
A
Chip deselect to data retention time
0
–
–
ns
Operation recovery time
55
–
–
ns
Parameter
VDR
ICCDR
tR
Conditions
VCC for data retention
[12]
tCDR [13]
[14]
Description
Data retention current
VCC = 1.0 V, CE > VCC - 0.2 V, or (BHE and BLE)
> VCC0.2V, VIN > VCC - 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 3. Data Retention Waveform [15]
VCC
CE or
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.0 V
VCC(min)
tR
BHE.BLE
Note
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
12. Chip enable (CE) and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
13. Tested initially and after any design or process changes that may affect these parameters
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s
15. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 001-08030 Rev. *H
Page 6 of 16
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CY62137FV18 MoBL®
Switching Characteristics
Over the Operating Range
Parameter[16, 17]
Description
55 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
ns
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
tLZOE
OE LOW to low Z [18]
5
–
ns
tHZOE
OE HIGH to high Z [18, 19]
–
18
ns
10
–
ns
[18]
tLZCE
CE LOW to low Z
tHZCE
CE HIGH to high Z [18, 19]
–
18
ns
tPU
CE LOW to power up
0
–
ns
tPD
CE HIGH to power down
–
55
ns
tDBE
BLE/BHE LOW to data valid
–
55
ns
tLZBE
BLE/BHE LOW to Low Z [18]
10
–
ns
tHZBE
BLE/BHE HIGH to High Z [18, 19]
–
18
ns
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to high Z [18, 19]
–
18
ns
tLZWE
WE HIGH to low Z [18]
10
–
ns
Write Cycle [20]
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
18. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state
20. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 001-08030 Rev. *H
Page 7 of 16
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CY62137FV18 MoBL®
Switching Waveforms
Figure 4. Read Cycle No.1 (Address Transition Controlled)[21, 22]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
21. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 001-08030 Rev. *H
Page 8 of 16
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CY62137FV18 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled)[ 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 26
tHD
DATAIN
tHZOE
Figure 7. Write Cycle No. 2 (CE Controlled)[24, 25]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 26
tHZOE
Notes
24. Data I/O is high impedance if OE = VIH.
25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-08030 Rev. *H
Page 9 of 16
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CY62137FV18 MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled)[27]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 28
tHD
DATAIN
tLZWE
tHZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[27]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 28
tSD
tHD
DATAIN
tLZWE
Notes
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals
Document #: 001-08030 Rev. *H
Page 10 of 16
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CY62137FV18 MoBL®
Truth Table
CE
WE
OE
BHE BLE
Inputs or Outputs
Mode
Power
H
X
X
X[29]
[29]
X
X
H
H
High Z
Deselect or power down
Standby (ISB)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
High Z
Output dsabled
Active (ICC)
L
H
H
L
H
High Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
X
[29]
High Z
Deselect or power down
Standby (ISB)
X
Note
29. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate
voltage levels on these pins is not permitted
Document #: 001-08030 Rev. *H
Page 11 of 16
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CY62137FV18 MoBL®
Ordering Information
Speed
(ns)
55
Package
Diagram
Ordering Code
CY62137FV18LL-55BVXI
Package Type
Operating
Range
51-85150 48-Ball VFBGA (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of other parts.
Ordering Code Definition
CY
621
3
7F
V18
LL
55
XXX
X
Tem perature Grades
I = Industrial
Package Type BVX: VFBGA (Pb-free)
Speed Grade
Low Power
Voltage Range = 1.8 V typical
Bus W idth = X16
F = 90nm Technology
Density = 2 M bit
M oBL SRAM Fam ily
Com pany ID: CY = Cypress
Document #: 001-08030 Rev. *H
Page 12 of 16
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CY62137FV18 MoBL®
Package Diagram
Figure 10. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
Document #: 001-08030 Rev. *H
Page 13 of 16
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CY62137FV18 MoBL®
Acronyms
Acronym
Description
CMOS
complementary metal oxide semiconductor
I/O
input/output
SRAM
static random access memory
VFBGA
very fine ball grid array
TSOP
thin small outline package
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
A
microamperes
mA
milliampere
MHz
megahertz
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Document #: 001-08030 Rev. *H
Page 14 of 16
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CY62137FV18 MoBL®
Document History Page
Document Title: CY62137FV18 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 001-08030
REV.
ECN NO. Submission
Date
Orig. of
Change
Description of Change
**
463660
See ECN
NXR
New datasheet
*A
469180
See ECN
NSI
Minor change: moved to external web
*B
569125
See ECN
NXR
Converted from preliminary to final
Replaced 45 ns speed bin with 55 ns speed bin
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 A to 1 A
Changed the ISB2(max) value from 2.5 A to 5 A
Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5
A to 4 A
*C
869500
See ECN
VKN
Added footnote #12 related to tACE
*D
908120
See ECN
VKN
Added footnote #8 related to ISB2 and ICCDR
Made footnote #13 applicable to AC parameters from tACE
Changed tWC specification from 45 ns to 55 ns
Changed tSCE, tAW, tPWE, tBW specification from 35 ns to 40 ns
Changed tHZWE specification from 18 ns to 20 ns
*E
1274728
See ECN
*F
2943752
06/03/2010
VKN
*G
3055165
10/12/2010
RAME
Added Contents
Added Acronyms and Units of Measure
Update Package Diagram from *E to *F
Added Ordering Code Definition details.
Changed ISB1/ISB2/ICCDR test conditions to reflect byte power down feature
*H
3061313
10/15/2010
RAME
Minor Changes: Corrected CE to CE and WE to WE in Figures 7 and 8
Document #: 001-08030 Rev. *H
VKN/AESA Changed tWC specification from 55 ns to 45 ns
Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns
Changed tHZWE specification from 20 ns to 18 ns
Added Contents
Added footnote related to Chip enable and Byte enables in Truth Table
Updated Package Diagram
Added Sales, Solutions, and Legal Information
Page 15 of 16
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Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-08030 Rev. *H
Revised October 15, 2010
Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
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