eorex EM48AM1644VBC Preliminary 256Mb (4M×4Bank×16) Synchronous DRAM Features Description • 2 x 4 banks x 2 Mbit x 16 organisation ( Two 128MBit chips stacked in multi-chip package) • Fully Synchronous to Positive Clock Edge • Single 2.7V ~ 3.6V Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length –1/2/4/8/ full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 4/8) • Burst Read with Single-bit Write Operation • Deep Power Down Mode. • Auto Refresh and Self Refresh • Special Function Support. – PASR (Partial Array Self Refresh) – Auto TCSR (Temperature Compensated Self Refresh) • Programmable Driver Strength Control – Full Strength or 1/2, 1/4 of Full Strength • 4,096 Refresh Cycles / 64ms (15.625us) The EM48AM1684VBC is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2 x 4 banks x 2 Mbit by 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.0/3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS. Available packages:TFBGA 54B 12mm x 8mm. Ordering Information Part No Organization Max. Freq Package Grade Pb EM48AM1644VBC-75F 2 die X 8M X 16 133MHz @CL3 TFBGA -54B Commercial Free EM48AM1644VBC-75FE 2 die X 8M X 16 133MHz @CL3 TFBGA -54B Extend temp. Free * EOREX reserves the right to change products or specification without notice. May. 2007 www.eorex.com 1/19 eorex EM48AM1644VBC Preliminary Pin Assignment: BGA 54B 1 2 3 7 8 9 VSS DQ15 VSSQ A VDDQ DQ0 VDD DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5 DQ8 /CS1 VSS E VDD LDQM DQ7 UDQM CLK CKE F /CAS /RAS /WE NC A11 A9 G BA0 BA1 /CS0 A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD 54ball BGA / (12mm × 8mm) May. 2007 www.eorex.com 2/19 eorex Preliminary EM48AM1644VBC Pin Description (Simplified) Pin Name F2 CLK G9,E2 /CS0,/CS1 F3 CKE H7,H8,J8,J7,J3, J2,H3,H2,H1,G3, H9,G2 A0~A11 G7,G8 BA0, BA1 F8 /RAS F7 /CAS F9 /WE F1/E8 UDQM/LDQM A8,B9,B8,C9,C8, D9,D8,E9,E1,D2, D1,C2,C1,B2,B1, A2 A9,E7,J9/ A1,E3,J1 A7,B3,C7,D3/ A3,B7,C3,D7 E2 DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC Function (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) when active All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple memory banks. CS is considered part of the command code (Clock Enable) Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers. (Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM. (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection) This pin is recommended to be left No Connection on the device. May. 2007 www.eorex.com 3/19 eorex Preliminary EM48AM1644VBC Absolute Maximum Rating Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.3 ~ +4.6 V VDD, VDDQ Power Supply Voltage -0.3 ~ +4.6 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +150 V °C 1 W TOP Operating Temperature Range TSTG Storage Temperature Range PD Power Dissipation °C IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=3.3V, f=1MHz, TA=25°C) Symbol Parameter Min. CCLK Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance CI CO Typ. Max. Units 4 8 pF 4 8 pF 6 10 pF Recommended DC Operating Conditions (TA=0°C ~+70°C) Symbol Parameter Min. Typ. Max. Units VDD Power Supply Voltage 2.7 3.3 3.6 V VDDQ Power Supply Voltage (for I/O Buffer) 2.7 3.3 3.6 V Input Logic High Voltage 2.2 VDD+0.3 V -0.3 0.5 V VIH VIL Input Logic Low Voltage Note: * All voltages referred to VSS. * VIH (max.) = 5.6V for pulse width 3ns * VIL (min.) = -2.0V for pulse width 3ns May. 2007 www.eorex.com 4/19 eorex Preliminary EM48AM1644VBC Recommended DC Operating Conditions (VDD=3.3V±0.3V, TA=0°C ~ 70°C) Symbol Parameter (Note 1) ICC1 Operating Current ICC2P Precharge Standby Current in Power Down Mode ICC2PS ICC2N Precharge Standby Current in Non-power Down Mode ICC2NS ICC3P ICC3PS ICC3N Active Standby Current in Power Down Mode Active Standby Current in Non-power Down Mode ICC3NS ICC4 Operating Current (Burst (Note 2) Mode) ICC5 Refresh Current ICC6 (Note 3) Self Refresh Current Test Conditions Max. Units 60 mA 1 mA 1 mA 20 mA 2 mA 10 mA Burst length=1, tRC≥tRC(min.), IOL=0mA, One bank active CKE≤VIL(max.), tCK=15ns CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable CKE≤VIL(max.), tCK=15ns CKE≤VIL(max.), tCK= ∞ CKE≥VIL(min.), tCK=15ns, /CS≥VIH(min.) Input signals are changed one time during 30ns CKE≥VIL(min.), tCK= ∞ , Input signals are stable 2 mA 40 mA 20 mA tCCD≥2CLKs, IOL=0mA 70 mA tRC≥tRC(min.), 95 mA CKE≤0.2V (Note 4) mA 0.4 *All voltages referenced to VSS. Note 1: ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Input signals are changed only one time during tCK (min.) CS0/CS1 interleave for each refresh command. Note 4: Standard power version. Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions IIL Input Leakage Current IOL Output Leakage Current 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled VOH High Level Output Voltage IO=-0.2mA VOL Low Level Output Voltage IO=+0.2mA May. 2007 Min. Typ. Max. Units -5 +5 uA -5 +5 uA 2.4 V 0.4 V www.eorex.com 5/19 eorex Preliminary EM48AM1644VBC Block Diagram May. 2007 www.eorex.com 6/19 eorex EM48AM1644VBC Preliminary AC Operating Test Conditions (VDD=3.3V±0.3V, TA=0°C ~70°C) Item Conditions Output Reference Level 0.5*VDDQ / 0.5* VDDQ Output Load See diagram as below Input Signal Level 2.4V/0.4V Transition Time of Input Signals 1ns Input Reference Level VDDQ/2 AC Operating Test Characteristics (VDD=3.3V±0.3V, TA=0°C ~70°C) Symbol Parameter CL=3 -7.5 Min. Max. 7.5 Units tCK Clock Cycle Time tAC Access Time form CLK tCH CLK High Level Width 3 ns tCL CLK Low Level Width 3 ns tOH Data-out Hold Time tHZ Data-out High Impedance (Note 5) Time tLZ Data-out Low Impedance Time 1.5 ns tIH Input Hold Time 1.5 ns tIS Input Setup Time 2.5 ns CL=2 10 CL=3 6 CL=2 8 CL=3 2.2 CL=2 2.2 ns ns ns CL=3 7 CL=2 9 ns * All voltages referenced to VSS. Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. May. 2007 www.eorex.com 7/19 eorex EM48AM1644VBC Preliminary AC Operating Test Characteristics (Continued) (VDD=3.3V±0.3V, TA=0°C ~70°C) Symbol tRC tRAS tRP tRCD tRRD Parameter ACTIVE to ACTIVE Command (Note 6) Period ACTIVE to PRECHARGE (Note 6) Command Period PRECHARGE to ACTIVE (Note 6) Command Period ACTIVE to READ/WRITE Delay (Note 6) Time ACTIVE(one) to ACTIVE(another) (Note 6) Command -7.5 Min. Max. 67.5 45 Units ns 100K ns 22.5 ns 22.5 ns 15 ns tCCD READ/WRITE Command to READ/WRITE Command 1 CLK tDPL Date-in to PRECHARGE Command 2 CLK 1 CLK tBDL tROH tREF Date-in to BURST Stop Command Data-out to High CL=3 Impedance from CL=2 PRECHARGE Command 3 Refresh Time (4,096 cycle) CLK 64 ms * All voltages referenced to VSS. Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole number) Recommended Power On and Initialization The following power on and initialization sequence guarantees the device is preconditioned to each user’s specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same time) After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register. Because the mode register will power up in an unknown state, it should be loaded prior to apply any operational command. And a extended mode register set command will be issued to program specific mode of self-refresh operation (PASR). Then, the SDRAM is ready for normal operation. May. 2007 www.eorex.com 8/19 eorex EM48AM1644VBC Preliminary SE LF Ex it SE LF Simplified State Diagram E CK E CK ACT T BS ad e wit PR E h Wr i te wit h R ad Re E PR May. 2007 www.eorex.com 9/19 eorex EM48AM1644VBC Preliminary Address Input for Mode Register Set BA1 BA0 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Burst Length Sequential Interleave A2 A1 A0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 Reserved Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Full Page Reserved 1 1 1 Burst Type A3 Interleave 1 Sequential 0 CAS Latency A6 A5 A4 Reserved 0 0 0 Reserved 0 0 1 2 0 1 0 3 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 BA1 BA0 A11 A10 A9 A8 A7 Operation Mode 0 0 0 0 0 0 0 Normal 0 0 0 0 1 0 0 Burst Read with Single-bit Write May. 2007 www.eorex.com 10/19 eorex Preliminary EM48AM1644VBC Burst Type (A3) Burst Length 2 4 8 A2 A1 A0 Sequential Addressing Interleave Addressing X X 0 01 01 X X 0 10 10 X 0 0 0123 0123 X 0 1 1230 1032 X 1 0 2301 2301 X 1 1 3012 3210 0 0 0 01234567 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 76543210 Full Page* n n n Cn Cn+1 Cn+2…… * Page length is a function of I/O organization and column addressing ×16 (CA0 ~ CA8): Full page = 512bits May. 2007 - www.eorex.com 11/19 eorex EM48AM1644VBC Preliminary Extended Mode Register Set ( EMRS ) The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. BA1 BA0 A11 A10 A9 A8 A7 1 0 0 0 0 0 0 A6 A5 DS A4 A3 0 0 A2 A1 A0 PASR Self Refresh Coverage A2 A1 A0 All Banks 0 0 0 Two Banks (BA1=0) 0 0 1 One Bank (BA0=BA1=0) 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Half of One Bank (BA0=BA1=0 ,Row Address MSB=0) 1 0 1 Quarter of One Bank (BA0=BA1=0 ,Row Address 2 MSB=0) 1 1 0 Reserved 1 1 1 Driver Strength A6 A5 full 0 0 1/2 Strength 0 1 1/4 Strength 1 0 Reserved 1 1 BA1 MRS 0 Normal 1 EMRS May. 2007 www.eorex.com 12/19 eorex EM48AM1644VBC Preliminary Output Drive Strength The normal drive strength got all outputs is specified to be LV-CMOS. By setting EMRS specific parameter on A6 and A5, driving capability of data output drivers is selected. Partial Array Self Refresh In EMRS setting ,memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data outside the defined area will not be retained during self-refresh. 1. Command Truth Table Command Symbol CKE n-1 n H X /CS /RAS /CAS /WE BA0, BA1 A10 A11, A9~A10 Ignore Command DESL H X X X X X X No Operation NOP H X L H H H X X X Burst Stop BSTH H X L H H L X X X Read READ H X L H L H V L V READA H X L H L H V H V Write WRIT H X L H L L V L V Write with Auto Pre-charge WRITA H X L L H H V H V Bank Activate ACT H X L L H H V V V Pre-charge Select Bank PRE H X L L H L V L X Pre-charge All Banks PALL H X L L H L X H X L V Read with Auto Pre-charge Mode Register Set MRS H X L L L L L H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input May. 2007 www.eorex.com 13/19 eorex EM48AM1644VBC Preliminary 2. DQM Truth Table Command CKE Symbol n-1 n /CS Data Write/Output Enable ENB H X H Data Mask/Output Disable MASK H X L Upper Byte Write Enable/Output Enable BSTH H X L Read READ H X L READA H X L Write WRIT H X L Write with Auto Pre-charge WRITA H X L Bank Activate ACT H X L Pre-charge Select Bank PRE H X L Pre-charge All Banks PALL H X Read with Auto Pre-charge L Mode Register Set MRS H X H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input L 3. CKE Truth Table Item Activating Any Clock Suspend Idle Command Symbol Clock Suspend Mode Entry Clock Suspend Mode Clock Suspend Mode Exit CKE n-1 n H L L L /CS /RAS /CAS /WE Addr. X X X X X X X X X X L H X X X X X CBR Refresh Command REF H H L L L H X Idle Self Refresh Entry SELF H L L L L L H X Self Refresh Self Refresh Exit H L H H H X L H H X X X X Idle Power Down Entry H L X X X X X X X X X Power Down Power Down Exit L H X Remark H = High level, L = Low level, X = High or Low level (Don't care) May. 2007 www.eorex.com 14/19 eorex EM48AM1644VBC Preliminary 4. Operative Command Table (Note 7) Current State Idle Row Active Read /CS /R /C /W Addr. Command Action H X X X X DESL Nop or power down L H H X X NOP or BST Nop or power down L H L H BA/CA/A10 READ/READA ILLEGAL L L L H L L L H H L H L BA/CA/A10 BA/RA BA, A10 WRIT/WRITA ACT PRE/PALL L L L H X REF/SELF ILLEGAL Row activating Nop Refresh or self refresh L H L L L X H H L X H L L X X H Op-Code X X BA/CA/A10 MRS DESL NOP or BST READ/READA Mode register accessing Nop Nop (Note 11) Begin read: Determine AP L H L L BA/CA/A10 WRIT/WRITA Begin write: Determine AP (Note 9) (Note 8) (Note 8) (Note 9) (Note 9) (Note 10) (Note 11) L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Pre-charge L L H L L L L X H H L L X H H H L X H L X Op-Code X X X REF/SELF MRS DESL NOP BST L H L H BA/CA/A10 READ/READA ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Terminate burst, new read: (Note 13) Determine AP L L L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L L L L H L X Op-Code REF/SELF MRS H X X X X DESL L H H H X NOP L H H L X BST L H L H BA/CA/A10 READ/READA L L L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Write ILLEGAL (Note 12) (Note 10) Terminate burst, start write: (Note 13, 14) Determine AP ILLEGAL (Note 9) Terminate burst, pre-charging (Note 10) ILLEGAL ILLEGAL Continue burst to end → Write recovering Continue burst to end → Write recovering Burst stop → Row active Terminate burst, start read: (Note 13, 14) Determine AP 7, 8 Terminate burst, new write: (Note 13) Determine AP 7 ILLEGAL (Note 9) Terminate burst, pre-charging (Note 15) ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care) L L L L L L H L X Op-Code REF/SELF MRS May. 2007 www.eorex.com 15/19 eorex EM48AM1644VBC Preliminary 4. Operative Command Table (Continued) (Note 7) Current State Read with AP Write with AP Pre-charging Row Activating /CS /R /C /W Addr. Command Action H X X X X DESL L H H H X NOP L L H H H L L H X BA/CA/A10 BST READ/READA Continue burst to end → Pre-charging Continue burst to end → Pre-charging ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L L L L H L L L H L BA, A10 X Op-Code PRE/PALL REF/SELF MRS H X X X X DESL L H H H X NOP L L H H H L L H X BA/CA/A10 BST READ/READA ILLEGAL ILLEGAL ILLEGAL Burst to end → Write recovering with auto pre-charge Continue burst to end → Write recovering with auto pre-charge ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L H L L L L L L X H H H H L L X H H L L H L X H L H BA, A10 X Op-Code X X X BA/CA/A10 PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L L L H L L L L L L L X H H H H H L L X H H L H L H L X H L H BA/RA BA, A10 X Op-Code X X X BA/CA/A10 ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter idle after tRCD Nop → Enter idle after tRCD ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L L L L H L L L H L BA, A10 X Op-Code PRE/PALL REF/SELF MRS (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9, 16) (Note 9) ILLEGAL ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge May. 2007 www.eorex.com 16/19 eorex EM48AM1644VBC Preliminary 4. Operative Command Table (Continued) (Note 7) Current State Write Recovering Write Recovering with AP Refreshing Mode Register Accessing /CS /R /C /W Addr. Command Action H L L L L X H H H H X H H L L X H L H L X X X BA/CA/A10 BA/CA/A10 DESL NOP BST READ/READA WRIT/WRITA Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Start read, Determine AP (Note 14) New write, Determine AP L L H H BA/RA ACT L L L H L L L L L L X H H H H L L X H H L L H L X H L H BA, A10 X Op-Code X X X BA/CA/A10 PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL ILLEGAL ILLEGAL Nop → Enter pre-charge after tDPL Nop → Enter pre-charge after tDPL Nop → Enter pre-charge after tDPL (Note 9, 14) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L L L H L L L L H L L L L L L L X H H L L X H H H H H L L X H L H L X H H L H L H L X X X X X X H L X BA/RA BA, A10 X Op-Code X X X X X X X X X L L X X X ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS ILLEGAL (Note 9) (Note 9) (Note 9) (Note 9) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle. Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. Note 9: Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. Note 11: Illegal if tRCD is not satisfied. Note 12: Illegal if tRAS is not satisfied. Note 13: Must satisfy burst interrupt condition. Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 15: Must mask preceding data which don't satisfy tDPL. Note 16: Illegal if tRRD is not satisfied. May. 2007 www.eorex.com 17/19 eorex EM48AM1644VBC Preliminary 5. Command Truth Table for CKE Current State Self Refresh Self Refresh Recovery Power Down Both Banks Idle CKE n-1 n Any State Other than Listed above /R /C /W Addr. H X X X X X X L L L L L H H H H H H H H H H H H L H H H H L L L L H L L L X H L L L H L L L X H H L X X H H L X H H L X H L X X X H L X X H L X X X X X X X X X X X X X X X X X X X X X X X X X X X H X X X X X X L L H H H H H H H H H H L H H H H H L L L L X X H L L L L H L L L X X X H L L L X H L L X X X X H L L X X H L X X X X X H L X X X H X X L L L L Op-Code H Row Active /CS L Action INVALID, CLK(n-1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) would exit power down Exit power down → Idle Maintain power down mode Refer to operations in Operative Command Table X Op-Code Refresh Refer to operations in Operative Command Table X L X X X X X X H X X X X X X L X X X X X X H H X X X X H L X X X X X (Note 17) Self refresh Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table Begin clock suspend next cycle (Note 18) Exit clock suspend next cycle Maintain clock suspend Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 17: Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. Notes 18: Must be legal command as defined in Operative Command Table L L H L X X X X X X May. 2007 X X X X www.eorex.com 18/19 eorex Preliminary EM48AM1644VBC Package Description May. 2007 www.eorex.com 19/19