AD ADM1067ASU-REEL Super sequencer with open-loop margining dac Datasheet

Super Sequencer® with
Open-Loop Margining DACs
ADM1067
FEATURES
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1
ADM1067
VX1
VX2
VX3
VX4
VX5
SMBus
INTERFACE
VREF
DUALFUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
VP1
VP3
PROGRAMMABLE
RESET
GENERATORS
VP4
(SFDs)
VP2
A0
VH
EEPROM
CONFIGURABLE
OUTPUT
DRIVERS
PDO1
(HV CAPABLE
OF DRIVING
GATES OF
N-CHANNEL FET)
PDO4
CONFIGURABLE
OUTPUT
DRIVERS
PDO7
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO9
SFDGND
VDDCAP
PDO2
PDO3
PDO5
PDO6
PDO8
PDO10
GND
VDD
ARBITRATOR
VCCP
MDN
MUP
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
04635-001
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0 % accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision
Supplies up to 14.4 V on VH
Supplies up to 6 V on VPn (VP1 to VP4)
5 dual-function inputs, VXn (VX1 to VX5)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable output drivers (PDO1 to PDO10)
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Open-loop margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow
voltage adjustment via dc-to-dc converter trim/feedback
node
Device powered by the highest of VPn, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
Available in 2 packages
40-lead, 6 mm × 6 mm LFCSP
48-lead, 7 mm × 7 mm TQFP
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1067 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems. In addition to these
functions, the ADM1067 integrates six 8-bit voltage output
DACs. These circuits can be used to implement an open-loop
margining system, which enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.
(continued on Page 3)
For more information about the ADM1067 register map,
refer to the AN-698 Application Note.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADM1067
TABLE OF CONTENTS
Features .............................................................................................. 1
Warnings...................................................................................... 19
Functional Block Diagram .............................................................. 1
SMBus Jump/Unconditional Jump .......................................... 19
Applications....................................................................................... 1
Sequencing Engine Application Example ............................... 20
General Description ......................................................................... 1
Fault and Status Reporting........................................................ 21
Revision History ............................................................................... 2
Supply Margining ........................................................................... 22
Specifications..................................................................................... 4
Overview ..................................................................................... 22
Pin Configurations and Function Descriptions ........................... 7
Open-Loop Margining .............................................................. 22
Absolute Maximum Ratings............................................................ 9
Writing to the DACs .................................................................. 22
Thermal Resistance ...................................................................... 9
Choosing the Size of the Attenuation Resistor....................... 23
ESD Caution.................................................................................. 9
DAC Limiting/Other Safety Features ...................................... 23
Typical Performance Characteristics ........................................... 10
Applications Diagram .................................................................... 24
Powering the ADM1067 ................................................................ 13
Communicating with the ADM1067........................................... 25
Inputs................................................................................................ 14
Configuration Download at Power-Up................................... 25
Supply Supervision..................................................................... 14
Updating the Configuration ..................................................... 25
Programming the Supply Fault Detectors............................... 14
Updating the Sequencing Engine............................................. 26
Input Comparator Hysteresis.................................................... 15
Internal Registers........................................................................ 26
Input Glitch Filtering ................................................................. 15
EEPROM ..................................................................................... 26
Supply Supervision with VXn Inputs ...................................... 15
Serial Bus Interface..................................................................... 26
VXn Pins as Digital Inputs........................................................ 15
SMBus Protocols for RAM and EEPROM.............................. 29
Outputs ............................................................................................ 17
Write Operations ........................................................................ 29
Supply Sequencing through Configurable Output Drivers .. 17
Read Operations......................................................................... 30
Default Output Configuration.................................................. 18
Outline Dimensions ....................................................................... 32
Sequencing Engine ......................................................................... 19
Ordering Guide .......................................................................... 32
Overview...................................................................................... 19
REVISION HISTORY
11/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features.......................................................................... 1
Changes to Figure 2.......................................................................... 3
Changes to Table 1............................................................................ 4
Changes to Table 2............................................................................ 7
Changes to Absolute Maximum Ratings Section......................... 9
Changes to Programming the Supply Fault
Detectors Section............................................................................ 14
Changes to Table 6.......................................................................... 14
Added the Default Output Configuration Section..................... 18
Changes to Fault Reporting Section............................................. 21
Changes to Figure 28...................................................................... 24
Changes to the Identifying the ADM1067
on the SMBus Section .................................................................... 26
Changes to Figure 30 and Figure 31............................................. 28
Changes to Ordering Guide .......................................................... 32
1/05—Rev. 0 to Rev. A
Changes to Figure 1...........................................................................1
Changes to Absolute Maximum Ratings Section..........................8
Change to Supply Sequencing through Configurable
Output Drivers Section.................................................................. 16
Changes to Figure 28...................................................................... 22
Change to Table 9 ........................................................................... 25
10/04—Revision 0: Initial Version
Rev. B | Page 2 of 32
ADM1067
GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining capability can be used for
in-circuit testing of a board during production (for example, to
verify the board functionality at −5% of nominal supplies). It
can also be used dynamically to accurately control the output
voltage of a dc-to-dc converter.
for driving the gate of an N-channel FET that can be placed in
the path of a supply.
The device provides up to 10 programmable inputs for
monitoring under, over, or out-of-window faults on up to 10
supplies. In addition, 10 programmable outputs can be used as
logic enables. Six of them can also provide up to a 12 V output
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
10µF
REFOUT
REFGND
SDA SCL A1
A0
SMBus
INTERFACE
VREF
ADM1067
The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
DEVICE
CONTROLLER
GPI SIGNAL
CONDITIONING
OSC
EEPROM
CONFIGURABLE
O/P DRIVER
(HV)
SFD
VX1
PDO1
PDO2
VX2
VX3
PDO3
VX4
GPI SIGNAL
CONDITIONING
VX5
VP1
SFD
SELECTABLE
ATTENUATOR
SEQUENCING
ENGINE
SFD
VP2
VP3
CONFIGURABLE
O/P DRIVER
(HV)
PDO4
CONFIGURABLE
O/P DRIVER
(LV)
PDO5
VH
SELECTABLE
ATTENUATOR
PDO8
SFD
CONFIGURABLE
O/P DRIVER
(LV)
AGND
VDDCAP
10µF
PDO6
PDO7
VP4
VDD
ARBITRATOR
PDO9
PDO10
MDN
VCCP
10µF
REG 5.25V
CHARGE PUMP
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
Figure 2. Detailed Block Diagram
Rev. B | Page 3 of 32
PDOGND
GND
04635-002
MUP
ADM1067
SPECIFICATIONS
VH = 3.0 V to 14.4 V 1 , VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPn
VPn
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPn
Additional Currents
All PDO FET Drivers On
Min
Typ
Max
Unit
Test Conditions/Comments
4.75
6.0
14.4
5.4
V
V
V
V
μF
Minimum supply required on one of VPn, VH
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
4.2
6
mA
VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
mA
3.0
2.7
10
1
2.2
1
10
mA
mA
mA
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP
6 DACs on with 100 μA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
±0.05
%
Midrange and high range
Current Available from VDDCAP
DACs Supply Current
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPn Pins
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXn Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
2
6
2.5
±0.05
2.5
1.25
0.573
6
3
1.375
1
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x80 Output Voltage
V
V
%
Low range and midrange
V
V
V
No input attenuation error
MΩ
0.573
Threshold Resolution
Digital Glitch Filter
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
14.4
6
mA
1.375
±1
V
%
8
0
100
Bits
μs
μs
8
Bits
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error +
input attenuation error
Minimum programmable filter length
Maximum programmable filter length
6 DACs are individually selectable for centering on one of four
output voltage ranges
0.592
0.796
0.997
1.247
0.6
0.8
1
1.25
601.25
2.36
0.603
0.803
1.003
1.253
±0.75
±0.4
V
V
V
V
mV
mV
LSB
LSB
Same range, independent of center point
Endpoint corrected
Rev. B | Page 4 of 32
ADM1067
Parameter
Gain Error
Maximum Load Current (Source)
Maximum Load Current (Sink)
Maximum Load Capacitance
Settling Time into 50 pF Load
Load Regulation
PSRR
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance
VOH
IOUTAVG
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH
VOL
IOL 2
ISINK2
RPULL-UP
ISOURCE (VPn)2
Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXn, A0, A1, MUP, MDN)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current,
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
Min
Typ
Max
1
Unit
%
μA
μA
pF
μs
mV
dB
dB
Per mA
DC
100 mV step in 20 ns with 50 pF load
V
mV
mV
μF
dB
No load
Sourcing current, IDACnMAX = −100 μA
Sinking current, IDACnMAX = 100 μA
Capacitor required for decoupling, stability
DC
14
13.5
kΩ
V
V
μA
IOH = 0
IOH = 1 μA
2 V < VOH < 7 V
4.5
V
V
V
VPU (pull-up to VDDCAP or VPn) = 2.7 V, IOH = 0.5 mA
VPU to VPn = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
0.50
20
60
29
2
V
mA
mA
kΩ
mA
10
110
μA
kHz
IOL = 20 mA
Maximum sink current per PDO pin
Maximum total sink for all PDOs
Internal pull-up
Current load on any VPn pull-ups, that is, total source current
available through any number of PDO pull-up switches
configured onto any one
VPDO = 14.4 V
All on-chip time delays derived from this clock
100
100
50
2
2.5
60
40
2.043
2.048
−0.25
0.25
2.053
1
60
11
10.5
500
12.5
12
20
2.4
VPU −
0.3
0
16
20
90
100
2.0
0.8
−1
1
5
20
2.0
0.8
0.4
400
4.7
4.7
4
4.7
V
V
μA
μA
pF
μA
V
V
V
Test Conditions/Comments
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
VIN = 0
VDDCAP = 4.75, TA = 25°C, if known logic state is required
IOUT = −3.0 mA
kHz
μs
μs
μs
μs
Rev. B | Page 5 of 32
ADM1067
Parameter
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
1
2
Min
4
Typ
Max
1000
300
250
5
1
10
Unit
μs
μs
μs
ns
ns
μA
Test Conditions/Comments
VIN = 0
μs
At least one of the VH, VPn pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
Specification is not production tested, but is supported by characterization data at initial product release.
Rev. B | Page 6 of 32
ADM1067
PDOGND
NC
31
VCCP
PDOGND
32
A0
VCCP
33
A1
A0
34
SCL
A1
35
SDA
SCL
36
MUP
SDA
37
MDN
MUP
38
VDDCAP
MDN
39
GND
VDDCAP
40
NC
GND
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
NC 1
36 NC
PIN 1
INDICATOR
30
PDO1
VX1 2
29
PDO2
VX2 3
34 PDO2
VX3 3
28
PDO3
VX3 4
33 PDO3
VX4 4
27
PDO4
VX4 5
26
PDO5
VX5 6
ADM1067
25
PDO6
VP1 7
VP2 7
24
PDO7
VP2 8
TOP VIEW
(Not to Scale)
VP3 8
23
PDO8
VP3 9
28 PDO8
VP4 9
22
PDO9
VP4 10
27 PDO9
VH 10
21
PDO10
VH 11
26 PDO10
NC 12
25 NC
PIN 1
INDICATOR
ADM1067
TOP VIEW
(Not to Scale)
31 PDO5
30 PDO6
29 PDO7
15
16
17
18
19
20
21
22
23
24
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
NC
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
04635-004
14
REFOUT
NC = NO CONNECT
13
NC
20
REFGND
19
DAC6
18
DAC5
17
DAC4
16
DAC3
15
DAC2
14
DAC1
13
NC
AGND
12
REFGND
11
REFOUT
VP1 6
32 PDO4
NC
VX5 5
35 PDO1
AGND
VX2 2
04635-003
VX1 1
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin Number
LFCSP 1 TQFP
13
1, 12, 13, 16,
24, 25, 36,
37, 48
1 to 5
2 to 6
Mnemonic
NC
Description
No Connection.
VX1 to VX5
(VXn)
VP1 to VP4
(VPn)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a
supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V
to 1.375 V.
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
2.048 V Reference Output. Note that the capacitor must be connected between this pin and
REFGND. A 10 μF capacitor is recommended for this purpose.
Voltage Output DACs. These pins default to high impedance at power-up.
6 to 9
7 to 10
10
11
VH
11
12
14
14
15
17
AGND 2
REFGND2
REFOUT
15 to 20
18 to 23
21 to 30
26 to 35
31
32
38
39
DAC1 to
DAC6
PDO10 to
PDO1
PDOGND2
VCCP
33
34
35
36
37
40
41
42
43
44
A0
A1
SCL
SDA
MUP
Programmable Output Drivers.
Ground Return for Output Drivers.
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND. A 10 μF capacitor is recommended for this purpose.
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Open-drain output requires external resistive pull-up.
SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
Digital Input. Forces DACs to their lowest value, causing the voltage at the feedback node to drop.
This is compensated for by an increase in the supply output voltage, thus margining up.
Rev. B | Page 7 of 32
ADM1067
Pin Number
LFCSP 1 TQFP
38
45
Mnemonic
MDN
39
46
VDDCAP
40
47
GND2
1
2
Description
Digital Input. Forces DACs to their highest value, causing the voltage at the feedback node to rise.
This is compensated for by a decrease in the supply output voltage, thus margining down.
Device Supply Voltage. Linearly regulated from the highest of the VPn, VH pins to a typical of 4.75 V.
Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is
recommended for this purpose.
Supply Ground.
Note that the LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.
In a typical application, all ground pins are connected together.
Rev. B | Page 8 of 32
ADM1067
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Voltage on VH Pin
Voltage on VPn Pins
Voltage on VXn Pins
Voltage on A0, A1 Pins
Voltage on REFOUT Pin
Voltage on VDDCAP, VCCP Pins
Voltage on DACn Pins
Voltage on PDOn Pins
Voltage on SDA, SCL Pins
Voltage on GND, AGND, PDOGND, REFGND Pins
Voltage on MUP and MDN Pins
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature
Soldering Vapor Phase, 60 sec
ESD Rating, All Pins
Rating
16 V
7V
−0.3 V to +6.5 V
−0.3 V to +7 V
5V
6.5 V
6.5 V
16 V
7V
−0.3 V to +0.3 V
VDDCAP + 0.6 V
±5 mA
±20 mA
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
40-Lead LFCSP
48-Lead TQFP
ESD CAUTION
215°C
2000 V
Rev. B | Page 9 of 32
θJA
25
50
Unit
°C/W
°C/W
ADM1067
TYPICAL PERFORMANCE CHARACTERISTICS
6
180
160
5
140
120
IVP1 (μA)
3
2
80
60
40
04635-050
1
0
100
0
1
2
3
4
5
20
0
6
04635-053
VVDDCAP (V)
4
0
1
2
3
VVP1 (V)
4
5
6
VVP1 (V)
Figure 5. VVDDCAP vs. VVP1
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
5.0
6
4.5
5
4.0
3.5
3.0
IVH (mA)
3
2
2.0
1.5
1.0
04635-051
1
0
2.5
0
2
4
6
8
10
12
14
04635-054
VVDDCAP (V)
4
0.5
0
16
0
2
4
6
8
10
12
14
16
VVH (V)
VVH (V)
Figure 9. IVH vs. VVH (VH as Supply)
Figure 6. VVDDCAP vs. VVH
5.0
350
4.5
300
4.0
250
IVH (μA)
3.0
2.5
2.0
1.5
200
150
100
1.0
0
1
2
3
4
5
0
6
VVP1 (V)
04635-055
0.5
0
50
04635-052
IVP1 (mA)
3.5
0
1
2
3
4
VVH (V)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
Figure 10. IVH vs. VVH (VH Not as Supply)
Rev. B | Page 10 of 32
5
6
ADM1067
14
10
8
6
DAC 20kΩ
BUFFER
OUTPUT
47pF
4
0
04635-056
2
0
2.5
5.0
7.5
10.0
12.5
PROBE
POINT
1
04635-059
VPDO1 CHARGE PUMPED
12
15.0
ILOAD CURRENT (μA)
CH1 200mV
Figure 11. VPDO1 (FET Drive Mode) vs. ILOAD
M1.00μs
CH1
756mV
Figure 14. Transient Response of DAC Code Change into Typical Load
5.0
4.5
4.0
VPDO1 (V)
3.5
3.0
VP1 = 5V
2.5
VP1 = 3V
2.0
DAC 100kΩ
BUFFER
OUTPUT
1.5
PROBE
POINT
0.5
0
1
2
3
4
5
1
04635-060
04635-057
1.0
6
ILOAD (mA)
CH1 200mV
Figure 12. VPDO1 (Strong Pull-Up to VP) vs. ILOAD
4.5
1.005
4.0
1.004
VP1 = 5V
944mV
1.002
DAC OUTPUT
3.0
2.5
VP1 = 3V
2.0
1.5
1.001
VP1 = 3.0V
1.000
VP1 = 4.75V
0.999
0.998
1.0
0.997
0.5
04635-058
VPDO1 (V)
CH1
1.003
3.5
0
M1.00μs
Figure 15. Transient Response of DAC to Turn-On from HI-Z State
0
10
20
30
40
50
04635-065
0
1V
0.996
0.995
–40
60
ILOAD (μA)
–20
0
20
40
60
TEMPERATURE (°C)
Figure 13. VPDO1 (Weak Pull-Up to VP) vs. ILOAD
Figure 16. DAC Output vs. Temperature
Rev. B | Page 11 of 32
80
100
ADM1067
2.058
VP1 = 3.0V
2.048
VP1 = 4.75V
2.043
2.038
–40
04635-061
REFOUT (V)
2.053
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. REFOUT vs. Temperature
Rev. B | Page 12 of 32
ADM1067
POWERING THE ADM1067
An external capacitor to GND is required to decouple the onchip supply from noise. This capacitor should be connected to
the VDDCAP pin, as shown in Figure 18. The capacitor has
another use during brownouts (momentary loss of power).
Under these conditions, when the input supply (VPn or VH)
dips transiently below VDD, the synchronous rectifier switch
immediately turns off so that it does not pull VDD down. The
VDD capacitor can then act as a reservoir to keep the device
active until the next highest supply takes over the powering of
the device. A 10 μF capacitor is recommended for this
reservoir/decoupling function.
Note that when two or more supplies are within 100 mV of each
other, the supply that first takes control of VDD keeps control.
For example, if VP1 is connected to a 3.3 V supply, VDD powers
up to approximately 3.1 V through VP1. If VP2 is then connected
to another 3.3 V supply, VP1 still powers the device, unless VP2
goes 100 mV higher than VP1.
VDDCAP
VP1
IN
OUT
4.75V
LDO
EN
VP2
IN
OUT
4.75V
LDO
EN
VP3
IN
OUT
4.75V
LDO
EN
VP4
IN
OUT
4.75V
LDO
EN
VH
IN
OUT
4.75V
LDO
EN
SUPPLY
COMPARATOR
Figure 18. VDD Arbitrator Operation
Rev. B | Page 13 of 32
INTERNAL
DEVICE
SUPPLY
04635-022
The ADM1067 is powered from the highest voltage input on
either the positive-only supply inputs (VPn) or the high voltage
supply input (VH). This technique offers improved redundancy,
because the device is not dependent on any particular voltage
rail to keep it operational. The same pins are used for supply
fault detection (discussed in the Supply Supervision section). A
VDD arbitrator on the device chooses which supply to use. The
arbitrator can be considered an OR’ing of five LDOs together. A
supply comparator chooses the highest input to provide the onchip supply. There is minimal switching loss with this
architecture (~0.2 V), resulting in the ability to power the
ADM1067 from a supply as low as 3.0 V. Note that the supply
on the VXn pins cannot be used to power the device.
ADM1067
INPUTS
The resolution is given by
SUPPLY SUPERVISION
The ADM1067 has 10 programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VPn (VP1 to VP4) by default. The other five
inputs are labeled VXn (VX1 to VX5) and have dual
functionality. They can be used as either supply fault detectors,
with similar functionality as VH and VPn, or CMOS-/TTLcompatible logic inputs to the devices. Therefore, the ADM1067
can have up to 10 analog inputs, a minimum of five analog inputs
and five digital inputs, or a combination. If an input is used as
an analog input, it cannot be used as a digital input. Therefore, a
configuration requiring 10 analog inputs has no available digital
inputs. Table 6 shows the details of each of the inputs.
RANGE
SELECT
ULTRA
LOW
+
VPn
VREF
OV
COMPARATOR
–
GLITCH
FILTER
–
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limit of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 5. Voltage Range Limits
Voltage Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
6.0 to 14.4
FAULT
OUTPUT
VB (V)
0.573
1.25
2.5
6.0
VR (V)
0.802
1.75
3.5
9.6
VT = (VR × N)/255 + VB
where:
UV
FAULT TYPE
COMPARATOR
SELECT
04635-023
MID
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
The threshold value required is given by
+
LOW
Step Size = Threshold Range/255
Figure 19. Supply Fault Detector Block
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1067 has up to 10 supply fault detectors (SFDs) on its
10 input channels. These highly programmable reset generators
enable the supervision of up to 10 supply voltages. The supplies
can be as low as 0.573 V and as high as 14.4 V. The inputs can
be configured to detect an undervoltage fault (the input voltage
drops below a preprogrammed value), an overvoltage fault (the
input voltage rises above a preprogrammed value) or an out-ofwindow fault (undervoltage or overvoltage). The thresholds can
be programmed to an 8-bit resolution in registers provided in
the ADM1067. This translates to a voltage resolution that is
dependent on the range selected.
VT is the desired threshold voltage (UV or OV).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is given
by
N = 255 × (VT − VB)/VR
For example, if the user wants to set a 5 V OV threshold on
VP1, the code to be programmed in the PS1OVTH register
(discussed in the AN-698 Application Note) is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
Table 6. Input Functions, Thresholds, and Ranges
Input
VH
Function
High V Analog Input
VPn
Positive Analog Input
VXn
High-Z Analog Input
Digital Input
Voltage Range (V)
2.5 to 6.0
6.0 to 14.4
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
0.573 to 1.375
0 to 5
Maximum Hysteresis
425 mV
1.02 V
97.5 mV
212 mV
425 mV
97.5 mV
N/A
Rev. B | Page 14 of 32
Voltage Resolution (mV)
13.7
32.9
3.14
6.8
13.7
3.14
N/A
Glitch Filter (μs)
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
ADM1067
INPUT COMPARATOR HYSTERESIS
SUPPLY SUPERVISION WITH VXn INPUTS
The UV and OV comparators shown in Figure 19 are always
looking at VPn. To avoid chattering (multiple transitions when
the input is very close to the set threshold level), these comparators have digitally programmable hysteresis. The hysteresis can
be programmed up to the values shown in Table 6.
The VXn inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected
as an analog (SFD) input, the VXn pins have very similar
functionality to the VH and VPn pins. The major difference
is that the VXn pins have only one input range: 0.573 V to
1.375 V. Therefore, these inputs can directly supervise only the
very low supplies. However, the input impedance of the VXn pins
is high, allowing an external resistor divide network to be
connected to the pin. Thus, any supply can be potentially
divided down into the input range of the VXn pin and be
supervised. This enables the ADM1067 to monitor other
supplies such as +24 V, +48 V, and −5 V.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program how much above the
UV threshold the input must rise again before a UV fault is
deasserted. Similarly, the user can program how much below
the OV threshold an input must fall again before an OV fault is
deasserted.
The hysteresis figure is given by
VHYST = VR × NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 6.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators,
allowing the user to remove any spurious transitions such as
supply bounce at turn-on. The glitch filter function is additional
to the digitally programmable hysteresis of the SFD comparators. The glitch filter timeout is programmable up to 100 μs.
For example, when the glitch filter timeout is 100 μs, any pulses
appearing on the input of the glitch filter block that are less than
100 μs in duration are prevented from appearing on the output
of the glitch filter block. Any input pulse that is longer than
100 μs appears on the output of the glitch filter block. The
output is delayed with respect to the input by 100 μs. The
filtering process is shown in Figure 20.
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT
INPUT PULSE LONGER
THAN GLITCH FILTER TIMEOUT
PROGRAMMED
TIMEOUT
PROGRAMMED
TIMEOUT
INPUT
INPUT
TGF
T0
TGF
T0
TGF
T0
TGF
VXn PINS AS DIGITAL INPUTS
As mentioned in the Supply Supervision with VXn Inputs
section, the VXn input pins on the ADM1067 have dual functionality. The second function is as a digital input to the device.
Therefore, the ADM1067 can be configured for up to five digital
inputs. These inputs are TTL-/CMOS- compatible. Standard
logic signals can be applied to the pins: RESET from reset
generators, PWRGD signals, fault flags, manual resets, and so
on. These signals are available as inputs to the SE, and therefore,
can be used to control the status of the PDOs. The inputs can be
configured to detect either a change in level or an edge.
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, once the logic transition is detected, a pulse of
programmable width is output from the digital block. The
width is programmable from 0 μs to 100 μs.
OUTPUT
OUTPUT
The secondary SFDs are fixed to the same input range as the
primary SFD. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be
generated on a single supply using only one pin. For example, if
VP1 is set to output a fault if a 3.3 V supply drops to 3.0 V, VX1
can be set to output a warning at 3.1 V. Warning outputs are
available for readback from the status registers. They are also
OR’ed together and fed into the sequencing engine (SE),
allowing warnings to generate interrupts on the PDOs.
Therefore, in this example, if the supply drops to 3.1 V, a
warning is generated, and remedial action can be taken before
the supply drops out of tolerance.
04635-024
T0
An additional supply supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedicated analog inputs, VPn and VH. The analog function of VX1
is mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is
mapped to VH. In this case, these SFDs can be viewed as a
secondary or warning SFD.
Figure 20. Input Glitch Filter Function
Rev. B | Page 15 of 32
ADM1067
VXn
(DIGITAL INPUT)
When configured as digital inputs, each VXn pin has a weak
(10 μA) pull-down current source available for placing the input
in a known condition, even if left floating. The current source, if
selected, weakly pulls the input to GND.
Rev. B | Page 16 of 32
+
DETECTOR
GLITCH
FILTER
TO
SEQUENCING
ENGINE
–
VREF = 1.4V
Figure 21. VXn Digital Input Function
04635-027
The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can be used to
debounce a manual reset switch.
ADM1067
OUTPUTS
SUPPLY SEQUENCING THROUGH CONFIGURABLE
OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1067 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
•
Open-drain with weak pull-up to VPn
•
Open-drain with strong pull-up to VPn
•
Strong pull-down to GND
•
Internally charge-pumped high drive (12 V, PDO1 to
PDO6 only)
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which is used to isolate, for example, a cardside voltage from a backplane supply (a PDO can sustain greater
than 10.5 V into a 1 μA load). The pull-down switches can also
be used to drive status LEDs directly.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is to be taken with
the PDOs based on the condition of the ADM1067 inputs.
Therefore, the PDOs can be set up to assert when the SFDs are
in tolerance, the correct input signals are received on the VXn
digital pins, no warnings are received from any of the inputs of
the device, and so on. The PDOs can be used for a variety of
functions. The primary function is to provide enable signals for
LDOs or dc-to-dc converters that generate supplies locally on a
board. The PDOs can also be used to provide a POWER_GOOD
signal when all the SFDs are in tolerance, or a RESET output if
one of the SFDs goes out of specification (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOnCFG configuration register (see the AN-698 Application Note for details).
The data sources are as follows:
•
Output from the SE.
•
Directly from the SMBus. A PDO can be configured so the
SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down
sequence.
•
On-Chip Clock. A 100 kHz clock is generated on the
device. This clock can be made available on any of the
PDOs. It can be used, for example, to clock an external
device such as an LED.
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:
Open-drain (allowing the user to connect an external pullup resistor)
•
Open-drain with weak pull-up to VDD
•
Open-drain with strong pull-up to VDD
VFET (PDO1 TO PDO6 ONLY)
VDD
VP4
10Ω
20kΩ
10Ω
20kΩ
VP1
SEL
10Ω
CFG4 CFG5 CFG6
20kΩ
SE DATA
PDO
SMBus DATA
Figure 22. Programmable Driver Output
Rev. B | Page 17 of 32
04635-028
CLK DATA
20kΩ
•
ADM1067
DEFAULT OUTPUT CONFIGURATION
All of the internal registers in an unprogrammed ADM1067
device from the factory are set to 0. Because of this, the PDOs are
pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.
All PDOs behave as follows as the input supply to the
ADM1067 ramps up on VPn or VH:
•
Input supply 0 V to 1 V. PDOs high impedance.
•
Input supply 1 V to 2.7 V. PDOs pulled to GND by a weak
(20 kΩ) on-chip pull-down resistor.
•
Supply > 2.7 V. Factory programmed devices continue to
pull all PDOs to GND by a weak (20 kΩ) on-chip pull-down
resistor. Programmed devices download current EEPROM
configuration data and the programmed setup is latched. PDO
then goes to the state demanded by the configuration. This
provides a known condition for the PDOs during power-up.
The internal pull-down can be overdriven with an external pullup of suitable value tied from the PDO pin to the required pull-up
voltage. The 20 kΩ resistor must be accounted for in calculating
a suitable value. For example, if PDOn must be pulled up to 3.3 V,
and 5 V is available as an external supply, the pull-up resistor
value is given by
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
Rev. B | Page 18 of 32
RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
ADM1067
SEQUENCING ENGINE
OVERVIEW
The SE state machine comprises 63 state cells. Each state has the
following attributes:
•
Monitors signals indicating the status of the 10 input pins,
VP1 to VP4, VH, and VX1 to VX5.
•
Can be entered from any other state.
•
Three exit routes move the state machine onto a next state:
sequence detection, fault monitoring, and timeout.
•
Delay timers for the sequence and timeout blocks can be
programmed independently and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
•
Output condition of the 10 PDO pins is defined and fixed
within a state.
•
Transition from one state to the next is made in less than
20 μs, which is the time needed to download a state
definition from EEPROM to the SE.
MONITOR
FAULT
STATE
TIMEOUT
SEQUENCE
04635-029
The ADM1067’s sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards such as power-up and power-down sequence
control, fault event handling, interrupt generation on warnings,
among others. A watchdog function that verifies the continued
operation of a processor clock can be integrated into the SE
program. The SE can also be controlled via the SMBus, giving
software or firmware control of the board sequencing.
Figure 23. State Cell
The ADM1067 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be
generated when the ADC readings violate their limit register
value or when secondary voltage monitors on VPn or VH are
triggered. The warnings are OR’ed together and are available as
a single warning input to each of the three blocks that enable
exiting from a state.
SMBus JUMP/UNCONDITIONAL JUMP
The SE can be forced to advance to the next state unconditionally. This enables the user to force the SE to advance. Examples
of where this could be used include moving to a margining state
or debugging a sequence. The SMBus jump or go-to command
can be seen as another input to sequence and timeout blocks,
which provide an exit from each state.
Table 7. Sample Sequence State Entries
State
IDLE1
IDLE2
EN3V3
Sequence
If VX1 is low , go to state IDLE2.
If VP1 is okay, go to state EN3V3.
If VP2 is okay, go to state EN2V5.
DIS3V3
EN2V5
If VX1 is high, go to state IDLE1.
If VP3 is okay, go to state PWRGD.
DIS2V5
FSEL1
FSEL2
PWRGD
If VX1 is high, go to state IDLE1.
If VP3 is not okay, go to state DIS2V5.
If VP2 is not okay, go to state DIS3V3.
If VX1 is high, go to state DIS2V5.
Timeout
Monitor
If VP2 is not okay after 10 ms, go to
state DIS3V3.
If VP1 is not okay, go to state IDLE1.
If VP3 is not okay after 20 ms, go to
state DIS2V5.
If VP1 or VP2 is not okay, go to state FSEL2.
If VP1 or VP2 is not okay, go to state FSEL2.
If VP1 is not okay, go to state IDLE1.
If VP1, VP2, or VP3 is not okay, go to state
FSEL1.
Rev. B | Page 19 of 32
ADM1067
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the sequencing engine (SE). Figure 24 shows how the simple
building block of a single SE state can be used to build a powerup sequence for a 3-supply system.
Table 8 lists the PDO outputs for each state in the same SE
implementation. In this system, the presence of a good 5 V
supply on VP1 and the VX1 pin held low are the triggers
required for a power-up sequence to start. The sequence next
intends to turn on the 3.3 V supply, and then the 2.5 V supply
(assuming successful turn-on of the 3.3 V supply). Once all
three supplies are good, the PWRGD state is entered, where the
SE remains until a fault occurs on one of the three supplies or
until it is instructed to go through a power-down sequence by
VX1 going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections describe the
individual blocks and use the sample application in Figure 24 to
demonstrate the state machine’s actions.
Sequence Detector
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the SE inputs
to change state, and is most often used as the gate on successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 25 is a block diagram of
the sequence detector.
VP1
SUPPLY FAULT
DETECTION
SEQUENCE
DETECTOR
SEQUENCE
STATES
VX5
LOGIC INPUT CHANGE
OR FAULT DETECTION
TIMER
IDLE1
WARNINGS
VX1 = 0
INVERT
IDLE2
SELECT
VP1 = 1
MONITOR FAULT
STATES
Figure 25. Sequence Detector Block Diagram
TIMEOUT
STATES
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 24, the FSEL1
and FSEL2 states first identify which of the VP1, VP2, or VP3
pins has faulted, and then they take the appropriate action.
EN3V3
10ms
VP1 = 0
VP2 = 1
EN2V5
Monitoring Fault Detector
DIS3V3
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate, which can detect when an input deviates from its
expected condition. The clearest demonstration of the use of
this block is in the PWRGD state, where the monitor block
indicates that a failure on one or more of the VP1, VP2, or VP3
inputs has occurred.
20ms
(VP1 + VP2) = 0
VX1 = 1
VP3 = 1
PWRGD
DIS2V5
VP2 = 0
(VP1 + VP2 + VP3) = 0
VX1 = 1
(VP1 +
VP2) = 0
VX1 = 1
FSEL1
04635-032
FORCE FLOW
(UNCONDITIONAL JUMP)
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the user needs to react
as quickly as possible. Some latency occurs when moving out of
this state, however, because it takes a finite amount of time
(~20 μs) for the state configuration to download from EEPROM
into the SE. Figure 26 is a block diagram of the monitoring fault
detector.
VP3 = 0
FSEL2
VP1 = 0
04635-030
VP2 = 0
Figure 24. Sample Application Flow Diagram
Table 8. PDO Outputs for Each State
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
0
0
0
IDLE2
0
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
Rev. B | Page 20 of 32
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
ADM1067
MONITORING FAULT
DETECTOR
The power-up sequence progresses when this change is
detected. If, however, the supply fails (perhaps due to a short
circuit overloading this supply), the timeout block traps the
problem. In this example, if the 3.3 V supply fails within 10 ms,
the SE moves to the DIS3V3 state and turns off this supply by
bringing PDO1 low. It also indicates that a fault has occurred by
taking PDO3 high. Timeout delays from 100 μs to 400 ms can
be programmed.
1-BIT FAULT
DETECTOR
VP1
FAULT
SUPPLY FAULT
DETECTION
MASK
SENSE
1-BIT FAULT
DETECTOR
VX5
FAULT AND STATUS REPORTING
FAULT
LOGIC INPUT CHANGE
OR FAULT DETECTION
MASK
SENSE
1-BIT FAULT
DETECTOR
MASK
04635-033
FAULT
WARNINGS
Figure 26. Monitoring Fault Detector Block Diagram
Timeout Detector
The timeout detector allows the user to trap a failure to make
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 24, the timeout nextstate transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted upon entry to this
state (on the PDO1 output pin) to turn on a 3.3 V supply. This
supply rail is connected to the VP2 pin, and the sequence detector looks for the VP2 pin to go above its UV threshold, which is
set in the supply fault detector (SFD) attached to that pin.
The ADM1067 has a fault latch for recording faults. Two registers
are set aside for this purpose, FSTAT1 and FSTAT2. A single bit
is assigned to each input of the device, and a fault on that input
sets the relevant bit. The contents of the fault register can be
read out over the SMBus to determine which input(s) faulted.
The fault register can be enabled/disabled in each state. To latch
data from one state, simply ensure that the fault latch is disabled
in the following state. This ensures that only real faults are
captured and not, for example, undervoltage conditions that
may be present during a power-up or power-down sequence.
The ADM1067 also has a number of status registers. These
include more detailed information, such as whether an
undervoltage or overvoltage fault is present on a particular
input faulted, as well as information on ADC limit faults. Note
that the data in the status registers is not latched in any way and,
therefore, is subject to change at any time.
See the AN-698 Application Note for full details about the
ADM1067 registers.
Rev. B | Page 21 of 32
ADM1067
SUPPLY MARGINING
OVERVIEW
To implement open-loop margining:
It is often necessary for the system designer to adjust supplies,
either to optimize their level or force them away from nominal
values to characterize the system performance under these
conditions. This is a function typically performed during an incircuit test (ICT), such as when the manufacturer wants to
guarantee that the product under test functions correctly at
nominal supplies minus 10%.
1.
Disable the six DAC outputs.
2.
Set the DAC output voltage equal to the voltage on the
feedback node.
3.
Enable the DAC.
4.
Assert MUP (drive logic high). The DAC voltage moves
down to the value set in the DNLIM register (see the
AN-698 Application Note). The output of the dc-to-dc
converter rises to compensate for this, that is, margin up.
5.
Assert MDN (drive logic high). The DAC voltage moves down
to the value set in the DPLIM register (see the AN-698
Application Note). The output of the dc-to-dc converter
drops to compensate for this, that is, margin down.
OPEN-LOOP MARGINING
The simplest method of margining a supply is to implement an
open-loop technique. A popular method for this is to switch extra
resistors into the feedback node of a power module, such as a
dc-to-dc converter or low dropout regulator (LDO). The extra
resistor alters the voltage at the feedback or trim node and forces
the output voltage to margin up or down by a certain amount.
The ADM1067 can perform open-loop margining for up to six
supplies. The six on-board voltage DACs (DAC1 to DAC6) can
drive into the feedback pins of the power modules to be
margined. The simplest circuit to implement this function is an
attenuation resistor that connects the DACn pin to the feedback
node of a dc-to-dc converter. When the DACn output voltage is
set equal to the feedback voltage, no current flows into the
attenuation resistor, and the dc-to-dc output voltage does not
change. Taking DACn above the feedback voltage forces current
into the feedback node, and the output of the dc-to-dc
converter is forced to fall to compensate for this. The dc-to-dc
output can be forced high by setting the DACn output voltage
lower than the feedback node voltage. The series resistor can be
split in two, and the node between them decoupled with a
capacitor to ground. This can help to decouple any noise picked
up from the board. Decoupling to a ground local to the dc-todc converter is recommended.
VIN
μCONTROLLER
VOUT
ADM1067
DEVICE
CONTROLLER
(SMBus)
OUTPUT
FEEDBACK
GND
ATTENUATION
RESISTOR
DACOUTn
DAC
PCB
TRACE NOISE
DECOUPLING
CAPACITOR
04635-067
DC/DC
CONVERTER
Figure 27. Open-Loop Margining System Using the ADM1067
The ADM1067 can be commanded to margin a supply up or
down over the SMBus by updating the values on the relevant
DAC output.
Steps 1 to 3 ensure that when the DACn output buffer is turned
on, it has little effect on the dc-to-dc output. The DAC output
buffer is designed to power up without glitching. It does this by
first powering up the buffer to follow the pin voltage and does
not drive out onto the pin at this time. Once the output buffer is
properly enabled, the buffer input is switched over to the DAC,
and the output stage of the buffer is turned on. Output glitching
is negligible.
The margining method above assumes that margin up and margin down DAC limits have been preloaded into the ADM1067
and that only one margin up and margin down level are required.
Alternatively, a DACn output level can be dynamically altered
by an SMBus write to that DACn output register.
WRITING TO THE DACs
Four DAC ranges are offered. They can be placed with midcode
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
placed to correspond to the most common feedback voltages.
Centering the DAC outputs in this way provides the best use of
the DAC resolution. For most supplies, it is possible to place the
DAC midcode at the point where the dc-to-dc output is not
modified, thereby giving half of the DAC range to margin up
and the other half to margin down.
The DAC output voltage is set by the code written to the DACn
register. The voltage is linear with the unsigned binary number
in this register. Code 0x7F is placed at the midcode voltage, as
described previously.
The output voltage is given by the following equation:
DAC Output = (DACn − 0x7F)/255 × 0.6015 + VOFF
where VOFF is one of the four offset voltages.
Rev. B | Page 22 of 32
ADM1067
There are 256 DAC settings available. The midcode value is
located at DAC Code 0x7F, as close as possible to the middle
of the 256 code range. The full output swing of the DACs is
+302 mV (+128 codes) and −300 mV (−127 codes) around the
selected midcode voltage. The voltage range for each midcode
voltage is shown in Table 9.
Table 9. Ranges for Midcode Voltages
Midcode
Voltage (V)
0.6
0.8
1.0
1.25
Minimum Voltage
Output (V)
0.300
0.500
0.700
0.950
Maximum Voltage
Output (V)
0.902
1.102
1.302
1.552
This equation demonstrates that, if the user wants the output
voltage to change by ±300 mV, then R1 = R3. If the user wants the
output voltage to change by ±600 mV, then R1 = 2 × R3, and so on.
It is best to use the full DAC output range to margin a supply.
Choosing the attenuation resistor in this way provides the most
resolution from the DAC. In other words, with one DAC code
change, the smallest effect on the dc-to-dc output voltage is
induced. If the resistor is sized up to use a code such as 27(dec)
to 227(dec) to move the dc-to-dc output by ±5%, then it takes
100 codes to move 5% (each code moves the output by 0.05%).
This is beyond the readback accuracy of the ADC, but should
not prevent the user from building a circuit to use the most
resolution.
DAC LIMITING/OTHER SAFETY FEATURES
CHOOSING THE SIZE OF THE ATTENUATION
RESISTOR
How much this DAC voltage swing affects the output voltage of
the dc-to-dc converter that is being margined is determined by
the size of the attenuation resistor, R3.
Because the voltage at the feedback pin remains constant, the
current flowing from the feedback node to GND via R2 is a
constant. In addition, the feedback node itself is high
impedance. This means that the current flowing through R1 is
the same as the current flowing through R3. Therefore, direct
relationship exists between the extra voltage drop across R1
during margining and the voltage drop across R3.
This relationship is given by the following equation:
∂VOUT =
R1
(VFB − VDACOUT)
R3
Limit registers (called DPLIMn and DNLIMn) on the device
offer the user some protection from firmware bugs, which can
cause catastrophic board problems by forcing supplies beyond
their allowable output ranges. Essentially, the DAC code written
into the DACn register is clipped such that the code used to set
the DAC voltage is actually given by
DAC Code
= DACn, DACn ≥ DNLIMn and DACn ≤ DPLIMn
= DNLIMn,
DACn < DNLIMn
= DPLIMn,
DACn > DPLIMn
In addition, the DAC output buffer is three-stated, if DNLIMn
> DPLIMn. By programming the limit registers in this way, the
user can make it very difficult for the DAC output buffers to be
turned on at all during normal system operation (these are
among the registers downloaded from EEPROM at startup).
where:
∂VOUT is the change in VOUT.
VFB is the voltage at the feedback node of the dc-to-dc converter.
VDACOUT is the voltage output of the margining DAC.
Rev. B | Page 23 of 32
ADM1067
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-DC1
5V OUT
3V OUT
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
POWER_ON
RESET_L
VH
VP1
VP2
VP3
VP4
VX1
VX2
VX3
EN
3.3V OUT
PDO1
PDO2
IN
DC-DC2
PDO3
PDO4
PDO5
VX4
PDO6
PDO7
VX5
MARGIN UP
MARGIN DOWN
OUT
ADM1067
PDO8
PDO9
PDO10
DAC1*
MUP
MDN
EN
OUT
2.5V OUT
POWER_GOOD
SIGNAL_VALID
IN
SYSTEM RESET
DC-DC3
EN
OUT
1.8V OUT
3.3V OUT
VCCP VDDCAP REFOUT GND
IN
LDO
10µF
10µF
10µF
EN
OUT
0.9V OUT
3.3V OUT
IN
EN
OUT
DC-DC4
Figure 28. Applications Diagram
Rev. B | Page 24 of 32
1.2V OUT
TRIM
04635-068
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6
WILL ALLOW MARGINING FOR UP TO
SIX VOLTAGE RAILS.
ADM1067
COMMUNICATING WITH THE ADM1067
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1067 (such as UV/OV
thresholds, glitch filter timeouts, and PDO configurations) is
dictated by the contents of RAM. The RAM is comprised of
digital latches that are local to each of the functions on the
device. The latches are double-buffered and have two identical
latches, Latch A and Latch B. Therefore, when an update to a
function occurs, the contents of Latch A are updated first, and
then the contents of Latch B are updated with identical data.
The advantages of this architecture are explained in detail in
this section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:
1.
2.
3.
4.
5.
6.
With no power applied to the device, the PDOs are high
impedance.
When 1 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPn), the PDOs are weakly pulled
to GND with a 20 kΩ impedance.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
The EEPROM downloads its contents to all Latch As.
Once the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
The first state definition is downloaded from EEPROM
into the SE 0.5 ms after the configuration download
completes.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1067 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
EEPROM into the RAM registers, the user may need to alter the
configuration of functions on the ADM1067, such as changing
the UV or OV limit of an SFD, changing the fault output of an
SFD, or adjusting the rise time delay of one of the PDOs.
The ADM1067 provides several options that allow the user to
update the configuration over the SMBus interface. The
following three options are controlled in the UPDCFG register:
Option 1
Update the configuration in real time. The user writes to RAM
across the SMBus and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1067 remains unchanged
and continues to operate in the original setup until the
instruction is given to update the Latch Bs.
Option 3
Change EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to
the RAM registers. Again, with this method, the configuration of
the ADM1067 remains unchanged and continues to operate in
the original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents, if
revisions to the configuration are unsatisfactory. For example, if
the user needs to alter an OV threshold, the RAM register can
be updated as described in Option 1. However, if the user is not
satisfied with the change and wants to revert to the original
programmed value, the device controller can issue a command
to download the EEPROM contents to the RAM again, as
described in Option 3, restoring the ADM1067 to its original
configuration.
The topology of the ADM1067 makes this type of operation
possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1
leaves the double-buffered latches open at all times. If Bit 0 is set
to 0 and a RAM write occurs across the SMBus, only the first
side of the double-buffered latch is written to. The user must
then write a 1 to Bit 1 of the UPDCFG register. This generates a
pulse to update all the second latches at once. EEPROM writes
occur in a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If low, the contents of a page cannot be
erased, even if the command code for page erasure is
programmed across the SMBus. The bit map for the UPDCFG
register is shown in the AN-698 Application Note. A flow chart
for download at power-up and subsequent configuration
updates is shown in Figure 29.
Rev. B | Page 25 of 32
ADM1067
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH A
LATCH B
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
04635-035
POWER-UP
(VCC > 2.5V)
Figure 29. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has its own dedicated 512-byte EEPROM for storing state definitions, providing
63 individual states with a 64-bit word each (one state is
reserved). At power-up, the first state is loaded from the SE
EEPROM into the engine itself. When the conditions of this
state are met, the next state is loaded from EEPROM into the
engine, and so on. The loading of each new state takes approximately 10 μs.
To alter a state, the required changes must be made directly to
EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to EEPROM.
INTERNAL REGISTERS
The ADM1067 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
The major differences between the EEPROM and other
registers are as follows:
•
•
•
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Page 0 to Page 6, starting at Address 0xF800, hold the configuration data for the applications on the ADM1067 (such as
the SFDs and PDOs). These EEPROM addresses are the same as
the RAM register addresses, prefixed by F8. Page 7 is reserved.
Page 8 to Page 15 are for customer use.
Data can be downloaded from EEPROM to RAM in one of the
following ways:
•
•
Address Pointer Register
This register contains the address that selects one of the other
internal registers. When writing to the ADM1067, the first byte
of data is always a register address that is written to the address
pointer register.
An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
Writing to EEPROM is slower than writing to RAM.
Writing to the EEPROM should be restricted, because it
has a limited write/cycle life of typically 10,000 write
operations due to the usual EEPROM wear-out mechanisms.
At power-up, when Page 0 to Page 6 are downloaded.
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6.
SERIAL BUS INTERFACE
These registers provide control and configuration for various
operating parameters of the ADM1067.
The ADM1067 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device,
under the control of a master device. It takes approximately
1 ms after power-up for the ADM1067 to download from its
EEPROM. Therefore, access to the ADM1067 is restricted until
the download is complete.
EEPROM
Identifying the ADM1067 on the SMBus
The ADM1067 has two 512-byte cells of nonvolatile, electrically
erasable, programmable read-only memory (EEPROM), from
Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1067 is powered down. One EEPROM cell
contains the configuration data of the device; the other contains
the state definitions for the SE. Although referred to as read-only
memory, the EEPROM can be written to, as well as read from,
via the serial bus in exactly the same way as the other registers.
The ADM1067 has a 7-bit serial bus slave address. The device is
powered up with a default serial bus address. The five MSBs of
the address are set to 01111; the two LSBs are determined by the
logical states of Pin A1 and Pin A0. This allows the connection
of four ADM1067s to one SMBus.
Configuration Registers
Rev. B | Page 26 of 32
ADM1067
Table 10. Serial Bus Slave Address
A0 Pin
Low
Low
High
High
1
A1 Pin
Low
High
Low
High
Hex Address
0x78
0x7A
0x7C
0x7E
7-Bit Address
0111100X1
0111101X1
0111110X1
0111111X1
X = Read/Write bit. The address is shown only as the first 7 MSBs.
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 11 lists these registers
with their values and functions.
2.
Table 11. Identification Register Values and Functions
Name
MANID
Address
0xF4
Value
0x41
REVID
MARK1
MARK2
0xF5
0xF6
0xF7
0x02
0x00
0x00
Function
Manufacturer ID for Analog
Devices
Silicon revision
Software brand
Software brand
General SMBus Timing
Figure 30, Figure 31, and Figure 32 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations section and Read Operations section.
The general SMBus protocol operates as follows:
1.
3.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data-line SDA, while the serial clock-line SCL remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether
data is written to or read from the slave device (0 = write,
1 = read).
Rev. B | Page 27 of 32
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and by holding it low during the high
period of this clock pulse.
All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the
R/W bit is a 0, the master writes to the slave device. If the
R/W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-tohigh transition when the clock is high could be interpreted
as a stop signal. If the operation is a write operation, the
first data byte after the slave address is a command byte.
This tells the slave device what to expect next. It could be
an instruction telling the slave device to expect a block
write, or it could simply be a register address telling the
slave where subsequent data is to be written. Because data
can flow in only one direction, as defined by the R/W bit,
sending a command to a slave device during a read
operation is not possible. Before a read operation, it could
be necessary to perform a write operation to tell the slave
what sort of read operation to expect and/or the address
from which data is to be read.
When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the
data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device releases the SDA
line during the low period before the ninth clock pulse, but
the slave device does not pull it low. This is known as no
acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, and then high
during the 10th clock pulse to assert a stop condition.
ADM1067
1
9
1
9
SCL
1
1
1
1
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
SCL
(CONTINUED)
SDA
(CONTINUED)
9
D7
D6
D5
D4
D3
D0
ACK. BY
SLAVE
D2
D1
1
D7
D0
9
D6
D5
ACK. BY
SLAVE
FRAME 3
DATA BYTE
D4
D3
D2
D1
D0
ACK. BY
SLAVE
FRAME N
DATA BYTE
STOP
BY
MASTER
04635-036
0
SDA
Figure 30. General SMBus Write Timing Diagram
1
9
1
9
SCL
1
1
1
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
FRAME 1
SLAVE ADDRESS
D6
D5
D4
D3
9
D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY
MASTER
D0
1
D7
FRAME 2
DATA BYTE
D6
D5
ACK. BY
MASTER
D4
9
D3
D2
FRAME N
DATA BYTE
D1
D0
NO ACK.
STOP
BY
MASTER
Figure 31. General SMBus Read Timing Diagram
tR
tF
t HD; STA
t LO W
SCL
t HI G H
t HD; STA
t HD; DAT
t SU; STA
t SU; STO
t SU; DAT
t BUF
P
S
S
Figure 32. Serial Bus Timing Diagram
Rev. B | Page 28 of 32
P
04635-038
SDA
04635-037
0
SDA
ADM1067
The ADM1067 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00
to Address 0xDF; EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both RAM and EEPROM
as single data bytes. Data can be written only to unprogrammed
EEPROM locations. To write new data to a programmed location, it must first be erased. EEPROM erasure cannot be done at
the byte level. The EEPROM is arranged as 32 pages of 32 bytes
each, and an entire page must be erased.
•
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before
writing to one or more EEPROM memory locations that
are already programmed, the page or pages containing
those locations must first be erased. EEPROM memory is
erased by writing a command byte.
The master sends a command code that tells the slave
device to erase the page. The ADM1067 command code
for a page erasure is 0xFE (1111 1110). Note that, for a
page erasure to take place, the page address has to be given
in the previous write word transaction (see the Write
Byte/Word section). In addition, Bit 2 in the UPDCFG
register (Address 0x90) must be set to 1.
1
S
2
SLAVE
ADDRESS
WRITE OPERATIONS
Start
Stop
Read
Write
Acknowledge
No acknowledge
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
write bit (low).
3.
The addressed slave device asserts ACK on SDA.
4.
The master sends a command code.
5.
The slave asserts ACK on SDA.
6.
The master asserts a stop condition on SDA and the
transaction ends.
As soon as the ADM1067 receives the command byte, page
erasure begins. The master device can send a stop command
as soon as it sends the command byte. Page erasure takes approximately 20 ms. If the ADM1067 is accessed before erasure
is complete, it responds with a no acknowledge (NACK).
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master sends a data byte (or asserts a stop condition at
this point).
9. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
•
To write a register address to RAM for a subsequent single
byte read from the same address, or a block read or write
starting at that address, as shown in Figure 33.
W
3
4
5
6
A
RAM
ADDRESS
(0x00 TO 0xDF)
A
P
To write a single byte of data to RAM. In this case, the
command byte is the RAM address from 0x00 to 0xDF and
the only data byte is the actual data, as shown in Figure 35.
1
2
3
4
5
RAM
S SLAVE W A
ADDRESS
A
ADDRESS
(0x00 TO 0xDF)
04635-039
S
P
In the ADM1067, the write byte/word protocol is used for three
purposes:
In the ADM1067, the send byte protocol is used for two
purposes:
2
A
1.
2.
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
SLAVE
ADDRESS
A
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
Send Byte
1
6
Write Byte/Word
The ADM1067 uses the following SMBus write protocols.
•
5
6
DATA A P
Figure 35. Single Byte Write to RAM
Figure 33. Setting a RAM Address for Subsequent Read
Rev. B | Page 29 of 32
7 8
04635-041
S
P
R
W
A
A
4
COMMAND
BYTE
(0xFE)
Figure 34. EEPROM Page Erasure
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 33 to Figure 41.
•
•
•
•
•
•
W
3
04635-040
•
SMBus PROTOCOLS FOR RAM AND EEPROM
ADM1067
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case,
the command byte is the high byte of the EEPROM address
from 0xF8 to 0xFB. The only data byte is the low byte of
the EEPROM address, as shown in Figure 36.
1
2
3
4
5
•
•
Figure 36. Setting an EEPROM Address
Because a page consists of 32 bytes, only the 3 MSBs of the
address low byte are important f or page erasure. The lower
five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to EEPROM. In this case, the
command byte is the high byte of the EEPROM address
from 0xF8 to 0xFB. The first data byte is the low byte of the
EEPROM address, and the second data byte is the actual
data, as shown in Figure 37.
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF), to avoid writing to
invalid addresses.
An addresses cross a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1067 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for repeated
or block write operations. The ADM1067 pulls SCL low and
extends the clock pulse when it cannot accept any more data.
READ OPERATIONS
The ADM1067 uses the following SMBus read protocols.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
9 10
1.
The master device asserts a start condition on SDA.
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
P
S ADDRESS W A
A
HIGH BYTE
LOW BYTE A DATA A
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
2.
The master sends the 7-bit slave address followed by the
read bit (high).
1
2
3
4
5
6
7
8
04635-043
•
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
7 8
6
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S ADDRESS W A
A
A P
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
04635-042
•
Figure 37. Single Byte Write to EEPROM
3.
The addressed slave device asserts ACK on SDA.
Block Write
4.
The master receives a data byte.
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1067, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
5.
The master asserts no acknowledge on SDA.
6.
The master asserts a stop condition on SDA, and the
transaction ends.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1067 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7. The slave asserts ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts ACK on SDA after each data byte.
10. The master asserts a stop condition on SDA to end the
transaction.
2
3
4
5
6
7
8
9
10
SLAVE
0xFC
BYTE
DATA A DATA A DATA A P
S ADDRESS
W A COMMAND
(BLOCK WRITE) A COUNT A
1
2
N
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
Figure 39. Single Byte Read from EEPROM or RAM
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1067, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as
follows:
04635-044
1
1
04635-045
1.
2.
In the ADM1067, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 39.
Figure 38. Block Write to EEPROM or RAM
Rev. B | Page 30 of 32
ADM1067
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
S
2
3
4
5 6
7
8
9
10
11
Error Correction
The ADM1067 provides the option of issuing a packet error
correction (PEC) byte after a write to RAM, a write to EEPROM,
a block write to RAM/EEPROM, or a block read from RAM/
EEPROM. This enables the user to verify that the data received
by or sent from the ADM1067 is correct. The PEC byte is an
optional byte sent after that last data byte has been written to or
read from the ADM1067. The protocol is as follows:
1.
2.
C(x) = x8 + x2 + x1 + 1
See the SMBus 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 41.
1
12
The ADM1067 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the
PEC byte is incorrect.
A no acknowledge (NACK) is generated after the PEC byte
to signal the end of the read.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
2
3
4
5 6
7
8
9
10
11
SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
13 14 15
13 14
DATA
A
32
12
S SLAVE
W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A
ADDRESS
(BLOCK READ)
ADDRESS
COUNT
1
P
04635-046
1
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts ACK on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1067 command
code for a block read is 0xFD (1111 1101).
The slave asserts ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts ACK on SDA.
The ADM1067 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1067
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus 1.1 specification.
The master asserts ACK on SDA.
The master receives 32 data bytes.
The master asserts ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
DATA
32
A PEC A P
Figure 41. Block Read from EEPROM or RAM with PEC
Figure 40. Block Read from EEPROM or RAM
Rev. B | Page 31 of 32
04635-047
1.
2.
ADM1067
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
30
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
5.75
BCS SQ
1.00
0.85
0.80
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
12° MAX
40
1
21
20
10
11
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 42. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
36
48
1
PIN 1
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
12
13
25
24
VIEW A
0.50
0.27
BSC
0.22
LEAD PITCH
0.17
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 43. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1067ACP
ADM1067ACP-REEL
ADM1067ACP-REEL7
ADM1067ACPZ 1
ADM1067ASU
ADM1067ASU-REEL
ADM1067ASU-REEL7
ADM1067ASUZ1
EVAL-ADM1067LFEB
EVAL-ADM1067TQEB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
48-Lead TQFP
48-Lead TQFP
48-Lead TQFP
48-Lead TQFP
Evaluation Kit (LFCSP Version)
Evaluation Kit (TQFP Version)
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04635-0-11/06(B)
Rev. B | Page 32 of 32
Package Option
CP-40
CP-40
CP-40
CP-40
SU-48
SU-48
SU-48
SU-48
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