AD ADUM5400ARWZ Quad-channel isolator with integrated dc-to-dc converter Datasheet

Quad-Channel Isolator with
Integrated DC-to-DC Converter
ADuM5400
FEATURES
GENERAL DESCRIPTION
isoPower integrated, isolated dc-to-dc converter
Regulated 5 V output
500 mW output power
Quad dc-to-25 Mbps (NRZ) signal isolation channels
Schmitt trigger inputs
16-lead SOIC package with >8 mm creepage
High temperature operation: 105°C maximum
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
The ADuM54001 device is a quad-channel digital isolator with
isoPower®, an integrated, isolated dc-to-dc converter. Based on
the Analog Devices, Inc., iCoupler® technology, the dc-to-dc
converter provides up to 500 mW of regulated, isolated power
with 5.0 V input and 5.0 V output voltages. This architecture
eliminates the need for a separate, isolated dc-to-dc converter in
low power, isolated designs. The iCoupler chip scale transformer
technology is used to isolate the logic signals and the magnetic
components of the dc-to-dc converter. The result is a small
form factor, total isolation solution.
The ADuM5400 isolator provides four independent isolation
channels in two speed grades (see the Ordering Guide for more
information).
isoPower uses high frequency switching elements to transfer
power through its transformer. Special care must be taken
during printed circuit board (PCB) layout to meet emissions
standards. Refer to the AN-0971 application note for details
on board layout recommendations.
APPLICATIONS
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Power supply start-up bias and gate drives
Isolated sensor interfaces
Industrial PLCs
FUNCTIONAL BLOCK DIAGRAM
OSC
RECT
REG
VIA 3
4-CHANNEL iCOUPLER CORE
VIB 4
VIC 5
16 VISO
15 GNDISO
14 VOA
13 VOB
ADuM5400
12 VOC
VID 6
11 VOD
VDDL 7
10 VISO
GND1 8
9
GNDISO
07509-001
VDD1 1
GND1 2
Figure 1.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADuM5400
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................8
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................9
General Description ......................................................................... 1
Terminology .................................................................................... 11
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 12
Revision History ............................................................................... 2
PCB Layout ................................................................................. 12
Specifications..................................................................................... 3
EMI Considerations ................................................................... 12
Electrical Characteristics ............................................................. 3
Propagation Delay Parameters ................................................. 13
Package Characteristics ............................................................... 5
DC Correctness and Magnetic Field Immunity ..................... 13
Regulatory Information ............................................................... 5
Power Consumption .................................................................. 14
Insulation and Safety Related Specifications ............................ 5
Power Considerations ................................................................ 14
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6
Thermal Analysis ....................................................................... 15
Recommended Operating Conditions ...................................... 6
Outline Dimensions ....................................................................... 16
Absolute Maximum Ratings............................................................ 7
Ordering Guide .......................................................................... 16
Insulation Lifetime ..................................................................... 15
ESD Caution .................................................................................. 7
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADuM5400
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ VDD1 ≤ 5.5 V; each voltage is relative to its respective ground. All minimum/maximum specifications apply over the entire
recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 5.0 V.
Table 1.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
DC to 2 Mbps Data Rate 1
Maximum Output Supply Current 2
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO(LINE)
VISO(LOAD)
VISO(RIP)
4.7
5.0
1
1
75
5.4
V
mV/V
%
mV p-p
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
20 MHz bandwidth,
CBO = 0.1 μF||10 μF, IISO = 90 mA
CBO = 0.1 μF||10 μF, IISO = 90 mA
VISO(N)
fOSC
fPWM
IISO(MAX)
5
200
180
625
mV p-p
MHz
kHz
100
mA
34
%
Efficiency at Maximum Output
Supply Current 3
IDD1 Supply Current, No VISO Load
IDD1(Q)
19
IDD1 Supply Current, Full VISO Load
IDD1(MAX)
290
mA
IDD1(D)
64
mA
IISO(LOAD)
89
mA
VUV+
VUV−
VUVH
2.7
2.4
0.3
V
V
V
25 Mbps Data Rate (CRWZ Grade Only)
IDD1 Supply Current, No VISO Load
Available VISO Supply Current 4
Undervoltage Lockout, VDD1, VDDL, and
VISO Supplies 5
Positive Going Threshold
Negative Going Threshold
Hysteresis
iCoupler DATA CHANNELS
I/O Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
AC SPECIFICATIONS
ADuM5400ARWZ
Minimum Pulse Width 6
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Propagation Delay Skew
Channel-to-Channel Matching
IIA, IIB, IIC, IID
VIH
VIL
VOAH, VOBH,
VOCH, VODH
−20
0.7 × VIDD1
+0.01
VISO − 0.3
5.0
VISO − 0.5
4.8
0.0
0.0
30
+20
PW
IOx = −20 μA, VIx = VIxH
0.1
V
V
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
0.4
V
IOx = 4 mA, VIx = VIxL
1000
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
55
Rev. 0 | Page 3 of 16
IISO = 0 mA, CL = 15 pF, 12.5 MHz
logic signal frequency
CL = 15 pF, 12.5 MHz logic signal
frequency
μA
V
V
V
0.3 × VIDD1
VOAL, VOBL,
VOCL, VODL
mA
VISO > 4.5 V, dc to 1 MHz logic
signal frequency
IISO = 100 mA, dc to 1 MHz logic
signal frequency
IISO = 0 mA, dc to 1 MHz logic
signal frequency
CL = 0 pF, dc to 1 MHz logic signal
frequency, VDD = 4.5 V, IISO = 100 mA
100
40
50
50
ADuM5400
Parameter
ADuM5400CRWZ
Minimum Pulse Width6
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL|
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing Directional Channels
For All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
Refresh Rate
Symbol
Min
Typ
PW
Max
Unit
Test Conditions/Comments
40
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
15
6
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
15
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
25
tPHL, tPLH
PWD
45
60
6
5
tR/tF
|CMH|
25
2.5
35
ns
kV/μs
|CML|
25
35
kV/μs
1.0
Mbps
fr
1
The contributions of supply current values for all four channels are combined at identical data rates.
The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
3
The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
4
This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.
5
Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built
into the detection threshold to prevent oscillations and noise sensitivity.
6
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
2
Rev. 0 | Page 4 of 16
ADuM5400
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction to Ambient Thermal
Resistance
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.2
4.0
45
Max
Unit
Ω
pF
pF
°C/W
Test Conditions
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces 3
1
The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
2
REGULATORY INFORMATION
The ADuM5400 is approved by the organizations listed in Table 3. Refer to Table 8 and to the Insulation Lifetime section for details
regarding the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 3.
UL
Recognized under 1577 Component
Recognition Program 1
Single Protection 2500 V RMS Isolation Voltage
File E214100
1
2
CSA (Pending)
Approved under CSA Component
Acceptance Notice #5A
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
File 205078
VDE (Pending)
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM5400 is proof-tested by applying an insulation test voltage of ≥3000 V rms for 1 sec (current leakage detection limit = 10 μA).
In accordance with DIN V VDE V 0884-10, each ADuM5400 is proof-tested by applying an insulation test voltage of ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking
Index)
Isolation Group
L(I01)
Value
2500
>8.0
Unit
V rms
mm
L(I02)
>8.0
mm
CTI
0.017 min
>175
mm
V
IIIa
Rev. 0 | Page 5 of 16
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
ADuM5400
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
The ADuM5400 is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval.
Table 5.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Conditions
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
RS
150
555
>109
°C
mA
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 2)
Case Temperature
Side 1 Current, IDD1
Insulation Resistance at TS
VIO = 500 V
Thermal Derating Curve
500
400
300
200
100
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
07509-003
SAFE OPERATING VDD1 CURRENT (mA)
600
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values
on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter
Operating Temperature Range
Supply Voltages1
Minimum Load2
1
2
Symbol
TA
VDD
IISO(MIN)
Min
−40
4.5
10
Max
+105
5.5
Unit
°C
V
mA
Each voltage is relative to its respective ground.
If the external load is less than the specified value, the power supply PWM can generate excess switching noise, potentially causing data integrity issues.
Rev. 0 | Page 6 of 16
ADuM5400
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature (TA)
Supply Voltages (VDD1, VISO) 1
VISO Supply Current 2
−40°C to +85°C
−40°C to +105°C
Input Voltage (VIA, VIB, VIC, VID)1, 3
Output Voltage (VOA, VOB, VOC, VOD)1, 3
Average Output Current
per Data Output Pin 4
Common-Mode Transients 5
Rating
−55°C to +150°C
−40°C to +85°C
−0.5 V to +7.0 V
100 mA
60 mA
−0.5 V to VDDI + 0.5 V
−0.5 V to VISO + 0.5 V
−10 mA to +10 mA
ESD CAUTION
−100 kV/μs to +100 kV/μs
1
Each voltage is relative to its respective ground.
VISO provides current for dc and dynamic loads on the Side 2 I/O channels.
This current must be included when determining the total VISO supply
current.
3
VDD1 and VISO refer to the supply voltages on the input and output sides of
a given channel, respectively. See the PCB Layout section.
4
See Figure 2 for maximum rated current values for various temperatures.
5
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up
or permanent damage.
2
Table 8. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1
Parameter
AC Voltage
Bipolar Waveform
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Maximum
Unit
Reference Standard
424
V peak
50-year minimum lifetime
600
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
600
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Rev. 0 | Page 7 of 16
ADuM5400
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VIC 5
ADuM5400
13 VOB
TOP VIEW
(Not to Scale) 12 VOC
VID 6
11
VOD
VDDL 7
10
VISO
GND1 8
9
GNDISO
07509-004
VIB 4
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
6
7
9, 15
VIA
VIB
VIC
VID
VDDL
GNDISO
10, 16
VISO
11
12
13
14
VOD
VOC
VOB
VOA
Description
Primary Supply Voltage, 4.5 V to 5.5 V.
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Logic Power Supply Voltage. This pin must be connected to VDD1 and have a dedicated bypass capacitor.
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is
recommended that both pins be connected to a common ground.
Secondary Supply Voltage Output for External Loads, 5.0 V. These pins are not tied together internally
and must be connected together on the PCB.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Table 10. Truth Table (Positive Logic)
VIx Input 1
High
Low
1
VDD1/VDDL State
Powered
Powered
VDD1/VDDL Input (V)
5.0
5.0
VISO State
Powered
Powered
VISO Output (V)
5.0
5.0
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
Rev. 0 | Page 8 of 16
VOx Output1
High
Low
Operation
Normal operation, data is high
Normal operation, data is low
ADuM5400
TYPICAL PERFORMANCE CHARACTERISTICS
Each voltage is relative to its respective ground; all typical specifications are at TA = 25°C.
4.0
5V IN/5V OUT
35
3.5
INPUT CURRENT (A)
25
20
15
3.5
POWER
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
30
EFFICIENCY (%)
4.0
1.0
10
POWER (W)
40
1.0
IDD
0.5
0
0.02
0.04
0.06
0.08
OUTPUT CURRENT (A)
0.10
0.12
0
3.0
07509-005
0
0.5
3.5
4.0
4.5
5.0
5.5
6.0
0
6.5
07509-008
5
INPUT VOLTAGE (V)
Figure 4. Typical Power Supply Efficiency at 5 V/5 V
Figure 7. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage
OUTPUT VOLTAGE
(500mV/DIV)
1.0
0.9
VDD1 = 5V, VISO = 5V
0.7
0.6
0.5
10% LOAD
90% LOAD
0.4
0.3
0.2
0.1
0
0.02
0.04
0.06
IISO (A)
0.08
0.10
0.12
(100µs/DIV)
07509-006
0
07509-009
DYNAMIC LOAD
POWER DISSIPATION (W)
0.8
Figure 8. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
Figure 5. Typical Total Power Dissipation vs. IISO with Data Channels Idle
0.12
5V OUTPUT RIPPLE (10mV/DIV)
0.10
OUTPUT CURRENT (A)
5V IN/5V OUT
0.08
0.06
0.04
0
0.05
0.10
0.15
0.20
INPUT CURRENT (A)
0.25
0.30
0.35
Figure 6. Typical Isolated Output Supply Current, IISO, as a Function of External
Load, No Dynamic Current Draw at 5 V/5 V
Rev. 0 | Page 9 of 16
BW = 20MHz (400ns/DIV)
07509-011
0
07509-007
0.02
Figure 9. Typical VISO = 5 V Output Voltage Ripple at 90% Load
ADuM5400
3.0
20
2.5
SUPPLY CURRENT (mA)
12
5V IN/5V OUT
8
4
1.5
5V
1.0
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 10. Typical ICH Supply Current per Forward Data Channel
(15 pF Output Load)
0
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 11. Typical IISO(D) Dynamic Supply Current per Output
(15 pF Output Load)
Rev. 0 | Page 10 of 16
07509-016
0
2.0
0.5
07509-013
SUPPLY CURRENT (mA)
16
ADuM5400
TERMINOLOGY
IDD1(Q)
IDD1(Q) is the minimum operating current drawn at the VDD1
pin when there is no external load at VISO and the I/O pins
are operating below 2 Mbps, requiring no additional dynamic
supply current.
IDD1(D)
IDD1(D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps
with the full capacitive load representing the maximum dynamic
load conditions. Treat resistive loads on the outputs separately
from the dynamic load.
IDD1(MAX)
IDD1(MAX) is the input current under full dynamic and VISO load
conditions.
tPHL Propagation Delay
tPHL propagation delay is measured from the 50% level of the
falling edge of the VIx signal to the 50% level of the falling edge
of the VOx signal.
tPLH Propagation Delay
tPLH propagation delay is measured from the 50% level of the
rising edge of the VIx signal to the 50% level of the rising edge
of the VOx signal.
Propagation Delay Skew (tPSK)
tPSK is the magnitude of the worst-case difference in tPHL and/or
tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the
recommended operating conditions.
Channel-to-Channel Matching
Channel-to-channel matching is the absolute value of the
difference in propagation delays between two channels when
operated with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. 0 | Page 11 of 16
ADuM5400
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5400 works on
principles that are common to most modern power supplies. It
has a secondary side controller architecture with isolated pulsewidth modulation (PWM) feedback. VDD1 power is supplied to
an oscillating circuit that switches current into a chip scale air
core transformer. Power transferred to the secondary side is
rectified and regulated to 5 V. The secondary (VISO) side
controller regulates the output by creating a PWM control
signal that is sent to the primary (VDD1) side by a dedicated
iCoupler data channel. The PWM modulates the oscillator
circuit to control the power being sent to the secondary side.
Feedback allows for significantly higher power and efficiency.
length may result in data corruption. Consider a bypass capacitor
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless
both common ground pins are connected together close to the
package.
The ADuM5400 implements undervoltage lockout (UVLO)
with hysteresis on the VDD1, VDDL, and VISO power supplies. This
feature ensures that the converter does not enter oscillation due
to noisy input power or slow power-on ramp rates.
Figure 12. Recommended PCB Layout
A minimum load current of 10 mA is recommended to ensure
optimum load regulation. Smaller loads can generate excess noise
on chip due to short or erratic PWM pulses. Excess noise generated this way can cause data corruption in some circumstances.
PCB LAYOUT
The ADuM5400 digital isolator with integrated 0.5 W isoPower
dc-to-dc converter requires no external interface circuitry for
the logic interfaces. Power supply bypassing is required at the
input and output supply pins (see Figure 12). Note that a low
ESR bypass capacitor is required between Pin 1 and Pin 2,
within 2 mm of the chip leads.
The power supply section of the ADuM5400 uses a 180 MHz
oscillator frequency to efficiently pass power through its chip
scale transformers. In addition, normal operation of the data
section of the iCoupler introduces switching transients on the
power supply pins. Bypass capacitors are required and must
provide transient suppression at several operating frequencies.
Noise suppression requires a low inductance, high frequency
capacitor that is effective at 180 MHz and 360 MHz. Ripple
suppression and proper regulation require a large value capacitor
to provide bulk current at 625 kHz. These are most conveniently
connected between Pin 1 and Pin 2 for VDD1 and between Pin 15
and Pin 16 for VISO. To suppress noise and reduce ripple, a
parallel combination of at least two capacitors is required. The
recommended capacitor values are 0.1 μF and 10 μF for VDD1.
The smaller capacitor must have low ESR; for example, use of a
ceramic capacitor is advised.
Note that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
Installing the bypass capacitor with traces more than 2 mm in
BYPASS < 2mm
VDD1
VISO
GND1
GNDISO
VIB
VIC
VOA
ADuM5400
VOB
VOC
VID
VOD
VDDL
VISO
GND1
GNDISO
07509-017
VIA
In applications involving high common-mode transients, ensure
that board capacitive coupling across the isolation barrier is
minimized. Furthermore, design the board layout so that any
coupling that does occur affects all pins on a given component
side equally. Failure to ensure this can cause differential voltages
between pins, exceeding the absolute maximum ratings for the
device (specified in Table 7) and thereby leading to latch-up
and/or permanent damage.
The ADuM5400 is a power device that dissipates about 1 W
of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation
device, the device depends primarily on heat dissipation into
the PCB through the GND pins. If the device is used at high
ambient temperatures, provide a thermal path from the GND pins
to the PCB ground plane. The board layout in Figure 12 shows
enlarged pads for Pin 8 (GND1) and Pin 9 (GNDISO). Large
diameter vias should be implemented from the pad to the
ground, and power planes should be used to reduce inductance.
Multiple vias in the thermal pads can significantly reduce temperatures inside the chip. The dimensions of the expanded pads are
at the discretion of the designer and depend on the available
board space.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5400 components
must operate at a very high frequency to allow efficient power
transfer through the small transformers. This creates high
frequency currents that can propagate in circuit board ground
and power planes, causing edge emissions and dipole radiation
between the primary and secondary ground planes. Grounded
enclosures are recommended for applications that use these
devices. If grounded enclosures are not possible, follow good RF
design practices in the layout of the PCB. See www.analog.com
for the most current PCB layout recommendations specifically
for the ADuM5400.
Rev. 0 | Page 12 of 16
ADuM5400
50%
tPHL
50%
Figure 13. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM5400 component.
1
0.1
0.01
0.001
1k
100k
10k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 14. Maximum Allowable External Magnetic Flux Density
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM540x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or
reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 1 μs,
periodic sets of refresh pulses indicative of the correct input
state are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than approximately 5 μs,
the input side is assumed to be unpowered or nonfunctional, in
which case the isolator output is forced to a default state by the
watchdog timer circuit. This situation should occur in the
ADuM5400 only during power-up and power-down operations.
The limitation on the ADuM5400 magnetic field immunity is
set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to falsely set or reset
the decoder. The following analysis defines the conditions
under which this can occur.
The 3.3 V operating condition of the ADuM5400 is examined
because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude of >1.0 V.
The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated.
The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
10
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and is of the worst-case polarity), the received pulse is reduced
from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM5400 transformers. Figure 15 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 15, the ADuM5400 is extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For
example, at a magnetic field frequency of 1 MHz, a 0.5 kA current
placed 5 mm away from the ADuM5400 is required to affect the
operation of the component.
1000
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 15. Maximum Allowable Current
for Various Current-to-ADuM5400 Spacings
Rev. 0 | Page 13 of 16
100M
07509-020
OUTPUT (VOx)
07509-018
tPLH
MAXIMUM ALLOWABLE CURRENT (kA)
INPUT (VIx)
100
07509-019
Propagation delay is a parameter that describes the time it takes a
logic signal to propagate through a component (see Figure 13).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high output.
Given the geometry of the receiving coil in the ADuM5400 and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 14.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
PROPAGATION DELAY PARAMETERS
ADuM5400
Note that in the presence of strong magnetic fields and high
frequencies, any loops formed by PCB traces may induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler
data channels, as well as to the power converter. For this reason,
the quiescent currents drawn by the data converter and the
primary and secondary I/O channels cannot be determined
separately. All of these quiescent power demands have been
combined into the IDD1(Q) current, as shown in Figure 16. The
total IDD1 supply current is equal to the sum of the quiescent
operating current; the dynamic current, IDD1(D), demanded by
the I/O channels; and any external IISO load.
IDD1(Q)
IDD1(D)
IISO
E
CONVERTER
PRIMARY
IDDP(D)
SECONDARY
DATA
I/O
4-CHANNEL
Figure 16. Power Consumption Within the ADuM5400
Dynamic I/O current is consumed only when operating a channel
at speeds higher than the refresh rate of fr. The dynamic current
of each channel is determined by its data rate. Figure 10 shows
the current for a channel in the forward direction, meaning that
the input is on the VDD1 side of the part.
The following relationship allows the total IDD1 current to be
calculated:
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4
(1)
where:
IDD1 is the total supply input current.
ICHn is the current drawn by a single channel determined from
Figure 10.
IISO is the current drawn by the secondary side external load.
E is the power supply efficiency at 100 mA load from Figure 4
at the VISO and VDD1 condition of interest.
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
IISO(LOAD) = IISO(MAX) − Σ IISO(D)n; n = 1 to 4
The preceding analysis assumes a 15 pF capacitive load on
each data output. If the capacitive load is larger than 15 pF,
the additional current must be included in the analysis of IDD1
and IISO(LOAD).
POWER CONSIDERATIONS
The ADuM5400 power input, the data input channels on the
primary side, and the data output channels on the secondary
side are all protected from premature operation by UVLO
circuitry. Below the minimum operating voltage, the power
converter holds its oscillator inactive, and all input channel
drivers and refresh circuits are idle. Outputs are held in a low
state to prevent transmission of undefined states during powerup and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached.
IISO(D)
07509-021
PRIMARY
DATA
I/O
4-CHANNEL
CONVERTER
SECONDARY
IISO(MAX) is the maximum external secondary side load current
available at VISO.
IISO(D)n is the dynamic load current drawn from VISO by an
output channel, as shown in Figure 11.
(2)
where:
IISO(LOAD) is the current available to supply an external secondary
side load.
The primary side input channels sample the input and send a
pulse to the inactive secondary output. As the secondary side
converter begins to accept power from the primary, the VISO
voltage starts to rise. When the secondary side UVLO is reached,
the secondary side outputs are initialized to their default low
state until data, either from a logic transition or a dc refresh
cycle, is received from the corresponding primary side input. It
can take up to 1 μs after the secondary side is initialized for the
state of the output to correlate to the primary side input.
The dc-to-dc converter section goes through its own power-up
sequence. When UVLO is reached, the primary side oscillator
also begins to operate, transferring power to the secondary power
circuits. The secondary VISO voltage is below its UVLO limit at
this point; the regulation control signal from the secondary is
not being generated. The primary side power oscillator is allowed
to free run in this circumstance, supplying the maximum amount
of power to the secondary, until the secondary voltage rises to its
regulation setpoint. This creates a large inrush current transient
at VDD1. When the regulation point is reached, the regulation
control circuit produces the regulation control signal that modulates the oscillator on the primary side. The VDD1 current is
reduced and is then proportional to the load current. The
inrush current is less than the short-circuit current shown in
Figure 7. The duration of the inrush depends on the VISO load
conditions and the current available at the VDD1 pin.
Because the rate of charge of the secondary side is dependent on
load conditions, the input voltage, and the output voltage level
selected, ensure that the design allows the converter to stabilize
before valid data is required.
Rev. 0 | Page 14 of 16
ADuM5400
THERMAL ANALYSIS
The ADuM5400 consists of four internal die attached to a split
lead frame with two die attach paddles. For the purposes of
thermal analysis, the die are treated as a thermal unit, with the
highest junction temperature reflected in the θJA from Table 2.
The value of θJA is based on measurements taken with the part
mounted on a JEDEC standard 4-layer board with fine width
traces and still air. Under normal operating conditions, the
ADuM5400 operates at full load up to 85°C and at derated load
up to 105°C.
Any cross-insulation voltage waveform that does not conform
to Figure 18 or Figure 19 should be treated as a bipolar ac waveform, and its peak voltage limited to the 50-year lifetime voltage
value listed in Table 8.
The voltage presented in Figure 19 is shown as sinusoidal for
illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
RATED PEAK VOLTAGE
0V
Figure 17. Bipolar AC Waveform
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation depends on the characteristics of the voltage
waveform applied across the insulation. Analog Devices conducts
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM5400.
Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors
for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest.
Table 8 summarizes the peak voltages for 50 years of service life
in several operating conditions. In many cases, the working
voltage approved by agency testing is higher than the 50-year
service life voltage. Operation at working voltages higher than
the service life voltage listed can lead to premature insulation
failure.
The insulation lifetime of the ADuM5400 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates,
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 17, Figure 18, and Figure 19 illustrate these
different isolation voltage waveforms.
Rev. 0 | Page 15 of 16
RATED PEAK VOLTAGE
07509-024
•
The UVLO level is reached and the outputs are placed in
their high impedance state.
The outputs detect a lack of activity from the inputs and
the outputs transition to their default low state until the
secondary power reaches UVLO and the outputs transition
to their high impedance state.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 8 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases.
0V
Figure 18. DC Waveform
RATED PEAK VOLTAGE
0V
Figure 19. Unipolar AC Waveform
07509-023
•
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines
the maximum working voltage recommended by Analog Devices.
07509-022
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary until one of these events occurs:
ADuM5400
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
032707-B
1
Figure 20. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADuM5400ARWZ1, 2
ADuM5400CRWZ1, 2
1
2
Number
of Inputs,
VDD1 Side
4
4
Number
of Inputs,
VISO Side
0
0
Maximum
Data Rate
(Mbps)
1
25
Maximum
Propagation
Delay, 5 V (ns)
100
60
Maximum
Pulse Width
Distortion (ns)
40
6
Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option.
Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07509-0-10/08(0)
Rev. 0 | Page 16 of 16
Temperature
Range
−40°C to +105°C
−40°C to +105°C
Package
Description
16-Lead SOIC_W
16-Lead SOIC_W
Package
Option
RW-16
RW-16