Cypress CY29943ACT 2.5v or 3.3v 200-mhz 1:18 clock distribution buffer Datasheet

CY29943
2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer
Features
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Description
200-MHz clock support
2.5V or 3.3V operation
LVPECL clock input
LVCMOS-/LVTTL-compatible inputs
18 clock outputs: drive up to 36 clock lines
200 ps max. output-to-output skew
Output Enable control
Pin compatible with MPC942P
Available in Industrial and Commercial
32-pin LQFP package
The CY29943 is a low-voltage 200-MHz clock distribution
buffer with an LVPECL-compatible input clock. All other control
inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs
are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can
drive 50Ω series or parallel terminated transmission lines. For
series terminated transmission line, each output can drive one
or two traces giving the device an effective fanout of 1:36. Low
output-to-output skews make the CY29943 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Block Diagram
32
31
30
29
28
27
26
25
Q0
Q1
Q2
VDD
Q3
Q4
Q5
VSS
Pin Configuration
VDD
18
PECL_CLK
PECL_CLK#
1
2
3
4
5
6
7
8
CY29943
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
Q17
Q16
Q15
VSS
Q14
Q13
Q12
VDD
9
10
11
12
13
14
15
16
OE
Q0-Q17
VSS
VSS
OE
NC
PECL_CLK
PECL_CLK#
VDD
VDD
Cypress Semiconductor Corporation
Document #: 38-07285 Rev. *C
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised December 21, 2002
CY29943
Pin Description[1]
Pin
Name
PWR
5
PECL_CLK
I, PU
PECL Input Clock
6
PECL_CLK#
I, PD
PECL Input Clock
3
OE
I, PU
Output Enable. When HIGH, all the outputs are enabled. When set
LOW, the outputs are at high impedance.
9, 10, 11, 13,
14, 15, 18, 19,
20, 22, 23, 24,
26, 27, 28, 30,
31, 32
Q(17:0)
7, 8, 16, 21, 29
VDD
3.3V or 2.5V Power Supply
1, 2, 12, 17, 25
VSS
Common Ground
4
NC
No Connection
VDD
I/O
O
Description
Clock Outputs
Note:
1. PD = internal pull-down, PU = internal pull-up.
Document #: 38-07285 Rev. *C
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CY29943
Maximum Ratings[2]
Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters (VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, over the specified temperature range)
Parameter
Description
Conditions
Min.
VIL
Input Low Voltage
VSS
VIH
Input High Voltage
2.0
IIL
Input Low Current[3]
IIH
Input High Current[3]
VPP
Peak-to-Peak Input
Voltage
VCMR
Common Mode
Range[4]
PECL_CLK
VOL
Output Low Voltage[5]
IOL = 20 mA
VOH
Output High Voltage[5]
IOH = –20 mA, VDD = 3.3V
2.4
IOH = –16 mA, VDD = 2.5V
2.0
IDDQ
Quiescent Supply
Current
IDD
Dynamic Supply
Current
Zout
Output Impedance
Cin
Input Capacitance
Typ.
Max.
Unit
0.8
V
VDD
V
–200
µA
200
µA
500
1000
mV
VDD = 3.3V
VDD – 1.4
VDD – 0.6
V
VDD = 2.5V
VDD – 1.0
VDD – 0.6
0.5
V
V
5
VDD = 3.3V, Outputs @ 150 MHz,
CL = 15 pF
285
VDD = 3.3V, Outputs @ 200 MHz,
CL = 15 pF
335
VDD = 2.5V, Outputs @ 150 MHz,
CL = 15 pF
200
VDD = 2.5V, Outputs @ 200 MHz,
CL = 15 pF
240
7
mA
VDD = 3.3V
8
12
16
VDD = 2.5V
10
15
20
4
mA
Ω
pF
Notes:
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification.
5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07285 Rev. *C
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CY29943
AC Parameters[6] (VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, over the specified temperature range)
Parameter
Description
Fmax
Input Frequency
Tpd
PECL_CLK to Q Delay[7, 8]
FoutDC
Output Duty Cycle[7, 8, 9]
Tskew
Output-to-Output Skew[7, 8]
Tskew(pp)
Part-to-Part Skew[10]
Tskew(pp)
Part-to-Part Skew[11]
Tr/Tf
Output Clocks Rise/Fall
Time[7, 8]
Conditions
Min.
Typ.
Max.
Unit
200
MHz
ns
VDD = 3.3V
2.0
3.5
4.0
VDD = 2.5V
2.6
4.0
5.2
40
60
%
200
ps
VDD = 3.3V
1.7
ns
VDD = 2.5V
2.2
0.2
0.8V to 2.0V,
VDD = 3.3V
1.0
ns
1.1
ns
0.5V to 1.8V,
VDD = 2.5V
CY29943 DUT
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
RT = 50 ohm
VTT
Figure 1. PECL_CLK CY29943 Test Reference for VCC = 3.3V and VCC = 2.5V
PECL_CLK
PECL_CLK
VPP
VCMR
VCC
Q
VCC /2
tPD
GND
Figure 2. Propagation Delay (TPD) Test Reference
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50Ω transmission lines.
8. Outputs loaded with 15 pF each.
9. See Figure 1.
10. Across temperature and voltage ranges, includes output skew.
11. For a specific temperature and voltage, includes output skew.
Document #: 38-07285 Rev. *C
Page 4 of 7
CY29943
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (FoutDC)
VCC
VCC /2
GND
VCC
VCC /2
tSK(0)
GND
Figure 4. Output-to-Output Skew tsk(0)
Document #: 38-07285 Rev. *C
Page 5 of 7
CY29943
Ordering Information
Part Number
CY29943AI
Package Type
Production Flow
32-pin LQFP
Industrial, –40°C to +85°C
CY29943AIT
32-pin LQFP–Tape and Reel
Industrial, –40°C to +85°C
CY29943AC
32-pin LQFP
Commercial, 0°C to +70°C
32-pin LQFP–Tape and Reel
Commercial, 0°C to +70°C
CY29943ACT
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07285 Rev. *C
Page 6 of 7
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29943
Document History Page
Document Title: CY29943 2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer
Document Number: 38-07285
ECN NO.
Issue
Date
**
111096
02/07/02
BRK
New data sheet
*A
116779
08/14/02
HWT
Add Commercial Temperature range in the ordering Information
REV.
Orig. of
Change
*B
118744
09/18/02
HWT
*C
122877
12/21/02
RBI
Document #: 38-07285 Rev. *C
Description of Change
Update output duty cycle on page 4
Add power up requirements to maximum rating information.
Page 7 of 7
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