Intersil DG181AP/883B High-speed drivers with jfet switch Datasheet

Semiconductor
DG181 thru DG191
CT
ODU ODUCT
R
P
PR
TE
45
OLE
UTE
April 1999
OBS UBSTIT 49, HI-51051
S
0
E
I-5
IH5
SIBL G185: H I-5051, IH5043
POS
H
D
0
,
,
9
3 ,
03
84
Features
DG1 90: DG4 043, HI-0
DG1 91: HI-5
• Constant ON-Resistance
for Signals to ±10V (DG182,
DG1
High-Speed Drivers with JFET Switch
Description
The DG181 thru DG191 series of analog gates consist of 2
or 4 N-channel junction-type field-effect transistors (JFET)
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8V to 2V) to control the
ON-OFF state of each switch. The driver is designed to
provide a turn-off speed which is faster than turn-on speed,
so that break-before-make action is achieved when
switching from one channel to another. In the ON state, each
switch conducts current equally well in both directions. In the
OFF condition, the switches will block voltages up to 20V
peak-to-peak. Switch-OFF input-output isolation 50dB at
10MHz, due to the low output impedance of the FET-gate
driving circuit.
DG185, DG188, DG191), to ±7.5V (All Devices)
• ±15V Power Supplies
• <2nA Leakage from Signal Channel in Both ON and
OFF States
• TTL, DTL, RTL Direct Drive Compatibility
• tON, tOFF <150ns, Break-Before-Make Action
• Cross-Talk and Open Switch Isolation >50dB at 10MHz
(75Ω Load)
Functional Diagrams (Typical Channel)
DG186, DG187, DG188 - ONE AND TWO CHANNEL
SPDT AND SPST CIRCUIT CONFIGURATION
VL
DG183, DG184, DG185 - TWO CHANNEL DPST
CIRCUIT CONFIGURATION
VL
V+
S1
D1
IN
V+
S
D
IN
S2
D2
GND
S
D
GND
V-
V-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright
© Harris Corporation 1999
1
File Number
3114.4
DG181 Series
Part Number Information (Continued)
Part Number Information
PART NUMBER
TYPE
RDS(ON)
(MAX)
PACKAGE
PART NUMBER
TYPE
RDS(ON)
(MAX)
PACKAGE
DG181AA
Dual SPST
30Ω
10 Lead CAN
DG187AA
SPDT
30Ω
10 Lead CAN
DG181AA/883B
Dual SPST
30Ω
10 Lead CAN
DG187AA/883B
SPDT
30Ω
10 Lead CAN
DG181AP
Dual SPST
30Ω
14 Lead SBDIP
DG187AP
SPDT
30Ω
14 Lead SBDIP
DG181AP/883B
Dual SPST
30Ω
14 Lead SBDIP
DG187AP/883B
SPDT
30Ω
14 Lead SBDIP
DG181BA
Dual SPST
30Ω
10 Lead CAN
DG187BA
SPDT
30Ω
10 Lead CAN
DG181BP
Dual SPST
30Ω
14 Lead SBDIP
DG187BP
SPDT
30Ω
14 Lead SBDIP
DG182AA
Dual SPST
75Ω
10 Lead CAN
DG188AA
SPDT
75Ω
10 Lead CAN
DG182AA/883B
Dual SPST
75Ω
10 Lead CAN
DG188AA/883B
SPDT
75Ω
10 Lead CAN
DG182AP
Dual SPST
75Ω
14 Lead SBDIP
DG188AP
SPDT
75Ω
14 Lead SBDIP
DG182AP/883B
Dual SPST
75Ω
14 Lead SBDIP
DG188AP/883B
SPDT
75Ω
14 Lead SBDIP
DG182BA
Dual SPST
75Ω
10 Lead CAN
DG188BA
SPDT
75Ω
10 Lead CAN
DG182BP
Dual SPST
75Ω
14 Lead SBDIP
DG188BP
SPDT
75Ω
14 Lead SBDIP
DG184AP
Dual DPST
30Ω
16 Lead SBDIP
DG190AP
Dual SPDT
30Ω
16 Lead SBDIP
DG184AP/883B
Dual DPST
30Ω
16 Lead SBDIP
DG190AP/883B
Dual SPDT
30Ω
16 Lead SBDIP
DG184BP
Dual DPST
30Ω
16 Lead SBDIP
DG190BP
Dual SPDT
30Ω
16 Lead SBDIP
DG185AP
Dual DPST
75Ω
16 Lead SBDIP
DG191AP
Dual SPDT
75Ω
16 Lead SBDIP
DG185AP/883B
Dual DPST
75Ω
16 Lead SBDIP
DG191AP/883B
Dual SPDT
75Ω
16 Lead SBDIP
DG185BP
Dual DPST
75Ω
16 Lead SBDIP
DG191BP
Dual SPDT
75Ω
16 Lead SBDIP
2
DG181 Series
Pinouts and Switching State Diagrams
DUAL SPST - DG181, DG182
(TO-100 METAL CAN)
TOP VIEW
DUAL SPST - DG181, DG182
(CDIP)
TOP VIEW
S2
10
S1
1
9
D2
D1
2
8
IN2
IN1
3
7
V-
4
V+
6
5
GND
S1 1
14 S2
D1 2
13 D2
NC 3
12 NC
NC 4
11 NC
IN1 5
10 IN2
V+ 6
9 V-
VL 7
8 GND
VL
DUAL DPST - DG184, DG185
(CDIP)
TOP VIEW
D1
1
16 S1
NC
2
15 IN1
D3
3
14 V-
S3
4
13 GND
S4
5
12 VL
D4
6
11 V+
NC
7
10 IN2
D2
8
9 S2
SPDT - DG187, DG188
(TO-100 METAL CAN)
TOP VIEW
D2
10
D1
1
9
S2
S1
2
8
NC
IN
3
7
V-
4
V+
6
5
GND
VL
SPDT - DG187, DG188
(CDIP)
TOP VIEW
DUAL SPDT - DG190, DG191
(CDIP)
TOP VIEW
NC 1
14 NC
D1
1
16 S1
NC 2
13 NC
NC
2
15 IN1
D3
3
14 V-
S3
4
13 GND
S4
5
12 VL
D4
6
11 V+
NC
7
10 IN2
D2
8
9 S2
D1 3
12 D2
S1 4
11 S2
IN 5
10 NC
V+ 6
9 V-
VL 7
8 GND
3
DG181 Series
Absolute Maximum Ratings
Thermal Information
V+ - V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
V+ - VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
VD - V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
VD - VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22V
VL - V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
VL - VIN, VL - GND, VIN - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
GND - V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27V
GND - VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Current (S or D) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . +300oC
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Maximum Power Dissipation †
TO Metal Can Packages . . . . . . . . . . . . . . . . . . . . . . . . . . 450mW
Derate 6mW/ oC above +75oC
Ceramic DIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 825mW
Derate 11mW/ oC above +75oC
† Device mounted with all leads welded or soldered to PC board.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
DEVICE
NUMBER
PARAMETER
V+ = +15V, V- = -15V, VL = 5V, Unless Otherwise Specified
(NOTE 1)
TEST CONDITIONS
A SERIES
B SERIES
-55oC
+25oC
+125oC
-20oC
+25oC
+85oC
UNITS
SWITCH
DG181, DG182,
DG184, DG185,
DG187, DG188,
DG190, DG191
VS = 10V, VD = -10V,
V+ = 10V, V- = -20V,
VIN = “OFF”
-
±1
100
-
±5
100
nA
DG181, DG184,
DG187, DG190
VS = 7.5V, VD = -7.5V,
VIN = “OFF”
-
±1
100
-
±5
100
nA
DG182, DG185,
DG188, DG191
VS = 10V, VD = -10V,
VIN = “OFF”
-
±1
100
-
±5
100
nA
DG181, DG182,
DG184, DG185,
DG187, DG188,
DG190, DG191
VS = 10V, VD = -10V,
V+ = 10V, V- = -20V,
VIN = “OFF”
-
±1
100
-
±5
100
nA
DG181, DG184,
DG187, DG190
VS = 7.5V, VD = -7.5V,
VIN = “OFF”
-
±1
100
-
±5
100
nA
DG182, DG185,
DG188, DG191
VS = 10V, VD = -10V,
VIN = “OFF”
-
±1
100
-
±5
100
nA
DG181, DG184,
DG187, DG190
VD = VS = -7.5V, VIN = “ON”
-
±2
-200
-
-10
-200
nA
DG182, DG185,
DG188, DG191
VD = VS = -10V, VIN = “ON”
-
±2
-200
-
-10
-200
nA
IINL
All
VIN = 0V
-250
-250
-250
-250
-250
-250
µA
IINH
All
VIN = 5V
-
10
20
-
10
20
µA
30Ω Switches
See Switching Time
Test Circuit
-
150
-
-
180
-
ns
IS(OFF)
ID(OFF)
ID(ON) + IS(ON)
INPUT
DYNAMIC
tON
75Ω Switches
tOFF
30Ω and 75Ω
Switches
CS(OFF)
DG181, DG182,
DG184, DG185,
DG187, DG188,
DG190, DG191
CD(ON) +
CS(ON)
OFF Isolation
-
250
-
-
300
-
ns
-
130
-
-
150
-
ns
VS = -5V, ID = 0, f = 1MHz
9 Typical
pF
VD = +5V, IS = 0, f = 1MHz
6 Typical
pF
VD = VS = 0, f = 1MHz
14 Typical
pF
Typically >50dB at 10MHz
-
RL = 75Ω, CL = 3pF
4
DG181 Series
Electrical Specifications
DEVICE
NUMBER
V+ = +15V, V- = -15V, VL = 5V, Unless Otherwise Specified (Continued)
(NOTE 1)
TEST CONDITIONS
A SERIES
B SERIES
-55oC
+25oC
+125oC
-20oC
+25oC
+85oC
UNITS
-
1.5
-
-
1.5
-
mA
DG184, DG185
-
0.1
-
-
0.1
-
mA
DG187, DG188
-
0.8
-
-
0.8
-
mA
DG181, DG182,
DG190, DG191
-
-5.0
-
-
-5.0
-
mA
DG184, DG185
-
-4.0
-
-
-4.0
-
mA
DG187, DG188
-
-3.0
-
-
-3.0
-
mA
DG181, DG182,
DG184, DG185,
DG190, DG191
-
4.5
-
-
4.5
-
mA
DG187, DG188
-
3.2
-
-
3.2
-
mA
PARAMETER
SUPPLY
I+
I-
IL
DG181, DG182,
DG190, DG191
IGND
All
I+
DG181, DG182,
DG190, DG191
I-
IL
IGND
VIN = 5V
-
-2.0
-
-
-2.0
-
mA
-
1.5
-
-
1.5
-
mA
DG184, DG185
-
3.0
-
-
3.0
-
mA
DG187, DG188
-
0.8
-
-
0.8
-
mA
DG181, DG182,
DG190, DG191
-
-5.0
-
-
-5.0
-
mA
DG184, DG185
-
-5.5
-
-
-5.5
-
mA
DG187, DG188
-
-3.0
-
-
-3.0
-
mA
DG181, DG182,
DG184, DG185,
DG190, DG191
-
4.5
-
-
4.5
-
mA
DG187, DG188
-
3.2
-
-
3.2
-
mA
All
-
-2.0
-
-
-2.0
-
mA
+85oC
UNITS
VIN = 0V
NOTE:
1. See Switching State Diagrams for VIN “ON” and VIN “OFF” Test Conditions.
Electrical Specifications
DEVICE
NUMBER
Maximum Resistances (RDS(ON) MAX)
TEST CONDITIONS (NOTE 1)
V+ = 15V, V- = -15V, VL = 5V
MILITARY
TEMPERATURE
-55oC
+25oC
INDUSTRIAL
TEMPERATURE
+125oC
-20oC
+25oC
DG181
VD = -7.5V
30
30
60
50
50
75
Ω
DG182
VD = -10V
75
75
100
100
100
150
Ω
DG184
VD = -7.5V
30
30
60
50
50
75
Ω
IS = -10mA, VIN = “ON”
DG185
VD = -10V
75
75
150
100
100
150
Ω
DG187
VD = -7.5V
30
30
60
50
50
75
Ω
Ω
DG188
VD = -10V
75
75
150
100
100
150
DG190
VD = -7.5V
30
30
60
50
50
75
Ω
DG191
VD = -10V
75
75
150
100
100
150
Ω
NOTES:
1. See Switching State Diagrams for VIN “ON” and VIN “OFF” Test Conditions.
2. Normally the minimum signal handling capability of the DG181 thru DG191 family is 20V peak to peak for the 75Ω switches and 15V peakto-peak for the 30Ω (refer ID and IS tests above).
3. For other Analog Signals, the following guidelines can be used: proper switch turn-off requires that V- ≤ VANALOG(peak) - VP where VP =
7.5V for the 80Ω switches and VP = 5.0V for 75Ω switches e.g., - 10V minimum (-peak) analog signal and a 75Ω switch (VP = 5V), requires
that V- ≤ -10V -5V = -15V.
5
DG181 Series
DUAL DPST - DG184/185
DUAL SPST - DG181/182
TEST CONDITIONS
TEST CONDITIONS
VIN “ON” = 0.8V
All Channels
VIN “ON” = 2.0V
All Channels
VIN “OFF” = 2.0V
All Channels
VIN “OFF” = 0.8V
All Channels
NOTE:
NOTE:
1. Switch states are for logic “1” input = 2.0V.
1. Switch states are for logic “1” input = 2.0V.
SPDT - DG190/191
SPDT - DG187/188
TEST CONDITIONS
TEST CONDITIONS
VIN “ON” = 2.0V
Channel 1
VIN “ON” = 2.0V
Channel 1 and 2
VIN “ON” = 0.8V
Channel 2
VIN “ON” = 0.8V
Channel 3 and 4
VIN “OFF” = 2.0V
Channel 2
VIN “OFF” = 2.0V
Channel 3 and 4
VIN “OFF” = 0.8V
Channel 1
VIN “OFF” = 0.8V
Channel 1 and 2
NOTE:
NOTE:
1. Switch states are for logic “1” input = 2.0V.
1. Switch states are for logic “1” input = 2.0V.
Switching Time Test Circuits
+5V
VL
LOGIC 3V
INPUT
tR < 10ns
tF < 10ns
SWITCH
INPUT
50%
50%
0V
tON, VS = +10V
tOFF, VS = -10V
LOGIC
INPUT
SWITCH
V
INPUT S
S1
IN1
GND
t ON
D1
SWITCH
OUTPUT
VO
RL
1kΩ
CL
30pF
90%
90%
SWITCH 0V
OUTPUT
+15V
VCC
t OFF
0V
V-15V
(REPEAT TEST FOR
ALL CHANNELS)
VO = VS
FIGURE 1. SWITCHING TIME TEST WAVEFORMS (Note 1)
RL
RL + RDS(ON)
FIGURE 2. SWITCHING TIME TEST CIRCUIT (Note 2)
NOTES:
1. Switch output waveform shown for VS = constant with logic input waveform as shown.
2. VS may be + or - as per switching time test circuit. VO is the steady state output with switch on. Feedthrough via gate capacitance may
result in spikes at leading and trailing edge of output waveform.
6
DG181 Series
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
-A-
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
LEAD FINISH
c1
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
INCHES
(c)
SECTION A-A
D S
D
BASE
PLANE
S2
Q
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
ccc M C A - B S D S
eA/2
c
aaa M C A - B S D S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
MILLIMETERS
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
M
-
0.0015
-
0.038
2
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
N
14
14
8
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
7
DG181 Series
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
-A-
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
LEAD FINISH
c1
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
INCHES
(c)
SECTION A-A
D S
D
BASE
PLANE
S2
Q
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
ccc M C A - B S D S
eA/2
c
aaa M C A - B S D S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
MILLIMETERS
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
M
-
0.0015
-
0.038
2
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
N
16
16
8
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
8
DG181 Series
Metal Can Packages (Can)
T10.B MIL-STD-1835 MACY1-X10 (A2)
REFERENCE PLANE
A
10 LEAD METAL CAN PACKAGE
e1
L
L2
L1
INCHES
ØD2
A
A
k1
Øe
ØD ØD1
2
N
1
β
Øb1
Øb
F
α
k
C
L
BASE AND
SEATING PLANE
Q
BASE METAL
Øb1
LEAD FINISH
Øb2
SECTION A-A
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.185
4.19
4.70
-
Øb
0.016
0.019
0.41
0.48
1
Øb1
0.016
0.021
0.41
0.53
1
Øb2
0.016
0.024
0.41
0.61
-
ØD
0.335
0.375
8.51
9.52
-
ØD1
0.305
0.335
7.75
8.51
-
ØD2
0.110
0.160
2.79
4.06
-
e
0.230 BSC
5.84 BSC
-
e1
0.115 BSC
2.92 BSC
-
F
-
0.040
-
1.02
-
k
0.027
0.034
0.69
0.86
-
k1
0.027
0.045
0.69
1.14
2
L
0.500
0.750
12.70
19.05
1
L1
-
0.050
-
1.27
1
L2
0.250
-
6.35
-
1
Q
0.010
0.045
0.25
1.14
-
α
36o BSC
36o BSC
3
β
36o BSC
36o BSC
3
N
10
10
4
Rev. 0 5/18/94
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
9
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