ATMEL ATTINY13-12SI 8-bit avr microcontroller with 1k bytes in-system programmable flash Datasheet

Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
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– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 1K Byte of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
– 64 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 64 Bytes Internal SRAM
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Peripheral Features
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
Operating Voltage:
– 1.8 - 5.5V for ATtiny13V
– 2.7 - 5.5V for ATtiny13
Speed Grade
– ATtiny13V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V
– ATtiny13: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 240µA
– Power-down Mode:
< 0.1µA at 1.8V
8-bit
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
ATtiny13
Preliminary
Pin Configurations
Figure 1. Pinout ATtiny13
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
(PCINT4/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/ADC1/T0/PCINT2)
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
Rev. 2535B–AVR–01/04
Overview
The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
8-BIT DATABUS
STACK
POINTER
SRAM
VCC
PROGRAM
COUNTER
GND
PROGRAM
FLASH
WATCHDOG
OSCILLATOR
CALIBRATED
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
TIMING AND
CONTROL
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
INTERRUPT
UNIT
X
Y
Z
PROGRAMMING
LOGIC
ALU
DATA
EEPROM
STATUS
REGISTER
ADC /
ANALOG COMPARATOR
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
RESET
CLKI
PB0-PB5
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ATtiny13
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATtiny13 provides the following features: 1K byte of In-System Programmable
Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and
External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with
internal Oscillator, and three software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and
Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC
Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize
switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology.
The On-chip ISP Flash allows the Program memory to be re-programmed In-System
through an SPI serial interface, by a conventional non-volatile memory programmer or
by an On-chip boot code running on the AVR core.
The ATtiny13 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny13 as listed on
page 49.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table
12 on page 30. Shorter pulses are not guaranteed to generate a reset.
About Code
Examples
This documentation contains simple code examples that briefly show how to use various
parts of the device. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
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AVR CPU Core
Introduction
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.
Architectural Overview
Figure 3. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the Program
memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept
enables instructions to be executed in every clock cycle. The Program memory is InSystem Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
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ATtiny13
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these
address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt
Vector in the Interrupt Vector table. The interrupts have priority in accordance with their
Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as
the Data Space locations following those of the Register File, 0x20 - 0x5F.
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
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Status Register
The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, as
described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
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ATtiny13
General Purpose
Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
•
One 8-bit output operand and one 8-bit result input
•
Two 8-bit output operands and one 8-bit result input
•
Two 8-bit output operands and one 16-bit result input
•
One 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
General
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers,
and most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a Data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to
index any register in the file.
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The X-register, Y-register, and
Z-register
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
15
X-register
XH
XL
7
0
R27 (0x1B)
YH
YL
7
0
R29 (0x1D)
Z-register
0
R26 (0x1A)
15
Y-register
0
7
0
7
0
R28 (0x1C)
15
ZH
7
0
ZL
7
R31 (0x1F)
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set
reference for details).
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM is defined to the last
address in SRAM during on reset. The Stack Pointer must be set to point above 0x60.
The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by
two when data is popped from the Stack with return from subroutine RET or return from
interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit
Read/Write
Initial Value
8
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
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ATtiny13
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock
source for the chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 7. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
Reset and Interrupt
Handling
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate Program Vector in the Program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on
page 40. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is
INT0 – the External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.
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There are basically two types of interrupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt
Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to
avoid interrupts during the timed EEPROM write sequence..
Assembly Code Example
in r16, SREG
cli
; store SREG value
; disable interrupts during timed sequence
sbi EECR, EEMWE
; start EEPROM write
sbi EECR, EEWE
out SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
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ATtiny13
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles the Program Vector address for the actual interrupt
handling routine is executed. During this four clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack
Pointer is incremented by two, and the I-bit in SREG is set.
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AVR ATtiny13
Memories
This section describes the different memories in the ATtiny13. The AVR architecture
has two main memory spaces, the Data memory and the Program memory space. In
addition, the ATtiny13 features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
In-System Reprogrammable Flash
Program Memory
The ATtiny13 contains 1K byte On-chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATtiny13 Program Counter (PC) is nine bits wide, thus addressing the 512 Program
memory locations. “Memory Programming” on page 100 contains a detailed description
on Flash data serial downloading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see
the LPM – Load Program memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 9.
Figure 8. Program Memory Map
Program Memory
0x0000
0x01FF
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ATtiny13
SRAM Data Memory
Figure 9 shows how the ATtiny13 SRAM Memory is organized.
The lower 160 Data memory locations address both the Register File, the I/O memory
and the internal data SRAM. The first 32 locations address the Register File, the next 64
locations the standard I/O memory, and the last 64 locations address the internal data
SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal
data SRAM in the ATtiny13 are all accessible through all these addressing modes. The
Register File is described in “General Purpose Register File” on page 7.
Figure 9. Data Memory Map
Data Memory
32 Registers
64 I/O Registers
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Internal SRAM
(64 x 8)
0x009F
Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clkCPU cycles as described in Figure
10.
Figure 10. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address
Compute Address
Address valid
Write
Data
WR
Read
Data
RD
Memory Access Instruction
Next Instruction
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EEPROM Data Memory
The ATtiny13 contains 64 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the
EEPROM Data Register, and the EEPROM Control Register. For a detailed description
of Serial data downloading to the EEPROM, see page 103.
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in Table 1. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user
code contains instructions that write the EEPROM, some precautions must be taken. In
heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page
18 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “Atomic Byte Programming” on page 16 and “Split Byte Programming”
on page 16 for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
EEPROM Address Register –
EEARL
Bit
7
6
5
4
3
2
1
0
–
–
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
X
X
X
X
X
X
EEARL
• Bits 7..6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 5..0 – EEAR5..0: EEPROM Address
The EEPROM Address Register – EEARL – specifies the EEPROM address in the 64
bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
63. The initial value of EEARL is undefined. A proper value must be written before the
EEPROM may be accessed.
EEPROM Data Register –
EEDR
Bit
7
6
5
4
3
2
1
0
EEDR7
EEDR6
EEDR5
EEDR4
EEDR3
EEDR2
EEDR1
EEDR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
EEDR
• Bits 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEARL.
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ATtiny13
2535B–AVR–01/04
ATtiny13
EEPROM Control Register –
EECR
Bit
7
6
5
4
3
2
1
0
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
X
X
0
0
X
0
EECR
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use and will always read as 0 in ATtiny13. For compatibility
with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 6 – Res: Reserved Bit
This bit is reserved in the ATtiny13 and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that
will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write
operations in two different operations. The Programming times for the different modes
are shown in Table 1. While EEPE is set, any write to EEPMn will be ignored. During
reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
Table 1. EEPROM Mode Bits
EEPM1
EEPM0
Programming
Time
0
0
3.4 ms
Erase and Write in one operation (Atomic Operation)
0
1
1.8 ms
Erase Only
1
0
1.8 ms
Write Only
1
1
–
Operation
Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a
constant interrupt when Non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at
the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE
has been written to one by software, hardware clears the bit to zero after four clock
cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the
EEPROM. When EEPE is written, the EEPROM will be programmed according to the
EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has
elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is
halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When
the correct address is set up in the EEARL Register, the EERE bit must be written to
15
2535B–AVR–01/04
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed. The user should poll the
EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEARL Register.
Atomic Byte Programming
Using Atomic Byte Programming is the simplest mode. When writing a byte to the
EEPROM, the user must write the address into the EEARL Register and data into EEDR
Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is
written) will trigger the erase/write operation. Both the erase and write cycle are done in
one operation and the total programming time is given in Table 1. The EEPE bit remains
set until the erase and write operations are completed. While the device is busy with
programming, it is not possible to do any other EEPROM operations.
Split Byte Programming
It is possible to split the erase and write cycle in two different operations. This may be
useful if the system requires short access time for some limited period of time (typically
if the power supply voltage falls). In order to take advantage of this method, it is required
that the locations to be written have been erased before the write operation. But since
the erase and write operations are split, it is possible to do the erase operations when
the system allows doing time-critical operations (typically after Power-up).
Erase
To erase a byte, the address must be written to EEARL. If the EEPMn bits are 0b01,
writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set until the
erase operation completes. While the device is busy programming, it is not possible to
do any other EEPROM operations.
Write
To write a location, the user must write the address into EEARL and the data into EEDR.
If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written)
will trigger the write operation only (programming time is given in Table 1). The EEPE bit
remains set until the write operation completes. If the location to be written has not been
erased before write, the data that is stored must be considered as lost. While the device
is busy with programming, it is not possible to do any other EEPROM operations.
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “Oscillator Calibration Register –
OSCCAL” on page 22.
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ATtiny13
The following code examples show one assembly and one C function for erase, write, or
atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g.,
by disabling interrupts globally) so that no interrupts will occur during execution of these
functions.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set Programming mode
ldi
r16, (0<<EEPM1)|(0<<EEPM0)
out
EECR, r16
; Set up address (r17) in address register
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned char ucAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set Programming mode */
EECR = (0<<EEPM1)|(0>>EEPM0)
/* Set up address and data registers */
EEARL = ucAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
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2535B–AVR–01/04
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r17) in address register
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in
r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned char ucAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEARL = ucAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
Preventing EEPROM
Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using EEPROM, and the same design solutions should
be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EE PR O M da ta co rrupt i o n c an eas il y be av oi de d b y f o l lo wi ng t hi s de si gn
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
VCC reset protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply voltage is
sufficient.
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ATtiny13
I/O Memory
The I/O space definition of the ATtiny13 is shown in “Register Summary” on page 153.
All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between
the 32 general purpose working registers and the I/O space. I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and
SBIC instructions. Refer to the instruction set section for more details. When using the
I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
When addressing I/O Registers as data space using LD and ST instructions, 0x20 must
be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
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System Clock and
Clock Options
Clock Systems and their
Distribution
Figure 11 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 26. The clock systems
are detailed below.
Figure 11. Clock Distribution
General I/O
Modules
ADC
clkI/O
clkADC
CPU Core
RAM
Flash and
EEPROM
clkCPU
AVR Clock
Control Unit
clkFLASH
Reset Logic
Source clock
Clock
Multiplexer
External Clock
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Calibrated RC
Oscillator
CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O
clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if
the I/O clock is halted.
Flash Clock – clkFLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
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ATtiny13
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ATtiny13
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as
shown below. The clock from the selected source is input to the AVR clock generator,
and routed to the appropriate modules.
Table 2. Device Clocking Options Select(1)
Device Clocking Option
CKSEL1..0
Calibrated Internal RC Oscillator
01, 10
External Clock
00
128 kHz Internal Oscillator
11
Note:
1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the
CPU wakes up from Power-down or Power-save, the selected clock source is used to
time the start-up, ensuring stable Oscillator operation before instruction execution starts.
When the CPU starts from reset, there is an additional delay allowing the power to reach
a stable level before commencing normal operation. The Watchdog Oscillator is used
for timing this real-time part of the start-up time. The number of WDT Oscillator cycles
used for each time-out is shown in Table 3.
Table 3. Number of Watchdog Oscillator Cycles
Default Clock Source
Typ Time-out
Number of Cycles
4 ms
512
64 ms
8K (8,192)
The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. The
default clock source setting is therefore the Internal RC Oscillator running at 9.6 MHz
with longest start-up time and an initial system clock prescaling of 8. This default setting
ensures that all users can make their desired clock source setting using an In-System or
High-voltage Programmer.
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2535B–AVR–01/04
Calibrated Internal RC
Oscillator
The calibrated internal RC Oscillator provides an 9.6 MHz or 4.8 MHz clock. The frequency is the nominal value at 3V and 25°C. If the frequency exceeds the specification
of the device (depends on VCC ), the CKDIV8 Fuse must be programmed in order to
divide the internal frequency by 8 during start-up. See “System Clock Prescaler” on
page 24. for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 4. If selected, it will operate with no external
components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this
calibration gives a frequency within ± 10% of the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is
possible to achieve ± 3% accuracy at any given VCC and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the
Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 102.
Table 4. Internal Calibrated RC Oscillator Operating Modes
CKSEL1..0
Nominal Frequency
(1)
9.6 MHz
10
01
Note:
4.8 MHz
1. The device is shipped with this option selected.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 5..
Table 5. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
SUT1..0
Start-up Time
from Power-down
Additional Delay from
Reset (VCC = 5.0V)
00
6 CK
14CK
01
6 CK
14CK + 4 ms
Fast rising power
6 CK
14CK + 64 ms
Slowly rising power
(1)
10
11
Note:
Oscillator Calibration Register
– OSCCAL
Recommended Usage
BOD enabled
Reserved
1. The device is shipped with this option selected.
Bit
7
6
5
4
3
2
1
0
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
OSCCAL
Device Specific Calibration Value
• Bit 7 – Res: Reserved Bit
This bit is reserved bit in the ATtiny13 and will always read as zero.
• Bits 6..0 – CAL6..0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip
Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing nonzero values to this register will increase the frequency of the internal Oscillator. Writing
0x7F to the register gives the highest available frequency. The calibrated Oscillator is
used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 2% above the nominal frequency. Otherwise, the EEPROM or Flash
22
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ATtiny13
write may fail. Note that the Oscillator is intended for calibration to 9.6 MHz or 4.8 MHz.
Tuning to other values is not guaranteed, as indicated in Table 6.
Avoid changing the calibration value in large steps when calibrating the calibrated internal RC Oscillator to ensure stable operation of the MCU. A variation in frequency of
more than 2% from one cycle to the next can lead to unpredictable behavior. Changes in
OSCCAL should not exceed 0x20 for each calibration.
Table 6. Internal RC Oscillator Frequency Range
External Clock
OSCCAL Value
Min Frequency in Percentage of
Nominal Frequency
Max Frequency in Percentage of
Nominal Frequency
0x00
50%
100%
0x3F
75%
150%
0x7F
100%
200%
To drive the device from an external clock source, CLKI should be driven as shown in
Figure 12. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”.
Figure 12. External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
CLKI
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 7.
Table 7. Start-up Times for the External Clock Selection
SUT1..0
Start-up Time from Powerdown and Power-save
Additional Delay from
Reset
00
6 CK
14CK
01
6 CK
14CK + 4 ms
Fast rising power
10
6 CK
14CK + 64 ms
Slowly rising power
11
Recommended Usage
BOD enabled
Reserved
When applying an external clock, it is required to avoid sudden changes in the applied
clock frequency to ensure stable operation of the MCU. A variation in frequency of more
than 2% from one clock cycle to the next can lead to unpredictable behavior. It is
required to ensure that the MCU is kept in Reset during such changes in the clock
frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of
the internal clock frequency while still ensuring stable operation. Refer to “System Clock
Prescaler” on page 24 for details.
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2535B–AVR–01/04
128 kHz Internal
Oscillator
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz.
The frequency is nominal at 3V and 25°C. This clock may be select as the system clock
by programming the CKSEL Fuses to “11”.
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 8.
Table 8. Start-up Times for the 128 kHz Internal Oscillator
SUT1..0
Start-up Time from Powerdown and Power-save
Additional Delay from
Reset
00
6 CK
14CK
01
6 CK
14CK + 4 ms
Fast rising power
10
6 CK
14CK + 64 ms
Slowly rising power
11
System Clock Prescaler
Clock Prescale Register –
CLKPR
Recommended Usage
BOD enabled
Reserved
The ATtiny13 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC,
clkCPU, and clkFLASH are divided by a factor as shown in Table 9.
Bit
7
6
5
4
3
2
1
0
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
CLKPR
See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS
bits are written. Rewriting the CLKPCE bit within this time-out period does neither
extend the time-out period, nor clear the CLKPCE bit.
• Bits 6..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 9.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
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ATtiny13
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits
are reset to “0011”, giving a division factor of eight at start up. This feature should be
used if the selected clock source has a higher frequency than the maximum frequency
of the device at the present operating conditions. Note that any value can be written to
the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Table 9. Clock Prescaler Select
Switching Time
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
0
0
1
1
8
0
1
0
0
16
0
1
0
1
32
0
1
1
0
64
0
1
1
1
128
1
0
0
0
256
1
0
0
1
Reserved
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
When switching between prescaler settings, the System Clock Prescaler ensures that
no glitches occur in the clock system and that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to
determine the state of the prescaler – even if it were readable, and the exact time it
takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2
before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the
new prescaler setting.
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2535B–AVR–01/04
Power Management
and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choice for low power applications.
Sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR provides various sleep modes allowing the user to tailor the
power consumption to the application’s requirements.
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic
one and a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, or Power-down) will be
activated by the SLEEP instruction. See Table 10 for a summary. If an enabled interrupt
occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted
for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register
File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs
during sleep mode, the MCU wakes up and executes from the Reset Vector.
Figure 11 on page 20 presents the different clock systems in the ATtiny13, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for power management.
Bit
7
6
5
4
3
2
1
0
–
PUD
SE
SM1
SM0
—
ISC01
ISC00
Read/Write
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is
the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one
just before the execution of the SLEEP instruction and to clear it immediately after waking up.
• Bits 4, 3 – SM1..0: Sleep Mode Select Bits 2..0
These bits select between the three available sleep modes as shown in Table 10.
Table 10. Sleep Mode Select
SM1
SM0
Sleep Mode
0
0
Idle
0
1
ADC Noise Reduction
1
0
Power-down
1
1
Reserved
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny13 and will always read as zero.
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ATtiny13
Idle Mode
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter,
Watchdog, and the interrupt system to continue operating. This sleep mode basically
halts clkCPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt
is not required, the Analog Comparator can be powered down by setting the ACD bit in
the Analog Comparator Control and Status Register – ACSR. This will reduce power
consumption in Idle mode. If the ADC is enabled, a conversion starts automatically
when this mode is entered.
ADC Noise Reduction
Mode
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O,
clkCPU, and clkFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external
level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise
Reduction mode.
Power-down Mode
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts,
and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog
Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt
can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of
asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 52 for details.
Table 11. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
clkADC
Main Clock
Source Enabled
INT0 and
Pin Change
SPM/
EEPROM
Ready
ADC
Other I/O
Watchdog
Interrupt
Wake-up Sources
X
X
X
X
X
X
X
X
X
X
X(1)
X
X
ADC Noise
Reduction
Power-down
Note:
Oscillators
clkIO
Idle
clkFLASH
Sleep Mode
clkCPU
Active Clock Domains
X(1)
X
X
1. For INT0, only level interrupt.
27
2535B–AVR–01/04
Minimizing Power
Consumption
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 77 for details on ADC operation.
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on
page 74 for details on how to configure the Analog Comparator.
Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be turned
off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in
all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 32 for details on how to configure the Brown-out Detector.
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in
the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be
used immediately. Refer to “Internal Voltage Reference” on page 34 for details on the
start-up time.
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Interrupts” on page 40 for details on how to configure the Watchdog Timer.
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power.
The most important thing is then to ensure that no pins drive resistive loads. In sleep
modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the
input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to the section “Digital Input
Enable and Sleep Modes” on page 45 for details on which pins are enabled. If the input
buffer is enabled and the input signal is left floating or has an analog signal level close to
VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to VCC/2 on an input pin can cause significant current even in active
mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to “Digital Input Disable Register 0 – DIDR0” on page 76 for details.
28
ATtiny13
2535B–AVR–01/04
ATtiny13
System Control and
Reset
Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a
RJMP – Relative Jump – instruction to the reset handling routine. If the program never
enables an interrupt source, the Interrupt Vectors are not used, and regular program
code can be placed at these locations. The circuit diagram in Figure 13 shows the reset
logic. Table 12 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source
goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the
internal reset. This allows the power to reach a stable level before normal operation
starts. The time-out period of the delay counter is defined by the user through the SUT
and CKSEL Fuses. The different selections for the delay period are presented in “Clock
Sources” on page 21.
Reset Sources
The ATtiny13 has four sources of reset:
•
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (VPOT).
•
External Reset. The MCU is reset when a low level is present on the RESET pin for
longer than the minimum pulse length.
•
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
•
Brown-out Reset. The MCU is reset when the supply voltage VCC is below the
Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.
29
2535B–AVR–01/04
Figure 13. Reset Logic
DATA BUS
PORF
BORF
EXTRF
WDRF
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
BODLEVEL [1..0]
Pull-up Resistor
SPIKE
FILTER
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
CKSEL[1:0]
SUT[1:0]
Table 12. Reset Characteristics(1)
Symbol
Parameter
Condition
Power-on Reset
Threshold Voltage
(rising)
TA = -40 - 85°C
Power-on Reset
Threshold Voltage
(falling)(2)
TA = -40 - 85°C
VRST
RESET Pin Threshold
Voltage
VCC = 1.8V - 5.5V
tRST
Minimum pulse width on
RESET Pin
VCC = 1.8V - 5.5V
VPOT
Notes:
30
Min
0.1 VCC
Typ
Max
Units
1.2
V
1.1
V
0.9 VCC
V
2.5
µs
1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below VPOT
(falling)
ATtiny13
2535B–AVR–01/04
ATtiny13
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 12. The POR is activated whenever V CC is below the
detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines
how long the device is kept in RESET after VCC rise. The RESET signal is activated
again, without any delay, when VCC decreases below the detection level.
Figure 14. MCU Start-up, RESET Tied to VCC
VCC
RESET
VPOT
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 15. MCU Start-up, RESET Extended Externally
VCC
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
31
2535B–AVR–01/04
External Reset
An External Reset is generated by a low level on the RESET pin if enabled. Reset
pulses longer than the minimum pulse width (see Table 12) will generate a reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a reset. When
the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge,
the delay counter starts the MCU after the Time-out period – tTOUT – has expired.
Figure 16. External Reset During Operation
CC
Brown-out Detection
ATtiny13 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level
during operation by comparing it to a fixed trigger level. The trigger level for the BOD
can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure
spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
Table 13. BODLEVEL Fuse Coding(1)
BODLEVEL [1..0] Fuses
Note:
Min VBOT
Typ VBOT
Max VBOT
11
BOD Disabled
10
1.8
01
2.7
00
4.3
Units
V
1. VBOT may be below nominal minimum operating voltage for some devices. For
devices where this is the case, the device is tested down to VCC = VBOT during the
production test. This guarantees that a Brown-out Reset will occur before VCC drops
to a voltage where correct operation of the microcontroller is no longer guaranteed.
Table 14. Brown-out Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VHYST
Brown-out Detector Hysteresis
50
mV
tBOD
Min Pulse Width on Brown-out Reset
2
µs
When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOTin Figure 17), the Brown-out Reset is immediately activated. When VCC increases above
the trigger level (VBOT+ in Figure 17), the delay counter starts the MCU after the Timeout period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level
for longer than tBOD given in Table 12.
32
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 17. Brown-out Reset During Operation
VCC
VBOT+
VBOT-
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period
tTOUT. Refer to page 40 for details on operation of the Watchdog Timer.
Figure 18. Watchdog Reset During Operation
CC
CK
MCU Status Register –
MCUSR
The MCU Status Register provides information on which reset source caused an MCU
Reset.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
WDRF
BORF
EXTRF
PORF
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
MCUSR
See Bit Description
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
33
2535B–AVR–01/04
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and
then reset the MCUSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the
Reset Flags.
Internal Voltage
Reference
ATtiny13 features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC.
Voltage Reference Enable
Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used.
The start-up time is given in Table 15. To save power, the reference is not always turned
on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [1..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting
the ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the
user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user
can avoid the three conditions above to ensure that the reference is turned off before
entering Power-down mode.
Table 15. Internal Voltage Reference Characteristics(1)
Symbol
Parameter
Min
Typ
Max
Units
VBG
Bandgap reference voltage
1.0
1.1
1.2
V
tBG
Bandgap reference start-up time
40
70
µs
IBG
Bandgap reference current
consumption
15
Note:
34
µA
1. Values are guidelines only. Actual values are TBD.
ATtiny13
2535B–AVR–01/04
ATtiny13
Watchdog Timer
ATmega48/88/168 has an Enhanced Watchdog Timer (WDT). The main features are:
• Clocked from separate On-chip Oscillator
• 3 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
128kHz
OSCILLATOR
WATCHDOG
RESET
WDE
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
Figure 19. Watchdog Timer
WDP0
WDP1
WDP2
WDP3
MCU RESET
WDIF
WDIE
INTERRUPT
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz
oscillator. The WDT gives an interrupt or a system reset when the counter reaches a
given time-out value. In normal operation mode, it is required that the system uses the
WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out
value is reached. If the system doesn't restart the counter, an interrupt or system reset
will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can
be used to wake the device from sleep-modes, and also as a general system timer. One
example is to limit the maximum time allowed for certain operations, giving an interrupt
when the operation has run longer than expected. In System Reset mode, the WDT
gives a reset when the timer expires. This is typically used to prevent system hang-up in
case of runaway code. The third mode, Interrupt and System Reset mode, combines the
other two modes by first giving an interrupt and then switch to System Reset mode. This
mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer
to System Reset mode. With the fuse programmed the System Reset mode bit (WDE)
and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The
sequence for clearing WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit
(WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits
(WDP) as desired, but with the WDCE bit cleared. This must be done in one
operation.
35
2535B–AVR–01/04
The following code example shows one assembly and one C function for turning off the
Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling
interrupts globally) so that no interrupts will occur during the execution of these
functions.
Assembly Code Example(1)
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in
r16, MCUSR
andi
r16, (0xff & (0<<WDRF))
out
MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
in
r16, WDTCR
ori
r16, (1<<WDCE) | (1<<WDE)
out
WDTCR, r16
; Turn off WDT
ldi
r16, (0<<WDE)
out
WDTCR, r16
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out
*/
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
__enable_interrupt();
}
Note:
1. The example code assumes that the part specific header file is included.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or
brown-out condition, the device will be reset and the Watchdog Timer will stay enabled.
If the code is not set up to handle the Watchdog, this might lead to an eternal loop of
time-out resets. To avoid this situation, the application software should always clear the
36
ATtiny13
2535B–AVR–01/04
ATtiny13
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.
The following code example shows one assembly and one C function for changing the
time-out value of the Watchdog Timer.
Assembly Code Example(1)
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
in
r16, WDTCR
ori
r16, (1<<WDCE) | (1<<WDE)
out
WDTCR, r16
; --
Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi
r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
out
WDTCR, r16
; --
Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed sequence */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Note:
1. The example code assumes that the part specific header file is included.
Note: The Watchdog Timer should be reset before any change of the WDP bits, since a
change in the WDP bits can result in a time-out when switching to a shorter time-out
period.
Watchdog Timer Control
Register - WDTCR
Bit
7
6
5
4
3
2
1
0
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
X
0
0
0
WDTCR
37
2535B–AVR–01/04
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is
configured for interrupt. WDIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is
executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog
Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog
Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the
Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first
time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt
vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using
the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each
interrupt. This should however not be done within the interrupt service routine itself, as
this might compromise the safety-function of the Watchdog System Reset mode. If the
interrupt is not executed before the next time-out, a System Reset will be applied.
Table 16. Watchdog Timer Configuration
WDTON
WDE
WDIE
Mode
Action on Time-out
0
0
0
Stopped
None
0
0
1
Interrupt Mode
Interrupt
0
1
0
System Reset Mode
Reset
0
1
1
Interrupt and System
Reset Mode
Interrupt, then go to
System Reset Mode
1
x
x
System Reset Mode
Reset
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the
WDE bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when
WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple
resets during conditions causing failure, and a safe start-up after the failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer
is running. The different prescaling values and their corresponding time-out periods are
shown in Table 17 on page 39.
38
ATtiny13
2535B–AVR–01/04
ATtiny13
.
Table 17. Watchdog Timer Prescale Select
WDP3
WDP2
WDP1
WDP0
Number of WDT Oscillator
Cycles
Typical Time-out at
VCC = 5.0V
0
0
0
0
2K (2048) cycles
16 ms
0
0
0
1
4K (4096) cycles
32 ms
0
0
1
0
8K (8192) cycles
64 ms
0
0
1
1
16K (16384) cycles
0.125 s
0
1
0
0
32K (32768) cycles
0.25 s
0
1
0
1
64K (65536) cycles
0.5 s
0
1
1
0
128K (131072) cycles
1.0 s
0
1
1
1
256K (262144) cycles
2.0 s
1
0
0
0
512K (524288) cycles
4.0 s
1
0
0
1
1024K (1048576) cycles
8.0 s
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Reserved
39
2535B–AVR–01/04
Interrupts
Interrupt Vectors in
ATtiny13
This section describes the specifics of the interrupt handling as performed in ATtiny13.
For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt
Handling” on page 9.
Table 18. Reset and Interrupt Vectors
Vector
No.
Program
Address
Source
Interrupt Definition
1
0x0000
RESET
External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset
2
0x0001
INT0
External Interrupt Request 0
3
0x0002
PCINT0
Pin Change Interrupt Request 0
4
0x0003
TIM0_OVF
Timer/Counter Overflow
5
0x0004
EE_RDY
EEPROM Ready
6
0x0005
ANA_COMP
Analog Comparator
7
0x0006
TIM0_COMPA
Timer/Counter Compare Match A
8
0x0007
TIM0_COMPB
Timer/Counter Compare Match B
9
0x0008
WDT
Watchdog Time-out
10
0x0009
ADC
ADC Conversion Complete
If the program never enables an interrupt source, the Interrupt Vectors are not used, and
regular program code can be placed at these locations. The most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATtiny13 is:
Address Labels Code
Comments
0x0000
rjmp
RESET
; Reset Handler
0x0001
rjmp
EXT_INT0
; IRQ0 Handler
0x0002
rjmp
PCINT0
; PCINT0 Handler
0x0003
rjmp
TIM0_OVF
; Timer0 Overflow Handler
0x0004
rjmp
EE_RDY
; EEPROM Ready Handler
0x0005
rjmp
ANA_COMP
; Analog Comparator Handler
0x0006
rjmp
TIM0_COMPA
; Timer0 CompareA Handler
0x0007
rjmp
TIM0_COMPB
; Timer0 CompareB Handler
0x0008
rjmp
WATCHDOG
; Watchdog Interrupt Handler
0x0009
rjmp
ADC
; ADC Conversion Handler
;
0x000A
0x000B
RAM
RESET: ldi
out
0x000C
0x000D
...
40
r16, low(RAMEND); Main program start
SPL,r16
sei
<instr>
...
; Set Stack Pointer to top of
; Enable interrupts
xxx
...
...
ATtiny13
2535B–AVR–01/04
ATtiny13
I/O Ports
Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The
same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough
to drive LED displays directly. All port pins have individually selectable pull-up resistors
with a supply-voltage invariant resistance. All I/O pins have protection diodes to both
VCC and Ground as indicated in Figure 20. Refer to “Electrical Characteristics” on page
115 for a complete list of parameters.
Figure 20. I/O Pin Equivalent Schematic
Rpu
Logic
Pxn
Cpin
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case
“x” represents the numbering letter for the port, and a lower case “n” represents the bit
number. However, when using the register or bit defines in a program, the precise form
must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally
as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 51.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction
Register are read/write. However, writing a logic one to a bit in the PINx Register, will
result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up
Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when
set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on
page 42. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described
in “Alternate Port Functions” on page 46. Refer to the individual module sections for a
full description of the alternate functions.
41
2535B–AVR–01/04
Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 21 shows a
functional description of one I/O-port pin, here generically called Pxn.
Figure 21. General Digital I/O(1)
PUD
Q
D
DDxn
Q CLR
WDx
RESET
DATA BUS
RDx
1
Q
Pxn
D
0
PORTxn
Q CLR
RESET
WRx
SLEEP
WPx
RRx
SYNCHRONIZER
D
Q
L
Q
D
RPx
Q
PINxn
Q
clk I/O
PUD:
SLEEP:
clkI/O:
Note:
Configuring the Pin
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clkI/O, SLEEP, and PUD are common to all ports.
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O-Ports” on page 51, the DDxn bits are accessed at the
DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at
the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when
reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
42
ATtiny13
2535B–AVR–01/04
ATtiny13
Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
Switching Between Input and
Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b10) as an intermediate step.
Table 19 summarizes the control signals for the pin value.
Table 19. Port Pin Configurations
Reading the Pin Value
DDxn
PORTxn
PUD
(in MCUCR)
I/O
Pull-up
0
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled
low.
0
1
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output Low (Sink)
1
1
X
Output
No
Output High (Source)
Comment
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 21, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
22 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min
respectively.
Figure 22. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
INSTRUCTIONS
XXX
XXX
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd, max
t pd, min
43
2535B–AVR–01/04
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a
single signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 23. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay tpd through the synchronizer is one system
clock period.
Figure 23. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
0xFF
out PORTx, r16
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd
44
ATtiny13
2535B–AVR–01/04
ATtiny13
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and
define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is
included to be able to read back the value recently assigned to some of the pins.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi
r16,(1<<PB4)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out
PORTB,r16
out
DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in
r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
...
Note:
Digital Input Enable and Sleep
Modes
1. For the assembly program, two temporary registers are used to minimize the time
from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
As shown in Figure 21, the digital input signal can be clamped to ground at the input of
the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Power-save mode, and Standby mode to avoid high
power consumption if some input signals are left floating, or have an analog signal level
close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also
overridden by various other alternate functions as described in “Alternate Port Functions” on page 46.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the
external interrupt is not enabled, the corresponding External Interrupt Flag will be set
45
2535B–AVR–01/04
when resuming from the above mentioned Sleep mode, as the clamping in these sleep
mode produces the requested logic change.
Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined
level. Even though most of the digital inputs are disabled in the deep sleep modes as
described above, floating inputs should be avoided to reduce current consumption in all
other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal
pull-up. In this case, the pull-up will be disabled during reset. If low power consumption
during reset is important, it is recommended to use an external pull-up or pull-down.
Connecting unused pins directly to VCC or GND is not recommended, since this may
cause excessive currents if the pin is accidentally configured as an output.
Alternate Port Functions
46
Most port pins have alternate functions in addition to being general digital I/Os. Figure
24 shows how the port pin control signals from the simplified Figure 21 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but
the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 24. Alternate Port Functions(1)
PUOExn
PUOVxn
1
PUD
0
DDOExn
DDOVxn
1
Q
D
DDxn
0
Q CLR
WDx
PVOExn
RESET
RDx
1
DATA BUS
PVOVxn
1
Pxn
Q
0
D
0
PORTxn
PTOExn
Q CLR
DIEOExn
WPx
RESET
DIEOVxn
WRx
1
0
RRx
SLEEP
SYNCHRONIZER
D
SET
Q
RPx
Q
D
PINxn
L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
PTOExn:
Note:
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
clkI/O:
DIxn:
AIOxn:
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each
pin.
47
2535B–AVR–01/04
Table 20 summarizes the function of the overriding signals. The pin and port indexes
from Figure 24 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
Table 20. Generic Description of Overriding Signals for Alternate Functions
Signal Name
Full Name
Description
PUOE
Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is
enabled when {DDxn, PORTxn, PUD} = 0b010.
PUOV
Pull-up Override
Value
If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of the
DDxn, PORTxn, and PUD Register bits.
DDOE
Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled
by the DDOV signal. If this signal is cleared, the Output
driver is enabled by the DDxn Register bit.
DDOV
Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/disabled
when DDOV is set/cleared, regardless of the setting of
the DDxn Register bit.
PVOE
Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the
port value is controlled by the PVOV signal. If PVOE is
cleared, and the Output Driver is enabled, the port Value
is controlled by the PORTxn Register bit.
PVOV
Port Value
Override Value
If PVOE is set, the port value is set to PVOV, regardless
of the setting of the PORTxn Register bit.
PTOE
Port Toggle
Override Enable
If PTOE is set, the PORTxn Register bit is inverted.
DIEOE
Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by
the DIEOV signal. If this signal is cleared, the Digital Input
Enable is determined by MCU state (Normal mode, sleep
mode).
DIEOV
Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state
(Normal mode, sleep mode).
DI
Digital Input
This is the Digital Input to alternate functions. In the
figure, the signal is connected to the output of the
schmitt-trigger but before the synchronizer. Unless the
Digital Input is used as a clock source, the module with
the alternate function will use its own synchronizer.
AIO
Analog
Input/Output
This is the Analog Input/Output to/from alternate
functions. The signal is connected directly to the pad, and
can be used bi-directionally.
The following subsections shortly describe the alternate functions for each port, and
relate the overriding signals to the alternate function. Refer to the alternate function
description for further details.
48
ATtiny13
2535B–AVR–01/04
ATtiny13
MCU Control Register –
MCUCR
Bit
7
6
5
4
3
2
1
0
–
PUD
SE
SM1
SM0
–
ISC01
ISC00
Read/Write
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bits 7, 2– Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn
and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
See “Configuring the Pin” on page 42 for more details about this feature.
Alternate Functions of Port B
The Port B pins with alternate function are shown in Table 21.
Table 21. Port B Pins Alternate Functions
Port Pin
Notes:
Alternate Function
PB5
RESET/dW/ADC0/PCINT5(1)
PB4
ADC2/PCINT4(2)
PB3
ADC3/CLKI/PCINT3(3)
PB2
SCK/ADC1/T0/PCINT2(4)
PB1
MISO/AIN1/OC0B/INT0/PCINT1/RXD(5)
PB0
MOSI/AIN0/OC0A/PCINT0/TXD(6)
1.
2.
3.
4.
Reset pin, debugWire I/O, ADC Input channel, or Pin Change Interrupt.
ADC Input channel or Pin Change Interrupt.
ADC Input channel, Clock Input, or Pin Change Interrupt.
Serial Clock Input, Timer/Counter Clock Input, ADC Input Channel 0, or Pin Change
Interrupt.
5. Serial Data Input, Analog Comparator Negative Input, Output Compare and PWM
Output B for Timer/Counter, External Interrupt 0 or Pin Change Interrupt.
6. Serial Data Output, Analog Comparator Positive Input, Output Compare and PWM
Output A for Timer/Counter, or Pin Change Interrupt.
Table 22 and Table 23 on page 50 relate the alternate functions of Port B to the overriding signals shown in Figure 24 on page 47.
49
2535B–AVR–01/04
Table 22. Overriding Signals for Alternate Functions in PB5..PB3
Signal
Name
PB5/RESET/
ADC0/PCINT5
(1)
(1)
• DWEN
PB4/ADC2/PCINT4
PB3/ADC3/CLKI/PCINT3
0
0
PUOE
RSTDISBL
PUOV
1
0
0
DDOE
RSTDISBL(1) • DWEN(1)
0
0
DDOV
debugWire Transmit
0
0
PVOE
0
0
0
PVOV
0
0
0
PTOE
0
0
0
DIEOE
RSTDISBL(1) + (PCINT5 •
PCIE + ADC0D)
PCINT4 • PCIE + ADC2D
PCINT3 • PCIE + ADC3D
DIEOV
ADC0D
ADC2D
ADC3D
DI
PCINT5 Input
PCINT4 Input
PCINT3 Input
AIO
RESET Input, ADC0 Input
ADC2 Input
ADC3 Input
Note:
1. 1 when the Fuse is “0” (Programmed).
Table 23. Overriding Signals for Alternate Functions in PB2..PB0
50
Signal
Name
PB2/SCK/ADC1/
T0/PCINT2
PB1/MISO/AIN1/
OC0B/INT0/PCINT1
PB0/MOSI/AIN0/AREF/
OC0A/PCINT0
PUOE
0
0
0
PUOV
0
0
0
DDOE
0
0
0
DDOV
0
0
0
PVOE
0
OC0B Enable
OC0A Enable
PVOV
0
OC0B
OC0A
PTOE
0
0
0
DIEOE
PCINT2 • PCIE + ADC1D
PCINT1 • PCIE + AIN1D
PCINT0 • PCIE + AIN0D
DIEOV
ADC1D
AIN1D
AIN0D
DI
T0/INT0/
PCINT2 Input
PCINT1 Input
PCINT0 Input
AIO
ADC1 Input
Analog Comparator
Negative Input
Analog Comparator
Positive Input
ATtiny13
2535B–AVR–01/04
ATtiny13
Register Description for
I/O-Ports
Port B Data Register – PORTB
Bit
Port B Data Direction Register
– DDRB
Port B Input Pins Address –
PINB
7
6
5
4
3
2
1
0
–
–
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
–
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
–
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
N/A
N/A
N/A
N/A
N/A
N/A
PORTB
DDRB
PINB
51
2535B–AVR–01/04
External Interrupts
The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are
configured as outputs. This feature provides a way of generating a software interrupt.
Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSK
Register control which pins contribute to the pin change interrupts. Pin change interrupts
on PCINT5..0 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set
up as indicated in the specification for the MCU Control Register – MCUCR. When the
INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as
long as the pin is held low. Note that recognition of falling or rising edge interrupts on
INT0 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 20. Low level interrupt on INT0 is detected asynchronously. This implies
that this interrupt can be used for waking the part also from sleep modes other than Idle
mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the
required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 20.
MCU Control Register –
MCUCR
The External Interrupt Control Register A contains control bits for interrupt sense
control.
Bit
7
6
5
4
3
2
1
0
–
PUD
SE
SM1
SM0
–
ISC01
ISC00
Read/Write
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 24. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Table 24. Interrupt 0 Sense Control
52
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
ATtiny13
2535B–AVR–01/04
ATtiny13
General Interrupt Mask
Register – GIMSK
Bit
7
6
5
4
3
2
1
–
INT0
PCIE
–
–
–
–
0
–
Read/Write
R
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
GIMSK
• Bits 7, 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the External Interrupt Control Register A (EICRA) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK0
Register.
General Interrupt Flag
Register – GIFR
Bit
7
6
5
4
3
2
1
–
INTF0
PCIF
–
–
–
–
0
–
Read/Write
R
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
GIFR
• Bits 7, 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it. This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes
set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it.
53
2535B–AVR–01/04
Pin Change Mask Register –
PCMSK
Bit
7
6
5
4
3
2
1
0
–
–
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
1
1
1
1
1
1
PCMSK
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0
Each PCINT5..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
54
ATtiny13
2535B–AVR–01/04
ATtiny13
8-bit Timer/Counter0
with PWM
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent
Output Compare Units, and with PWM support. It allows accurate program execution
timing (event management) and wave generation. The main features are:
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• Clear Timer on Compare Match (Auto Reload)
• Glitch Free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 25. For the
actual placement of I/O pins, refer to “Pinout ATtiny13” on page 1. CPU accessible I/O
Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on
page 66.
Figure 25. 8-bit Timer/Counter Block Diagram
Count
Clear
Direction
TOVn
(Int.Req.)
Control Logic
clkTn
Clock Select
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
=0
OCnA
(Int.Req.)
Waveform
Generation
=
OCnA
DATA BUS
OCRnA
Fixed
TOP
Value
Waveform
Generation
=
OCnB
OCRnB
TCCRnA
Registers
OCnB
(Int.Req.)
TCCRnB
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are
8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked
with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in
the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the T0 pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with
the Timer/Counter value at all times. The result of the compare can be used by the
Waveform Generator to generate a PWM or variable frequency output on the Output
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Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 57. for details.
The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which
can be used to generate an Output Compare interrupt request.
Definitions
Many register and bit references in this section are written in general form. A lower case
“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the
Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when
using the register or bit defines in a program, the precise form must be used, i.e.,
TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 25 are also used extensively throughout the document.
Table 25. Definitions
BOTTOM
The counter reaches the BOTTOM when it becomes 0x00.
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The
assignment is dependent on the mode of operation.
Timer/Counter Clock
Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select
(CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on
clock sources and prescaler, see “Timer/Counter Prescaler” on page 72.
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 26 shows a block diagram of the counter and its surroundings.
Figure 26. Counter Unit Block Diagram
TOVn
(Int.Req.)
DATA BUS
Clock Select
count
TCNTn
clear
Control Logic
clkTn
Edge
Detector
Tn
direction
( From Prescaler )
bottom
top
Signal description (internal signals):
56
count
Increment or decrement TCNT0 by 1.
direction
Select between increment and decrement.
clear
Clear TCNT0 (set all bits to zero).
clkTn
Timer/Counter clock, referred to as clkT0 in the following.
top
Signalize that TCNT0 has reached maximum value.
bottom
Signalize that TCNT0 has reached minimum value (zero).
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ATtiny13
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal
clock source, selected by the Clock Select bits (CS02:0). When no clock source is
selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed
by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has
priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in
the Timer/Counter Control Register B (TCCR0B). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output
Compare output OC0A. For more details about advanced counting sequences and
waveform generation, see “Modes of Operation” on page 60.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation
selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the
comparator signals a match. A match will set the Output Compare Flag (OCF0A or
OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is
automatically cleared when the interrupt is executed. Alternatively, the flag can be
cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the
WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme
values in some modes of operation (See “Modes of Operation” on page 60.).
Figure 27 shows a block diagram of the Output Compare unit.
Figure 27. Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator
OCnx
FOCn
WGMn1:0
COMnX1:0
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The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of
operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR0x Compare Registers to either top or bottom of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical
PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double
buffering is disabled the CPU will access the OCR0x directly.
Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare
Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be
updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define
whether the OC0x pin is set, cleared or toggled).
Compare Match Blocking by
TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that
occur in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when
the Timer/Counter clock is enabled.
Using the Output Compare
Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one
timer clock cycle, there are risks involved when changing TCNT0 when using the Output
Compare Unit, independently of whether the Timer/Counter is running or not. If the
value written to TCNT0 equals the OCR0x value, the Compare Match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value
equal to BOTTOM when the counter is down-counting.
The setup of the OC0x should be performed before setting the Data Direction Register
for the port pin to output. The easiest way of setting the OC0x value is to use the Force
Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their
values even when changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare
value. Changing the COM0x1:0 bits will take effect immediately.
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Compare Match Output
Unit
The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next
Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 28
shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O
Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0
bits are shown. When referring to the OC0x state, the reference is for the internal OC0x
Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.
Figure 28. Compare Match Output Unit, Schematic
COMnx1
COMnx0
FOCn
Waveform
Generator
D
Q
1
OCnx
DATA BUS
D
0
OCn
Pin
Q
PORT
D
Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0x) from the
Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as
output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before
the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 66.
Compare Output Mode and
Waveform Generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no
action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 26 on page 66. For fast PWM
mode, refer to Table 27 on page 66, and for phase correct PWM refer to Table 28 on
page 67.
A change of the COM0x1:0 bits state will have effect at the first Compare Match after
the bits are written. For non-PWM modes, the action can be forced to have immediate
effect by using the FOC0x strobe bits.
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Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and
Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See “Compare Match
Output Unit” on page 59.).
For detailed timing information refer to Figure 32, Figure 33, Figure 34 and Figure 35 in
“Timer/Counter Timing Diagrams” on page 64.
Normal Mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then
restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag
(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The
TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV0
Flag, the timer resolution can be increased by software. There are no special cases to
consider in the Normal mode, a new counter value can be written anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using
the Output Compare to generate waveforms in Normal mode is not recommended,
since this will occupy too much of the CPU time.
Clear Timer on Compare
Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used
to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for
the counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 29. The counter value
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and
then counter (TCNT0) is cleared.
Figure 29. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
OCn
(Toggle)
Period
(COMnx1:0 = 1)
1
2
3
4
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be
used for updating the TOP value. However, changing TOP to a value close to BOTTOM
when the counter is running with none or a low prescaler value must be done with care
since the CTC mode does not have the double buffering feature. If the new value written
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to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare
Match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle
its logical level on each Compare Match by setting the Compare Output mode bits to
toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless
the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f OC0 = fclk_I/O /2 when OCR0A is set to zero (0x00). The waveform
frequency is defined by the following equation:
f clk_I/O
f OCnx = ------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnx )
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high
frequency PWM waveform generation option. The fast PWM differs from the other PWM
option by its single-slope operation. The counter counts from BOTTOM to TOP then
restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when
WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is
cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In
inverting Compare Output mode, the output is set on Compare Match and cleared at
BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM
mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation,
rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP
value. The counter is then cleared at the following timer clock cycle. The timing diagram
for the fast PWM mode is shown in Figure 30. The TCNT0 value is in the timing diagram
shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0
slopes represent Compare Matches between OCR0x and TCNT0.
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Figure 30. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
TCNTn
OCn
(COMnx1:0 = 2)
OCn
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If
the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the
COM0A1:0 bits to one allows the AC0A pin to toggle on Compare Matches if the
WGM02 bit is set. This option is not available for the OC0B pin (See Table 27 on page
66). The actual OC0x value will only be visible on the port pin if the data direction for the
port pin is set as output. The PWM waveform is generated by setting (or clearing) the
OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or
setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from
TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ----------------N ⋅ 256
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating
a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM,
the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A
equal to MAX will result in a constantly high or low output (depending on the polarity of
the output set by the COM0A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The
waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is
set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double
buffer feature of the Output Compare unit is enabled in the fast PWM mode.
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Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase
correct PWM waveform generation option. The phase correct PWM mode is based on a
dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then
from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when
WGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is
cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set
on the Compare Match while down-counting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches
TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value
will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 31. The TCNT0 value is in the timing diagram shown as
a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.
Figure 31. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCn
(COMnx1:0 = 2)
OCn
(COMnx1:0 = 3)
Period
1
2
3
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter
reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the
COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02
bit is set. This option is not available for the OC0B pin (See Table 28 on page 67). The
actual OC0x value will only be visible on the port pin if the data direction for the port pin
is set as output. The PWM waveform is generated by clearing (or setting) the OC0x
Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x
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and TCNT0 when the counter decrements. The PWM frequency for the output when
using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnx PCPWM = ----------------N ⋅ 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
At the very start of period 2 in Figure 31 OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
Timer/Counter Timing
Diagrams
•
OCR0A changes its value from MAX, like in Figure 31. When the OCR0A value is
MAX the OCn pin value is the same as the result of a down-counting Compare
Match. To ensure symmetry around BOTTOM the OCn value at MAX must
correspond to the result of an up-counting Compare Match.
•
The timer starts counting from a value higher than the one in OCR0A, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
The Timer/Counter is a synchronous design and the timer clock (clk T0 ) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set. Figure 32 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 32. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 33 shows the same timing data, but with the prescaler enabled.
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Figure 33. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 34 shows the setting of OCF0B in all modes and OCF0A in all modes except
CTC mode and PWM mode, where OCR0A is TOP.
Figure 34. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 35 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 35. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with
Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
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8-bit Timer/Counter
Register Description
Timer/Counter Control
Register A – TCCR0A
Bit
7
6
5
4
3
2
1
0
COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0A
• Bits 7:6 – COM01A:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the
COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 26 shows the COM0A1:0 bit functionality when the
WGM02:0 bits are set to a normal or CTC mode (non-PWM).
Table 26. Compare Output Mode, non-PWM Mode
COM01
COM00
Description
0
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match
1
1
Set OC0A on Compare Match
Table 27 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast
PWM mode.
Table 27. Compare Output Mode, Fast PWM Mode(1)
COM01
COM00
0
0
Normal port operation, OC0A disconnected.
0
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match, set OC0A at TOP
1
1
Set OC0A on Compare Match, clear OC0A at TOP
Note:
66
Description
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 61 for more details.
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Table 28 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to
phase correct PWM mode.
Table 28. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
0
0
Normal port operation, OC0A disconnected.
0
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
1
1
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Note:
Description
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 63 for more details.
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the
COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 26 shows the COM0A1:0 bit functionality when the
WGM02:0 bits are set to a normal or CTC mode (non-PWM).
Table 29. Compare Output Mode, non-PWM Mode
COM01
COM00
Description
0
0
Normal port operation, OC0B disconnected.
0
1
Toggle OC0B on Compare Match
1
0
Clear OC0B on Compare Match
1
1
Set OC0B on Compare Match
Table 27 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast
PWM mode.
Table 30. Compare Output Mode, Fast PWM Mode(1)
COM01
COM00
0
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on Compare Match, set OC0B at TOP
1
1
Set OC0B on Compare Match, clear OC0B at TOP
Note:
Description
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 61 for more details.
67
2535B–AVR–01/04
Table 28 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to
phase correct PWM mode.
Table 31. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
0
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1
1
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Note:
Description
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 63 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used, see Table 32. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare
Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see
“Modes of Operation” on page 60).
Table 32. Waveform Generation Mode Bit Description
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
Mode
WGM2
WGM1
WGM0
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
TOP
MAX
4
1
0
0
Reserved
–
–
–
5
1
0
1
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
1
1
0
Reserved
–
–
–
7
1
1
1
Fast PWM
OCRA
TOP
TOP
Notes:
68
Timer/Counter
Mode of
Operation
1. MAX
= 0xFF
2. BOTTOM = 0x00
ATtiny13
2535B–AVR–01/04
ATtiny13
Timer/Counter Control
Register B – TCCR0B
Bit
7
6
5
4
3
2
1
0
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
Read/Write
W
W
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the
FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit.
The OC0A output is changed according to its COM0A1:0 bits setting. Note that the
FOC0A bit is implemented as a strobe. Therefore it is the value present in the
COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the
FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit.
The OC0B output is changed according to its COM0B1:0 bits setting. Note that the
FOC0B bit is implemented as a strobe. Therefore it is the value present in the
COM0B1:0 bits that determines the effect of the forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “Timer/Counter Control Register A – TCCR0A” on page 66.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 33. Clock Select Bit Description
CS02
CS01
CS00
Description
0
0
0
No clock source (Timer/Counter stopped)
0
0
1
clkI/O/(No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
1
clkI/O/64 (From prescaler)
1
0
0
clkI/O/256 (From prescaler)
69
2535B–AVR–01/04
Table 33. Clock Select Bit Description (Continued)
CS02
CS01
CS00
Description
1
0
1
clkI/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
Timer/Counter Register –
TCNT0
Bit
7
6
5
4
3
2
1
0
TCNT0[7:0]
TCNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)
the Compare Match on the following timer clock. Modifying the counter (TCNT0) while
the counter is running, introduces a risk of missing a Compare Match between TCNT0
and the OCR0x Registers.
Output Compare Register A –
OCR0A
Bit
7
6
5
4
3
2
1
0
OCR0A[7:0]
OCR0A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0A pin.
Output Compare Register B –
OCR0B
Bit
7
6
5
4
3
2
1
0
OCR0B[7:0]
OCR0B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register B contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0B pin.
Timer/Counter Interrupt Mask
Register – TIMSK0
Bit
7
6
5
4
3
2
1
0
–
–
–
–
OCIE0B
OCIE0A
TOIE0
–
Read/Write
R
R
R
R
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0
0
TIMSK0
• Bits 7..4, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is
70
ATtiny13
2535B–AVR–01/04
ATtiny13
executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in
the Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is
executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set
in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
Timer/Counter 0 Interrupt Flag
Register – TIFR0
Bit
7
6
5
4
3
2
1
0
–
–
–
–
OCF0B
OCF0A
TOV0
–
Read/Write
R
R
R
R
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0
0
TIFR0
• Bits 7..4, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 3 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and
the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF0B is
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B
(Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the
Timer/Counter Compare Match Interrupt is executed.
• Bit 2 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and
the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared
by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0
Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare
Match Interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0
Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 32,
“Waveform Generation Mode Bit Description” on page 68.
71
2535B–AVR–01/04
Timer/Counter
Prescaler
The Timer/Counter can be clocked directly by the system clock (by setting the
CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock
frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from
the prescaler can be used as a clock source. The prescaled clock has a frequency of
either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of
the Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock
select, the state of the prescaler will have implications for situations where a prescaled
clock is used. One example of prescaling artifacts occurs when the timer is enabled and
clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from
when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
External Clock Source
An external clock source applied to the T0 pin can be used as Timer/Counter clock
(clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization
logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 36 shows a functional equivalent block diagram of the T0 synchronization and edge
detector logic. The registers are clocked at the positive edge of the internal system clock
(clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 36. T0 Pin Sampling
Tn
D
Q
D
Q
D
Tn_sync
(To Clock
Select Logic)
Q
LE
clk I/O
Synchronization
Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at
least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse
is generated.
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
72
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 37. Prescaler for Timer/Counter0
clk I/O
Clear
PSR10
T0
Synchronization
clkT0
Note:
General Timer/Counter
Control Register – GTCCR
1. The synchronization logic on the input pins (T0) is shown in Figure 36.
Bit
7
6
5
4
3
2
1
0
TSM
–
–
–
–
–
–
PSR10
Read/Write
R/W
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSR10 bit is kept, hence keeping the Prescaler
Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to
zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally
cleared immediately by hardware, except if the TSM bit is set.
73
2535B–AVR–01/04
Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on
the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can
trigger a separate interrupt, exclusive to the Analog Comparator. The user can select
Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 38.
Figure 38. Analog Comparator Block Diagram(2)
BANDGAP
REFERENCE
ACBG
ACME
ADEN
ADC MULTIPLEXER
OUTPUT (1)
Notes:
ADC Control and Status
Register B – ADCSRB
1. See Table 35 on page 76.
2. Refer to Figure 1 on page 1 and Table 23 on page 50 for Analog Comparator pin
placement.
Bit
7
6
5
4
3
2
1
0
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is
zero), the ADC multiplexer selects the negative input to the Analog Comparator. When
this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on
page 76.
Analog Comparator Control
and Status Register – ACSR
Bit
7
6
5
4
3
2
1
0
ACD
ACBG
ACO
ACI
ACIE
–
ACIS1
ACIS0
Read/Write
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Initial Value
0
0
N/A
0
0
0
0
0
ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off.
This bit can be set at any time to turn off the Analog Comparator. This will reduce power
consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt
can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
74
ATtiny13
2535B–AVR–01/04
ATtiny13
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the
Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the
Analog Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to
ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode
defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if
the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny13 and will always read as zero.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 34.
Table 34. ACIS1/ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
0
0
Comparator Interrupt on Output Toggle.
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge.
1
1
Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt
can occur when the bits are changed.
75
2535B–AVR–01/04
Analog Comparator
Multiplexed Input
It is possible to select any of the ADC3..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the
ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer
Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is
zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 35. If ACME is cleared or ADEN is set, AIN1 is
applied to the negative input to the Analog Comparator.
Table 35. Analog Comparator Multiplexed Input
Digital Input Disable Register
0 – DIDR0
ACME
ADEN
MUX1..0
0
x
xx
AIN1
1
1
xx
AIN1
1
0
00
ADC0
1
0
01
ADC1
1
0
10
ADC2
1
0
11
ADC3
Bit
Analog Comparator Negative Input
7
6
5
4
3
2
1
0
–
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR0
• Bits 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled.
The corresponding PIN Register bit will always read as zero when this bit is set. When
an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not
needed, this bit should be written logic one to reduce power consumption in the digital
input buffer.
76
ATtiny13
2535B–AVR–01/04
ATtiny13
Analog to Digital
Converter
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
10-bit Resolution
0.5 LSB Integral Non-linearity
± 2 LSB Absolute Accuracy
13 - 260 µs Conversion Time
Up to 15 kSPS at Maximum Resolution
Four Multiplexed Single Ended Input Channels
Optional Left Adjustment for ADC Result Readout
0 - VCC ADC Input Voltage Range
Selectable 1.1V ADC Reference Voltage
Free Running or Single Conversion Mode
ADC Start Conversion by Auto Triggering on Interrupt Sources
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
The ATtiny13 features a 10-bit successive approximation ADC. The ADC is connected
to a 4-channel Analog Multiplexer which allows four single-ended voltage inputs constructed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the
ADC is held at a constant level during conversion. A block diagram of the ADC is shown
in Figure 39.
Internal reference voltages of nominally 1.1V or VCC are provided On-chip.
77
2535B–AVR–01/04
Figure 39. Analog to Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
INTERRUPT
FLAGS
ADTS[2:0]
15
TRIGGER
SELECT
ADC[9:0]
ADPS0
ADPS1
ADIF
ADPS2
ADATE
ADEN
0
ADC DATA REGISTER
(ADCH/ADCL)
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADSC
MUX1
MUX0
ADLAR
REFS1
ADC MULTIPLEXER
SELECT (ADMUX)
ADIE
ADIF
8-BIT DATA BUS
MUX DECODER
CHANNEL SELECTION
PRESCALER
VCC
START
CONVERSION LOGIC
INTERNAL 1.1V
REFERENCE
SAMPLE & HOLD
COMPARATOR
10-BIT DAC
+
ADC3
ADC2
ADC1
INPUT
MUX
ADC MULTIPLEXER
OUTPUT
ADC0
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents GND and the maximum value represents
the voltage on VCC or an internal 1.1V reference voltage.
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the
ADC input pins, can be selected as single ended inputs to the ADC.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the
ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally
be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content
of the data registers belongs to the same conversion. Once ADCL is read, ADC access
to data registers is blocked. This means that if ADCL has been read, and a conversion
completes before ADCH is read, neither register is updated and the result from the con-
78
ATtiny13
2535B–AVR–01/04
ATtiny13
version is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is
re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes.
When ADC access to the data registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit,
ADSC. This bit stays high as long as the conversion is in progress and will be cleared by
hardware when the conversion is completed. If a different data channel is selected while
a conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The
trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see
description of the ADTS bits for a list of the trigger sources). When a positive edge
occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is
started. This provides a method of starting conversions at fixed intervals. If the trigger
signal still is set when the conversion completes, a new conversion will not be started. If
another positive edge occurs on the trigger signal during conversion, the edge will be
ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or
the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered
without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event.
Figure 40. ADC Auto Trigger Logic
ADTS[2:0]
PRESCALER
START
ADIF
CLKADC
ADATE
SOURCE 1
.
.
.
.
SOURCE n
CONVERSION
LOGIC
EDGE
DETECTOR
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion
as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first
conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this
mode the ADC will perform successive conversions independently of whether the ADC
Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in
ADCSRA to one. ADSC can also be used to determine if a conversion is in progress.
The ADSC bit will be read as one during a conversion, independently of how the conversion was started.
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Prescaling and
Conversion Timing
Figure 41. ADC Prescaler
ADEN
START
Reset
7-BIT ADC PRESCALER
CK/128
CK/64
CK/32
CK/16
CK/8
CK/4
CK/2
CK
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
By default, the successive approximation circuitry requires an input clock frequency
between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10
bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a
higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits
in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by
setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN
bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize
the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal
conversion and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In
Single Conversion mode, ADSC is cleared simultaneously. The software may then set
ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the
sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see
Table 36.
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Figure 42. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
Conversion
First Conversion
Cycle Number
1
2
12
13
14
16
15
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock
ADEN
ADSC
ADIF
Sign and MSB of Result
ADCH
LSB of Result
ADCL
MUX and REFS
Update
Conversion
Complete
Sample & Hold
MUX and REFS
Update
Figure 43. ADC Timing Diagram, Single Conversion
One Conversion
Cycle Number
1
2
3
4
5
6
7
8
9
Next Conversion
10
11
12
13
1
2
3
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Sample & Hold
Conversion
Complete
MUX and REFS
Update
MUX and REFS
Update
Figure 44. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Cycle Number
1
2
3
4
5
6
7
8
9
Next Conversion
10
11
12
13
1
2
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Prescaler
Reset
Sample &
Hold
Conversion
Complete
Prescaler
Reset
MUX and REFS
Update
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Figure 45. ADC Timing Diagram, Free Running Conversion
One Conversion
Cycle Number
11
12
Next Conversion
13
1
2
3
4
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Sample & Hold
Conversion
Complete
MUX and REFS
Update
Table 36. ADC Conversion Time
Sample & Hold (Cycles
from Start of Conversion)
Conversion Time
(Cycles)
First conversion
14.5
25
Normal conversions
1.5
13
2
13.5
Condition
Auto Triggered conversions
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Changing Channel or
Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the
conversion starts on the following rising ADC clock edge after ADSC is written. The user
is thus advised not to write new channel or reference selection values to ADMUX until
one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic.
Special care must be taken when updating the ADMUX Register, in order to control
which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If
the ADMUX Register is changed in this period, the user cannot tell if the next conversion
is based on the old or the new settings. ADMUX can be safely updated in the following
ways:
1. When ADATE or ADEN is cleared.
2. During conversion, minimum one ADC clock cycle after the trigger event.
3. After a conversion, before the Interrupt Flag used as trigger source is
cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next
ADC conversion.
ADC Input Channels
When changing channel selections, the user should observe the following guidelines to
ensure that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion.
The channel selection may be changed one ADC clock cycle after writing one to ADSC.
However, the simplest method is to wait for the conversion to complete before changing
the channel selection.
In Free Running mode, always select the channel before starting the first conversion.
The channel selection may be changed one ADC clock cycle after writing one to ADSC.
However, the simplest method is to wait for the first conversion to complete, and then
change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions
will reflect the new channel selection.
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ADC Voltage Reference
The reference voltage for the ADC (VREF ) indicates the conversion range for the ADC.
Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be
selected as either VCC, or internal 1.1V reference, or external AREF pin. The first ADC
conversion result after switching reference voltage source may be inaccurate, and the
user is advised to discard this result.
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to
reduce noise induced from the CPU core and other I/O peripherals. The noise canceler
can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the
following procedure should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt
must be enabled.
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.
3. If no other interrupts occur before the ADC conversion completes, the ADC
interrupt will wake up the CPU and execute the ADC Conversion Complete
interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion
Complete interrupt request will be generated when the ADC conversion
completes. The CPU will remain in active mode until a new sleep command
is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes
than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to
ADEN before entering such sleep modes to avoid excessive power consumption.
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Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 46. An analog
source applied to ADCn is subjected to the pin capacitance and input leakage of that
pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance
(combined resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately
10 kΩ or less. If such a source is used, the sampling time will be negligible. If a source
with higher impedance is used, the sampling time will depend on how long time the
source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this
minimizes the required charge transfer to the S/H capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present to
avoid distortion from unpredictable signal convolution. The user is advised to remove
high frequency components with a low-pass filter before applying the signals as inputs
to the ADC.
Figure 46. Analog Input Circuitry
IIH
ADCn
1..100 kΩ
CS/H= 14 pF
IIL
VCC/2
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Analog Noise Canceling
Techniques
Digital circuitry inside and outside the device generates EMI which might affect the
accuracy of analog measurements. If conversion accuracy is critical, the noise level can
be reduced by applying the following techniques:
1. Keep analog signal paths as short as possible. Make sure analog tracks run
over the analog ground plane, and keep them well away from high-speed
switching digital tracks.
2. Use the ADC noise canceler function to reduce induced noise from the CPU.
3. If any port pins are used as digital outputs, it is essential that these do not
switch while a conversion is in progress.
ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n
steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
•
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal
transition (at 0.5 LSB). Ideal value: 0 LSB.
Figure 47. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
•
86
VREF Input Voltage
Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the
last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below
maximum). Ideal value: 0 LSB
ATtiny13
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ATtiny13
Figure 48. Gain Error
Gain
Error
Output Code
Ideal ADC
Actual ADC
VREF Input Voltage
•
Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the
maximum deviation of an actual transition compared to an ideal transition for any
code. Ideal value: 0 LSB.
Figure 49. Integral Non-linearity (INL)
Output Code
INL
Ideal ADC
Actual ADC
VREF
•
Input Voltage
Differential Non-linearity (DNL): The maximum deviation of the actual code width
(the interval between two adjacent transitions) from the ideal code width (1 LSB).
Ideal value: 0 LSB.
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Figure 50. Differential Non-linearity (DNL)
Output Code
0x3FF
1 LSB
DNL
0x000
0
ADC Conversion Result
VREF Input Voltage
•
Quantization Error: Due to the quantization of the input voltage into a finite number
of codes, a range of input voltages (1 LSB wide) will code to the same value. Always
± 0.5 LSB.
•
Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition
compared to an ideal transition for any code. This is the compound effect of offset,
gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5
LSB.
After the conversion is complete (ADIF is high), the conversion result can be found in
the ADC Result Registers (ADCL, ADCH).
For single ended conversion, the result is
V IN ⋅ 1024
ADC = -------------------------V REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 37 on page 89 and Table 38 on page 89). 0x000 represents analog
ground, and 0x3FF represents the selected reference voltage minus one LSB.
ADC Multiplexer Selection
Register – ADMUX
Bit
7
6
5
4
3
2
1
0
–
REFS0
ADLAR
–
–
–
MUX1
MUX0
Read/Write
R
R/W
R/W
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADMUX
• Bit 7 – Res: Reserved Bit
This bit is reserved bit in the ATtiny13 and will always read as zero.
• Bit 6 – REFS0: Reference Selection Bit
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ATtiny13
This bit selects the voltage reference for the ADC, as shown in Table 37. If this bit is
changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 37. Voltage Reference Selections for ADC
REFS0
Voltage Reference Selection
0
VCC used as analog reference.
1
Internal Voltage Reference.
Bit 5 – ADLAR: ADC Left Adjust Result
•
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data
Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right
adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see “The
ADC Data Register – ADCL and ADCH” on page 90.
• Bits 4:2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 1:0 – MUX1:0: Analog Channel Selection Bits
The value of these bits selects which combination of analog inputs are connected to the
ADC. See Table 38 for details. If these bits are changed during a conversion, the
change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
Table 38. Input Channel Selections
MUX1..0
ADC Control and Status
Register A – ADCSRA
Bit
Single Ended Input
00
ADC0 (PB5)
01
ADC1 (PB2)
10
ADC2 (PB4)
11
ADC3 (PB3)
7
6
5
4
3
2
1
0
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRA
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after
ADSC has been written after the ADC has been enabled, or if ADSC is written at the
same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal
13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
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When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start
a conversion on a positive edge of the selected trigger signal. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated.
The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in
SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.
Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the
input clock to the ADC.
Table 39. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
The ADC Data Register –
ADCL and ADCH
ADLAR = 0
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
8
–
–
–
–
–
–
ADC9
ADC8
ADCH
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADLAR = 1
Bit
Read/Write
90
15
14
13
12
11
10
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
–
–
–
–
–
–
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
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ATtiny13
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is
sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is
read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared
(default), the result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion
Result” on page 88.
ADC Control and Status
Register B – ADCSRB
Bit
7
6
5
4
3
2
1
0
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bits 7, 5..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will
trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no
effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
Note that switching from a trigger source that is cleared to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will
start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 40. ADC Auto Trigger Source Selections
Digital Input Disable Register
0 – DIDR0
ADTS2
ADTS1
ADTS0
0
0
0
Free Running mode
0
0
1
Analog Comparator
0
1
0
External Interrupt Request 0
0
1
1
Timer/Counter Compare Match A
1
0
0
Timer/Counter Overflow
1
0
1
Timer/Counter Compare Match B
1
1
0
Pin Change Interrupt Request
Bit
Trigger Source
7
6
5
4
3
2
1
0
–
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR0
• Bits 5..2 – ADC3D..ADC0D: ADC3..0 Digital Input Disable
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When this bit is written logic one, the digital input buffer on the corresponding ADC pin is
disabled. The corresponding PIN register bit will always read as zero when this bit is set.
When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is
not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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debugWIRE On-chip
Debug System
Features
•
•
•
•
•
•
•
•
•
•
Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different
non-volatile memories.
Physical Interface
When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port
pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled
and becomes the communication gateway between target and emulator.
Complete Program Flow Control
Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin
Real-time Operation
Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
Unlimited Number of Program Break Points (Using Software Break Points)
Non-intrusive Operation
Electrical Characteristics Identical to Real Device
Automatic Configuration System
High-Speed Operation
Programming of Non-volatile Memories
Figure 51. The debugWIRE Setup
1.8 - 5.5V
VCC
dW
dW(RESET)
GND
Figure 51 shows the schematic of a target MCU, with debugWIRE enabled, and the
emulator connector. The system clock is not affected by debugWIRE and will always be
the clock source selected by the CKSEL Fuses.
When designing a system where debugWIRE will be used, the following observations
must be made for correct operation:
•
Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ.
However, the pull-up resistor is optional.
•
Connecting the RESET pin directly to VCC will not work.
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Software Break Points
•
Capacitors inserted on the RESET pin must be disconnected when using
debugWire.
•
All external reset sources must be disconnected.
debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio ® will insert a BREAK instruction in the Program
memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing
from the Program memory. A break can be inserted manually by putting the BREAK
instruction in the program.
The Flash must be re-programmed each time a Break Point is changed. This is automatically handled by AVR Studio through the debugWIRE interface. The use of Break
Points will therefore reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to end customers.
Limitations of
debugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as
External Reset (RESET). An External Reset source is therefore not supported when the
debugWIRE is enabled.
The debugWIRE system accurately emulates all I/O functions when running at full
speed, i.e., when the program in the CPU is running. When the CPU is stopped, care
must be taken while accessing some of the I/O Registers via the debugger (AVR Studio). See the debugWIRE documentation for detailed description of the limitations.
A programmed DWEN Fuse enables some parts of the clock system to be running in all
sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN
Fuse should be disabled when debugWire is not used.
debugWIRE Related
Register in I/O Memory
debugWire Data Register –
DWDR
The following section describes the registers used with the debugWire.
Bit
7
6
5
4
3
2
1
0
DWDR[7:0]
DWDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The DWDR Register provides a communication channel from the running program in
the MCU to the debugger. This register is only accessible by the debugWIRE and can
therefore not be used as a general purpose register in the normal operations.
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Self-Programming
the Flash
The device provides a Self-Programming mechanism for downloading and uploading
program code by the MCU itself. The Self-Programming can use any available data
interface and associated protocol to read code and write (program) that code into the
Program memory.
The Program memory is updated in a page by page fashion. Before programming a
page with the data stored in the temporary page buffer, the page must be erased. The
temporary page buffer is filled one word at a time using SPM and the buffer can be filled
either before the Page Erase command or between a Page Erase and a Page Write
operation:
Alternative 1, fill the buffer before a Page Erase
•
Fill temporary page buffer
•
Perform a Page Erase
•
Perform a Page Write
Alternative 2, fill the buffer after Page Erase
•
Perform a Page Erase
•
Fill temporary page buffer
•
Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for
example in the temporary page buffer) before the erase, and then be re-written. When
using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature
which allows the user software to first read the page, do the necessary changes, and
then write back the modified data. If alternative 2 is used, it is not possible to read the
old data while loading since the page is already erased. The temporary page buffer can
be accessed in a random sequence. It is essential that the page address used in both
the Page Erase and Page Write operation is addressing the same page.
Performing Page Erase by
SPM
To execute Page Erase, set up the address in the Z-pointer, write “00000011” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in
R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register.
Other bits in the Z-pointer will be ignored during this operation.
•
Filling the Temporary Buffer
(Page Loading)
The CPU is halted during the Page Erase operation.
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing
SPMCSR. The content of PCWORD in the Z-register is used to address the data in the
temporary buffer. The temporary buffer will auto-erase after a Page Write operation or
by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is
not possible to write more than one time to each address without erasing the temporary
buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded
will be lost.
Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “00000101” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in
R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the
Z-pointer must be written to zero during this operation.
•
The CPU is halted during the Page Write operation.
95
2535B–AVR–01/04
Addressing the Flash
During SelfProgramming
The Z-pointer is used to address the SPM commands.
Bit
15
14
13
12
11
10
9
8
ZH (R31)
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZL (R30)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
7
6
5
4
3
2
1
0
Since the Flash is organized in pages (see Table 46 on page 102), the Program Counter
can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are
addressing the pages. This is shown in Figure 52. Note that the Page Erase and Page
Write operations are addressed independently. Therefore it is of major importance that
the software addresses the same page in both the Page Erase and Page Write
operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction
addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Figure 52. Addressing the Flash During SPM(1)
BIT
15
ZPCMSB
ZPAGEMSB
Z - REGISTER
1 0
0
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PROGRAM MEMORY
PAGE
PCWORD
WORD ADDRESS
WITHIN A PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note:
96
1. The different variables used in Figure 52 are listed in Table 46 on page 102.
ATtiny13
2535B–AVR–01/04
ATtiny13
Store Program Memory
Control and Status Register –
SPMCSR
The Store Program Memory Control and Status Register contains the control bits
needed to control the Program memory operations.
Bit
7
6
5
4
3
2
1
0
–
–
–
CTPB
RFLB
PGWRT
PGERS
SELFPRGEN
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPMCSR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and always read as zero.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page
buffer will be cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the
SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in
the Z-pointer) into the destination register. See “EEPROM Write Prevents Writing to
SPMCSR” on page 98 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction
within four clock cycles executes Page Write, with the data stored in the temporary
buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and
R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no
SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction
within four clock cycles executes Page Erase. The page address is taken from the high
part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear
upon completion of a Page Erase, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire Page Write operation.
• Bit 0 – SELFPRGEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one
together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction
will have a special meaning, see description above. If only SELFPRGEN is written, the
following SPM instruction will store the value in R1:R0 in the temporary page buffer
addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit
will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SELFPRGEN bit
remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the
lower five bits will have no effect.
97
2535B–AVR–01/04
EEPROM Write Prevents
Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEWE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
Reading the Fuse and Lock
Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR.
When an LPM instruction is executed within three CPU cycles after the RFLB and
SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the
destination register. The RFLB and SELFPRGEN bits will auto-clear upon completion of
reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no
SPM instruction is executed within four CPU cycles. When RFLB and SELFPRGEN are
cleared, LPM will work as described in the Instruction set Manual.
Bit
7
6
5
4
3
2
1
0
Rd
–
–
–
–
–
–
LB2
LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for
reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and
set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed
within three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR, the
value of the Fuse Low byte (FLB) will be loaded in the destination register as shown
below. Refer to Table 45 on page 101 for a detailed description and mapping of the
Fuse Low byte.
Bit
7
6
5
4
3
2
1
0
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set
in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination
register as shown below. Refer to Table XXX on page XXX for detailed description and
mapping of the Fuse High byte.
Bit
7
6
5
4
3
2
1
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that
are unprogrammed, will be read as one.
98
ATtiny13
2535B–AVR–01/04
ATtiny13
Preventing Flash Corruption
During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same
as for board level systems using the Flash, and the same design solutions should be
applied.
A Flash program corruption can be caused by two situations when the voltage is too low.
First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage
for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one
is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if
the operating voltage matches the detection level. If not, an external low VCC
reset protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply
voltage is sufficient.
2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This
will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional
writes.
Programming Time for Flash
when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 41 shows the typical
programming time for Flash accesses from the CPU.
Table 41. SPM Programming Time
Symbol
Min Programming Time
Max Programming Time
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
3.7 ms
4.5 ms
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2535B–AVR–01/04
Memory
Programming
This section describes the different methods for Programming the ATtiny13 memories.
Program And Data
Memory Lock Bits
The ATtiny13 provides two Lock bits which can be left unprogrammed (“1”) or can be
programmed (“0”) to obtain the additional security listed in Table 43. The Lock bits can
only be erased to “1” with the Chip Erase command.
Program memory can be read out via the debugWIRE interface when the DWEN fuse is
programmed, even if the Lock Bits are set. Thus, when Lock Bit security is required,
should always debugWIRE be disabled by clearing the DWEN fuse.
Table 42. Lock Bit Byte(1)
Lock Bit Byte
Description
Default Value
7
–
1 (unprogrammed)
6
–
1 (unprogrammed)
5
–
1 (unprogrammed)
4
–
1 (unprogrammed)
3
–
1 (unprogrammed)
2
–
1 (unprogrammed)
LB2
1
Lock bit
1 (unprogrammed)
LB1
0
Lock bit
1 (unprogrammed)
Note:
Bit No
1. “1” means unprogrammed, “0” means programmed
Table 43. Lock Bit Protection Modes(1)(2)
Memory Lock Bits
LB Mode
LB2
LB1
1
1
1
No memory lock features enabled.
0
Further programming of the Flash and EEPROM is
disabled in High-voltage and Serial Programming mode.
The Fuse bits are locked in both Serial and High-voltage
Programming mode.(1) debugWire is disabled.
0
Further programming and verification of the Flash and
EEPROM is disabled in High-voltage and Serial
Programming mode. The Fuse bits are locked in both
Serial and High-voltage Programming mode.(1) debugWire
is disabled.
2
3
Notes:
100
Protection Type
1
0
1. Program the Fuse bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
ATtiny13
2535B–AVR–01/04
ATtiny13
Fuse Bytes
The ATtiny13 has two Fuse bytes. Table 44 and Table 45 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are
read as logical zero, “0”, if they are programmed.
Table 44. Fuse High Byte
Fuse High Byte
Bit No
Description
Default Value
–
7
–
1 (unprogrammed)
–
6
–
1 (unprogrammed)
–
5
–
1 (unprogrammed)
SELFPRGEN
4
Self Programming Enable
1 (unprogrammed)
DWEN(3)
3
debugWire Enable
1 (unprogrammed)
BODLEVEL1
(1)
2
Brown-out Detector trigger level
1 (unprogrammed)
BODLEVEL0
(1)
1
Brown-out Detector trigger level
1 (unprogrammed)
0
External Reset disable
1 (unprogrammed)
RSTDISBL
Notes:
(4)
1. See Table 13 on page 32 for BODLEVEL Fuse decoding.
2. See “Alternate Functions of Port B” on page 49 for description of RSTDISBL and
DWEN Fuses.
3. DWEN must be unprogrammed when Lock Bit security is required. See “Program
And Data Memory Lock Bits” on page 100.
4. When programming the RSTDISBL Fuse, High-voltage Serial programming has to be
used to change fuses to perform further programming.
Table 45. Fuse Low Byte
Fuse Low Byte
Bit No
Description
Default Value
SPIEN(1)
7
Enable Serial Program
and Data Downloading
0 (programmed, SPI prog.
enabled)
EESAVE
6
EEPROM memory is
preserved through the
Chip Erase
1 (unprogrammed,
EEPROM not preserved)
WDTON(2)
5
Watchdog Timer always
on
1 (unprogrammed)
(5)
4
Divide clock by 8
0 (programmed)
SUT1
3
Select start-up time
1 (unprogrammed)(3)
SUT0
2
Select start-up time
0 (programmed)(3)
CKSEL1
1
Select Clock source
1 (unprogrammed)(4)
CKSEL0
0
Select Clock source
0 (programmed)(4)
CKDIV8
Notes:
1. The SPIEN Fuse is not accessible in SPI Programming mode.
2. See “Watchdog Timer Control Register - WDTCR” on page 37 for details.
3. The default value of SUT1..0 results in maximum start-up time for the default clock
source. See Table 5 on page 22 for details.
4. The default setting of CKSEL1..0 results in internal RC Oscillator @ 9.6 MHz. See
Table 4 on page 22 for details.
5. See “System Clock Prescaler” on page 24 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are
locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the
Lock bits.
101
2535B–AVR–01/04
Latching of Fuses
The fuse values are latched when the device enters programming mode and changes of
the fuse values will have no effect until the part leaves Programming mode. This does
not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses
are also latched on Power-up in Normal mode.
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device.
This code can be read in both serial and High-voltage Programming mode, also when
the device is locked. The three bytes reside in a separate address space.
For the ATtiny13 the signature bytes are:
1. 0x000: 0x1E (indicates manufactured by Atmel).
2. 0x001: 0x90 (indicates 1 KB Flash memory).
3. 0x002: 0x07 (indicates ATtiny13 device when 0x001 is 0x90).
Calibration Byte
Signature area of the ATtiny13 has one byte of calibration data for the internal RC Oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is
automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.
Page Size
Table 46. No. of Words in a Page and No. of Pages in the Flash
Flash Size
512 words (1K byte)
Page Size
PCWORD
No. of Pages
PCPAGE
PCMSB
16 words
PC[3:0]
32
PC[8:4]
8
Table 47. No. of Words in a Page and No. of Pages in the EEPROM
102
EEPROM Size
Page Size
PCWORD
No. of Pages
PCPAGE
EEAMSB
64 bytes
4 bytes
EEA[1:0]
16
EEA[5:2]
5
ATtiny13
2535B–AVR–01/04
ATtiny13
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 48 on page 103, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface.
Figure 53. Serial Programming and Verify(1)
+1.8 - 5.5V
PB5
RESET
VCC
GND
Notes:
PB2
SCK
PB1
MISO
PB0
MOSI
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock
source to the CLKI pin.
Table 48. Pin Mapping Serial Programming
Symbol
Pins
I/O
Description
MOSI
PB0
I
Serial Data in
MISO
PB1
O
Serial Data out
SCK
PB2
I
Serial Clock
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
103
2535B–AVR–01/04
Serial Programming
Algorithm
When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK.
When reading data from the ATtiny13, data is clocked on the falling edge of SCK. See
Figure 54 and Figure 55 for timing details.
To program and verify the ATtiny13 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in Table 50):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In
some systems, the programmer can not guarantee that SCK is held low during
power-up. In this case, RESET must be given a positive pulse of at least two
CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of
synchronization. When in sync. the second byte (0x53), will echo back when
issuing the third byte of the Programming Enable instruction. Whether the echo
is correct or not, all four bytes of the instruction must be transmitted. If the 0x53
did not echo back, give RESET a positive pulse and issue a new Programming
Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one
byte at a time by supplying the 5 LSB of the address and data together with the
Load Program memory Page instruction. To ensure correct loading of the page,
the data low byte must be loaded before data high byte is applied for a given
address. The Program memory Page is stored by loading the Write Program
memory Page instruction with the 3 MSB of the address. If polling is not used,
the user must wait at least tWD_FLASH before issuing the next page. (See Table
49.) Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the
address and data together with the appropriate Write instruction. An EEPROM
memory location is first automatically erased before new data is written. If polling
is not used, the user must wait at least tWD_EEPROM before issuing the next byte.
(See Table 49.) In a chip erased device, no 0xFFs in the data file(s) need to be
programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the 2 LSB of the address and data
together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with
the 4 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The
remaining locations remain unchanged. If polling is not used, the used must wait
at least tWD_EEPROM before issuing the next page (See Table 47). In a chip erased
device, no 0xFF in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns
the content at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence
normal operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
104
ATtiny13
2535B–AVR–01/04
ATtiny13
Data Polling Flash
When a page is being programmed into the Flash, reading an address location within
the page being programmed will give the value 0xFF. At the time the device is ready for
a new page, the programmed value will read correctly. This is used to determine when
the next page can be written. Note that the entire page is written simultaneously and any
address within the page can be used for polling. Data polling of the Flash will not work
for the value 0xFF, so when programming this value, the user will have to wait for at
least tWD_FLASH before programming the next page. As a chip-erased device contains
0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be
skipped. See Table 49 for tWD_FLASH value.
Data Polling EEPROM
When a new byte has been written and is being programmed into EEPROM, reading the
address location being programmed will give the value 0xFF. At the time the device is
ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the
user should have the following in mind: As a chip-erased device contains 0xFF in all
locations, programming of addresses that are meant to contain 0xFF, can be skipped.
This does not apply if the EEPROM is re-programmed without chip erasing the device.
In this case, data polling cannot be used for the value 0xFF, and the user will have to
wait at least tWD_EEPROM before programming the next byte. See Table 49 for tWD_EEPROM
value.
Table 49. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol
Minimum Wait Delay
tWD_FLASH
4.5 ms
tWD_EEPROM
4.0 ms
tWD_ERASE
4.0 ms
tWD_FUSE
4.5 ms
Figure 54. Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)
MSB
LSB
SERIAL DATA OUTPUT
(MISO)
MSB
LSB
SERIAL CLOCK INPUT
(SCK)
SAMPLE
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2535B–AVR–01/04
Table 50. Serial Programming Instruction Set
Instruction Format
Instruction
Byte 1
Byte 2
Byte 3
Byte4
Programming Enable
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
Enable Serial Programming after
RESET goes low.
Chip Erase
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
Chip Erase EEPROM and Flash.
Read Program Memory
0010 H000
0000 000a
bbbb bbbb
oooo oooo
Read H (high or low) data o from
Program memory at word address a:b.
Load Program Memory Page
0100 H000
000x xxxx
xxxb bbbb
iiii iiii
Write H (high or low) data i to Program
memory page at word address b. Data
low byte must be loaded before Data
high byte is applied within the same
address.
Write Program Memory Page
0100 1100
0000 000a
bbxx xxxx
xxxx xxxx
Write Program memory Page at
address a:b.
Read EEPROM Memory
1010 0000
000x xxxx
xxbb bbbb
oooo oooo
Read data o from EEPROM memory at
address b.
Write EEPROM Memory
1100 0000
000x xxxx
xxbb bbbb
iiii iiii
Write data i to EEPROM memory at
address b.
Load EEPROM Memory
Page (page access)
1100 0001
0000 0000
0000 00bb
iiii iiii
Load data i to EEPROM memory page
buffer. After data is loaded, program
EEPROM page.
Write EEPROM Memory
Page (page access)
1100 0010
00xx xxxx
xxbb bb00
xxxx xxxx
Read Lock bits
0101 1000
0000 0000
xxxx xxxx
xxoo oooo
Read Lock bits. “0” = programmed, “1”
= unprogrammed. See Table 42 on
page 100 for details.
Write Lock bits
1010 1100
111x xxxx
xxxx xxxx
11ii iiii
Write Lock bits. Set bits = “0” to
program Lock bits. See Table 42 on
page 100 for details.
Read Signature Byte
0011 0000
000x xxxx
xxxx xxbb
oooo oooo
Read Signature Byte o at address b.
Write Fuse bits
1010 1100
1010 0000
xxxx xxxx
iiii iiii
Set bits = “0” to program, “1” to
unprogram.
Write Fuse High bits
1010 1100
1010 1000
xxxx xxxx
iiii iiii
Set bits = “0” to program, “1” to
unprogram. See Table 36 on page 82
for details.
Read Fuse bits
0101 0000
0000 0000
xxxx xxxx
oooo oooo
Read Fuse bits. “0” = programmed, “1”
= unprogrammed.
Read Fuse High bits
0101 1000
0000 1000
xxxx xxxx
oooo oooo
Read Fuse High bits. “0” = programmed, “1” = unprogrammed. See
Table 36 on page 82 for details.
Read Calibration Byte
0011 1000
000x xxxx
0000 0000
oooo oooo
Read Calibration Byte
Poll RDY/BSY
1111 0000
0000 0000
xxxx xxxx
xxxx xxxo
If o = “1”, a programming operation is
still busy. Wait until this bit returns to
“0” before applying another command.
Note:
106
Operation
Write EEPROM page at address b.
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
ATtiny13
2535B–AVR–01/04
ATtiny13
Serial Programming
Characteristics
Figure 55. Serial Programming Timing
MOSI
tSHOX
tOVSH
SCK
tSLSH
tSHSL
MISO
tSLIV
Table 51. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.5V
(Unless Otherwise Noted)
Symbol
Parameter
1/tCLCL
Oscillator Frequency (ATtiny13V)
tCLCL
Oscillator Period (ATtiny13V)
1/tCLCL
tCLCL
Oscillator Period (ATtiny13L, VCC = 2.7 - 5.5V)
Typ
0
Max
Units
1
MHz
1,000
ns
0
9.6
104
MHz
ns
Oscillator Frequency (ATtiny13, VCC = 4.5V 5.5V)
0
tCLCL
Oscillator Period (ATtiny13, VCC = 4.5V - 5.5V)
67
ns
tSHSL
SCK Pulse Width High
2 tCLCL*
ns
tSLSH
SCK Pulse Width Low
2 tCLCL*
ns
tOVSH
MOSI Setup to SCK High
tCLCL
ns
tSHOX
MOSI Hold after SCK High
2 tCLCL
ns
tSLIV
SCK Low to MISO Valid
1/tCLCL
Note:
High-voltage Serial
Programming
Oscillator Frequency (ATtiny13L, VCC = 2.7 5.5V)
Min
TBD
16
TBD
TBD
MHz
ns
1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz
This section describes how to program and verify Flash Program memory, EEPROM
Data memory, Lock bits and Fuse bits in the ATtiny13.
107
2535B–AVR–01/04
Figure 56. High-voltage Serial Programming
+11.5 - 12.5V
SERIAL CLOCK INPUT
+1.8 - 5.5V
PB5 (RESET)
VCC
PB3 (CLKI)
PB2
SCK
PB1
MISO
PB0
MOSI
GND
Table 52. Pin Name Mapping
Signal Name in High-voltage
Serial Programming Mode
Pin Name
I/O
Function
SDI
PB0
I
Serial Data Input
SII
PB1
I
Serial Instruction Input
SDO
PB2
O
Serial Data Output
SCI
PB3
I
Serial Clock Input (min. 220ns period)
The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns.
Table 53. Pin Values Used to Enter Programming Mode
108
Pin
Symbol
Value
SDI
Prog_enable[0]
0
SII
Prog_enable[1]
0
SDO
Prog_enable[2]
0
ATtiny13
2535B–AVR–01/04
ATtiny13
High-voltage Serial
Programming Algorithm
To program and verify the ATtiny13 in the High-voltage Serial Programming mode, the
following sequence is recommended (See instruction formats in Table 55):
Enter High-voltage Serial
Programming Mode
The following algorithm puts the device in High-voltage Serial Programming mode:
1. Apply 4.5 - 5.5V between VCC and GND.
2. Set RESET pin to “0” and toggle SCI at least six times.
3. Set the Prog_enable pins listed in Table 53 to “000” and wait at least 100 ns.
4. Apply VHVRST - 5.5V to RESET. Keep the Prog_enable pins unchanged for at
least tHVRST after the High-voltage has been applied to ensure the Prog_enable
signature has been latched.
5. Shortly after latching the Prog_enable signature, the device will actively output
data on the Prog_enable[2]/SDO pin, and the resulting drive contention may
increase the power consumption. To minimize this drive contention, release the
Prog_enable[2] pin after tHVRST has elapsed.
6. Wait at least 50 µs before giving any serial instructions on SDI/SII.
Table 54. High-voltage Reset Characteristics
RESET Pin High-voltage Threshold
Minimum High-voltage Period
for Latching Prog_enable
VCC
VHVRST
tHVRST
4.5V
11.5V
100 ns
5.5V
11.5V
100 ns
Supply Voltage
Considerations for Efficient
Programming
Chip Erase
The loaded command and address are retained in the device during programming. For
efficient programming, the following should be considered.
•
The command needs only be loaded once when writing or reading multiple memory
locations.
•
Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless
the EESAVE Fuse is programmed) and Flash after a Chip Erase.
•
Address High byte needs only be loaded before programming or reading a new 256
word window in Flash or 256 byte EEPROM. This consideration also applies to
Signature bytes reading.
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock
bits are not reset until the Program memory has been completely erased. The Fuse bits
are not changed. A Chip Erase must be performed before the Flash and/or EEPROM
are re-programmed.
Note:
1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is
programmed.
1. Load command “Chip Erase” (see Table 55).
2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.
3. Load Command “No Operation”.
109
2535B–AVR–01/04
Programming the Flash
The Flash is organized in pages, see Table 50 on page 106. When programming the
Flash, the program data is latched into a page buffer. This allows one page of program
data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory:
1. Load Command “Write Flash” (see Table 55).
2. Load Flash Page Buffer.
3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes
high for the “Page Programming” cycle to finish.
4. Repeat 2 through 3 until the entire Flash is programmed or until all data has
been programmed.
5. End Page Programming by Loading Command “No Operation”.
When writing or reading serial data to the ATtiny13, data is clocked on the rising edge of
the serial clock, see Figure 58, Figure 59 and Table 56 for details.
Figure 57. Addressing the Flash which is Organized in Pages
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
PCWORD[PAGEMSB:0]:
00
INSTRUCTION WORD
01
02
PAGEEND
Figure 58. High-voltage Serial Programming Waveforms
SDI
PB0
MSB
LSB
SII
PB1
MSB
LSB
SDO
PB2
SCI
PB3
110
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10
ATtiny13
2535B–AVR–01/04
ATtiny13
Programming the EEPROM
The EEPROM is organized in pages, see Table 51 on page 107. When programming
the EEPROM, the data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 55):
1. Load Command “Write EEPROM”.
2. Load EEPROM Page Buffer.
3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page
Programming” cycle to finish.
4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has
been programmed.
5. End Page Programming by Loading Command “No Operation”.
Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to Table 55):
1. Load Command "Read Flash".
2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO.
Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to Table 55):
1. Load Command “Read EEPROM”.
2. Read EEPROM Byte. The contents at the selected address are available at
serial output SDO.
Programming and Reading
the Fuse and Lock Bits
The algorithms for programming and reading the Fuse Low/High bits and Lock bits are
shown in Table 55.
Reading the Signature Bytes
and Calibration Byte
The algorithms for reading the Signature bytes and Calibration byte are shown in Table
55.
Power-off sequence
Set SCI to “0”. Set RESET to “1”. Turn VCC power off.
111
2535B–AVR–01/04
Table 55. High-voltage Serial Programming Instruction Set for ATtiny13
Instruction Format
Instruction
Chip Erase
Load “Write
Flash”
Command
Load Flash
Page Buffer
Instr.1/5
Instr.2/6
Instr.3
SDI
0_1000_0000_00
0_0000_0000_00
0_0000_0000_00
SII
0_0100_1100_00
0_0110_0100_00
0_0110_1100_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
SDI
0_0001_0000_00
SII
0_0100_1100_00
Enter Flash Programming code.
x_xxxx_xxxx_xx
SDI
0_ bbbb_bbbb _00
0_eeee_eeee_00
0_dddd_dddd_00
0_0000_0000_00
SII
0_0000_1100_00
0_0010_1100_00
0_0011_1100_00
0_0111_1101_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
SDI
0_0000_0000_00
SII
0_0111_1100_00
Load Flash High SDI
Address and
SII
Program Page
SDO
Instr 5.
0_0000_000a_00
0_0001_1100_00
0_0000_0000_00
0_0110_0100_00
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
SDI
0_0000_0010_00
SII
0_0100_1100_00
Wait after Instr 3 until SDO goes
high. Repeat Instr. 2 - 3 for each
loaded Flash Page until the entire
Flash or all data is programmed.
Repeat Instr. 1 for a new 256 byte
page. See Note 1.
Enter Flash Read mode.
SDO
x_xxxx_xxxx_xx
SDI
0_bbbb_bbbb_00
0_0000_000a_00
0_0000_0000_00
0_0000_0000_00
SII
0_0000_1100_00
0_0001_1100_00
0_0110_1000_00
0_0110_1100_00
x_xxxx_xxxx_xx
q_qqqq_qqqx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1000_00
0_0000_0000_00
0_0111_1100_00
SDO
x_xxxx_xxxx_xx
p_pppp_pppx_xx
SDI
0_0001_0001_00
SII
SDO
0_0100_1100_00
x_xxxx_xxxx_xx
SDI
SII
0_00bb_bbbb_00
0_0000_1100_00
0_eeee_eeee_00
0_0010_1100_00
0_0000_0000_00
0_0110_1101_00
0_0000_0000_00
0_0110_1100_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
SDI
0_0000_0000_00
0_0000_0000_00
SII
SDO
0_0110_0100_00
x_xxxx_xxxx_xx
0_0110_1100_00
x_xxxx_xxxx_xx
SDI
SII
0_00bb_bbbb_00
0_0000_1100_00
0_eeee_eeee_00
0_0010_1100_00
0_0000_0000_00
0_0110_1101_00
0_0000_0000_00
0_0110_0100_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
SDI
0_0000_0000_00
SII
SDO
0_0110_1100_00
x_xxxx_xxxx_xx
Load EEPROM
Page Buffer
Program
EEPROM Page
Write EEPROM
Byte
112
Repeat after Instr. 1 - 5 until the
entire page buffer is filled or until all
data within the page is filled. See
Note 1.
x_xxxx_xxxx_xx
Read Flash Low SDO
and High Bytes SDI
SII
Load “Write
EEPROM”
Command
Operation Remarks
Wait after Instr.3 until SDO goes
high for the Chip Erase cycle to
finish.
SDO
SDO
Load “Read
Flash”
Command
Instr.4
Repeat Instr. 1, 3 - 6 for each new
address. Repeat Instr. 2 for a new
256 byte page.
Instr 5 - 6.
Enter EEPROM Programming
mode.
Repeat Instr. 1 - 4 until the entire
page buffer is filled or until all data
within the page is filled. See Note
2.
Wait after Instr. 2 until SDO goes
high. Repeat Instr. 1 - 2 for each
loaded EEPROM page until the
entire EEPROM or all data is
programmed.
Repeat Instr. 1 - 5 for each new
address. Wait after Instr. 5 until
SDO goes high. See Note 3.
Instr. 5
ATtiny13
2535B–AVR–01/04
ATtiny13
Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 (Continued)
Instruction Format
Instruction
Load “Read
EEPROM”
Command
Instr.1/5
SDI
0_0000_0011_00
SII
0_0100_1100_00
Instr.2/6
Instr.3
Instr.4
Enter EEPROM Read mode.
SDO
x_xxxx_xxxx_xx
SDI
SII
0_bbbb_bbbb_00
0_0000_1100_00
0_aaaa_aaaa_00
0_0001_1100_00
0_0000_0000_00
0_0110_1000_00
0_0000_0000_00
0_0110_1100_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
q_qqqq_qqq0_00
SDI
0_0100_0100_00
0_A987_6543_00
0_0000_0000_00
0_0000_0000_00
SII
SDO
0_0100_1100_00
x_xxxx_xxxx_xx
0_0010_1100_00
x_xxxx_xxxx_xx
0_0110_0100_00
x_xxxx_xxxx_xx
0_0110_1100_00
x_xxxx_xxxx_xx
SDI
Write Fuse High
SII
Bits
SDO
0_0100_0000_00
0_000F_EDCB_00
0_0000_0000_00
0_0000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0010_1100_00
x_xxxx_xxxx_xx
0_0111_0100_00
x_xxxx_xxxx_xx
0_0111_1100_00
x_xxxx_xxxx_xx
SDI
0_0010_0000_00
0_0000_0021_00
0_0000_0000_00
0_0000_0000_00
SII
0_0100_1100_00
0_0010_1100_00
0_0110_0100_00
0_0110_1100_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
SDI
SII
0_0000_0100_00
0_0100_1100_00
0_0000_0000_00
0_0110_1000_00
0_0000_0000_00
0_0110_1100_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
A_9876_543x_xx
SDI
Read Fuse High
SII
Bits
SDO
0_0000_0100_00
0_0000_0000_00
0_0000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0111_1010_00
x_xxxx_xxxx_xx
0_0111_1110_00
x_xxFE_DCBx_xx
SDI
0_0000_0100_00
0_0000_0000_00
0_0000_0000_00
SII
SDO
0_0100_1100_00
x_xxxx_xxxx_xx
0_0111_1000_00
x_xxxx_xxxx_xx
0_0111_1100_00
x_xxxx_x21x_xx
SDI
0_0000_1000_00
0_0000_00bb_00
0_0000_0000_00
0_0000_0000_00
SII
0_0100_1100_00
0_0000_1100_00
0_0110_1000_00
0_0110_1100_00
SDO
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
q_qqqq_qqqx_xx
SDI
Read
SII
Calibration Byte
SDO
0_0000_1000_00
0_0100_1100_00
0_0000_0000_00
0_0000_1100_00
0_0000_0000_00
0_0111_1000_00
0_0000_0000_00
0_0111_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
p_pppp_pppx_xx
Read EEPROM
Byte
Write Fuse Low
Bits
Write Lock Bits
Read Fuse Low
Bits
Read Lock Bits
Read Signature
Bytes
Load “No
Operation”
Command
SDI
0_0000_0000_00
SII
0_0100_1100_00
SDO
Operation Remarks
Repeat Instr. 1, 3 - 4 for each new
address. Repeat Instr. 2 for a new
256 byte page.
Wait after Instr. 4 until SDO goes
high. Write A - 3 = “0” to program
the Fuse bit.
Wait after Instr. 4 until SDO goes
high. Write F - B = “0” to program
the Fuse bit.
Wait after Instr. 4 until SDO goes
high. Write 2 - 1 = “0” to program
the Lock Bit.
Reading A - 3 = “0” means the
Fuse bit is programmed.
Reading F - B = “0” means the
Fuse bit is programmed.
Reading 2, 1 = “0” means the Lock
bit is programmed.
Repeats Instr 2 4 for each
signature byte address.
x_xxxx_xxxx_xx
Note:
a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits,
x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = SUT0 Fuse, 6 = SUT1 Fuse, 7 = CKDIV8,
Fuse, 8 = WDTON Fuse, 9 = EESAVE Fuse, A = SPIEN Fuse, B = RSTDISBL Fuse, C = BODLEVEL0 Fuse, D= BODLEVEL1
Fuse, E = MONEN Fuse, F = SELFPRGEN Fuse
Notes:
1. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address.
2. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address.
3. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM.
Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase
of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming.
113
2535B–AVR–01/04
High-voltage Serial
Programming
Characteristics
Figure 59. High-voltage Serial Programming Timing
SDI (PB0), SII (PB1)
tIVSH
SCI (PB3)
tSHIX
tSLSH
tSHSL
SDO (PB2)
tSHOV
Table 56. High-voltage Serial Programming Characteristics VCC = 5.0V ± 10% (Unless
otherwise noted)
Symbol
114
Parameter
Min
Typ
Max
Units
tSHSL
SCI (PB3) Pulse Width High
110
ns
tSLSH
SCI (PB3) Pulse Width Low
110
ns
tIVSH
SDI (PB0), SII (PB1) Valid to SCI (PB3) High
50
ns
tSHIX
SDI (PB0), SII (PB1) Hold after SCI (PB3) High
50
ns
tSHOV
SCI (PB3) High to SDO (PB2) Valid
16
ns
tWLWH_PFB
Wait after Instr. 3 for Write Fuse Bits
2.5
ms
ATtiny13
2535B–AVR–01/04
ATtiny13
Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
DC Characteristics
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1)
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High-voltage
Condition
Min.
Typ.
-0.5
Except RESET pin
Max.
Units
0.2VCC
V
0.6VCC
(3)
VCC +0.5
V
0.9VCC
(3)
VCC +0.5
V
0.7
0.5
V
V
VIH2
Input High-voltage
RESET pin
VOL
Output Low Voltage(4)
(Port B)
IOL = 10 mA, VCC = 5V
IOL = 5 mA, VCC = 3V
VOH
Output High-voltage(5)
(Port B)
IOH = -10 mA, VCC = 5V
IOH = -5 mA, VCC = 3V
IIL
Input Leakage
Current I/O Pin
Vcc = 5.5V, pin low
(absolute value)
1
µA
IIH
Input Leakage
Current I/O Pin
Vcc = 5.5V, pin high
(absolute value)
1
µA
RRST
Reset Pull-up Resistor
30
80
kΩ
Rpu
I/O Pin Pull-up Resistor
20
50
kΩ
Active 1MHz, VCC = 2V
0.55
mA
Active 4MHz, VCC = 3V
3.5
mA
Active 8MHz, VCC = 5V
12
mA
Power Supply Current
ICC
Power-down mode
Notes:
4.2
2.5
V
V
Idle 1MHz, VCC = 2V
0.08
0.25
mA
Idle 4MHz, VCC = 3V
0.41
1.5
mA
Idle 8MHz, VCC = 5V
1.6
5.5
mA
WDT enabled, VCC = 3V
<5
16
µA
WDT disabled, VCC = 3V
< 0.5
8
µA
1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and
will be updated after characterization of actual silicon.
2. “Max” means the highest value where the pin is guaranteed to be read as low.
115
2535B–AVR–01/04
3. “Min” means the lowest value where the pin is guaranteed to be read as high.
4. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 60 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
5. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 60 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
External Clock Drive Waveforms
Figure 60. External Clock Drive Waveforms
V IH1
V IL1
External Clock Drive
Table 57. External Clock Drive
VCC = 1.8 - 5.5V
VCC = 2.7 - 5.5V
VCC = 4.5 - 5.5V
Symbol
Parameter
1/tCLCL
Clock Frequency
tCLCL
Clock Period
1000
104
62.5
ns
tCHCX
High Time
400
50
25
ns
tCLCX
Low Time
400
50
25
ns
tCLCH
Rise Time
2.0
1.6
0.5
µs
tCHCL
Fall Time
2.0
1.6
0.5
µs
∆tCLCL
Change in period from one clock cycle to the next
2
2
2
%
Maximum Speed vs. VCC
Min.
Max.
Min.
Max.
Min.
Max.
Units
0
1
0
9.6
0
16
MHz
Maximum frequency is depending on VCC. As shown in Figure 61 and Figure 62, the
Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 4.5V. To calculate
the maximum frequency at a given voltage in this interval, use this equation:
( V – 0.9 )
Frequency = ---------------------0.15
At 3 Volt, this gives:
( 3 – 0.9 )
Frequency = ---------------------- = 14
0.15
Thus, when VCC = 3V, maximum frequency will be 14 MHz.
116
ATtiny13
2535B–AVR–01/04
ATtiny13
To calculate required voltage for a maximum frequency, use this equation::
Voltage = 0.9 + 0.15 • f
At 19 MHz this gives:
Voltage = 0.9 + 0.15 • 19 = 3.75V
Thus, a maximum frequency of 19 MHz requires VCC = 3.75 V.
Figure 61. Maximum Frequency vs. VCC, ATtiny13V
12 MHz
Safe Operating Area
6 MHz
1.8V
2.7V
5.5V
Figure 62. Maximum Frequency vs. VCC, ATtiny13
24 MHz
12 MHz
Safe Operating Area
2.7V
4.5V
5.5V
117
2535B–AVR–01/04
ADC Characteristics – Preliminary Data
Table 58. ADC Characteristics, Single Ended Channels. -40°C - 85°C
Symbol
Parameter
Resolution
Min(1)
Single Ended Conversion
Units
10
Bits
LSB
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
3
LSB
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
Noise Reduction Mode
1.5
LSB
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
Noise Reduction Mode
2.5
LSB
Integral Non-linearity (INL)
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
1
LSB
Differential Non-linearity (DNL)
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
0.5
LSB
Gain Error
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
2.5
LSB
Offset Error
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
1.5
LSB
Conversion Time
Free Running Conversion
Input Voltage
13
260
µs
50
1000
kHz
GND
VREF
V
Input Bandwidth
VINT
Internal Voltage Reference
RAIN
Analog Input Resistance
118
Max(1)
2
Clock Frequency
Notes:
Typ(1)
Single Ended Conversion
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
Absolute accuracy (Including
INL, DNL, quantization error,
gain and offset error)
VIN
Condition
38.5
1.0
1.1
100
kHz
1.2
V
MΩ
1. Values are preliminary.
ATtiny13
2535B–AVR–01/04
ATtiny13
ATtiny13 Typical
Characteristics –
Preliminary Data
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins
configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage,
operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and
ambient temperature. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as
CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog
Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
Active Supply Current
Figure 63. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 - 1.0 MHz
1.2
5.5 V
1
5.0 V
ICC (mA)
0.8
4.5 V
4.0 V
0.6
3.3 V
2.7 V
0.4
1.8 V
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
119
2535B–AVR–01/04
Figure 64. Active Supply Current vs. Frequency (1 - 24 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 24 MHz
ICC (mA)
18
16
5.5V
14
5.0V
12
4.5V
10
4.0V
8
6
3.3V
4
2.7V
2
1.8V
0
0
2
4
6
8
10
12
14
16
18
20
22
24
Frequency (MHz)
Figure 65. Active Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 9.6 MHz
8
85 °C
-40 °C
7
6
25 °C
ICC (mA)
5
4
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
120
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 66. Active Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4.8 MHz
4.5
25 °C
-40 °C
85 °C
4
3.5
ICC (mA)
3
2.5
2
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 67. Active Supply Current vs. VCC (Internal WDT Oscillator, 128 kHz)
ACTIVE SUPPLY CURRENT vs. V CC
INTERNAL WD OSCILLATOR, 128 KHz
0.14
-40 °C
25 °C
85 °C
0.12
ICC (mA)
0.1
0.08
0.06
0.04
0.02
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
121
2535B–AVR–01/04
Figure 68. Active Supply Current vs. VCC (32 kHz External Clock)
ACTIVE SUPPLY CURRENT vs. V CC
32 kHz EXTERNAL CLOCK
0.04
25 °C
0.035
85 °C
0.03
ICC (mA)
0.025
0.02
0.015
0.01
0.005
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Idle Supply Current
Figure 69. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. LOW FREQUENCY
(0.1 - 1.0 MHz)
ICC (mA)
0.9
0.8
5.5 V
0.7
5.0 V
0.6
4.5 V
0.5
4.0 V
0.4
3.3 V
0.3
2.7 V
0.2
1.8 V
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
122
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 70. Idle Supply Current vs. Frequency (1 - 24 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 24 MHz
12
5.5V
5.0V
10
4.5V
ICC (mA)
8
6
4.0V
4
3.3V
2.7V
2
1.8V
0
0
2
4
6
8
10
12
14
16
18
20
22
24
Frequency (MHz)
Figure 71. Idle Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 9.6 MHz
2.5
85 °C
25 °C
-40 °C
ICC (mA)
2
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
123
2535B–AVR–01/04
Figure 72. Idle Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4.8 MHz
1.2
85 °C
25 °C
-40 °C
1
ICC (mA)
0.8
0.6
0.4
0.2
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 73. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL WD OSCILLATOR, 128 KHz
0.035
-40 °C
25 °C
85 °C
0.03
ICC (mA)
0.025
0.02
0.015
0.01
0.005
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
124
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 74. Idle Supply Current vs. VCC (32 kHz External Clock)
IDLE SUPPLY CURRENT vs. VCC
32kHz EXTERNAL CLOCK
10
9
85 °C
8
25 °C
-40 °C
ICC (uA)
7
6
5
4
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Power-Down Supply
Current
Figure 75. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
1.8
1.6
85 ˚C
1.4
ICC (uA)
1.2
1
0.8
-40 ˚C
25 ˚C
0.6
0.4
0.2
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
125
2535B–AVR–01/04
Figure 76. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
10
-40 ˚C
85 ˚C
25 ˚C
9
8
ICC (uA)
7
6
5
4
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Pin Pull-up
Figure 77. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 5V
160
140
25 ˚C
85 ˚C
120
-40 ˚C
IOP (uA)
100
80
60
40
20
0
0
1
2
3
4
5
6
VOP (V)
126
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 78. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 2.7
80
25 ˚C
85 ºC
70
60
-40 ˚C
IOP (uA)
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
VOP (V)
Figure 79. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V
120
-40 ˚C
25 ˚C
100
85 ˚C
IRESET (uA)
80
60
40
20
0
0
1
2
3
4
5
VRESET (V)
127
2535B–AVR–01/04
Figure 80. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 2.7V
60
25 ˚C
-40 ˚C
50
85 ˚C
IRESET (uA)
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
VRESET (V)
Pin Driver Strength
Figure 81. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
LOW POWER PORTS, VCC = 5V
70
-40 ˚C
60
25 ˚C
50
IOH (mA)
85 ˚C
40
30
20
10
0
0
1
2
3
4
5
6
VOH (V)
128
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 82. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
LOW POWER PORTS, VCC = 2.7V
25
-40 °C
IOH (mA)
20
25 °C
85 °C
15
10
5
0
0
0.5
1
1.5
2
2.5
3
VOH (V)
Figure 83. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 1.8V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
LOW POWER PORTS, VCC = 1.8V
7
-40 ˚C
25 ˚C
6
85 ˚C
IOH (mA)
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH (V)
129
2535B–AVR–01/04
Figure 84. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
LOW POWER PORTS, VCC = 5V
50
45
-40 ˚C
40
25 ˚C
IOL (mA)
35
85 ˚C
30
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
VOL (V)
Figure 85. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Low Power Ports, VCC = 2.7V
20
18
-40 ˚C
16
25 ˚C
IOL (mA)
14
85 ˚C
12
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
VOL (V)
130
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 86. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 1.8V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
LOW POWER PORTS, 1.8V
7
6
-40 ˚C
IOL (mA)
5
25 ˚C
85 ˚C
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOL (V)
Figure 87. I/O Pin Source Current vs. Output Voltage (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
90
80
-40 ˚C
70
25 ˚C
85 ˚C
IOH (mA)
60
50
40
30
20
10
0
2
3
4
5
6
VOH (V)
131
2535B–AVR–01/04
Figure 88. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
35
30
-40 ˚C
25 ˚C
25
IOH (mA)
85 ˚C
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
VOH (V)
Figure 89. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 1.8V
10
-40 ˚C
9
25 ˚C
8
85 ˚C
IOH (mA)
7
6
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH (V)
132
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 90. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
100
90
-40 ˚C
80
25 ˚C
IOL (mA)
70
85 ˚C
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
VOL (V)
Figure 91. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
40
35
-40 ˚C
30
25 ˚C
IOL (mA)
25
85 ˚C
20
15
10
5
0
0
0.5
1
1.5
2
2.5
VOL (V)
133
2535B–AVR–01/04
Figure 92. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 1.8V
14
12
-40 ˚C
IOL (mA)
10
25 ˚C
85 ˚C
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOL (V)
Figure 93. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 5V)
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
1.6
1.4
-40 ˚C
1.2
25 ˚C
IOH (mA)
1
85 ˚C
0.8
0.6
0.4
0.2
0
2
3
4
5
VOH (V)
134
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 94. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 2.7V)
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
2.5
-40 ˚C
2
IOH (mA)
25 ˚C
85 ˚C
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
VOH (V)
Figure 95. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 1.8V)
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 1.8V
2.5
-40 °C
2
IOH (mA)
25 °C
1.5
1
85 °C
0.5
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH (V)
135
2535B–AVR–01/04
Figure 96. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 5V)
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
14
-40 ˚C
12
25 ˚C
IOL (mA)
10
85 ˚C
8
6
4
2
0
0
0.5
1
1.5
2
2.5
VOL (V)
Figure 97. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 2.7V)
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
4.5
-40 ˚C
4
3.5
25 ˚C
IOL (mA)
3
85 ˚C
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
VOL (V)
136
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 98. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 1.8V)
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 1.8V
1.6
1.4
-40 ˚C
1.2
25 ˚C
IOL (mA)
1
85 ˚C
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOL (V)
Pin Thresholds and
Hysteresis
Figure 99. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1')
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
3
85 ˚C
25 ˚C
2.5
-40 ˚C
Threshold (V)
2
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
137
2535B–AVR–01/04
Figure 100. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0')
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
3
85 ˚C
25 ˚C
-40 ˚C
2.5
Threshold (V)
2
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
5
5.5
VCC (V)
Figure 101. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT HYSTERESIS vs. VCC
0.45
0.4
-40 ºC
Input Hysteresis (V)
0.35
0.3
25 ºC
0.25
0.2
85 ºC
0.15
0.1
0.05
0
1.5
2
2.5
3
3.5
4
4.5
VCC (V)
138
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 102. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIH, Reset Pin Read
as '1')
RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
3
2.5
Threshold (V)
2
-40 ˚C
1.5
25 ˚C
1
85 ˚C
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 103. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as
'0')
RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
2.5
Threshold (V)
2
1.5
85 ˚C
1
25 ˚C
0.5
-40 ˚C
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
139
2535B–AVR–01/04
Figure 104. Reset Pin as I/O - Pin Hysteresis vs. VCC
RESET PIN AS IO - PIN HYSTERESIS vs. VCC
0.7
0.6
-40 ºC
Input Hysteresis (V)
0.5
25 ºC
0.4
85 ºC
0.3
0.2
0.1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 105. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1')
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
2.5
Threshold (V)
2
1.5
-40 ˚C
1
85 ˚C
25 ˚C
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
140
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 106. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0')
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
2.5
Threshold (V)
2
1.5
1
0.5
85 ˚C
25 ˚C
-40 ˚C
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 107. Reset Input Pin Hysteresis vs. VCC
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
0.5
-40 ºC
Threshold (V)
0.4
0.3
85 ºC
0.2
25 ºC
0.1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
141
2535B–AVR–01/04
BOD Thresholds and
Analog Comparator
Offset
Figure 108. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.3V
4.5
Rising VCC
Threshold (V)
4.4
4.3
Falling VCC
4.2
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
Figure 109. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 2.7V
2.9
Rising V CC
Threshold (V)
2.8
2.7
Falling V CC
2.6
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
142
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 110. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 1.8V
1.9
Rising V CC
Threshold (V)
1.85
1.8
Falling V CC
1.75
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
Figure 111. Bandgap Voltage vs. VCC
BANDGAP VOLTAGE vs. VCC
1.06
Bandgap Voltage (V)
1.04
1.02
85ºC
25ºC
1
0.98
-40ºC
0.96
0.94
0.92
1.5
2.5
3.5
4.5
5.5
VCC (V)
143
2535B–AVR–01/04
Figure 112. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V)
ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE
VCC = 5V
0.008
85 °C
25 °C
-40 °C
Comparator Offset Voltage (V)
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Common Mode Voltage (V)
Figure 113. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC= 2.7V)
ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE
VCC = 2.7V
0.003
85 °C
Comparator Offset Voltage (V)
0.0025
25 °C
0.002
-40 °C
0.0015
0.001
0.0005
0
0
0.5
1
1.5
2
2.5
3
Common Mode Voltage (V)
144
ATtiny13
2535B–AVR–01/04
ATtiny13
Internal Oscillator Speed Figure 114. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
10.3
10.1
9.9
FRC (MHz)
9.7
9.5
5.5 V
9.3
4.5 V
9.1
2.7 V
8.9
1.8 V
8.7
8.5
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
Figure 115. Calibrated 9.6 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. VCC
11
10.5
85 ˚C
FRC (MHz)
10
25 ˚C
9.5
-40 ˚C
9
8.5
8
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
145
2535B–AVR–01/04
Figure 116. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
18
25 ˚C
16
FRC (MHz)
14
12
10
8
6
4
2
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
OSCCAL VALUE
Figure 117. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
5.1
5
F RC (MHz)
4.9
4.8
1.8 V
4.7
5.5 V
4.0 V
4.6
2.7 V
4.5
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
146
ATtiny13
2535B–AVR–01/04
ATtiny13
Figure 118. Calibrated 4.8 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. VCC
5.2
85 ˚C
FRC (MHz)
5
4.8
25 ˚C
-40 ˚C
4.6
4.4
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 119. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
10
25 ˚C
9
8
FRC (MHz)
7
6
5
4
3
2
1
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120 127
OSCCAL VALUE
147
2535B–AVR–01/04
Figure 120. 128 kHz Watchdog Oscillator Frequency vs. VCC
128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. VCC
120
-40 ˚C
FRC (kHz)
115
25 ˚C
110
85 ˚C
105
100
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 121. 128 kHz Watchdog Oscillator Frequency vs. Temperature
128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE
118
116
114
FRC (kHz)
112
110
1.8 V
108
2.7 V
4.0 V
5.5 V
106
104
102
100
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
148
ATtiny13
2535B–AVR–01/04
ATtiny13
Current Consumption of
Peripheral Units
Figure 122. Brownout Detector Current vs. VCC
BROWNOUT DETECTOR CURRENT vs. VCC
35
-40 ˚C
25 ˚C
85 ˚C
30
ICC (uA)
25
20
15
10
5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 123. ADC Current vs. VCC
ADC CURRENT vs. VCC
350
-40 ˚C
300
25 ˚C
ICC (uA)
250
85 ˚C
200
150
100
50
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
149
2535B–AVR–01/04
Figure 124. Analog Comparator Current vs. VCC
ANALOG COMPARATOR CURRENT vs. VCC
140
ICC (uA)
-40 ˚C
120
25 ˚C
100
85 ˚C
80
60
40
20
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
5
5.5
VCC (V)
Figure 125. Programming Current vs. VCC
PROGRAMMING CURRENT vs. Vcc
4
3.5
3
ICC (mA)
2.5
2
1.5
1
-40 °C
25 °C
0.5
85 °C
0
1.5
2
2.5
3
3.5
4
4.5
VCC (V)
150
ATtiny13
2535B–AVR–01/04
ATtiny13
Current Consumption in
Reset and Reset Pulse
width
Figure 126. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through
the Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP
0.14
5.5 V
0.12
5.0 V
ICC (mA)
0.1
4.5 V
0.08
4.0 V
0.06
3.3 V
2.7 V
0.04
1.8 V
0.02
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
Figure 127. Reset Supply Current vs. VCC (1 - 24 MHz, Excluding Current through the
Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
1 - 24 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP
ICC (mA)
3.5
3
5.5V
2.5
5.0V
2
4.5V
1.5
4.0V
1
3.3V
0.5
2.7V
1.8V
0
0
2
4
6
8
10
12
14
16
18
20
22
24
Frequency (MHz)
151
2535B–AVR–01/04
Figure 128. Reset Pulse Width vs. VCC
RESET PULSE WIDTH vs. V
CC
2500
Pulsewidth (ns)
2000
1500
1000
500
85 ºC
25 ºC
-40 ºC
0
1.8
2.1
2.5
2.7
3
3.3
3.5
4
4.5
5
5.5
6
VCC (V)
152
ATtiny13
2535B–AVR–01/04
ATtiny13
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
SREG
I
T
H
S
V
N
Z
C
page 6
0x3E
Reserved
–
–
–
–
–
–
–
–
0x3D
SPL
SP[7:0]
0x3C
Reserved
–
0x3B
GIMSK
–
INT0
PCIE
–
–
–
–
–
page 53
0x3A
GIFR
–
INTF0
PCIF
–
–
–
–
–
page 53
0x39
TIMSK0
–
–
–
–
OCIE0B
OCIE0A
TOIE0
–
page 70
0x38
TIFR0
–
–
–
–
OCF0B
OCF0A
TOV0
–
page 71
0x37
SPMCSR
–
–
–
CTPB
RFLB
PGWRT
PGERS
SELFPRGEN
page 97
–
PUD
SE
SM1
page 49
0x36
OCR0A
0x35
MCUCR
page 8
Timer/Counter – Output Compare Register A
page 70
SM0
–
ISC01
ISC00
0x34
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
page 33
0x33
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
page 66
0x32
TCNT0
Timer/Counter (8-bit)
page 70
0x31
OSCCAL
Oscillator Calibration Register
page 22
0x30
Reserved
–
COM0A1
COM0A0
COM0B1
–
COM0B0
–
0x2F
TCCR0A
0x2E
DWDR
DWDR[7:0]
0x2D
Reserved
–
0x2C
Reserved
–
0x2B
Reserved
–
0x2A
Reserved
–
0x29
OCR0B
Timer/Counter – Output Compare Register B
0x28
GTCCR
TSM
–
–
–
CLKPCE
–
–
–
Reserved
CLKPR
0x25
Reserved
–
0x24
Reserved
–
0x23
Reserved
–
0x22
Reserved
0x21
WDTCR
0x20
Reserved
0x1F
Reserved
EEARL
0x1D
EEDR
0x1C
EECR
WGM00
page 69
page 94
page 70
–
–
–
PSR10
page 73
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 24
WDE
WDP2
WDP1
WDP0
page 37
–
0x27
0x26
0x1E
WGM01
–
WDTIF
WDTIE
WDP3
WDCE
–
–
–
–
EEPROM Address Register
page 14
EEPROM Data Register
–
–
EEPM1
EEPM0
page 14
EERIE
EEMWE
EEWE
EERE
page 15
0x1B
Reserved
–
0x1A
Reserved
–
0x19
Reserved
0x18
PORTB
–
–
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
page 51
0x17
DDRB
–
–
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
page 51
0x16
PINB
–
–
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 51
0x15
PCMSK
–
–
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
page 54
0x14
DIDR0
–
–
ADC0D
ADC2D
ADC3D
ADC1D
EIN1D
AIN0D
page 76, page 91
0x13
Reserved
–
0x12
Reserved
–
0x11
Reserved
–
0x10
Reserved
–
0x0F
Reserved
–
0x0E
Reserved
–
0x0D
Reserved
–
0x0C
Reserved
–
0x0B
Reserved
–
0x0A
Reserved
–
0x09
Reserved
0x08
ACSR
ACD
ACBG
ACO
ACI
ACIE
–
ACIS1
ACIS0
page 74
0x07
ADMUX
–
REFS0
ADLAR
–
–
–
MUX1
MUX0
page 88
0x06
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
page 89
0x05
ADCH
ADC Data Register High Byte
0x04
ADCL
ADC Data Register Low Byte
0x03
ADCSRB
0x02
Reserved
–
0x01
Reserved
–
0x00
Reserved
–
–
–
–
ACME
–
–
–
page 90
page 90
ADTS2
ADTS1
ADTS0
page 91
153
2535B–AVR–01/04
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
154
ATtiny13
2535B–AVR–01/04
ATtiny13
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
Relative Jump
PC ← PC + k + 1
None
2
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC ← Z
None
3
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
None
BRANCH INSTRUCTIONS
RJMP
k
IJMP
RCALL
k
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
155
2535B–AVR–01/04
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I← 0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
Set Half Carry Flag in SREG
H←1
H
1
CLH
Clear Half Carry Flag in SREG
H←0
H
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
Rd ← Rr
None
1
MOVW
Rd, Rr
Copy Register Word
Rd+1:Rd ← Rr+1:Rr
None
1
LDI
Rd, K
Load Immediate
Rd ← K
None
1
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(z) ← R1:R0
None
LPM
SPM
IN
Rd, P
In Port
Rd ← P
None
OUT
P, Rr
Out Port
P ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
None
1
1
MCU CONTROL INSTRUCTIONS
NOP
No Operation
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR/Timer)
None
1
BREAK
Break
For On-chip Debug Only
None
N/A
156
ATtiny13
2535B–AVR–01/04
ATtiny13
Ordering Information
Power Supply
12(3)
24(3)
Notes:
Ordering Code
Package(1)
1.8 - 5.5
ATtiny13-12PI
ATtiny13-12PJ(2)
ATtiny13-12SI
ATtiny13-12SJ(2)
ATtiny13-12SSI
ATtiny13-12SSJ(2)
8P3
8P3
8S2
8S2
S8S1
S8S1
Industrial
(-40°C to 85°C)
2.7 - 5.5
ATtiny13-24PI
ATtiny13-24PJ(2)
ATtiny13-24SI
ATtiny13-24SJ(2)
ATtiny13-24SSI
ATtiny13-24SSJ(2)
8P3
8P3
8S2
8S2
S8S1
S8S1
Industrial
(-40°C to 85°C)
Speed (MHz)
Operation Range
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative.
3. For Speed vs. VCC, see “Maximum Speed vs. VCC” on page 116.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
S8S1
8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
157
2535B–AVR–01/04
Packaging Information
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
MIN
NOM
A
b2
b3
b
4 PLCS
Side View
L
0.210
NOTE
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
0.150
2
e
3
3
0.100 BSC
eA
L
Notes:
MAX
0.300 BSC
0.115
0.130
4
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
158
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
ATtiny13
2535B–AVR–01/04
ATtiny13
8S2
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
NOM
MAX
NOTE
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
∅
0˚
e
Notes: 1.
2.
3.
4.
5.
MIN
A
2, 3
8˚
1.27 BSC
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
C
159
2535B–AVR–01/04
S8S1
1
E1
E
N
Top View
e
b
A
A1
D
Side View
C
L
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
E
5.79
6.20
E1
3.81
3.99
A
1.35
1.75
A1
0.1
0.25
D
4.80
4.98
C
0.17
0.25
b
0.31
0.51
L
0.4
1.27
e
NOTE
1.27 BSC
0o
8o
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.
7/28/03
R
160
2325 Orchard Parkway
San Jose, CA 95131
TITLE
S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small
Outline (JEDEC SOIC)
DRAWING NO.
S8S1
REV.
A
ATtiny13
2535B–AVR–01/04
ATtiny13
Errata
The revision letter in this section refers to the revision of the ATtiny13 device.
ATtiny13 Rev. C
There are no known errata for this revision.
ATtiny13 Rev. B
•
•
•
•
•
Wrong values read after Erase Only operation
High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail
Device may lock for further programming
debugWIRE communication not blocked by lock-bits
Watchdog Timer Interrupt disabled
1. Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase
Only operation may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write
operation with 0xFF as data in order to erase a location. In any case, the Write Only
operation can be used as intended. Thus no special considerations are needed as
long as the erased location is not read before it is programmed.
2. High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may
fail
Writing to any of these locations and bits may in some occasions fail.
Problem Fix/Workaround
After a writing has been initiated, always observe the RDY/BSY signal. If the writing
should fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in
revision C.
3. Device may lock for further programming
Special combinations of fuse bits will lock the device for further programming effectively turning it into an OTP device. The following combinations of settings/fuse bits
will cause this effect:
–
128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled
RSTDISBL = 0.
–
9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled
RSTDISBL = 0.
–
4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled
RSTDISBL = 0.
Problem fix/ Workaround
Avoid the above fuse combinations. Selecting longer start-up time will eliminate the
problem.
4. debugWIRE communication not blocked by lock-bits
When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program
memory and EEPROM data memory can be read even if the lock-bits are set to
block further reading of the device.
161
2535B–AVR–01/04
Problem fix/ Workaround
Do not ship products with on-chip debug of the tiny13 enabled.
5. Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the
watchdog will be disabled, and the interrupt flag will automatically be cleared. This is
only applicable in interrupt only mode. If the Watchdog is configured to reset the
device in the watchdog time-out following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before a
new watchdog timeout occurs. This is done by selecting a long enough time-out
period.
ATtiny13 Rev. A
162
Revision A has not been sampled.
ATtiny13
2535B–AVR–01/04
ATtiny13
Datasheet Change
Log for ATtiny13
Changes from Rev.
2535A-06/03 to Rev.
2535B-01/04
Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Updated Figure 2 on page 2.
Updated Table 12 on page 30, Table 17 on page 39, Table 37 on page 89
and Table 57 on page 116.
Updated “Calibrated Internal RC Oscillator” on page 22.
Updated the whole “Watchdog Timer” on page 35.
Updated Figure 53 on page 103 and Figure 56 on page 108.
Updated registers “MCU Control Register – MCUCR” on page 49,
“Timer/Counter Control Register B – TCCR0B” on page 69 and “Digital
Input Disable Register 0 – DIDR0” on page 76.
Updated Absolute Maximum Ratings and DC Characteristics in “Electrical
Characteristics” on page 115.
Added “Maximum Speed vs. VCC” on page 116
Updated “ADC Characteristics – Preliminary Data” on page 118.
Updated “ATtiny13 Typical Characteristics – Preliminary Data” on page
119.
Updated “Ordering Information” on page 157.
Updated “Packaging Information” on page 158.
Updated “Errata” on page 161.
Changed instances of EEAR to EEARL.
163
2535B–AVR–01/04
164
ATtiny13
2535B–AVR–01/04
ATtiny13
Table of Contents
Features................................................................................................ 1
Pin Configurations............................................................................... 1
Overview ............................................................................................... 2
Block Diagram ...................................................................................................... 2
Pin Descriptions.................................................................................................... 3
About Code Examples......................................................................... 3
AVR CPU Core ..................................................................................... 4
Introduction ...........................................................................................................
Architectural Overview..........................................................................................
ALU – Arithmetic Logic Unit..................................................................................
Status Register .....................................................................................................
General Purpose Register File .............................................................................
Stack Pointer ........................................................................................................
Instruction Execution Timing.................................................................................
Reset and Interrupt Handling................................................................................
4
4
5
6
7
8
9
9
AVR ATtiny13 Memories ................................................................... 12
In-System Re-programmable Flash Program Memory .......................................
SRAM Data Memory...........................................................................................
EEPROM Data Memory......................................................................................
I/O Memory .........................................................................................................
12
13
14
19
System Clock and Clock Options .................................................... 20
Clock Systems and their Distribution ..................................................................
Clock Sources.....................................................................................................
Default Clock Source ..........................................................................................
Calibrated Internal RC Oscillator ........................................................................
External Clock.....................................................................................................
128 kHz Internal Oscillator..................................................................................
System Clock Prescaler......................................................................................
20
21
21
22
23
24
24
Power Management and Sleep Modes............................................. 26
Idle Mode ............................................................................................................
ADC Noise Reduction Mode...............................................................................
Power-down Mode..............................................................................................
Minimizing Power Consumption .........................................................................
27
27
27
28
System Control and Reset ................................................................ 29
Internal Voltage Reference ................................................................................. 34
Watchdog Timer ................................................................................................. 35
i
2535B–AVR–01/04
Interrupts ............................................................................................ 40
Interrupt Vectors in ATtiny13 .............................................................................. 40
I/O Ports.............................................................................................. 41
Introduction .........................................................................................................
Ports as General Digital I/O ................................................................................
Alternate Port Functions .....................................................................................
Register Description for I/O-Ports.......................................................................
41
42
46
51
External Interrupts ............................................................................. 52
8-bit Timer/Counter0 with PWM........................................................ 55
Overview.............................................................................................................
Timer/Counter Clock Sources.............................................................................
Counter Unit........................................................................................................
Output Compare Unit..........................................................................................
Compare Match Output Unit ...............................................................................
Modes of Operation ............................................................................................
Timer/Counter Timing Diagrams.........................................................................
8-bit Timer/Counter Register Description ...........................................................
55
56
56
57
59
60
64
66
Timer/Counter Prescaler ................................................................... 72
Analog Comparator ........................................................................... 74
Analog Comparator Multiplexed Input ................................................................ 76
Analog to Digital Converter .............................................................. 77
Features..............................................................................................................
Operation ............................................................................................................
Starting a Conversion .........................................................................................
Prescaling and Conversion Timing .....................................................................
Changing Channel or Reference Selection ........................................................
ADC Noise Canceler...........................................................................................
ADC Conversion Result......................................................................................
77
78
79
80
83
84
88
debugWIRE On-chip Debug System ................................................ 93
Features..............................................................................................................
Overview.............................................................................................................
Physical Interface ...............................................................................................
Software Break Points ........................................................................................
Limitations of debugWIRE ..................................................................................
debugWIRE Related Register in I/O Memory .....................................................
93
93
93
94
94
94
Self-Programming the Flash ............................................................. 95
Addressing the Flash During Self-Programming ................................................ 96
ii
ATtiny13
2535B–AVR–01/04
ATtiny13
Memory Programming..................................................................... 100
Program And Data Memory Lock Bits ..............................................................
Fuse Bytes........................................................................................................
Signature Bytes ................................................................................................
Calibration Byte ................................................................................................
Page Size .........................................................................................................
Serial Downloading...........................................................................................
High-voltage Serial Programming.....................................................................
High-voltage Serial Programming Algorithm.....................................................
High-voltage Serial Programming Characteristics ............................................
100
101
102
102
102
103
107
109
114
Electrical Characteristics................................................................ 115
Absolute Maximum Ratings*.............................................................................
DC Characteristics............................................................................................
External Clock Drive Waveforms ......................................................................
External Clock Drive .........................................................................................
Maximum Speed vs. VCC ..................................................................................
ADC Characteristics – Preliminary Data...........................................................
115
115
116
116
116
118
ATtiny13 Typical Characteristics – Preliminary Data ................... 119
Active Supply Current .......................................................................................
Idle Supply Current ...........................................................................................
Power-Down Supply Current ............................................................................
Pin Pull-up ........................................................................................................
Pin Driver Strength ...........................................................................................
Pin Thresholds and Hysteresis .........................................................................
BOD Thresholds and Analog Comparator Offset .............................................
Internal Oscillator Speed ..................................................................................
Current Consumption of Peripheral Units .........................................................
Current Consumption in Reset and Reset Pulse width.....................................
119
122
125
126
128
137
142
145
149
151
Register Summary ........................................................................... 153
Instruction Set Summary ................................................................ 155
Ordering Information ....................................................................... 157
Packaging Information .................................................................... 158
8P3 ................................................................................................................... 158
8S2 ................................................................................................................... 159
S8S1 ................................................................................................................. 160
Errata ................................................................................................ 161
ATtiny13 Rev. C................................................................................................ 161
ATtiny13 Rev. B................................................................................................ 161
ATtiny13 Rev. A................................................................................................ 162
iii
2535B–AVR–01/04
Datasheet Change Log for ATtiny13 .............................................. 163
Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04 ................................... 163
Table of Contents ................................................................................. i
iv
ATtiny13
2535B–AVR–01/04
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2535B–AVR–01/04