CXD3500R Timing Generator for LCD Panels Description The CXD3500R is a timing signal generator for driving the LCD panels of Sony data projectors. This chip has a built-in serial interface circuit which supports various SXGA (skip scan display), XGA, SVGA and VGA signals, and (double speed) NTSC and PAL signals through external control from a microcomputer, etc. Direct drive of LCD panels is possible using 5V drive. 64 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C, Vss = 0V) • Supply voltage VDD Vss – 0.5 to +7.0 V • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage VO Vss – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Features • Generates the drive pulses for the LCD panels of Sony high-temperature polycrystalline silicon TFT data projectors. • Supports various SXGA, XGA, SVGA and VGA signals. • Programmable output signals allow the optimal pulse output settings for each panel. • Programmable skip scan display allows skip scan display of various signals (SXGA → XGA, XGA → SVGA, Macintosh16 → SVGA, etc.) • Supports NTSC and PAL signals with line doublespeed display using a built-in double-speed controller. (clock frequency: 36MHz or less) (Line memory: µPD485505: NEC) • Allows control of sample-and-hold position of CXA2112R sample-and-hold driver. • Supports up/down inversion and/or right/left inversion. • Supports line inversion and field inversion. • AC drive of LCD panels during no signal Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +75 V °C Applications LCD projectors, etc. Structure Silicon gate CMOS IC Note) "Macintosh" is a registered trademark of Apple Computer Inc. "PC98" is a registered trademark of NEC Corp. "VGA" is a registered trademark of IBM Corp. Other company names and product names, etc. contained in these materials are trademarks or registered trademarks of the respective companies. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99112-PS CXD3500R XCLR CKI2 CKLIM CKI1 CKI3 Block Diagram 19 3 4 64 17 SYSTEM CLEAR SYNC DETECTOR HD 31 1 HSYNC 2 VSYNC IRACT 52 50 XVS RSTR 54 PLL COUNTER & DECODER RCK 57 AUX. PLL COUNTER & DECODER 51 XHS 53 ORACT RSTW 58 MASTER CLOCK WCK 59 24 HDN 63 56 H-POSITION COUNTER & DECODER HST 27 HCK1 28 VDD PULSE ELIMINATOR 8 HCK2 29 23 BLK 30 40 ENB1 32 55 PCG 36 VSS V-POSITION COUNTER & DECODER ENB2 38 H-TIMING PULSE GENERATOR CLP 39 PRG 42 RGTCNT 10 FRPCNT 11 V-TIMING PULSE GENERATOR SCTR 60 SCLK 61 5 VD 6 FLD 33 VCK 34 VST 43 FRP SERIAL DATA I/F 44 XFRP SDAT 62 7 INV SHP2B SHP2A SHP1B SHP1A DWN XRGT RGT MODE1 MODE2 MODE3 20 21 22 25 26 37 45 46 47 48 49 9 12 13 14 15 16 18 35 41 TEST –2– CXD3500R Pin Description Pin No. Symbol I/O Description Input pin for open status 1 HSYNC I Horizontal sync signal input — 2 VSYNC I Vertical sync signal input — 3 CKI2 Clock 2 input (Small signal: Vth = VDD/2, min. Vp-p = 0.5V) — 4 CKLIM I Clock input selector (CKI1 selected when open.) H 5 VD O VD pulse output — 6 FLD I/O FLD pulse I/O — 7 TEST0 — Test (Not connected.) — 8 VSS0 — GND — 9 TEST1 — Test (Not connected.) — 10 RGTCNT I Right/left inversion external control — 11 FRPCNT I FRP pulse inversion external control H 12 TEST2 — Test (Not connected.) — 13 TEST3 — Test (Not connected.) — 14 TEST4 — Test (Not connected.) — 15 TEST5 — Test (Not connected.) — 16 TEST6 — Test (Connect to GND.) — 17 CKI3 I Clock 3 input (for LAP) — 18 TEST7 — Test (Not connected.) H 19 XCLR I System clear (L: set to SVGA 60Hz) H 20 MODE3 O Parallel Out 3 output (Panel mode switching 3 output) — 21 MODE2 O Parallel Out 2 output (Panel mode switching 2 output) — 22 MODE1 O Parallel Out 1 output (Panel mode switching 1 output) — 23 VSS1 — GND — 24 VDD0 — VDD — 25 RGT O Right/left inversion discrimination signal output (H: Normal, L: Reverse) — 26 XRGT O Right/left inversion discrimination signal output (reverse polarity of RGT) — 27 HST O Horizontal display start pulse output — 28 HCK1 O Horizontal display clock pulse output — 29 HCK2 O Horizontal display clock pulse output — 30 BLK O BLK pulse output — 31 HD O HD pulse output — 32 ENB1 O ENB1 pulse output — 33 VCK O Vertical display clock pulse output — I/O ∗ H: Pull up –3– CXD3500R Pin No. Symbol I/O Description Input pin for open status 34 VST O Vertical display start pulse output — 35 TEST8 — Test (Not connected.) — 36 PCG O Precharge timing pulse output — 37 DWN O Up/down inversion discrimination signal output (H: Down, L: Up) — 38 ENB2 O ENB2 pulse output — 39 CLP O Pedestal clamp pulse output for CXA2112R — 40 VSS2 — GND — 41 TEST9 — Test (Not connected.) — 42 PRG O Precharge signal pulse output — 43 FRP O AC drive inversion timing output — 44 XFRP O AC drive inversion timing output (reverse polarity of FRP) — 45 SHP1A O External sample-and-hold driver control signal (for CXA2112R) — 46 SHP1B O External sample-and-hold driver control signal (for CXA2112R) — 47 SHP2A O External sample-and-hold driver control signal (for CXA2112R) — 48 SHP2B O External sample-and-hold driver control signal (for CXA2112R) — 49 INV O External sample-and-hold driver control signal (for CXA2112R) — 50 XVS O Vertical auxiliary pulse output — 51 XHS O Horizontal auxiliary pulse output — 52 IRACT O LAP control pulse output — 53 ORACT O LAP control pulse output — 54 RSTR O Reset read output (for high-speed line buffer) — 55 VSS3 — GND — 56 VDD1 — VDD — 57 RCK O Read clock output (for high-speed line buffer) — 58 RSTW O Reset write output (for high-speed line buffer) — 59 WCK O Write clock output (for high-speed line buffer) — 60 SCTR I Chip select input (serial transfer block) — 61 SCLK I Serial clock input (serial transfer block) — 62 SDAT I Serial data input (serial transfer block) — 63 HDN O Phase comparator pulse output — 64 CKI1 I Clock 1 input (TTL) — ∗ H: Pull up –4– CXD3500R Electrical Characteristics (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C) 1. DC characteristics Item Symbol Conditions Typ. Max. 5.0 5.5 V VDD V Supply voltage VDD 4.5 Input, output voltages VI, VO VSS VIH Input voltage 1 Logical threshold value Input voltage 2 VIL 2.2 TTL input 0.8 Small amplitude input 0.3VDD VIL VIN 50MHz sine wave 0.5 Feedback resistor RFB VIN = Vss or VDD 250k VIH VIL VT– Output voltage 2 Output voltage 3 1M 2.5M 0.3VDD 0.8 VOH IOH = –2mA VOL IOL = 4mA VOH IOH = –6mA VOL IOL = 4mA VOH IOH = –8mA VOL IOL = 8mA VDD – 0.8 0.4 VDD – 0.8 0.4 VDD – 0.8 0.4 ∗5 –10 IIL ∗7 –40 II ∗9 –40 40 IOZ ∗10 –40 40 Current consumption IDD ∗11 Output leak current ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 ∗9 ∗10 ∗11 V ∗1 V HSYNC, VSYNC, SCTR, SCLK, SDAT V ∗2 V ∗3 V ∗4 0.4 II Input leak current Ω 2.2 TTL Schmitt trigger input VT+ – VT– Output voltage 1 CKI2 Vp-p 0.7VDD CMOS input VT+ Input voltage 4 CKI1 V 0.7VDD Input amplitude Input voltage 3 V VDD/2 Vth VIH Unit Applicable pins Min. ∗6 10 –100 58 –240 ∗8 µA FLD µA SHP1A, SHP2A mA At a 30pF load CKLIM, RGTCNT, FRPCNT, CKI3, TEST7, XCLR MODE1, MODE2, MODE3, RGT, XRGT, DWN, SHP1B, SHP2B, INV VD, BLK, HD, ENB1, ENB2, VCK, VST, PCG, CLP, PRG, FRP, XFRP, XVS, XHS, IRACT, ORACT, HDN HST, HCK1, HCK2, RSTR, RCK, RSTW, WCK Normal input pins (VIN = Vss or VDD) HSYNC, VSYNC, RGTCNT, CKI3, SCTR, SCLK, SDAT, CKI1 Pins with pull-up resistors (VIN = Vss) CKLIM, FRPCNT, TEST7, XCLR Bidirectional pins (VIN = Vss or VDD) Tri-state (at high impedance, VIN = Vss or VDD) VDD = 5.0V, 55MHz input (actual measurement) –5– CXD3500R 2. AC characteristics (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C) Item Symbol Clock input cycle tr tf ∆t tH/(tH + tL) tL/(tH + tL) Output rise time Output fall time Cross-point time difference HCK1 Duty HCK2 Duty Applicable pins Min. CKI1 18.2 CKI2 18.2 Typ. Max. Conditions Unit All outputs 20 All outputs 20 HCK1, 2 –10 10 HCK1 48 52 HCK2 48 52 ns CL = 30pF % Note) The minimum value for the clock input cycle (CKI1) when using the built-in double-speed controller is 27ns. (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C) 3. Serial transfer AC characteristics Item Symbol Min. ts0 ts1 SCTR setup time with respect to rise of SCLK 4Tns SDAT setup time with respect to rise of SCLK 2Tns th0 th1 tW1L tW1H tW2 tW3 SCTR hold time with respect to rise of SCLK 4Tns SDAT hold time with respect to rise of SCLK 2Tns SCLK L level pulse width 2Tns SCLK H level pulse width 2Tns Typ. Max. 5Tns 5Tns T: Input clock cycle Note) Consider the frequency at free running (no signal). When the above characteristic specification is not satisfied at free running, IC operation including serial transfer is not guaranteed. 4. External clock input AC characteristics Symbol ts0 th0 ts0 th0 tWL/tWH ts0 th0 ts0 th0 tWL/tWH (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C) Item Conditions HSYNC setup time with respect to rise of CKI1 HSYNC hold time with respect to rise of CKI1 HSYNC setup time with respect to rise of CKI2 HSYNC hold time with respect to rise of CKI2 Min. SLCK∗1: H CKPOL∗2: H SLRS∗3: L 7 2 9 6 HSYNC setup time with respect to rise of CKI1 0 HSYNC setup time with respect to rise of CKI2 Max. Unit 4 CKI1,2 L/H level pulse width HSYNC hold time with respect to rise of CKI1 Typ. SLCK∗1: L CKPOL∗2: H T/2 ns 6 0 HSYNC hold time with respect to rise of CKI2 8 CKI1,2 L/H level pulse width 40 50 60 % ∗1, 2, 3: Serial data Add. 0A T: Input clock cycle Note) During external clock input, set serial data HR to L. The pulse synchronized to the horizontal sync signal is generated by detecting the front edge of the horizontal sync signal and then resetting the internal PLL counter. –6– CXD3500R 5. Timing definitions AC characteristics VDD 100% CKI1/2 0V tpr Output VDD 90% 10% 0V tr tf 90% tpf Output VDD 10% 0V VDD HCK1 50% 50% 0V VDD 50% HCK2 50% 0V ∆t ∆t 50% HCK1 50% 50% tH tL Note) HCK2 is the reverse phase of HCK1. Serial transfer AC characteristics th0 ts0 SCTR 50% 50% tw1L SCLK tw1H tw2 50% 50% ts1 SDAT tw3 50% th1 D15 ts1 th1 D8 D14 D9 D7 D0 D15 Note) See "Serial transfer timing" on page 11 for the timing relationship between D15 to D0 and each pulse. External clock input AC characteristics th0 HSYNC (negative polarity) ts0 50% 50% twL CKI1, 2 th0 ts0 twH 50% 50% –7– 50% 50% CXD3500R Input Signal Protocol 1. Horizontal sync signal a) A standard signal (HSYNC) should be input for each mode. However, since the CXD3500R requires a double-speed signal as input during NTSC/PAL double-speed display when not using the built-in double-speed controller, the input specifications at that time are similar to those for normal data type sync signals, and there should not be a 1/2 offset with respect to the vertical sync signal. b) The input sync signal polarity is not fixed, and is set by the serial data (HPOL). 2. Vertical sync signal a) A sync-separated, normal-speed VSYNC should be input as the vertical sync signal. b) The input sync signal polarity is not fixed, and is set by the serial data (VPOL). c) The phase relationship between HSYNC and VSYNC is specified as follows for the CXD3500R. (1) XGA, Macintosh16, SVGA, VGA, PC-98 HSYNC VSYNC Sync signal phase reference (2) Double-speed NTSC Double-speed HSYNC VSYNC Sync signal phase reference (3) Double-speed PAL Double-speed HSYNC VSYNC Sync signal phase reference (4) NTSC Sync signal phase reference VSYNC ODD FIELD HSYNC EVEN FIELD H/2 –8– CXD3500R (5) PAL Sync signal phase reference VSYNC ODD FIELD HSYNC EVEN FIELD H/2 Notes) (2) and (3) show the timing when supporting input of double-speed signals. (4) and (5) show the timing when using the built-in double-speed controller (CXD3500R) and a line memory (µPD485505: NEC) –9– CXD3500R Description of Operation Sync signal input The HSYNC and VSYNC input pins support separate SYNC only. When using a composite SYNC input, perform sync separation using a separate sync separation IC, etc. Clock input (1) CKI1 and 2 pins CKI1 and 2 are the clock input pins from an external PLL IC. CKI1 is TTL level input, and CKI2 is small amplitude clock input. Internal operation is performed at 1/2 clock, so the CXD3500R has a built-in frequency divider which halves the input master clock, and can select this halved clock or a 1/2 clock input from an external source by the serial interface setting. However, the input clock should be 55MHz or less, so when using a master clock of more than 55MHz, input the 1/2 clock. The 1/N frequency divider output for the PLL IC is output from the HDN pin. The HDN polarity at this time is set by serial data HDNPOL. (2) CKI3 pin CKI3 is the clock input pin when using a scan converter that operates with the input sync signals and an asynchronous clock in the system. Since two types of clock are input in this case, the circuits that basically operate with the respective clocks of CKI1 and CKI2 are asynchronous. The input clock should be 55MHz or less. For details, see the explanation of pulse setting for the scan converter in this data sheet (starting on page 34). AC driving of LCD panels for no signal The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. However, master clock CKI1 or CKI2 must be input even during free running. Note that the recommended PLL IC CXA3106(A)Q does not output the clock when there is no HSYNC input. Horizontal direction pulse The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is dependent on the PLL free-running frequency. Vertical direction pulse The number of lines is counted by an internal counter and the vertical direction pulses (VST, FRP) are output at a specified cycle. For the CXD3500R, no signal (free running) status is judged if there is no VSYNC input for longer than the following periods (free running detection timing). PLSSL2, 1, 0 V cycle for no signal Free running detection L L L or L L H 701H 700H L H L to H L L 1001H 1000H H L H to H H H 1301H 1300H – 10 – CXD3500R XCLR pin The CXD3500R should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. At this time, the serial interface circuit is reset to the initial status (preset status). See page 38 for the preset settings. Serial transfer operation 1. Control method The CXD3500R operation timing is controlled by serial data. The control data is comprised of an 8-bit address and 8-bit data, and the individual data is loaded at the rise of SCLK. This loading operation starts from the fall of SCTR and is completed at the next rise of SCTR. Serial transfer timing SCTR SCLK SDAT D15 D14 D13 D12 D11 D10 D9 D8 Address D7 D6 D5 D4 Data – 11 – D3 D2 D1 D0 CXD3500R 2. Control data When using the CXD3500R, set the control data corresponding to each LCD panel and video signal according to the formats in the table below. Address Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 PLLP11 PLLP10 PLLP9 PLLP8 PLLP7 PLLP6 PLLP5 PLLP4 0 0 0 0 0 0 0 1 PLLP3 PLLP2 PLLP1 PLLP0 HP11 HP10 HP9 HP8 0 0 0 0 0 0 1 0 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 0 0 0 0 0 0 1 1 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 0 0 0 0 0 1 0 0 HSTW1 HSTW0 HSTP5 HSTP4 HSTP3 HSTP2 HSTP1 HSTP0 0 0 0 0 0 1 0 1 PCGU2 PCGU1 PCGU0 PCGD4 PCGD3 PCGD2 PCGD1 PCGD0 0 0 0 0 0 1 1 0 — — — 0 0 0 0 0 1 1 1 set 0 PCG FRP1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 VSTPOL HCKPOL VPOL 0 0 0 0 1 0 1 0 SLCNT SLFLD 0 0 0 0 1 0 1 1 BLKON BLKPOL FMBK 0 0 0 0 1 1 0 0 MBKZ3 MBKZ2 MBKZ1 MBKZ0 MBKB3 MBKB2 MBKB1 MBKB0 0 0 0 0 1 1 0 1 VGAV 0 0 0 0 1 1 1 0 XGBK 0 0 0 0 1 1 1 1 — — 0 0 0 1 0 0 0 0 SLLAP LPCK 0 0 0 1 0 0 0 1 IRD11 IRD10 IRD9 IRD8 IRD7 IRD6 IRD5 IRD4 0 0 0 1 0 0 1 0 IRD3 IRD2 IRD1 IRD0 IRU11 IRU10 IRU9 IRU8 0 0 0 1 0 0 1 1 IRU7 IRU6 IRU5 IRU4 IRU3 IRU2 IRU1 IRU0 0 0 0 1 0 1 0 0 VRSP3 VRSP2 VRSP1 VRSP0 ORP11 ORP10 ORP9 ORP8 0 0 0 1 0 1 0 1 ORP7 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 VSTFX HCKFX HCKM HR SLRS DWN PRGD4 PRGD3 PRGD2 PRGD1 PRGD0 FRP0 FRPP3 FRPP2 FRPP1 FRPP0 INV SHP3 SHP1 SHP0 HPOL HDNPOL CLPPOL CLPW CLPP CKPOL SLCK PLSSL2 PLSSL1 PLSSL0 MBKA4 MBKA3 MBKA2 MBKA1 MBKA0 DSP RGT HDON HAXON VAXON — SHP2 — PO/MODE3 PO/MODE2 PO/MODE1 set 0 set 0 set 0 SPON — — set 0 set 0 SLCKL ORRS4 ORRS3 ORRS2 ORRS1 ORRS0 ORP5 ORP4 ORP3 ORP2 ORP1 ORP0 ORD11 ORD10 ORD9 ORD8 ORD7 ORD6 ORD5 ORD4 1 ORD3 ORD2 ORD1 ORD0 ORU11 ORU10 ORU9 ORU8 0 0 ORU7 ORU6 ORU5 ORU4 ORU3 ORU2 ORU1 ORU0 0 0 1 HAXD11 HAXD10 HAXD9 HAXD8 HAXD7 HAXD6 HAXD5 HAXD4 1 0 1 0 HAXD3 HAXD2 HAXD1 HAXD0 HAXU11 HAXU10 HAXU9 HAXU8 1 1 0 1 1 HAXU7 HAXU6 HAXU5 HAXU4 HAXU3 HAXU2 HAXU1 HAXU0 0 1 1 1 0 0 VAXD11 VAXD10 VAXD9 VAXD8 VAXD7 VAXD6 VAXD5 VAXD4 0 0 1 1 1 0 1 VAXD3 VAXD2 VAXD1 VAXD0 VAXU11 VAXU10 VAXU9 VAXU8 0 0 1 1 1 1 0 VAXU7 VAXU6 VAXU5 VAXU4 VAXU3 VAXU2 VAXU1 VAXU0 ORP6 — or : Setting invalid. Note) PLLP0, HP0, VP0, HSTW0, HSTP0, PCGU0, PCGD0, PRGD0, FRPP0, SHP0, MBKA0, MBKB0, MBKZ0, IRD0, IRU0, ORRS0, ORP0, ORD0, ORU0, HAXD0, HAXU0, VAXD0, VAXU0: LSB. Shaded bits (PLLP0, IRU0, ORPU, ORU0 and HAXU0) are indicated for reference, and actual data setting to these bits is invalid. – 12 – CXD3500R Each control data is described in detail below. The following descriptions define the width of one dot clock as "clk". PLLP11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 These bits set the frequency division ratio (master clock) of the internal 1/N frequency divider for the PLL. The data is 12 bits and the frequency division ratio can be set up to 4096. However, the internal logic circuits of this TG operate at 1/2 clock, so the PLLP0 setting is invalid. When N is an odd number, use an external frequency divider. The actual frequency division ratio should be set as follows. Number of clk for the horizontal period – 2 = Actual number of dots set Examples of settings for major modes are shown below. Note) When using an external frequency divider (serial data HR is L), these settings are not necessary. (They can also be set to all L.) 1) Macintosh16 (832 × 624) PLLP setting value = 1152 (horizontal period) – 2 → 1150 (LHLLLHHHHHHL: LSB) PLLP 11 10 9 8 7 6 5 4 3 2 1 0 Setting data L H L L L H H H H H H L 2) SVGA (800 × 600) PLLP setting value = 1056 (horizontal period) – 2 → 1054 (LHLLLLLHHHHL: LSB) PLLP 11 10 9 8 7 6 5 4 3 2 1 0 Setting data L H L L L L L L H H H L 3) VGA (640 × 480) PLLP setting value = 800 (horizontal period) – 2 → 798 (LLHHLLLHHHHL: LSB) PLLP 11 10 9 8 7 6 5 4 3 2 1 0 Setting data L L H H L L L H H H H L 4) PC98 (640 × 400) PLLP setting value = 848 (horizontal period) – 2 → 11 10 9 8 7 6 5 4 3 2 1 0 Setting data L L H H L H L L H H H L → 1558 (LHHLLLLHLHHL: LSB) PLLP 11 10 9 8 7 6 5 4 3 2 1 0 Setting data L H H L L L L H L H H L 6) PAL double speed (762 × 572) PLLP setting value = 1880 (horizontal period) – 2 ∗ VGA60 846 (LLHHLHLLHHHL: LSB) PLLP 5) NTSC double speed (640 × 480) PLLP setting value = 1560 (horizontal period) – 2 ∗ VESA SVGA60 → 1878 (LHHHLHLHLHHL: LSB) PLLP 11 10 9 8 7 6 5 4 3 2 1 0 Setting data L H H H L H L H L H H L – 13 – CXD3500R HP11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of with 12 bits is possible using the front edge of HSYNC as the reference. The HP setting range is from 0 to (N – 1). However, do not set HP to the number of frequency divisions N or higher, as the various pulses will not be output. The horizontal direction timing is interlinked using the falling edges of ENB1 and 2 as the reference. The following pulses are interlinked according to the HP11 to 0 setting. HST, HCK1, HCK2, ENB1, ENB2, PCG, PRG, CLP, BLK, VD, VCK transition point, FRP transition point, XFRP transition point, BLK transition point and VD transition point Thp Image display period HSYNC HST HDN Thp: Timing from the front edge of HSYNC to the HST pulse HSTP5 to 0: LLLLL, HDNPOL: H Minimum Thp setting values for each mode PLSSL2, 1, 0 Thp L L L 72 clk L L H 92 clk L H L 118 clk L H H 146 clk H L L 178 clk H L H 188 clk H H L 204 clk H H H 232 clk ∗ HSTP5, 4, 3, 2, 1, 0: All L Note) The time from HST until image display starts differs for each panel and its display area switching mode. In modes which apply a reset at the front edge of HSYNC (HR: L), the HDN pulse transition point is delayed by several dots relative to HSYNC. In these modes, Thp in the table above indicates the value using the HDN pulse transition point as the reference. 6 to 10 clk HSYNC HDN Reference: HDN transition point – 14 – HDNPOL: H CXD3500R VP7, 6, 5, 4, 3, 2, 1, 0 These bits set the vertical display start position. The minimum adjustment width is 1H of the output signal, and adjustment of up to 256H with 8 bits is possible using the front edge of VSYNC as the reference. In interlace signal double-speed mode, the vertical display start position can be set within a width of 1H relative to the double-speed converted signal. a) Non-interlace Minimum adjustment width Tvp VSYNC HSYNC VST VCK b) When using an interlace double-speed controller ODD field Tvp VSYNC HSYNC Minimum adjustment width VST VCK EVEN field Tvp VSYNC HSYNC VST VCK Minimum and maximum Tvp setting values VP 7 6 5 4 3 2 1 0 Min. L L L L L L L L Max. H H H H H H H H 4H 259H Note) The time from VST until image display starts differs for each panel. Also see the data sheets of the used panels. – 15 – CXD3500R VP The vertical display start position setting VP sets the value used to decode the internal counter. This internal counter is reset at the ENB1 and 2 pulse fall position when VSYNC is input, and counts up at each ENB1 and 2 pulse fall position thereafter. Therefore, when VSYNC is delayed relative to HSYNC and serial data HP is all L or a similar value, or when the HP11 to 0 setting is large and the ENB pulses fall near the end of the horizontal period, the vertical display start position is offset by 1H. VSYNC HSYNC ENB1, 2 The counter is reset at this timing. ENB1, 2 The counter is reset at this timing. When the HP11 to 0 setting is large. – 16 – CXD3500R Horizontal direction pulses The horizontal direction timing pulses for driving LCD panels are advanced and delayed interlinked with serial data HP11 to 0. The reference at this time is the falling edge of the ENB1 and 2 pulses. Except for during skip scan, the ENB1 and 2 pulse width is fixed by serial data PLSSL, and the pulse position is determined by serial data HP11 to 0. (See the Timing Charts.) The horizontal direction pulse position for other panels is generated by the internal counter that is reset at the ENB1 and 2 pulse fall position. HSTW1, 0 These bits set the HST pulse width. Normally set HSTW1 and 0 to LL for 6-dot simultaneous sampling panels (VGA, SVGA), and to HL for 12-dot simultaneous sampling panels (XGA). HSTW1, 0 HST pulse width L L 12 clk L H 18 clk H L 24 clk H H 48 clk HSTP5, 4 This sets the HST pulse rise position. The HST pulse rise position from the falling edge of the ENB1 and 2 pulses is as shown in the table below according to the PLSSL2, 1, 0 setting. However, note that the HSTP5 setting is invalid when PLSSL2 to 0 (described hereafter) is set from LLL to HLL. Thst ENB1, 2 HST Thst rise position PLSSL2, 1, 0 HSTP5, 4 L L L H H L H H L L L 70 clk 82 clk 70 clk 82 clk L L H 90 clk 102 clk 90 clk 102 clk L H L 116 clk 128 clk 116 clk 128 clk L H H 144 clk 156 clk 144 clk 156 clk H L L 176 clk 188 clk 176 clk 188 clk H L H 186 clk 198 clk 210 clk 222 clk H H L 202 clk 214 clk 226 clk 238 clk H H H 230 clk 242 clk 254 clk 266 clk Note) HST3, 2, 1, 0: LLLL – 17 – CXD3500R HSTP3, 2, 1, 0 These bits adjust the HST pulse start phase relative to HCK in 1-dot units. Set these bits as follows using HSTP5 to 0: LLLLLL (LSB) as the reference. Serial setting HCKM: L (6-dot simultaneous sampling) Reference Reference HST HCK1 HSTP5 to 0: LLLLHH (LSB) HSTP5 to 0: LLLLLL (LSB) 3 clk Reference Reference HST HCK1 HSTP5 to 0: LLLHHL (LSB) 11 clk 6 clk Reference HSTP5 to 0: LLHLHH (LSB) to LLHHHH (LSB) Same hereafter using this point as the reference. HST HCK1 HSTP5 to 0: LHLLLL (LSB) Note) HCK2 is the reverse polarity of HCK1. The timings shown above are for RGT: H, HCKPOL: H and HCKFX: L. Serial setting HCKM: H (12-dot simultaneous sampling) Reference Reference HST HCK1 HSTP5 to 0: LLLLLL (LSB) 12 clk HSTP5 to 0: LLLHHL (LSB) 6 clk Reference Reference Same hereafter using this point as the reference. HST HCK1 11 clk HSTP5 to 0: LLHLHH (LSB) to LLHHHH (LSB) HSTP5 to 0: LHLLLL (LSB) Note) HCK2 is the reverse polarity of HCK1. The timings shown above are for RGT: H, HCKPOL: H and HCKFX: L. – 18 – CXD3500R PCGU2, 1, 0 These bits adjust the PCG pulse rise position in 2-dot units. (However, serial data PCG: H) When serial data PCG is L, the PCGU2 to 0 setting is invalid and the PCG pulse rises at the same position as the FRP pulse transition point regardless of this setting. (interlinked with FRPP3, 2, 1, 0) PCGD4, 3, 2, 1, 0 These bits adjust the PCG pulse fall position in 2-dot units. However, the PCGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL. The PCGU2, 1, 0 and PCGD4, 3, 2, 1, 0 setting ranges are shown in the table below. Tpcd Tpcu ENB1, 2 PCG PCG: H Tpcu PLSSL2, 1, 0 PCGU2, 1, 0 Tpcd PCGD4∗, 3, 2, 1, 0 LLL HHH LLLLL HHHHH L L L 12 clk 28 clk 56 clk 86 clk L L H 18 clk 32 clk 74 clk 104 clk L H L 26 clk 40 clk 98 clk 128 clk L H H 36 clk 50 clk 124 clk 154 clk H L L 46 clk 60 clk 152 clk 182 clk H L H 48 clk 62 clk 150 clk 212 clk H H L 52 clk 66 clk 164 clk 226 clk H H H 58 clk 72 clk 190 clk 252 clk ∗: The PCGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL. Adjust the PCG pulse width to match the specifications for each LCD panel with the PCGU2 to 0 and PCGD4 to 0 settings. See the data sheets of the used panel for the PCG pulse width. – 19 – CXD3500R PRGD4, 3, 2, 1, 0 These bits adjust the PRG pulse fall position in 2-dot units. However, the PRGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL. The PRG pulse rise position is the same as the FRP pulse transition point. (interlinked with FRPP3, 2, 1, 0) The PRGD4, 3, 2, 1, 0 setting range is shown in the table below. Tprd ENB1, 2 PRG FRP Tpru setting range PLSSL2, 1, 0 PCGD4∗, 3, 2, 1, 0 PCGD4∗, 3, 2, 1, 0 LLLLL LHHHH HLLLL HHHHH L L L 62 clk 92 clk 62 clk 92 clk L L H 82 clk 112 clk 82 clk 112 clk L H L 108 clk 138 clk 108 clk 138 clk L H H 136 clk 166 clk 136 clk 166 clk H L L 168 clk 198 clk 168 clk 198 clk H L H 136 clk 166 clk 182 clk 212 clk H H L 142 clk 172 clk 196 clk 226 clk H H H 162 clk 192 clk 222 clk 252 clk ∗: The PRGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL. PCG This bit selects the new and old PCG pulse timing. When PCG is H, the PCGU2 to 0 setting shown on the previous page is selected. (new timing) When PCG is L, the PCG pulse rise position is interlinked with the FRP pulse transition point. (old timing) Set to match the timing specifications of the LCD panel. Set PCG to H for SVGA panels that support two-step precharge, and to L for other panels. FRP PCG: H PCG: L – 20 – CXD3500R FRP1, 0 These bits are the data for switching the LCD AC conversion signal FRP pulse cycle. Normally set FRP1, 0 to LL. FRP0 can also be controlled externally. → See SLCNT. 1H FRP1, 0: LL (1F/1H inversion) FRP1, 0: HL (2F/1H inversion) FRP1, 0: LH (1F inversion) FRP1, 0: HH (2F inversion) 1F FRPP3, 2, 1, 0 These bits adjust the FRP pulse transition point in 2-dot units. The PRG pulse rise position is the same as the FRP pulse transition point, and is interlinked with FRPP3 to 0. Tfrp ENB1, 2 FRP PCG Tfrp setting range PLSSL2, 1, 0 FRPP3, 2, 1, 0 LLLL HHHH L L L 16 clk 46 clk L L H 24 clk 54 clk L H L 36 clk 66 clk L H H 52 clk 82 clk H L L 68 clk 98 clk H L H 58 clk 88 clk H H L 62 clk 92 clk H H H 72 clk 102 clk – 21 – CXD3500R VSTFX, VSTPOL These bits set the VST pulse polarity. When VSTFX is H, the polarity of the VST pulse is positive regardless of other settings. Normally set VSTPOL to H. See the table below for details. Panel VSTFX VSTPOL DWN XGA H — — L L L L L H L H L L H H VST pulse polarity SVGA ∗ —: don't care HCKFX, HCKPOL These bits set the HCK1 and 2 pulse polarity. When HCKFX is H, the HCK1 and 2 pulse polarity is fixed regardless of the right/left inversion control setting RGT. However, the polarity is inverted by HCKPOL. See the table and figures below for details. HCKFX RGT HCKPOL HCK polarity H — L B H — H A L L L A L L H B L H L B L H H A ∗ —: don't care HST HST HCK1 HCK1 HCK2 HCK2 A in the table above B in the table above HSTW1, 0: LL, HSTP5 to 0: LLLLHH, HCKM: L HCKM This bit sets the HCK1 and 2 pulse width. When HCKM is L, the HCK1 and 2 pulse for 6-dot simultaneous sampling is output. When HCKM is H, the HCK1 and 2 pulse for 12-dot simultaneous sampling is output. Set the width to match the panel specifications. SVGA panel → 6-dot simultaneous sampling → HCKM: L XGA panel → 12-dot simultaneous sampling → HCKM: H – 22 – CXD3500R INV, SHP3, 2, 1, 0 This IC does not have a sample-and-hold pulse output, but instead allows control of the sample-and-hold position of the CXA2112R sample-and-hold driver and control of master clock inversion by setting the CXD3500R serial data and connecting the control pins. INV set by serial data is output as is from the INV (Pin 49). Connect this INV to INV_CNT (Pin 52) of the CXA2112R to allow CXA2112R dot clock phase inversion control from the TG. In addition, data set with SHP3, 2, 1, 0 is reflected to the SHP1A, SHP1B, SHP2A and SHP2B outputs (Pins 45, 46, 47 and 48) as shown in the table below. SHP3, 2, 1, 0 SHP2A, 2B, 1A, 1B SHP3, 2, 1, 0 SHP2A, 2B, 1A, 1B L L L L L L L L H L L L Z H L L L L L H L L Z L H L L H Z H Z L L L H L L L Z H H L H L Z H Z H L L H H L L H H H L H H Z H H H L H L L Z L L L H H L L H H L L L H L H Z L Z L H H L H H H Z L L H H L Z L Z H H H H L H H Z H L H H H Z L H H H H H H H H H H ∗ Z: High Impedance State The sample-and-hold position of the CXA2112R can be set by connecting SHP1A, 1B, 2A and 2B as shown in the figure below. See the CXA2112R data sheet for further details. CXA2112R , , CXD3500R SHP1A (Pin 45) (SHP2A (Pin 47)) 45 (47) SHP1B (Pin 46) (SHP2B (Pin 48)) 46 (48) R 1 (2) POS_CNT1 (Pin 1) (POS_CNT2 (Pin 2)) Note) The value of resistor R in the figure above differs according to the number of connected CXA2112R. – 23 – CXD3500R VPOL, HPOL These bits are the data for switching the input vertical and horizontal sync signal polarity. Since signal processing is performed with the sync signal polarity fixed to positive by the internal logic, the data must be switched according to the polarity of the input sync signal. Therefore, individually set VPOL and HPOL to H when the polarity of the input sync signal is positive, and to L when the polarity is negative. VSYNC may not be detected if the opposite polarity is set, so be sure to set the correct polarity. HDNPOL HDN (H return pulse) is the 1/N frequency divider output pulse for the PLL IC. The width of the HDN pulse is calculated according to the setting of PLLP11 to 1 for the value of frequency division N, and that value is N/2. HDNPOL is the data for setting the output polarity of this HDN pulse, and the relationship between its setting and the pulse polarity is shown in the figure below. HPOL: L N clk HSYNC HDNPOL: H HDN HDNPOL: L N/2 clk CLPPOL This bit sets the output polarity of pedestal clamp pulse CLP. When CLPPOL is H, the polarity of the CLP pulse is positive, and when CLPPOL is L, the polarity of the CLP pulse is negative. CLPW, CLPP These bits set the CLP pulse output width and output phase. Both the width and the phase can be set to two positions using 1 bit. The CLP pulse center position is fixed regardless of the CLPW setting. CLP pulse center Tclp ENB1, 2 CLP Wclp PLSSL2, 1, 0 Wclp Tclp CLPW: L CLPW: H CLPP: L CLPP: H L L L 32 clk 48 clk 48 clk 32 clk L L H 40 clk 60 clk 60 clk 40 clk L H L 50 clk 74 clk 77 clk 53 clk L H H 64 clk 96 clk 100 clk 68 clk H L L 80 clk 120 clk 124 clk 84 clk H L H 80 clk 120 clk 124 clk 84 clk H H L 86 clk 130 clk 133 clk 89 clk H H H 96 clk 144 clk 148 clk 100 clk – 24 – CXD3500R SLCNT Setting via the external control pins can be selected by setting SLCNT to H. The settings that can be made using the external pins are the right/left inversion discrimination settings RGT and XRGT, and the setting for switching the LCD panel AC conversion signal FRP and XFRP pulse cycle. SLCNT: L SLCNT: H Address: 0C Data 4 RGT External pin RGTCNT (Pin 10) Address: 07 Data 4 FRP0 External pin FRPCNT (Pin 11) SLFLD This bit selects FLD (Pin 6) IN/OUT pin input and output. The CXD3500R performs field identification internally. When SLFLD is L, the internally generated FLD pulse is selected and used for the internal circuit logic. The external FLD pulse is selected by setting SLFLD to H. For normal data type signals, the field identification pulse FLD is inverted every vertical period. The polarity at this time is not specified. Note) When inputting the FLD pulse from an external source, make sure that the FLD pulse transition point is 2H or more before the rising edge of VST. SLRS This bit switches the HSYNC edge-based 1/2 frequency divider reset on/off when generating the 1/2 clock using the internal frequency divider. When SLRS is H, reset is not applied; when SLRS is low, reset is applied every 1H. There is no need to set this bit when inputting a 1/2 clock from an external source. CKPOL This bit performs the input clock polarity switching settings. CLK1 and 2 pass through this clock polarity switching setting immediately after input. When CKPOL is L, the internal circuits operate according to the input clock and the reverse polarity clock. When setup and hold cannot be maintained because the phases of the HSYNC input and the master clock input to the TG are offset due to the set system, set CKPOL to a value that provides sufficient margin. SLCK This bit switches the clock between the internal 1/2 frequency division and external 1/2 clock input. When inputting an external 1/1 clock, set SLCK to H to 1/2 frequency divide the clock internally. When inputting an external 1/2 clock, set SLCK to L. When the master clock is 55MHz or more, input an external 1/2 frequency-divided clock and set SLCK to L. Note) Pulses with positions that can be set in 1-dot units (HST, HCK1, HCK2, ENB1, ENB2, PCG, PRG, CLP, BLK, VCK transition point, FRP transition point and XFRP transition point) use the internally inverted clock, so when inputting a 1/2 clock using an external frequency divider, these pulses may be offset if the 1/2 clock duty deviates from 50%. Therefore, set the duty of the input 1/2 clock as close to 50% as possible. – 25 – CXD3500R PLSSL2, 1, 0 These bits set the output timing mode. Switch the setting according to the dot clock frequency and blanking width of the input signal. When using a Sony SVGA panel, select one of the 5 modes from PLSSL2 to 0: LLL to HLL. When using a XGA panel, select one of the 3 modes from PLSSL2 to 0: HLH to HHH. The setting reference is shown in the table below. PLSSL2, 1, 0 LCD panel Setting reference L L L Dot clock: 20 to 30MHz L L H Dot clock: 25 to 40MHz L H L L H H Dot clock: 45 to 63MHz H L L Dot clock: 55 to 75MHz H L H Dot clock: 65 to 80MHz H H L H H H SVGA XGA Dot clock: 35 to 50MHz Dot clock: 75 to 85MHz Dot clock: 80 to 96MHz Note) When the horizontal blanking width is sufficient, use the mode one higher than the setting that results in the maximum value for that mode. Example) SVGA 60Hz: Dot clock 40MHz PLSSL2, 1, 0 can be set to LLH, but should be set to LHL instead in order to ensure sufficient margin. BLKON, BLKPOL These bits are switch the black frame display pulse BLK on/off and set the BLK polarity, respectively. When BLKON is H, the BLK pulse is output. In addition, the polarity of the BLK pulse is positive when BLKPOL is H, and negative when BLKPOL is L. Set BLKPOL to H for Sony SVGA panels, and to L for XGA panels. VST BLKON: H, BLKPOL: H BLK BLKON: L, BLKPOL: H BLK BLKON: H, BLKPOL: L BLK BLKON: L, BLKPOL: L BLK – 26 – CXD3500R FMBK This bit sets the FRP-related skip scan timing. When this bit is set, the FRP pulse transition point phase is offset by 1H relative to the VCK pulse. In this case, the skip scan position does not change when FMBK is either H or L. See the figure below. VST VCK FRP HST/PCG ENB FMBK: H (MAIN) FMBK: L (SUB) Note) Precautions when using skip scan When configuring a system by combining the Sony CXA2112R sample-and-hold driver and this TG, input the ENB2 pulse to Pin 12 (ENB) of the CXA2112R instead of the ENB1 pulse that is connected to the panel. If the ENB1 pulse is input to the CXA2112R and FMBK is L (SUB), the CXA2112R internal sample-andhold circuit may not be reset, causing the characteristics of the CXA2112R to deteriorate. When not using skip scan, either ENB1 or 2 may be input to Pin 12 (ENB) of the CXA2112R. MBKA4, 3, 2, 1, 0 MBKB3, 2, 1, 0 MBKZ3, 2, 1, 0 These bits set the skip scan display related settings. When not performing skip scan display, set all bits to L. See the setting examples on the next page. MBKA4, 3, 2, 1, 0 These bits set the skip scan main cycle. The setting range is from 2 to 31 cycles. When MBKA4 to 0 is LLLLL or LLLLH, skip scan is not performed. MBKB3, 2, 1, 0 These bits set the sub skip scan position. The setting range is from 2 to 15. See the figures on the next page. When MBKB3 to 0 is LLLL or LLLH, or when MBKB > MBKA, sub skip scan is not performed. – 27 – CXD3500R Example) MBKA4, 3, 2, 1, 0: LHLHL (10), MBKB3, 2, 1, 0: LHLH (5) Sub skip scan position specified by MBKB , , ,, VST VCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FRP ENB HST/PCG Cycle set by MBKA Note) Odd skip scan continuously skips only pulses of the same polarity. Depending on the system, this may cause DC to be applied to the panel. Therefore, set skip scan so that pulses of the same polarity are not continuously skipped. This can be accomplished during odd skip scan by doubling the setting to make it an even number, and then setting skip scan for the odd lines. Example) 1/9 skip scan → MBKA4 to 0: LHLLH, MBKB3 to 0: LLLL X VCK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 FRP Same polarity skip scan continues. To set 2/18 skip scan and odd line skip scan → MBKA4 to 0: HLLHL, MBKB3 to 0: HLLH O VCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 FRP – 28 – 2 3 4 5 6 7 8 9 CXD3500R MBKZ3, 2, 1, 0 These bits change the skip scan timing for each V cycle. These bits determine the skip scan timing for the next 1V period using the skip scan timing when the field identification pulse (FLD) is L as the reference. The optimal skip scan position can be set by setting a skip scan interval of 0 to 14H. (When MBKZ3 to 0 is LLLL or HHHH, the same line is skipped each field.) Example) MBKZ3, 2, 1, 0: LLHH (3) ,, , , Skip scan reference position VST VCK FRP ENB HST/PCG FLD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MBKA: 10, MBKB: 5, FLD: L VST VCK FRP ENB HST/PCG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FLD MBKA: 10, MBKB: 5, FLD: H Note) Observe the following points when setting MBKZ3 to 0. 1. When MBKB is 0 or 1, set the MBKZ value to MBKA or less. 2. In all other cases, set the MBKZ value to MBKB or less. – 29 – CXD3500R VGAV This bit switches the supported input signal between AV interlaced signals or data signals. Set VGAV to H for data signal input, and to L for AV signal input. When VGAV is L, the FLD pulse is generated by phase comparison using the value calculated from the serial setting PLLP11 to 0 value. Therefore, when using the FLD pulse generated by this TG, be sure to set PLLP11 to 0 regardless of the HR setting below (offset due to skip scan fields, etc.). HR This bit controls the input horizontal sync signal (HSYNC)-based PLL counter reset operation, and supports external clock input. (Reset operation is enabled when HR is L.) Resetting the internal PLL counter at the front edge of the input HSYNC generates an output pulse synchronized to HSYNC. When HR is L, there is no need to set PLLP11 to 0. This function should be used with systems which do not use a PLL. In addition, the master clock is loaded and reset is applied at the front edge of HSYNC in this mode, so be sure to input the input signal in a manner that ensures sufficient setup and hold times. Input horizontal sync signal (HSYNC) Reset the internal PLL counter at these timings. Note) Since H-POSITION specifications described in this data sheet are not satisfied due to the configuration of the internal logic, the picture center must be adjusted each time. DWN, RGT These bits set the up/down and/or right/left inversion discrimination data. These settings allow display to be performed in accordance with each display system. The serial setting DWN is reflected to the DWN (Pin 37). In addition, RGT is valid only when SLCNT is L. At this time the setting value is reflected to the RGT (Pin 25). See page 22 of this data sheet for the relationship between the DWN and VST pulses and the RGT and HCK pulses. – 30 – CXD3500R DSP This bit performs the double-speed display mode switching settings. Operation shifts to double-speed display mode when DSP is L. However, DSP should be set H for other modes. This function is only supported when the built-in double-speed controller is used. This controller is designed to use the µPD485505 (NEC/high-speed line buffer) as the system line memory IC, and generates the doublespeed processing pulses RSTW (reset write), WCK (write clock), RSTR (reset read) and RCK (read clock). The operation of the µPD485505 is as follows. Write operation is started at the RSTW timing, and this memory information is read at double speed at the RSTR timing which is delayed by 1/2H from the RSTW timing. Labeling the master clock frequency (MCK) as f, the write and read clock frequencies at this time are expressed as f/2 and f, respectively. However, the master clock should have a frequency of 36MHz or less when using this mode. See the data sheet for a detailed description of the µPD485505 operation. Note) This function cannot be used in modes which input the 1/2 clock from an external source. The RSTR position is calculated from the serial data PLLP11 to 0 setting value. Therefore, set serial data PLLP11 to 0 to the correct value when using this mode, regardless of the serial data HR setting. ADC LINE Mem. µPD485505 R, G, B IN RSTW WCK HSYNC VSYNC DAC RSTR RCK CXD3500R MCK: f Double-speed display system diagram HSYNC RSTW WCK f/2 RSTR f RCK HSYNC RSTW RSTR Double-speed display timing – 31 – CXD3500R PO/MODE3, 2, 1 These bits set the Parallel Out output. The values set by PO/MODE3, 2, 1 are output as is to MODE3 (Pin 20), MODE2 (Pin 21) and MODE1 (Pin 22). These outputs are normally connected to the pins for the LCD panel display area switching, so they should be used to set the panel display area, etc. via the serial settings to the TG. Examples) SVGA panels LCX016, LCX026, LCX031: Input the MODE1, 2 and 3 outputs to the panel inputs of the same name. LCX021: Input the MODE1 output to the MODE panel input pin. XGA panels LCX017, LCX023, LCX029: Input HB to MODE1 and VB to MODE2. SPON This bit switches on/off the special setting mode. The special setting mode is valid when this bit is H. When SPON is L, the data at addresses 0E and 0F (HEX) is L regardless of the settings. When SPON is L, the XGBK, HDON, HAXON and VAXON settings are all invalid, and the operation is in the mode where these settings are all L. XGBK This bit sets the timing output for black frame display on Sony XGA panels. When using the XGA panel black frame display mode, set XGBK to H. The output pulse timing is shown in the figure below. When not using black frame display, set XGBK to L. When using SVGA panels, BLKON: H, BLKPOL: H, SPON: L BLK PCG PRG When using XGA panels, BLKON: H, BLKPOL: L, SPON: H, XGBK: H BLK PCG PRG – 32 – CXD3500R HDON This bit performs the HD (Pin 31) pulse output switching settings. When HDON is L, the horizontal direction reference pulse is output. (See the Timing Charts.) When HDON is H, HD outputs a programmable pulse that is interlinked with HP11 to 0. The fall position of this pulse can be set by serial data HAXD9 to 1, and the rise position can be set by serial data HAXU9 to 1. A pulse of arbitrary position, width and polarity can be output at this position up to 700 clk from the ENB1 and 2 pulse fall position (reference). Example) HAXD9 to 1: LLHHLLLLL, HAXU9 to 1: LLLHLLLLL Arbitrary pulse output possible within the range of 700 clk ENB1, 2 64 clk HD 192 clk SPON: H, HDON: H HAXON This bit performs the XHS (Pin 51) pulse output switching settings. When HAXON is L, the normal XHS pulse is output. (See the Timing Charts.) When HAXON is H, a pulse synchronized to HSYNC can be output at an arbitrary position (1-dot units) and width (2-dot units). Set the pulse fall position in HAXD11 to 0, and the pulse rise position in HAXU11 to 0. However, the HAXU0 setting is invalid. When HAXD0 is H, the XHS pulse rise position also shifts backwards by 1 dot. The setting range is from 0 to (N – 1), but do not set HAXD11 to 1 and HAXU11 to 1 to the same value. VAXON This bit performs the XVS (Pin 50) pulse output switching settings. When VAXON is L, the normal XVS pulse is output. (See the Timing Charts.) When VAXON is H, a pulse synchronized to VSYNC can be output at an arbitrary position (1H units) and width (1H units). Set the pulse fall position in VAXD11 to 0, and the pulse rise position in VAXU11 to 0. The XVS pulse transition point at this time is the ENB1 and 2 pulse fall position. The reference position is the front edge of the ENB1 and 2 pulse that is 1H from the front edge of VSYNC. Labeling this position as 0, the pulse can be set to an arbitrary position. VSYNC ENB XVS Reference VAXON: H, VAXD11 to 0: LLLLLLLLLHHH, VAXU11 to 0: LLLLLLLLLLLL – 33 – CXD3500R Scan converter pulse settings Of the serial data below, set SLLAP to L when not using a scan converter that requires the control pulses output from this TG. In this case, other settings are not required. SLLAP SLLAP is used when converting the number of pixels using the scan converter, when the clock differs between input signals and output signals, etc. When SLLAP is L, the normal operating mode is used. When SLLAP is H, only the serial interface, PLL counter and phase comparator operate by the CKI1 or CKI2 synchronized to the input signal, and other internal blocks operate by CKI3. LPCK This setting is valid only when serial data SLLAP is H. When LPCK is L, the CKI1 or CKI2 synchronized to the input HSYNC is selected; when LPCK is H, the external asynchronous clock CKI3 is selected, and an output pulse that is asynchronous with the input HSYNC is output according to the number of frequency divisions set by serial data ORP11 to 0. SLCKL This setting is valid only when serial data SLLAP is H. This bit switches the clock between the internally 1/2 frequency-divided clock and the external 1/2 clock input. When inputting an external 1/1 clock, set SLCKL to H to 1/2 frequency divide the clock internally. When inputting an external 1/2 clock, set SLCKL to L. ORRS4, 3, 2, 1, 0 This setting is valid only when serial data SLLAP is H. When serial data SLLAP is L, an arbitrary ORACT pulse can be output synchronized to the input HSYNC. When SLLAP is H, this pulse is generated from a dedicated counter (loop counter similar to the PLL counter, and referred to as AUX. PLL COUNTER = OR counter in the Block Diagram) that operates by CKI3, an independent clock that is asynchronous to the input signal. In addition, pulses for LCD panel driving pulses are also generated at this time based on the output of this counter, enabling the LCD panel to be driven with a horizontal cycle and clock that differ from the input signal. The above OR counter applies a reset once every vertical period and at a specified input HSYNC cycle in order to synchronize to the input HSYNC. ORRS4 to 0 set the number of H cycles at which this HSYNC-based reset is performed. Reset is not applied at the H cycle when ORRS4 to 0 (LSB) is LLLLL, and applied at the set number of cycles for other settings. Reset can be applied from 1H to a maximum of 31H cycles. 4H V-SYNC IRACT ORACT Timing at which reset is applied to OR counter SLLAP: H, ORRS4 to 0: LLHLL, VRSP3 to 0: LLLH – 34 – CXD3500R IRD11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, IRU11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 IRACT (Pin 52) is an output pulse synchronized to the input HSYNC that can be output at an arbitrary position (1-dot units) and width (2-dot units). Set the pulse fall position in IRD11 to 0, and the pulse rise position in IRU11 to 0. However, the IRU0 setting is invalid. When IRD0 is H, the IRACT pulse rise position also shifts backwards by 1 dot. The setting range is from 0 to (N – 1), but do not set IRD11 to 1 and IRU11 to 1 to the same value. H-SYNC 128 clk IRACT IRD11 to 0: LLLLLLLLLLLL, IRU11 to 0: LLLLHLLLLLLL, HR: H When IRD0 is H, the pulse is shifted backwards by one dot without changing the pulse width. H-SYNC 128 clk IRACT 1 dot IRD11 to 0: LLLLLLLLLLLH, IRU11 to 0: LLLLHLLLLLLL, HR: H VRSP3, 2, 1, 0 The above-mentioned OR counter applies a reset once every vertical period and at a specified input HSYNC cycle. VRSP3, 2, 1, 0 sets the number of H after VSYNC input at which this one reset every vertical period is applied. Reset is not applied when VRSP3 to 0 (LSB) is LLLL or HHHH, and applied at the set position from 1H to a maximum of 14H after VSYNC for other settings. V-SYNC IRACT ORACT SLLAP: H, VRSP3 to 0: LLLH V-SYNC IRACT ORACT SLLAP: H, VRSP3 to 0: LHLH Timing at which reset is applied to OR counter – 35 – CXD3500R ORP11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 This setting is valid only when serial data SLLAP is H. ORP sets the number of frequency divisions for the above-mentioned OR counter. Like PLLP11 to 0, ORP is 12-bit data and the number of frequency divisions can be set in 2-dot units up to 4096. Set the actual frequency division ratio M as follows. M – 2 = Actual number of clk set However, the ORP0 setting is invalid. The number of frequency divisions set by ORP becomes the actual frequency division value of the horizontal direction timing pulses. Each pulse is asynchronous to the input HSYNC and output in sync with the OR counter. ORD11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, ORU11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 When serial data SLLAP is H, the ORACT (Pin 53) pulse is output synchronized to the OR counter that operates by the CKI3 clock that is asynchronous to the input HSYNC. This pulse can be output at an arbitrary position (1-dot units) and width (2-dot units). Set the pulse fall position in ORD11 to 0, and the pulse rise position in ORU11 to 0. However, the ORU0 setting is invalid. When IRD0 is H, the ORACT pulse rise position also shifts backwards by 1 dot. The setting range is from 0 to (M – 1), but do not set ORD11 to 1 and ORU11 to 1 to the same value. When serial data SLLAP is L, ORACT outputs the same pulse as the IRACT pulse synchronized to the input HSYNC according to the serial data ORU11 to 0 and ORD11 to 0 settings. The IRACT and ORACT pulses can be set independently. SLLAP: H (asynchronous to HSYNC) HSYNC IRACT ORACT SLLAP: L (synchronous to HSYNC) HSYNC IRACT ORACT IRD11 to 0: LLLLLLLLLLLL, IRU11 to 0: LLLLHLLLLLLL ORD11 to 0: LLLLLLLLLLLL, ORU11 to 0: LLLLHLLLLLLL – 36 – CXD3500R Auxiliary pulse settings HAXD11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, HAXU11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 These settings are valid only when serial data SPON and HDON are H, or when SPON and HAXON are H. (See page 33.) These bits are the setting data for the programmable pulses. When the above settings are made, the former switches the HD (Pin 31) output from the normal horizontal direction reference pulse to programmable pulse output, the latter switches the XHS (Pin 51) output to programmable pulse output, and this setting data is reflected. The HD pulse is output synchronized to serial data HP11 to 0. In addition, the XHS pulse is synchronized to the internal PLL counter, and can be output at an arbitrary position within one horizontal period. This setting is the same for both HDON and HAXON, so when both HDON and HAXON are H, the HD pulse and the XHS pulse cannot be adjusted independently. VAXD11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, VAXU11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 These settings are valid only when serial data SPON and VAXON are H. These bits are the setting data for the programmable pulses. When the above settings are made, the XVS (Pin 50) output switches to programmable pulse output, and this setting data is reflected. The XVS pulse is synchronized to the internal vertical counter, and can be output at an arbitrary position within one vertical period. (See page 33.) – 37 – CXD3500R Preset settings during power on Set Pin 19 (XCLR, system clear) to L during power on to reset the system. At this time the serial data is set to the preset setting status. Set XCLR to H level and then make all the necessary settings. The preset setting values are shown in the table below. Address Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 L H L L L L L L 0 0 0 0 0 0 0 1 H H H — L L L L 0 0 0 0 0 0 1 0 L H L L L H H L 0 0 0 0 0 0 1 1 L L L H L H L H 0 0 0 0 0 1 0 0 L L L L L L H H 0 0 0 0 0 1 0 1 H L L L L H L L 0 0 0 0 0 1 1 0 — — — L L H L L 0 0 0 0 0 1 1 1 L H L L H L L L 0 0 0 0 1 0 0 0 L L L L L L L L 0 0 0 0 1 0 0 1 H L L L L H L L 0 0 0 0 1 0 1 0 L L L H H L H L 0 0 0 0 1 0 1 1 L H L L L L L L 0 0 0 0 1 1 0 0 L L L L L L L L 0 0 0 0 1 1 0 1 H L L H H H L L 0 0 0 0 1 1 1 0 L L L L L L L L 0 0 0 0 1 1 1 1 — — — — — — L L 0 0 0 1 0 0 0 0 L L H L L L L L 0 0 0 1 0 0 0 1 L L L L L L L L 0 0 0 1 0 0 1 0 L L L L L L L L 0 0 0 1 0 0 1 1 H L L L L L L — 0 0 0 1 0 1 0 0 L L L L L H L L 0 0 0 1 0 1 0 1 L L L L H H H — 0 0 0 1 0 1 1 0 L L L L L L L L 0 0 0 1 0 1 1 1 L L L L L L L L 0 0 0 1 1 0 0 0 H L L L L L L — 0 0 0 1 1 0 0 1 L L L L L L L L 0 0 0 1 1 0 1 0 L L L L L L L L 0 0 0 1 1 0 1 1 H L L L L L L — 0 0 0 1 1 1 0 0 L L L L L L L L 0 0 0 1 1 1 0 1 L L L L L L L L 0 0 0 1 1 1 1 0 H L L L L L L L —: Setting invalid – 38 – CXD3500R XHS and XVS pulse output timing XHS pulses XHS pulses are output with negative polarity in 96-clock widths 34 clocks after the fall of the ORACT pulse when serial data HAXON is L. Therefore, in order to output XHS pulses correctly, set serial data ORD11 to 0 and ORU11 to 0, respectively. The preset timing is shown in the figure below. In addition, programmable pulses are output when serial data HAXON is H. HSYNC 128 clk ORACT 96 clk XHS 34 clk ORD11 to 0: LLLLLLLLLLLL, ORU11 to 0: LLLLHLLLLLLL XVS pulses XVS pulses are output with the VSYNC pulse that is latched by the XHS pulse when serial data VAXON is L. In addition, like XHS, programmable pulses are output when serial data VAXON is H. VSYNC HSYNC 2 clk XHS XHS XVS XVS – 39 – – 40 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 470 480 1 10 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 460 PLSSL2/1/0: L/L/L DWN: H VP: LLLHHHHL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: H BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: H/H/L VGA (IBM: fv 59.94Hz) 640 × 480 20 30 40 45 CXD3500R – 41 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 802 812 16 clk 822 0 10 20 30 40 96 clk 50 70 128 clk 128 clk 120 clk 60 96 clk 62 clk 62 clk 80 42 clk 90 32 clk 38 clk 100 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 792 110 48 clk 120 PLSSL2/1/0: L/L/L PLLP: LLHHLLLHHHHL (LSB) HP: LLLLLLHHLLHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLHH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: H/H/L (SVGA panel, VGA mode) VGA (IBM: fv 59.94Hz) 640 × 480 130 140 150 160 170 180 Loop Counter: 800 clk MCK f: 25.18MHz (39.72ns) CXD3500R – 42 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 470 480 1 10 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 460 20 PLSSL2/1/0: L/L/H DWN: H VP: LLLHHLHL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: H BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: H/H/L VGA (VESA72: fv 72.809Hz) 640 × 480 30 40 49 CXD3500R – 43 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 1850 1860 24 clk 1870 0 10 40 clk 20 30 40 50 70 128 clk 128 clk 120 clk 60 96 clk 80 74 clk 110 50 clk 120 40 clk 54 clk 128 clk 100 74 clk 90 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 1840 PLSSL2/1/0: L/L/H PLLP: LLHHLLHHHHHL (LSB) HP: LLLLLLHHLHHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLHH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: H/H/L (SVGA panel, VGA mode) VGA (VESA72: fv 72.809Hz) 640 × 480 130 140 150 160 170 Loop Counter: 832 clk MCK f: 31.50MHz (31.74ns) 179 CXD3500R – 44 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 580 590 600 1 10 20 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 571 PLSSL2/1/0: L/H/L DWN: H VP: LLLHLHHL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: H BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: H/L/L SVGA (VESA60: fv 60.32Hz) 800 × 600 30 40 50 53 CXD3500R – 45 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 926 936 946 956 966 976 986 996 1006 1016 1026 40 clk 1036 1046 0 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 916 10 34 clk 20 PLSSL2/1/0: L/H/L PLLP: LHLLLLLHHHHL (LSB) HP: LLLLLHLHLLLL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLLH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: L HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: H/L/L (SVGA panel, SVGA mode) SVGA (VESA60: fv 60.32Hz) 800 × 600 40 128 clk 128 clk 120 clk 128 clk 30 50 96 clk 60 70 79 Loop Counter: 1056 clk MCK f: 40.00MHz (25.00ns) CXD3500R – 46 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 90 100 110 120 92 clk 92 clk 130 140 88 clk 170 64 clk 160 50 clk 66 clk 150 180 190 200 210 220 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 80 230 240 PLSSL2/1/0: L/H/L PLLP: LHLLLLLHHHHL (LSB) HP: LLLLLHLHLLLL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLLH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: L HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: H/L/L (SVGA panel, SVGA mode) SVGA (VESA60: fv 60.32Hz) 800 × 600 250 260 270 280 290 Loop Counter: 1056 clk MCK f: 40.00MHz (25.00ns) 299 CXD3500R – 47 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 600 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 588 1 PLSSL2/1/0: L/H/H DWN: H VP: LLLHHLLL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: H BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: H/L/L SVGA (VESA72: fv 72.188Hz) 800 × 600 10 20 31 CXD3500R – 48 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 910 920 930 940 950 960 970 980 990 1000 1020 56 clk 1010 1030 0 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 900 10 34 clk 20 PLSSL2/1/0: L/H/H PLLP: LHLLLLLLHHHL (LSB) HP: LLLLLLLHHHHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLHL (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: L HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: H/L/L (SVGA panel, SVGA mode) SVGA (VESA72: fv 72.188Hz) 800 × 600 40 128 clk 128 clk 120 clk 120 clk 30 50 96 clk 60 70 79 Loop Counter: 1040 clk MCK f: 50.00MHz (20.00ns) CXD3500R – 49 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 90 100 120 32 clk 84 clk 120 clk 120 clk 110 76 clk 130 140 64 clk 150 160 170 180 190 200 210 220 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 80 230 240 PLSSL2/1/0: L/H/H PLLP: LHLLLLLLHHHL (LSB) HP: LLLLLLLHHHHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLHL (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: L HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: H/L/L (SVGA panel, SVGA mode) SVGA (VESA72: fv 72.188Hz) 800 × 600 250 260 270 280 290 299 Loop Counter: 1040 clk MCK f: 50.00MHz (20.00ns) CXD3500R – 50 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 600 610 620 624 1 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 596 10 PLSSL2/1/0: H/L/L DWN: H VP: LLHLLHLH (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: H BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: L/L/L Macintosh16 (fv 74.55Hz) 832 × 624 20 30 38 CXD3500R – 51 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 1032 1042 1052 1062 1072 1082 1092 1102 1112 1122 1142 32 clk 1132 0 10 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 1022 34 clk 20 64 clk 30 PLSSL2/1/0: H/L/L PLLP: LHLLLHHHHHHL (LSB) HP: LLLLLHLHHHHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLLH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/L/L (Mac16 panel, Mac16 mode) Macintosh16 (fv 74.55Hz) 832 × 624 50 120 clk 40 96 clk 128 clk 128 clk 60 70 80 89 Loop Counter: 1152 clk MCK f: 57.28MHz (17.46ns) CXD3500R – 52 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 100 110 120 130 140 150 170 144 clk 144 clk 160 190 224 clk 180 100 clk 200 210 230 80 clk 92 clk 220 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 90 240 250 PLSSL2/1/0: H/L/L PLLP: LHLLLHHHHHHL (LSB) HP: LLLLLHLHHHHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLLH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/L/L (Mac16 panel, Mac16 mode) Macintosh16 (fv 74.55Hz) 832 × 624 260 270 280 290 300 309 Loop Counter: 1152 clk MCK f: 57.28MHz (17.46ns) CXD3500R – 53 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 750 760 768 1 10 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 742 PLSSL2/1/0: H/L/H DWN: H VP: LLLHHHHL (LSB) FRP1/0: L/L VSTFX: H VSTPOL: H VPOL: L VGAV: H BLKON: L BLKPOL: L FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: L/H/H XGA (VESA60: fv 60.00Hz) 1024 × 768 20 30 40 45 CXD3500R – 54 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 1304 1314 1324 24 clk 1334 0 10 34 clk 20 30 40 50 136 clk 70 128 clk 128 clk 120 clk 60 96 clk 80 90 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 1294 100 110 PLSSL2/1/0: H/L/H PLLP: LHLHLLHHHHHL (LSB) HP: LLLLLHLHLLLL (LSB) HSTW1/0: H/L HSTP: LLLHHL (LSB) PCGU: HLL (LSB) PCGD: LHHLH (LSB) PCG: L PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: H HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/H/H (XGA panel, XGA mode) XGA (VESA60: fv 60.00Hz) 1024 × 768 120 130 140 150 160 169 Loop Counter: 1344 clk MCK f: 65.00MHz (15.38ns) CXD3500R – 55 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 180 200 80 clk 78 clk 110 clk 150 clk 150 clk 190 210 220 160 clk 230 240 250 260 270 280 290 300 310 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 170 320 330 PLSSL2/1/0: H/L/H PLLP: LHLHLLHHHHHL (LSB) HP: LLLLLHLHLLLL (LSB) HSTW1/0: H/L HSTP: LLLHHL (LSB) PCGU: HLL (LSB) PCGD: LHHLH (LSB) PCG: L PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: H HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/H/H (XGA panel, XGA mode) XGA (VESA60: fv 60.00Hz) 1024 × 768 340 350 360 370 380 389 Loop Counter: 1344 clk MCK f: 65.00MHz (15.38ns) CXD3500R – 56 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 940 950 960 1 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 932 10 PLSSL2/1/0: H/H/L DWN: H VP: LLHLLLHL (LSB) FRP1/0: L/L VSTFX: H VSTPOL: H VPOL: L VGAV: H BLKON: L BLKPOL: L FMBK: H MBKA: LHLHL (LSB) MBKB: LHLH (LSB) MBKZ: LLHH (LSB) DWN: H PO/MODE3/2/1: L/H/H (VESA60: fv 60.00Hz) 1280 × 960 20 30 40 CXD3500R – 57 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 1370 1380 1390 76 clk 1400 1410 1420 1430 0 10 34 clk 20 30 50 90 clk 40 70 128 clk 128 clk 120 clk 60 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 1360 90 96 clk 80 PLSSL2/1/0: H/H/L PLLP: LHLHHLLHHHHL (LSB) HP: LLLLLHLHLHLL (LSB) HSTW1/0: H/L HSTP: HLLHHL (LSB) PCGU: HLL (LSB) PCGD: LHLHH (LSB) PCG: L PRGD: LHHHH (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: H HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/H/H (XGA panel, skip scan mode) (VESA60: fv 60.00Hz) 1280 × 960 100 110 120 130 139 Loop Counter: 1440 clk MCK f: 86.4MHz (11.57ns) CXD3500R – 58 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 150 160 170 180 164 clk 164 clk 190 210 102 clk 250 clk 200 230 86 clk 148 clk 220 240 250 260 270 280 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 140 290 300 PLSSL2/1/0: H/H/L PLLP: LHLHHLLHHHHL (LSB) HP: LLLLLHLHLHLL (LSB) HSTW1/0: H/L HSTP: HLLHHL (LSB) PCGU: HLL (LSB) PCGD: LHLHH (LSB) PCG: L PRGD: LHHHH (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: H HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/H/H (XGA panel, skip scan mode) (VESA60: fv 60.00Hz) 1280 × 960 310 320 330 340 350 360 Loop Counter: 1440 clk MCK f: 86.4MHz (11.57ns) CXD3500R – 59 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 750 760 768 1 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 740 10 PLSSL2/1/0: H/H/H DWN: H VP: LLHLLLHL (LSB) FRP1/0: L/L VSTFX: H VSTPOL: H VPOL: L VGAV: H BLKON: L BLKPOL: L FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: L/H/H XGA (VESA85: fv 84.99Hz) 1024 × 768 20 30 40 CXD3500R – 60 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 1370 1380 1390 1400 1410 48 clk 1420 1430 0 10 34 clk 20 30 40 96 clk 50 70 128 clk 128 clk 120 clk 60 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 1360 96 clk 80 PLSSL2/1/0: H/H/H PLLP: LHLHLHLHHHHL (LSB) HP: LLLLLLHLHHLL (LSB) HSTW1/0: H/L HSTP: LLLHHL (LSB) PCGU: HLL (LSB) PCGD: HHLLH (LSB) PCG: L PRGD: LHHHH (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: H HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/H/H (XGA panel, XGA mode) XGA (VESA85: fv 84.99Hz) 1024 × 768 90 100 110 120 130 139 Loop Counter: 1376 clk MCK f: 94.50MHz (10.58ns) CXD3500R – 61 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 150 160 170 190 112 clk 160 clk 164 clk 164 clk 180 208 clk 200 210 86 clk 220 230 240 250 260 270 280 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 140 290 300 PLSSL2/1/0: H/H/H PLLP: LHLHLHLHHHHL (LSB) HP: LLLLLLHLHHLL (LSB) HSTW1/0: H/L HSTP: LLLHHL (LSB) PCGU: HLL (LSB) PCGD: HHLLH (LSB) PCG: L PRGD: LHHHH (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: H HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/H/H (XGA panel, XGA mode) XGA (VESA85: fv 84.99Hz) 1024 × 768 310 320 330 340 350 360 Loop Counter: 1376 clk MCK f: 94.50MHz (10.58ns) CXD3500R – 62 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 390 400 1 10 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 380 20 PLSSL2/1/0: L/L/L DWN: H VP: LLLHHHLL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: H BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: L/L/H PC98 (PC98: fv 56.40Hz) 640 × 400 30 40 47 CXD3500R – 63 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 788 798 808 64 clk 818 828 838 0 10 20 64 clk 30 40 50 70 128 clk 128 clk 120 clk 60 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 778 96 clk 64 clk 64 clk 80 38 clk 90 PLSSL2/1/0: L/L/L PLLP: LLHHLHLLHHHL (LSB) HP: LLLLLLHHLLHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLLH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: L HR: H RGT: H DSP: H SPON: L PO/MODE3/2/1: L/L/H (SVGA panel, PC98 mode) PC98 (PC98: fv 56.40Hz) 640 × 400 110 32 clk 38 clk 80 clk 100 120 130 140 149 Loop Counter: 848 clk MCK f: 21.05MHz (47.50ns) CXD3500R – 64 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 480 485 1 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 474 10 PLSSL2/1/0: L/L/L DWN: H VP: LLHLLLLL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: L BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: H/H/L NTSC (ODD) 640 × 480 20 23 CXD3500R – 65 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 240 243 244 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 231 250 PLSSL2/1/0: L/L/L DWN: H VP: LLHLLLLL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: L BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: H/H/L NTSC (EVEN) 640 × 480 260 266 CXD3500R – 66 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 1530 37 clk 1540 1550 0 10 20 30 40 60 128 clk 128 clk 32 clk 62 clk 80 90 38 clk 96 clk 42 clk 70 62 clk 120 clk 115 clk 50 100 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 1520 110 120 PLSSL2/1/0: L/L/L PLLP: LHHLLLLHLHHL (LSB) HP: LLLLLLHLLLLL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLHH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: H HR: H RGT: H DSP: L SPON: L PO/MODE3/2/1: H/H/L (SVGA panel, VGA mode) NTSC_1 640 × 480 130 140 115 clk 150 160 170 179 Loop Counter: 1560 clk MCK f: 24.54MHz (40.75ns) CXD3500R – 67 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 190 200 210 220 230 240 250 260 270 280 290 300 310 320 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 180 330 340 PLSSL2/1/0: L/L/L PLLP: LHHLLLLHLHHL (LSB) HP: LLLLLLHLLLLL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLHH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: H HR: H RGT: H DSP: L SPON: L PO/MODE3/2/1: H/H/L (SVGA panel, VGA mode) NTSC_2 640 × 480 350 360 370 380 780 789 Loop Counter: 1560 clk MCK f: 24.54MHz (40.75ns) CXD3500R – 68 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 280 288 289 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 276 PLSSL2/1/0: L/L/H DWN: H VP: LLHLHLHL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: L BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: L/H/L PAL (ODD) 762 × 572 300 306 CXD3500R – 69 – XVS XHS ORACT IRACT VD BLK FLDO FRP CLP PRG PCG ENB2 ENB1 HST FRP VCK VST (BLK) HDN HD HSYNC VSYNC 570 576 1 Note) The fifth row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 564 PLSSL2/1/0: L/L/H DWN: H VP: LLHLHLHL (LSB) FRP1/0: L/L VSTFX: L VSTPOL: H VPOL: L VGAV: L BLKON: H BLKPOL: H FMBK: L MBKA: LLLLL (LSB) MBKB: LLLL (LSB) MBKZ: LLLL (LSB) DWN: H PO/MODE3/2/1: L/H/L PAL (EVEN) 762 × 572 10 18 CXD3500R – 70 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 1850 37 clk 1860 1870 0 10 20 30 40 50 70 128 clk 128 clk 120 clk 138 clk 60 90 40 clk 74 clk 74 clk 96 clk 80 50 clk 100 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 1840 50 clk 110 120 PLSSL2/1/0: L/L/H PLLP: LHHHLHLHLHHL (LSB) HP: LLLLLLHLHHHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLLH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: H HR: H RGT: H DSP: L SPON: L PO/MODE3/2/1: L/H/L (SVGA panel, PAL mode) PAL_1 762 × 572 130 140 150 170 clk 160 170 179 Loop Counter: 1880 clk MCK f: 29.38MHz (34.04ns) CXD3500R – 71 – XHS ORACT IRACT WCK RSTW RCK RSTR BLK CLP FRP VCK PRG PCG ENB2 ENB1 HCK2 HCK1 HST HDN HD (BLK) HSYNC MCK 190 200 210 220 230 240 250 260 270 280 290 300 310 320 Note) The third row of the timing chart (BLK) is a pulse indicated as a reference and is not a pulse output from pins. 180 330 340 PLSSL2/1/0: L/L/H PLLP: LHHHLHLHLHHL (LSB) HP: LLLLLLHLHHHL (LSB) HSTW1/0: L/L HSTP: LLLLHH (LSB) PCGU: HLL (LSB) PCGD: LLLLH (LSB) PCG: H PRGD: LLHLL (LSB) FRPP: HLLL (LSB) HCKFX: L HCKM: L HCKPOL: H HPOL: L HDNPOL: H CLPPOL: H CLPW: L CLPP: H HR: H RGT: H DSP: L SPON: L PO/MODE3/2/1: L/H/L (SVGA panel, PAL mode) PAL_2 762 × 572 350 360 370 380 940 950 Loop Counter: 1880 clk MCK f: 29.38MHz (34.04ns) CXD3500R CXD3500R Application Circuit This IC allows direct drive of LCD panels. However, in this case insert resistor of several Ω to several tens of Ω in series. LCD signal processing IC CXA2111R S/H driver IC CXA2112R LCD panel VST VCK PCG TEST8 DWN CLP ENB2 VSS2 TEST9 FRP PRG XFRP SHP1A 49 INV SHP1B SHP2B SHP2A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ENB1 32 50 XVS HD 31 51 XHS BLK 30 52 IRACT HCK2 29 53 ORACT HCK1 28 54 RSTR Line buffer µPD485505 HST 27 55 VSS3 XRGT 26 RGT 25 56 VDD1 CXD3500R 57 RCK VDD0 24 58 RSTW MODE1 22 60 SCTR MODE2 21 61 SCLK MODE3 20 TEST7 18 VSS0 TEST1 5 6 7 8 9 10 11 12 13 14 15 16 TEST6 TEST0 4 TEST5 FLD 3 TEST4 VD 2 TEST3 CKLIM 1 TEST2 CKI2 TTL CLK/2 VSYNC 64 CKI1 FRPCNT XCLR 19 63 HDN RGTCNT 62 SDAT HSYNC Serial interface VSS1 23 59 WCK 10k CKI3 17 1µ /16V DSYNC 0.1µ VSYNC Sync signal input 24 21 HSYNC +5V 9 47µ /16V ∗ PLL IC ∗ PLL IC: Sony CXA3106(A)Q (built-in phase comparator, frequency divider) is recommended. 31 32 CLKL CLKH When not using skip scan, ENB1 and 2 are interchangeable. CXD2112R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 72 – CXD3500R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 + 0.08 0.18 – 0.03 16 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 73 –