ASAHI KASEI [AKD4353] AKD4353 Evaluation board Rev.A for AK4353 GENERAL DESCRIPTION The AKD4353 is an evaluation board for AK4353, 96kHz 24bit D/A converter with DIT. The AKD4353 has a digital interface with AKM’s wave generator using ROM data and AKM’s A/D converter evaluation boards. Therefore, it is easy to evaluate the AK4353. n Ordering guide AKD4353 --- Evaluation board for AK4353 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this.) FUNCTION • On-board clock generator • Compatible with 2 types of interface - Direct interface with AKM’s A/D converter evaluation boards and direct interface with AKM’s signal generator(AKD43XX) by 10pin header - On-board CS8414 as DIR which accepts optical input • BNC connector for external clock input • 10pin header for serial control interface • On-board mute circuit for analog output • Optical output for TX output 2.7∼5.5V GND Opt Out CS8414 (DIR) Opt In DZF Mute ROM or A/D AK4353 10pin Header Divider Rch MCKO External Clock Lch MCKI Clock Generator 10pin Header Control Figure 1. AKD4353 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM061401> ’00/04 -1- ASAHI KASEI [AKD4353] n External analog circuit J1(AOUTL) and J2(AOUTR) are used. The analog output signal range is nominally 3.1Vpp@5V. It is proportional to AVDD (Vout=0.62xAVDD). n Operation sequence 1) Set up the power supply lines. [AVDD] (red) = 2.7∼5.5V : for AVDD of AK4353 [3V] (orange) = 2.7∼5.5V : for DVDD of AK4353 [5V] (red) = 3.4∼5.5V : for logic [AGND] (black)= 0V : for analog ground (including AVSS and DVSS of AK4353) [DGND] (black)= 0V : for logic ground Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4353 should be reset once bringing SW1(-PD) “L” upon power-up. PORT2 CTRL SDA(ACK) SDA/CDTI SCL/CCLK -CS 4) Connect PORT2 with PC. Connect PORT2 with printer port (parallel port) of IBM-AT compatible PC by 10-line flat cable packed with the AKD4353. Take care of the direction of connector. There is a mark at 1pin. The direction of PORT2 is as the following figure. 9 1 10 2 5) Set up the software. Use the software named “AKD4353 Control Program” packed with the AKD4353. n Evaluation mode 1) Using A/D converted data <default> PORT3 (ADC/ROM) is used to interface with various AKM’s A/D converter evaluation boards. In case of using external clock through a BNC connector (J4), select BNC on JP14 (CLK) and short JP15 (XTE). JP6 JP7 JP12 JP13 LRCK BICK DIR_DATA DIR DIR DIR VD ADC ADC GND <KM061401> JP15 XTE JP14 CLK DIR BNC XTL ’00/04 -2- ASAHI KASEI [AKD4353] 2) Ideal sine wave generated by ROM data Digital signals generated by AKD43XX are used. PORT3 (ADC/ROM) is used to interface with AK43XX. Master clock is sent from AKD4353 to AKD43XX and LRCK, BICK, SDTI are supplied from AKD43XX to AKD4353. In case of using external clock through a BNC connector (J4), select “BNC” on JP14 (CLK) and short JP15 (XTE). JP6 JP7 JP12 JP13 LRCK BICK DIR_DATA DIR JP15 XTE JP14 CLK DIR DIR VD ADC ADC GND DIR BNC XTL 3) DIR(CS8414) PORT4 (TORX174) is used for the evaluation using such as test disk. The DIR generates MCKI, BICK, LRCK, SDTI from the received data through optical connector. In this case, the EXT bit of AK4353 should be “1” (External clock mode). Select “RCA” or “OPT” on JP16 (RCA/OPT) in case of using RCA connector (J3) or optical connector (PORT4: TORX174). JP6 JP7 JP12 JP13 LRCK BICK DIR_DATA DIR JP15 XTE JP14 CLK DIR DIR VD ADC ADC GND DIR BNC XTL n Clock (MCLK,BICK,LRCK) set up In case of using evaluation mode 1), JP9,10 and 17 should be set up as follows. They need no care for other evaluation mode. MCLK 128fs JP9 (X_MCLK) x1 256fs x1 512fs x2 1024fs x4 JP10 (X_LRCK) x1/128 BICK JP17 (X_BICK) x1/4 x1/2 x1 x1/8 x1/4 x1/2 x1/8 x1/4 x1/2 x1/8 x1/4 x1/2 32fs 64fs 128fs x1/256 32fs 64fs 128fs x1/256 32fs 64fs 128fs x1/256 32fs 64fs 128fs Table 1. Clock set up <KM061401> default ’00/04 -3- ASAHI KASEI [AKD4353] n DIP switch (SW2) set up No.1 to 5 set the mode of AK4353 and No.6 to 8 set the mode of CS8414. No. 1 2 3 4 5 6 7 8 Pin CAD1 CAD0 I2C TTL TST M2 M1 M0 OFF <default> ON Chip address (2bit) 3-wire serial I2C bus CMOS level TTL level always “ON” Digital interface format of CS8414 (See table 3.) (Note) Table 2. DIP switch set-up (Note: M2-0 should be selected at only evaluation mode 3. In other mode, these should be “OFF”.) Mode 0 1 2 3 4 5 Format M2 M1 M0 JP9 DIF2 DIF1 DIF0 16bit, LSB justified 1 0 1 THR 0 0 0 18bit, LSB justified 1 1 0 THR 0 0 1 20bit, LSB justified 0 1 0 24bit, LSB justified 0 1 1 24bit, MSB justified 0 0 0 INV 1 0 0 I2S 0 1 0 THR 1 0 1 Table 3. Digital interface format set-up (Note: 1=”ON”, 0=”OFF”. DIF2-0 should be selected by serial control. CS8414 does not correspond to 20/24bit LSB justified format.) n Serial control mode The AK4353 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10-line flat cable packed with the AKD4353. There are two modes: 3-wire serial & I2C bus. JP4 should be shorted at 3-wire serial control mode. Chip address can be selected by SW2(MODE)-No.1(CAD1) and No.2(CAD0). n Other jumper pins set up [JP1](GND): Analog ground and digital ground Open: Separated <default> Short: Common (The connector “DGND” can be open.) [JP2](5V-3V): DVDD of AK4353 and power supply to logic Open: Independent <default> Short: Same (The connector “3V” should be open.) <KM061401> ’00/04 -4- ASAHI KASEI [AKD4353] [JP3](DVDD): DVDD of AK4353 3V: Independent of AVDD <default> AVDD: Same as AVDD (The connector “3V” can be open.) [JP5](DZF): Mute circuit ON: Used (Analog output is muted when DZF=”H”.) <default> OFF: Not used [JP11](SDTI): SDTI of AK4353 DATA: Data is input <default> GND: “0” data is input n The function of the toggle SW (SW1) Upper-side is “H” and lower-side is “L”. [SW1] (-PD): Resets the AK4353. Keep “H” during normal operation. n The indication content for LED [LED1] (VERF): Monitors VERF pin of the CS8414. LED turns on when some error has occurred to CS8414. [LED2] (PREM): Indicates whether the input data is pre-emphasis or not. LED turns on when the data is pre-emphasised. <KM061401> ’00/04 -5- ASAHI KASEI [AKD4353] MEASUREMENT RESULTS [Measurement condition] • Measurement unit : ROHDE & SCHWARZ, UPD04 • MCLK : 256fs • BICK : 64fs • fs : 44.1kHz, 96kHz • BW : 20Hz∼20kHz (fs=44.1kHz), 20Hz∼40kHz (fs=96kHz) • Bit : 24bit • Power Supply : AVDD=DVDD=5V, 3V • Interface : DIR (fs=44.1kHz), Serial Multiplex (fs=96kHz) • Temperature : Room fs=44.1kHz Parameter S/(N+D) DR S/N fs=96kHz Parameter S/(N+D) DR S/N Input signal 1kHz, 0dB 1kHz, -60dB no signal Input signal 1kHz, 0dB 1kHz, -60dB no signal Measurement filter 20kLPF 20kLPF 20kLPF, A-weighted 20kLPF 20kLPF, A-weighted 5V 97.0dB 99.0dB 102.3dB 99.0dB 102.3dB 3V 93.6dB 94.6dB 97.9dB 94.6dB 97.9dB Measurement filter 40kLPF 40kLPF 20kLPF, A-weighted 40kLPF 20kLPF, A-weighted 5V 92.5dB 97.0dB 101.5dB 97.0dB 101.5dB 3V 90.8dB 92.6dB 97.1dB 92.6dB 97.1dB [Measurement condition] • Measurement unit : Audio Precision, System two, Cascade • MCLK : 256fs • BICK : 64fs • fs : 44.1kHz, 96kHz • BW : 10Hz∼20kHz (fs=44.1kHz), 10Hz∼40kHz (fs=96kHz) • Bit : 24bit • Power Supply : AVDD=DVDD=5V, 3V • Interface : DIR • Temperature : Room fs=44.1kHz Parameter S/(N+D) DR S/N fs=96kHz Parameter S/(N+D) DR S/N Input signal 1kHz, 0dB 1kHz, -60dB no signal Input signal 1kHz, 0dB 1kHz, -60dB no signal Measurement filter 20kLPF 20kLPF 22kLPF, A-weighted 20kLPF 22kLPF, A-weighted 5V 97.4dB 98.8dB 101.6dB 98.6dB 101.8dB 3V 93.8dB 94.3dB 97.3dB 94.3dB 97.3dB Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted 5V 94.5dB 96.9dB 101.9dB 96.8dB 101.9dB 3V 91.5dB 92.2dB 97.3dB 92.2dB 97.3dB <KM061401> ’00/04 -6- ASAHI KASEI [AKD4353] n Plots [Measurement condition] • Measurement unit : Audio Precision, System two • MCLK : 256fs • BICK : 64fs • fs : 44.1kHz, 96kHz • Bit : 24bit • Power Supply : AVDD=DVDD=5V • Interface : DIR • Temperature : Room [Contents] 1. fs=44.1kHz Figure 1-1. THD+N vs. Input level Figure 1-2. THD+N vs. Input frequency Figure 1-3. Linearity Figure 1-4. Frequency response Figure 1-5. Cross-talk Figure 1-6. FFT (1kHz, 0dBFS) Figure 1-7. FFT (1kHz, -60dBFS) Figure 1-8. FFT (noise floor) Figure 1-9. FFT (out-of-band noise, ∼130kHz) 2. fs=96kHz Figure 2-1. THD+N vs. Input level Figure 2-2. THD+N vs. Input frequency Figure 2-3. Linearity Figure 2-4. Frequency response Figure 2-5. FFT (1kHz, 0dBFS) Figure 2-6. FFT (1kHz, -60dBFS) Figure 2-7. FFT (noise floor) <KM061401> ’00/04 -7- ASAHI KASEI [AKD4353] AKM AK4353 THD+N vs Input Level (AVDD=DVDD=5V, fs=44.1kHz, fin=1kHz) -90 -91 -92 -93 -94 -95 -96 -97 -98 d B r A -99 -100 -101 -102 -103 -104 -105 -106 -107 -108 -109 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 1-1. THD+N vs. Input level AKM AK4353 THD+N vs fin (AVDD=DVDD=5V, fs=44.1kHz, Input Level=0dBFS) -80 -81 -82 -83 -84 -85 -86 -87 -88 d B r A -89 -90 -91 -92 -93 -94 -95 -96 -97 -98 -99 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 1-2. THD+N vs. Input frequency <KM061401> ’00/04 -8- ASAHI KASEI [AKD4353] AKM AK4353 Linearity (AVDD=DVDD=5V, fs=44.1kHz, fin=1kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 1-3. Linearity AKM AK4353 Frequency Response (AVDD=DVDD=5V, fs=44.1kHz, Input Level=0dBFS) +0.5 +0.4 +0.3 +0.2 +0.1 d B r +0 A -0.1 -0.2 -0.3 -0.4 -0.5 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure 1-4. Frequency response <KM061401> ’00/04 -9- ASAHI KASEI [AKD4353] AKM AK4353 Cross-talk (AVDD=DVDD=5V, fs=44.1kHz, Input Level=0dBFS) -100 -101 -102 -103 -104 -105 -106 -107 -108 -109 d B -110 -111 -112 -113 -114 -115 -116 -117 -118 -119 -120 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 1-5. Cross-talk AKM AK4353 FFT (AVDD=DVDD=5V, fs=44.1kHz, fin=1kHz, Input Level=0dBFS) FFT points=16384, Avg=8, Window=Equirriple +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k Hz Figure 1-6. FFT (1kHz, 0dBFS) <KM061401> ’00/04 - 10 - ASAHI KASEI [AKD4353] AKM AK4353 FFT (AVDD=DVDD=5V, fs=44.1kHz, fin=1kHz, Input Level=-60dBFS) FFT points=16384, Avg=8, Window=Equirriple +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 1-7. FFT (1kHz, -60dBFS) AKM AK4353 FFT (AVDD=DVDD=5V, fs=44.1kHz, No signal input) FFT points=16384, Avg=8, Window=Equirriple +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 1-8. FFT (noise floor) <KM061401> ’00/04 - 11 - ASAHI KASEI AKM [AKD4353] AK4353 FFT (Outband noise ~130kHz; AVDD=DVDD=5V, fs=44.1kHz, No signal input) FFT points=16384, Avg=8, Window=Equirriple +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 600 1k 2k 5k 10k 20k 50k 100k Hz Figure 1-9. FFT (out-of-band noise) <KM061401> ’00/04 - 12 - ASAHI KASEI [AKD4353] AKM AK4353 THD+N vs Input Level (AVDD=DVDD=5V, fs=96kHz, fin=1kHz) -90 -91 -92 -93 -94 -95 -96 -97 -98 d B r A -99 -100 -101 -102 -103 -104 -105 -106 -107 -108 -109 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 2-1. THD+N vs. Input level AKM AK4353 THD+N vs fin (AVDD=DVDD=5V, fs=96kHz, Input Level=0dBFS) -80 -81 -82 -83 -84 -85 -86 -87 -88 d B r A -89 -90 -91 -92 -93 -94 -95 -96 -97 -98 -99 -100 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 2-2. THD+N vs. Input frequency <KM061401> ’00/04 - 13 - ASAHI KASEI [AKD4353] AKM AK4353 Linearity (AVDD=DVDD=5V, fs=96kHz, fin=1kHz) +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 1-3. Linearity AKM AK4353 Frequency Response (AVDD=DVDD=5V, fs=96kHz, Input Level=0dBFS) +0.5 +0.4 +0.3 +0.2 +0.1 d B r +0 A -0.1 -0.2 -0.3 -0.4 -0.5 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Hz Figure 1-4. Frequency response <KM061401> ’00/04 - 14 - ASAHI KASEI [AKD4353] AKM AK4353 FFT (AVDD=DVDD=5V, fs=96kHz, fin=1kHz, Input Level=0dBFS) FFT points=16384, Avg=8, Window=Equirriple +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 40k 20k 40k Hz Figure 2-5. FFT (1kHz, 0dBFS) Upper: Notch OFF, Lower: Notch ON AKM AK4353 FFT (AVDD=DVDD=5V, fs=96kHz, fin=1kHz, Input Level=-60dBFS) FFT points=16384, Avg=8, Window=Equirriple +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k Hz Figure 2-6. FFT (1kHz, -60dBFS) <KM061401> ’00/04 - 15 - ASAHI KASEI [AKD4353] AKM AK4353 FFT (AVDD=DVDD=5V, fs=96kHz, No signal input) FFT points=16384, Avg=8, Window=Equirriple +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 2-7. FFT (noise floor) <KM061401> ’00/04 - 16 - ASAHI KASEI [AKD4353 Control Program] AKD4353 Control Program ver 2.0 operation manual 1. Connect IBM-AT compatible PC with AKD4353 by 10-line type flat cable (packed with AKD4353). Take care of the direction of 10pin Header (Refer to manual of AKD4353). 2. Start up “WINDOWS 95” or “WINDOWS 98”. 3. Insert the floppy-disk labeled “AKD4353 Control Program ver 2.0” into the floppy-disk drive. 4. Set up “MS-DOS” from start menu. 5. Change directory to the floppy-disk drive(ex.a:) at MS-DOS prompt. 6. Type “ak4353”. 7. Then follow the displayed comment (See the following). ==================== <<Operating flow>> ===================== Input Control Mode (3-wire serial or I2C bus) Input Chip Address (2bit) Write data/ Display register map/ Reset etc.à loop ========================================================= ‘00/2 -1- ASAHI KASEI [AKD4353 Control Program] At first the following message is displayed: ****** AK4353 Control Program ver 2.0 , '00/2 ****** copyright(c) 2000, Asahi Kasei Microsystems co.,ltd. All rights reserved. Input control mode 0: 3-wire Serial, 1: I2C Bus : Input 0 or 1. Then the following is displayed: Input Chip Address(CAD1,CAD0) (2 figure, binary) = Input chip address in 2 figures of binary. Set CAD1 and CAD0 before the AKD4353 is powered up. When hanging CAD1 and CAD0, set SW1(-PD) “L”, then “H” after that. After chip address is defined, the following default register map is displayed (Loop starts from here): 3-wire Serial control mode CAD1-0=00 ----------------------------------ADDR = 00 : 0B <Control 1> ( 0 0 0 0 DIF2 DIF1 DIF0 RSTN ) ADDR = 01 : 01 <Control 2> ( 0 0 DFS1 DFS0 CKS2 CKS1 CKS0 RSTN ) ADDR = 02 : 94 <Control 3> ( PL3 PL2 PL1 PL0 DEM1 DEM0 ATC SMUTE) ADDR = 03 : FF <Lch ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 04 : FF <Rch ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 05 : 00 <TX> ( 0 0 0 0 0 0 V TXE ) ADDR = 06 : 00 <Ch Status 1>( 0 CS29 CS28 CS24 CS3 CS2 CS2 CS1 ) ADDR = 07 : 04 <Ch Status 2>( CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8 ) Input 1(Write), R(Reset), T(Table), I(Increment), D(Decrement) or S(Stop) : 1) If you input “1”, you can write data to AK4353. You can write data to AK4353 Input Register Address (2 figure, hex) (00-07) = Input register address in 2 figures of hexadecimal. Then current data of this address is displayed: ADDR = 00 : 0B <Control 1> ( 0 0 0 0 DIF2 DIF1 DIF0 RSTN ) 0 0 0 0 1 0 1 1 Input Register Data (2 figure, hex) (00-FF) = You can write control data to this address. Input control data in 2 figures of hexadecimal. Refer to datasheet of AK4353. Then the data written to this address is displayed: ADDR = 00 : 09 <Control 1> ( 0 0 0 0 DIF2 DIF1 DIF0 RSTN ) 0 0 0 0 1 0 0 1 ‘00/2 -2- ASAHI KASEI [AKD4353 Control Program] 2) If you input “R” or “r”, this program writes default data to all register addresses. 3) If you input “T” or “t”, current register map is displayed. 4) If you input “I” or “i”, this program increment data of current address by 1 (only for addr=03H or 04H). You can increment ATT value by 1step. 5) If you input “D” or “d”, this program decrement data of current address by 1 (only for addr=03H or 04H). You can decrement ATT value by 1step. 6) If you input “S” or “s”, this program is terminated. ‘00/2 -3- 5 4 3 2 1 JP1 GND Analog Ground JP2 3V 5V-3V 2 DVDD C5 0.1u for 74LVC541 C8 0.1u C9 + 0.1u for 74HCU04, 74LS07, 74HC14, 74AC74, 74HC4040 DVDD C11 10u L3 2 5V C14 0.1u 1k C160.1u MCKO C 5V R5 10k U3A H L C20 2 3 74HC14 U3B 4 2 3 4 5 6 7 8 9 MCKI BICK SDTI LRCK 74HC14 1 19 0.1u SW1 -PD 5 U3C U2 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 G1 G2 74LVC541 18 17 16 15 14 13 12 11 R29 R30 R31 R32 R33 (short) (short) (short) (short) (short) 1 3 JP3 DVDD R2 (short) 5.1 U? 1 MCKO DZF 2 TX NC 3 DVDD AVDD 4 DVSS AVSS 5 MCKI VCOM 6 BICK AOUTL 7 SDTI AOUTR 8 LRCK CAD0 9 CAD1 10 PDN CSN I2C 11 SCL/CCLK TTL 12 SDA/CDTI TST 1 C12 10u 11 74HC14 U3E 10 13 74HC14 U3F 12 13 U4C 1 74LS07 3 5V A 10 8 6 4 2 PORT2 9 -CS 7 SCK/CCLK 5 SDA/CDTI 3 SDA(ACK) 1 R3 220 AOUTL R4 27k C19 10u C R6 220 AOUTR R7 27k 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CAD1 CAD0 I2C TTL TST M2 M1 M0 DVDD B MODE 47k 2 SW2 U4B 4 74LS07 R10 10k R11 10k R12 10k R13 10k 11 U4E R14 10 DVDD A 10k 74LS07 U4D 8 9 CTRL Title Size 74LS07 A4 Date: 5 C15 10u 74LS07 74HC14 R1551 R1651 JP4 R1751 3-WIRE R1851 U4A C10 10u DZF 6 74LS07 U4F 12 AVDD2 C13 0.1u 24 23 22 21 20 19 18 17 16 15 14 13 RP1 5 AVDD 1 10u C17 0.1u B 9 2 C3 47u + AK4353 6 74HC14 U3D 8 1 M0 M1 M2 R1 (short) C2 47u 2 4 3 2 1 TOTX174 1 + 3V PORT1 5 IN VCC IF 6 GND D1 C1 47u + 6 C7 0.1u D L2 + 5 C6 0.1u AVDD + C4 0.1u L1 + 5V D + Digital Ground 4 3 2 Document Number AKD4353 Rev AK4353 A Monday, November 15, 1999 Sheet 1 1 of 2 2 0.1u D 3 TR1 RN1202 (10k,10k) OFF AVDD2 TR2 RN2202 (10k,10k) 3 2 C21 JP5 DZF D 1 ON DZF 1 1 3 1 4 2 5 R19 3 TR3 2SC3327 2 10k J1 AOUTL 1 1 AOUTL 3 AVDD2 TR5 RN2202 (10k,10k) 1 2 3 2 TR4 RN1202 (10k,10k) R20 3 TR6 2SC3327 J2 AOUTR 2 10k AOUTR JP6 LRCK X_LRCK ADC DIR_LRCK DIR X_BICK ADC DIR_BICK DIR C C LRCK JP7 BICK 1 THR U7A 1 2 INV VD 74HCU04 JP12 10k D 5 CLK DIR_DATA 12 D 11 CLK Q 6 74AC74 1 1 LED1 2 R23 VERF 1k 1 3 0.1u 10u 2 PREM R25 1k 1 OPT TORX174 C28 JP16 RCA/OPT 3 RCA J3 RCA R27 75 2 0.01u MCKI X_BICK X_BICK x1/128 x1/256 X_LRCK JP10 X_LRCK B 13 C30 DIR_LRCK DIR_BICK 0.1u U9 C Cd/F1 Cc/F0 Cb/E2 Ca/E1 C0/E0 VD+ DGND RXP RXN FSYNC SCK CS12/FCK U VERF Ce/F2 SDATA ERF M1 M0 VA+ AGND FILT MCK M2 M3 SEL CBL 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1M U7D 8 C23 10u U7E 9 10 74HCU04 M1 M0 C25 1 R24 JP14 CLK DIR BNC XTL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X1 11.2896MHz 2 JP15 11 XTE 74HCU04 0.1u C26 C27 (open) (open) C29 M2 R26 1k U7C 47n 6 5 74HCU04 C31 CS8414 A J4 BNC R28 51 Title 0.01u Size A3 Date: 5 5 6 7 8 Q 8 74AC74 2 74HCU04 L4 + LED2 +C22 U5 MCKO U7B 4 10u C24 1 2 3 4 x1 x1/2 x1/4 x1/8 74HCU04 1 4 3 2 1 9 7 6 5 3 2 4 13 12 14 15 1 U7F 1 5 PORT4 6 GND VCC GND 5 OUT Q1 Q2 RST Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 74HC4040 12 1 VD 2 6 9 Q CLK 5V 2 R22 1k JP13 DIR L5 47u A U8B Q CL 3 13 2 B 5V 11 10 U8A 3 DATA R21 PR SDTI 4 2 PR JP11 SDTI ADC/ROM 5V 3 GND U6 10 x1 x2 x4 X_MCLK 3 PORT3 10 9 8 7 6 CL 1 2 3 4 5 JP9 1 GND MCLK BICK LRCK SDATA AD/ROM JP8 BICK_PHASE 2 BICK 4 3 2 Document Number AKD4353 Rev Interface Monday, November 15, 1999 Sheet 1 A 2 of 2 IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. 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