DATASHEET CA3338, CA3338A FN1850 Rev 4.00 July 2004 CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters The CA3338 family are CMOS/SOS high speed R2R voltage output digital-to-analog converters. They can operate from a single +5V supply, at video speeds, and can produce “rail-to-rail” output swings. Internal level shifters and a pin for an optional second supply provide for an output range below digital ground. The data complement control allows the inversion of input data while the latch enable control provides either feedthrough or latched operation. Both ends of the R2R ladder network are available externally and may be modulated for gain or offset adjustments. In addition, “glitch” energy has been kept very low by segmenting and thermometer encoding of the upper 3 bits. The CA3338 is manufactured on a sapphire substrate to give low dynamic power dissipation, low output capacitance, and inherent latch-up resistance. Features • CMOS/SOS Low Power • R2R Output, Segmented for Low “Glitch” • CMOS/TTL Compatible Inputs • Fast Settling: (Typ) to 1/2 LSB . . . . . . . . . . . . . . . . . . 20ns • Feedthrough Latch for Clocked or Unclocked Use • Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 LSB • Data Complement Control • High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . . 50MHz • Unipolar or Bipolar Operation • Pb-free Available Applications Ordering Information • TV/Video Display PART NUMBER LINEARITY (INL, DNL) TEMP. RANGE (°C) PKG. PACKAGE DWG. # CA3338E 1.0 LSB -40 to 85 16 Ld PDIP E16.3 CA3338EZ (Note) 1.0 LSB -40 to 85 16 Ld PDIP E16.3 (Pb-free) CA3338AE 0.75 LSB -40 to 85 16 Ld PDIP E16.3 CA3338AEZ (Note) 0.75 LSB -40 to 85 16 Ld PDIP E16.3 (Pb-free) CA3338M 1.0 LSB -40 to 85 CA3338MZ (Note) 1.0 LSB -40 to 85 CA3338AM 0.75 LSB CA3338AMZ (Note) 0.75 LSB • Digital Waveform Generator • Direct Digital Synthesis Pinout CA3338, CA3338A (PDIP, SOIC) TOP VIEW D7 1 16 VDD 16 Ld SOIC M16.3 D6 2 15 LE 16 Ld SOIC M16.3 (Pb-free) D5 3 14 COMP D4 4 13 VREF+ -40 to 85 16 Ld SOIC M16.3 D3 5 12 VOUT -40 to 85 16 Ld SOIC M16.3 (Pb-free) D2 6 11 VREF - D1 7 10 VEE VSS 8 9 D0 Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. FN1850 Rev 4.00 July 2004 • High Speed Oscilloscope Display Page 1 of 10 CA3338, CA3338A Functional Diagram 16 13 VDD VREF+ 8R LE 15 8R 12 8R 3-BIT TO 7-LINE THERMOMETER ENCODER 14 COMP D7 D6 D5 D4 D3 D2 D1 D0 VSS VOUT 8R 4R R 1 2 3 4 5 4R LEVEL SHIFTERS FEEDTHROUGH LATCHES 2R 2R 2R 6 2R R R R R 7 9 8 2R 2R R R 2R 11 VREF- 10 R 160 FN1850 Rev 4.00 July 2004 VEE Page 2 of 10 CA3338, CA3338A Absolute Maximum Ratings Thermal Information DC Supply-Voltage Range . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V (VDD - VSS or VDD - VEE, Whichever is Greater) Input Voltage Range Digital Inputs (LE, COMP D0 - D7). . . . VSS - 0.5V to VDD + 0.5V Analog Pins (VREF+, VREF -, VOUT) . . . .VDD - 8V to VDD + 0.5V DC Input Current Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . . 20mA Recommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5V Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) Plastic Package, E suffix, M suffix . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF - = GND, LE Clocked at 20MHz, RL 1 M, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS 8 - - Bits - - 1 LSB - - 0.75 LSB CA3338 - - 0.75 LSB CA3338A - - 0.5 LSB CA3338 - - 0.75 LSB CA3338A - - 0.5 LSB - - 0.25 LSB - MHz ACCURACY Resolution Integral Linearity Error See Figure 4 CA3338 CA3338A Differential Linearity Error Gain Error Offset Error See Figure 4 Input Code = FFHEX , See Figure 3 Input Code = 00HEX; See Figure 3 DIGITAL INPUT TIMING Update Rate To Maintain 1/2 LSB Settling DC 50 Update Rate VREF - = VEE = -2.5V, VREF+ = +2.5V DC 20 - MHz Set Up Time tSU1 For Low Glitch - -2 - ns Set Up Time tSU2 For Data Store - 8 - ns Hold Time tH For Data Store - 5 - ns Latch Pulse Width tW For Data Store - 5 - ns VREF - = VEE = -2.5V, VREF+ = +2.5V - 25 - ns Latch Pulse Width tW OUTPUT PARAMETERS RL Adjusted for 1VP-P Output Output Delay tD1 From LE Edge - 25 - ns Output Delay tD2 From Data Changing - 22 - ns Rise Time tr 10% to 90% of Output - 4 - ns Settling Time tS 10% to Settling to 1/2 LSB Output Impedance VREF+ = 6V, VDD = 6V Glitch Area Glitch Area FN1850 Rev 4.00 July 2004 VREF - = VEE = -2.5V,VREF+ = +2.5V - 20 - ns 120 160 200 - 150 - pV/s - 250 - pV/s Page 3 of 10 CA3338, CA3338A TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF - = GND, LE Clocked at 20MHz, RL 1 M, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS REFERENCE VOLTAGE VREF+ Range (+) Full Scale, Note 2 VREF - + 3 - VDD V VREF - Range (-) Full Scale, Note 2 VEE - VREF+ - 3 V VREF+ Input Current VREF+ = 6V, VDD = 6V - 40 50 mA SUPPLY VOLTAGE Static IDD or IEE Dynamic IDD or IEE LE = Low, D0 - D7 = High - 100 220 A LE = Low, D0 - D7 = Low - - 100 A VOUT = 10MHz, 0V to 5V Square Wave - 20 - mA Dynamic IDD or IEE VOUT = 10MHz, 2.5V Square Wave - 25 - mA VDD Rejection 50kHz Sine Wave Applied - 3 - mV/V 50kHz Sine Wave Applied - 1 - mV/V 2 - - V VEE Rejection DIGITAL INPUTS D0 - D7, LE, COMP High Level Input Voltage Note 2 Low Level Input Voltage Note 2 - - 0.8 V Leakage Current - 1 5 A Capacitance - 5 - pF - 200 - ppm/×oC TEMPERATURE COEFFICIENTS Output Impedance NOTE: 2. Parameter not tested. but guaranteed by design or characterization. FN1850 Rev 4.00 July 2004 Page 4 of 10 CA3338, CA3338A Pin Descriptions PIN NAME 1 D7 2 D6 Input 3 D5 Data 4 D4 Bits 5 D3 (High = True) 6 D2 7 D1 8 VSS 9 D0 10 VEE 11 VREF - 12 VOUT DESCRIPTION INPUT DATA Most Significant Bit LATCH ENABLE tD2 OUTPUT VOLTAGE Digital Ground 10% 1/ LSB 2 Latch Operation Analog Output Data is fed from input to output while LE is low: LE should be tied low for non-clocked operation. COMP 15 LE 16 VDD Data Complement Control input. Active High Latch Enable Input. Active Low Digital Power Supply, +5V Digital Signal Path The digital inputs (LE, COMP, and D0 - D7) are of TTL compatible HCT High Speed CMOS design: the loading is essentially capacitive and the logic threshold is typically 1.5V. The 8 data bits, D0 (weighted 20) through D7 (weighted 27), are applied to Exclusive OR gates (see Functional Diagram). The COMP (data complement) control provides the second input to the gates: if COMP is high, the data bits will be inverted as they pass through. The input data and the LE (latch enable) signals are next applied to a level shifter. The inputs, operating between the levels of VDD and VSS , are shifted to operate between VDD and VEE . VEE optionally at ground or at a negative voltage, will be discussed under bipolar operation. All further logic elements except the output drivers operate from the VDD and VEE supplies. The upper 3 bits of data, D5 through D7, are input to a 3-to-7 line bar graph encoder. The encoder outputs and D0 through D4 are applied to a feedthrough latch, which is controlled by LE (latch enable). INPUT DATA tW DATA FEEDTHROUGH tH tSU2 LATCHED FIGURE 1. DATA TO LATCH ENABLE TIMING FN1850 Rev 4.00 July 2004 90% Reference Voltage Negative Input 14 LATCHED 1/ LSB 2 FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING Analog Ground VREF+ Reference Voltage Positive Input LATCH ENABLE tS tr Least Significant Bit. Input Data Bit 13 tSU1 tD1 Non-clocked operation or changing data while LE is low is not recommended for applications requiring low output “glitch” energy: there is no guarantee of the simultaneous changing of input data or the equal propagation delay of all bits through the converter. Several parameters are given if the converter is to be used in either of these modes: tD2 gives the delay from the input changing to the output changing (10%), while tSU2 and tH give the set up and hold times (referred to LE rising edge) needed to latch data. See Figures 1 and 2. Clocked operation is needed for low “glitch” energy use. Data must meet the given tSU1 set up time to the LE falling edge, and the tH hold time from the LE rising edge. The delay to the output changing, tD1 , is now referred to the LE falling edge. There is no need for a square wave LE clock; LE must only meet the minimum tW pulse width for successful latch operation. Generally, output timing (desired accuracy of settling) sets the upper limit of usable clock frequency. Output Structure The latches feed data to a row of high current CMOS drivers, which in turn feed a modified R2R ladder network. The “N” channel (pull down) transistor of each driver plus the bottom “2R” resistor are returned to VREF - this is the (-) fullscale reference. The “P” channel (pull up) transistor of each driver is returned to VREF+, the (+) full-scale reference. In unipolar operation, VREF- would typically be returned to analog ground, but may be raised above ground (see specifications). There is substantial code dependent current that flows from VREF+ to VREF - (see VREF+ input current in specifications), so VREF - should have a low impedance path to ground. In bipolar operation, VREF - would be returned to a negative voltage (the maximum voltage rating to VDD must be Page 5 of 10 CA3338, CA3338A observed). VEE , which supplies the gate potential for the output drivers, must be returned to a point at least as negative as VREF -. Note that the maximum clocking speed decreases when the bipolar mode is used. STRAIGHT LINE FROM “0” SCALE TO FULL SCALE VOLTAGE = IDEAL TRANSFER CURVE = ACTUAL TRANSFER CURVE The ideal 8-bit D/A would have an output equal to VREF - with an input code of 00HEX (zero scale output), and an output equal to 255/256 of VREF+ (referred to VREF -) with an input code of FFHEX (full scale output). The difference between the ideal and actual values of these two parameters are the OFFSET and GAIN errors, respectively; see Figure 3. If the code into an 8-bit D/A is changed by 1 count, the output should change by 1/255 (full scale output - zero scale output). A deviation from this step size is a differential linearity error, see Figure 4. Note that the error is expressed in fractions of the ideal step size (usually called an LSB). Also note that if the (-) differential linearity error is less (in absolute numbers) than 1 LSB, the device is monotonic. (The output will always increase for increasing code or decrease for decreasing code). If the code into an 8-bit D/A is at any value, say “N”, the output voltage should be N/255 of the full scale output (referred to the zero scale output). Any deviation from that output is an integral linearity error, usually expressed in LSBs. See Figure 4. OUTPUT VOLTAGE AS A FRACTION OF VREF+ - VREF - Note that OFFSET and GAIN errors do not affect integral linearity, as the linearity is referenced to actual zero and full scale outputs, not ideal. Absolute accuracy would have to also take these errors into account. GAIN ERROR (SHOWN -) 255/256 = IDEAL TRANSFER CURVE = ACTUAL TRANSFER CURVE 254/256 253/256 OFFSET ERROR (SHOWN +) 3/256 2/256 1/256 0 00 01 02 03 FD FE FF INPUT CODE IN HEXADECIMAL (COMP = LOW) FIGURE 3. D/A OFFSET AND GAIN ERROR FN1850 Rev 4.00 July 2004 OUTPUT VOLTAGE Static Characteristics INTEGRAL LINEARITY ERROR (SHOWN -) A B C 0 00 A = IDEAL STEP SIZE (1/255 OF FULL SCALE -“0” SCALE VOLTAGE) B - A = +DIFFERENTIAL LINEARITY ERROR C - A = -DIFFERENTIAL LINEARITY ERROR INPUT CODE FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY ERROR Dynamic Characteristics Keeping the full-scale range (VREF+ - VREF -) as high as possible gives the best linearity and lowest “glitch” energy (referred to 1V). This provides the best “P” and “N” channel gate drives (hence saturation resistance) and propagation delays. The VREF+ (and VREF - if bipolar) terminal should be well bypassed as near the chip as possible. “Glitch” energy is defined as a spurious voltage that occurs as the output is changed from one voltage to another. In a binary input converter, it is usually highest at the most significant bit transition (7FHEX to 80HEX for an 8 bit device), and can be measured by displaying the output as the input code alternates around that point. The “glitch” energy is the area between the actual output display and an ideal one LSB step voltage (subtracting negative area from positive), at either the positive or negative-going step. It is usually expressed in pV/s. The CA3338 uses a modified R2R ladder, where the 3 most significant bits drive a bar graph decoder and 7 equally weighted resistors. This makes the “glitch” energy at each 1/8 scale transition (1FHEX to 20HEX , 3FHEX to 40HEX , etc.) essentially equal, and far less than the MSB transition would otherwise display. For the purpose of comparison to other converters, the output should be resistively divided to 1V full scale. Figure 5 shows a typical hook-up for checking “glitch” energy or settling time. The settling time of the A/D is mainly a function of the output resistance (approximately 160 in parallel with the load resistance) and the load plus internal chip capacitance. Both “glitch” energy and settling time measurements require very good circuit and probe grounding: a probe tip connector such as Tektronix part number 131-0258-00 is recommended. Page 6 of 10 CA3338, CA3338A CA3338 +5V 15 LE CLOCK +2.5V -2.5V 1-7, 9 D0 - D7 8 DATA BITS 12 VOUT 16 +5V REMOTE VOUT 13 VREF+ VDD R1 + 14 8 R3 PROBE TIP OR BNC CONNECTOR + VSS R2 11 VREF - COMP 10 VEE + DIGITAL GROUND ANALOG GROUND FUNCTION CONNECTOR R1 R2 R3 VOUT (P-P) Probe Tip 82 62 N/C 1V Match 93 Cable BNC 75 160 93 1V Match 75 Cable BNC 18 130 75 1V Match 50Cable BNC Short 75 50 0 79V Oscilloscope Display NOTES: 3. VOUT(P-P) is approximate, and will vary as ROUT of D/A varies. 4. All drawn capacitors are 0.1F multilayer ceramic/4.7F tantalum. 5. Dashed connections are for unipolar operation. Solid connection are for bipolar operation. FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT +6V 4.7F TAN + 0.1F CER. CA3338 15 LE VOUT 12 1-7, 9 8 DATA BITS + 4.7F TAN 0.1F CER. 14 8 VDD VREF+ COMPVREF VSS +3.00V AT 25mA 14 392 1% 3 13 11 + 10k 9 + 1. Both VREF+ pin and 392 resistor should be bypassed within 1/4 inch. 2. Keep nodal capacitance at CA3450 pin 3 as low as possible. UP TO 5 OUTPUT LINES FOR R = 75, 3 LINES FOR R = 50 R VOUT1 6 R VOUT = 1.5VPEAK 4, 5, 12, 13 R 392 1% NOTES: 11 CA3450 - 1k VEE 10 4.7F TAN 16 +5V 5pF 7, 8 D0 - D7 0.1F CER. CLOCK 0.1F CER. + ADJUST OFFSET VOUTN R 4.7F TAN -6V 3. VOUT Range = 3V at CA3450. FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES FN1850 Rev 4.00 July 2004 Page 7 of 10 CA3338, CA3338A TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND VREF VREF+ VREF STEP SIZE 2.50V 5.00V 4.608V 2.56V 5.12V -2.56V -2.50V 0 0 0 0.0200V 0.0195V 0.0180V 0.0200V 0.0195V Input Code 111111112=FFHEX1 5.1000V 4.9805V 4.5900V 2.5400V 2.4805V 11111102=FEHEX 5.0800 4.9610 4.5720 2.5200 2.4610 • • • 100000012=81HEX 100000002=80HEX 011111112=7FHEX HANDLING All inputs and outputs of CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in AN6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.” OPERATING 2.5800 2.5600 2.5400 2.5195 2.5000 2.4805 2.3220 0.0200 0.0195 2.3040 0.0000 0.0000 2.2860 - 0.0200 -0.0195 0.0200 0.0000 0.0195 0.0000 0.0180 0.0000 • • • 000000012=01HEX 000000002=00HEX Operating and Handling Considerations -2.5400 -2.4805 -2.5600 -2.5000 Applications The output of the CA3338 can be resistively divided to match a doubly terminated 50 or 75 line, although peak-to-peak swings of less than 1V may result. The output magnitude will also vary with the converter’s output impedance. Figure 5 shows such an application. Note that because of the HCT input structure, the CA3338 could be operated up to +7.5V VDD and VREF+ supplies and still accept 0V to 5V CMOS input voltages. OPERATING VOLTAGE During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause the absolute maximum ratings to be exceeded. INPUT SIGNALS To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS . Input currents must not exceed 20mA even when the power supply is off. UNUSED INPUTS A connection must be provided at every input terminal. All unused input terminals must be connected to either VCC or GND, whichever is appropriate. If larger voltage swings or better accuracy is desired, a high speed output buffer, such as the HA-5033, HA-2542, or CA3450, can be employed. Figure 6 shows a typical application, with the output capable of driving 2V into multiple 50terminated lines. FN1850 Rev 4.00 July 2004 Page 8 of 10 CA3338, CA3338A Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.355 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 N 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 0.204 18.66 16 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 16 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN1850 Rev 4.00 July 2004 Page 9 of 10 CA3338, CA3338A Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA 0.25(0.010) M H B M INCHES E -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e µ B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS 16 0o 16 8o 0o 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 1997-2004. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1850 Rev 4.00 July 2004 Page 10 of 10