CY7C0430BV CY7C0430CV 10 Gb/s 3.3V QuadPort™ DSE Family Features • Dual Chip Enables on all ports for easy depth expansion • QuadPort™ datapath switching element (DSE) family allows four independent ports of access for data path management and switching • High-bandwidth data throughput up to 10 Gb/s • 133-MHz[1] port speed x 18-bit-wide interface × 4 ports • High-speed clock to data access 4.2 ns (max.) • Separate upper-byte and lower-byte controls on all ports • Simple array partitioning — Internal mask register controls counter wrap-around — Counter-Interrupt flags to indicate wrap-around — Counter and mask registers readback on address • 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball pitch) • Synchronous pipelined device — 1-Mb (64K × 18) switch array • 0.25-micron CMOS for optimum speed/power • IEEE 1149.1 JTAG boundary scan • Commercial and industrial temperature ranges • 3.3V low operating power — Active = 750 mA (maximum) • Width and depth expansion capabilities — Standby = 15 mA (maximum • BIST (Built-In Self-Test) controller QuadPort DSE Family Applications PORT 1 PORT 3 PORT 2 PORT 4 BUFFERED SWITCH PORT 2 PORT 1 PORT 3 PORT 4 REDUNDANT DATA MIRROR Note: 1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz. Cypress Semiconductor Corporation Document #: 38-06027 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 23, 2006 CY7C0430BV CY7C0430CV PORT 1 PORT 2 PORT 4 PORT 3 DATA PATH AGGREGATOR Processor 1 Pre-processed DATA Path QuadPort DSE Family Processed DATA Path Processor 2 DATA PATH MANAGER FOR PARALLEL PACKET PROCESSING Queue #1 PORT 1 PORT 3 Queue #2 PORT 2 PORT 4 DATA CLASSIFICATION ENGINE Functional Description The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independent frequencies from one another. Each port can read or write up to 133 MHz[1], giving the device up to 10 Gb/s of data throughput. The device is 1-Mb (64K × 18) in density. Simultaneous reads are allowed for accesses to the same address location; however, simultaneous reading and writing to the same address is not allowed. Any port can write to a certain location while other ports are reading that location simultaneously, if the timing spec for port to port delay (tCCS) is met. The result of writing to the same location by more than one port at the same time is undefined. Data is registered for decreased cycle time. Clock to data valid tCD2 = 4.2 ns. Each port contains a burst counter on the input Document #: 38-06027 Rev. *B address register. After externally loading the counter with the initial address the counter will self-increment the address internally (more details to follow). The internal write pulse width is independent of the duration of the R/W input signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle is required with chip enables asserted to reactivate the outputs. The CY7C0430BV and CY7C0430CV (64K × 18 device) supports burst contains for simple array partitioning. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst Page 2 of 37 CY7C0430BV CY7C0430CV counter is loaded with an external address when the port’s Counter Load pin (CNTLD) is asserted LOW. When the port’s Counter Increment pin (CNTINC) is asserted, the address counter will increment on each subsequent LOW-to- HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. The counter can address the entire switch array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. A counter-mask register is used to control the counter wrap. The counter and mask register operations are described in more details in the following sections. The counter or mask register values can be read back on the bidirectional address lines by activating MKRD or CNTRD, respectively. The new features included for the QuadPort DSE family include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, readback of mask register value on address lines, interrupt flags for message passing, BIST, JTAG for boundary scan, and asynchronous Master Reset. Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks[2] Reset Logic MRST UBP1 LBP1 Port-1 Control Logic R/WP1 OEP1 CE0P1 TMS JTAG Controller TCK TDI CE1P1 CLKBIST TDO BIST CLKP1 18 Port 1 I/O I/O0P1- I/O17P1 CLKP1 A0P1–A15P1 MKLDP1 CNTLDP1 CNTINCP1 CNTRDP1 MKRDP1 CNTRSTP1 INTP1 CNTINTP1 Port 4 Logic Blocks[3] 16 Port 1 Counter/ Mask Reg/ Address Decode Port 1 64K × 18 QuadPort DSE Array Port 2 Port 2 Logic Blocks[3] Port 4 Port 3 Port 3 Logic Blocks[3] Notes: 2. Port 1 Control Logic Block is detailed on page 4. 3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks. Document #: 38-06027 Rev. *B Page 3 of 37 CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram (Address Readback is independent of CEs) R/WP1 W UBP1 CE0P1 CE1P1 LBP1 OEP1 I/O9P1–I/O17P1 I/O0P1–I/O8P1 9 Port-1 I/O Control 9 Addr. Read Port 1 Readback Register MRST 16 t1 rt MKLDP1 Decision Logic CLKP1 MRST CNTINTP1 Document #: 38-06027 Rev. *B Decode LBP1 UBP1 R/WP1 CE0P1 CE1P1 OEP1 CLKP1 MRST 2 rt CNTRSTP1 Port 1 Counter/ Address Register 64K × 18 QuadPort DSE Array Po CNTLDP1 Port 1 Address t3 Priority Po r MKRDP1 4 CNTRDP1 CNTINCP1 Po Port 1 Mask Register Po r A0P1–A15P1 Port 1 Interrupt Logic INTP1 Page 4 of 37 CY7C0430BV CY7C0430CV Pin Configuration 272-ball Grid Array (BGA) Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A LB P1 I/O17 P2 I/O15 P2 I/O13 P2 I/O11 P2 I/O9 P2 I/O16 P1 I/O14 P1 I/O12 P1 I/O10 P1 I/O10 P4 I/O12 P4 I/O14 P4 I/O16 P4 I/O9 P3 I/O11 P3 I/O13 P3 I/O15 P3 I/O17 P3 LB P4 B VDD1 UB P1 I/O16 P2 I/O14 P2 I/O12 P2 I/O10 P2 I/O17 P1 I/O13 P1 I/O11 P1 TMS TDI I/O11 P4 I/O13 P4 I/O17 P4 I/O10 P3 I/O12 P3 I/O14 P3 I/O16 P3 UB P4 VDD1 C A14 P1 A15 P1 CE1 P1 CE0 P1 R/W P1 I/O15 P1 VSS2 VSS2 I/O9 P1 TCK TDO I/O9 P4 VSS2 VSS2 I/O15 P4 R/W P4 CE0 P4 CE1 P4 A15 P4 A14 P4 D VSS1 A12 P1 A13 P1 OE P1 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE P4 A13 P4 A12 P4 VSS1 E A10 P1 A11 P1 MKRD P1 CNTRD P1 CNTRD P4 MKRD P4 A11 P4 A10 P4 F A7 P1 A8 P1 A9 P1 CNTINT P1 CNTINT P4 A9 P4 A8 P4 A7 P4 G VSS1 A5 P1 A6 P1 CNTINC P1 CNTINC P4 A6 P4 A5 P4 VSS1 H A3 P1 A4 P1 MKLD P1 CNTLD P1 CNTLD P4 MKLD P4 A4 P4 A3 P4 J VDD1 A1 P1 A2 P1 VDD GND[4] GND[4] GND[4] GND[4] VDD A2 P4 A1 P4 VDD1 K A0 P1 INT P1 CNTRST P1 CLK P1 GND[4] GND[4] GND[4] GND[4] CLK P4 CNTRST P4 INT P4 A0 P4 L A0 P2 INT P2 CNTRST P2 VSS GND[4] GND[4] GND[4] GND[4] VSS CNTRST P3 INT P3 A0 P3 M VDD1 A1 P2 A2 P2 CLK P2 GND[4] GND[4] GND[4] GND[4] CLK P3 A2 P3 A1 P3 VDD1 N A3 P2 A4 P2 MKLD P2 CNTLD P2 CNTLD P3 MKLD P3 A4 P3 A3 P3 P VSS1 A5 P2 A6 P2 CNTINC P2 CNTINC P3 A6 P3 A5 P3 VSS1 R A7 P2 A8 P2 A9 P2 CNTINT P2 CNTINT P3 A9 P3 A8 P3 A7 P3 T A10 P2 A11 P2 MKRD P2 CNTRD P2 CNTRD P3 MKRD P3 A11 P3 A10 P3 U VSS1 A12 P2 A13 P2 OE P2 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE P3 A13 P3 A12 P3 VSS1 V A14 P2 A15 P2 CE1 P2 CE0 P2 R/W P2 I/O6 P2 VSS2 VSS2 I/O0 P2 NC NC I/O0 P3 VSS2 VSS2 I/O6 P3 R/W P3 CE0 P3 CE1 P3 A15 P3 A14 P3 W VDD1 UB P2 I/O7 P1 I/O5 P1 I/O3 P1 I/O1 P1 I/O8 P2 I/O4 P2 I/O2 P2 MRST CLKBIST I/O2 P3 I/O4 P3 I/O8 P3 I/O1 P4 I/O3 P4 I/O5 P4 I/O7 P4 UB P3 VDD1 Y LB P2 I/O8 P1 I/O6 P1 I/O4 P1 I/O2 P1 I/O0 P1 1/O7 P2 I/O5 P2 I/O3 P2 I/O1 P2 I/O1 P3 I/O3 P3 I/O5 P3 I/O7 P3 I/O0 P4 I/O2 P4 I/O4 P4 I/O6 P4 I/O8 P4 LB P3 Note: 4. Central Leads are for thermal dissipation only. They are connected to device VSS. Document #: 38-06027 Rev. *B Page 5 of 37 CY7C0430BV CY7C0430CV Selection Guide fMAX2 CY7C0430CV –133 CY7C0430CV –100 Unit 133[1] 100 MHz Max Access Time (Clock to Data) 4.2 5.0 ns Max Operating Current ICC 750 600 mA Max Standby Current for ISB1 (All ports TTL Level) 200 150 mA Max Standby Current for ISB3 (All ports CMOS Level) 15 15 mA Pin Definitions Port 1 Port 2 Port 3 Port 4 Description A0P1–A15P1 A0P2–A15P2 A0P3–A15P3 A0P4–A15P4 Address Input/Output. I/O0P1–I/O17P1 I/O0P2–I/O17P2 I/O0P3–I/O17P3 I/O0P4–I/O17P4 Data Bus Input/Output. CLKP1 CLKP2 CLKP3 CLKP4 Clock Input. This input can be free running or strobed. Maximum clock input rate is fMAX. LBP1 LBP2 LBP3 LBP4 Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. UBP1 UBP2 UBP3 UBP4 Upper Byte Select Input. Same function as LB, but to the upper byte. CE0P1,CE1P1 CE0P2,CE1P2 CE0P3,CE1P3 CE0P4,CE1P4 Chip Enable Input. To select any port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). OEP1 OEP2 OEP3 OEP4 Output Enable Input. This signal must be asserted LOW to enable the I/O data lines during read operations. OE is asynchronous input. R/WP1 R/WP2 R/WP3 R/WP4 Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. MRST Master Reset Input. This is one signal for All Ports. MRST is an asynchronous input. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. CNTRSTP1 CNTRSTP2 CNTRSTP3 CNTRSTP4 Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is second to MRST in priority with respect to counter and mask register operations. MKLDP1 MKLDP2 MKLDP3 MKLDP4 Mask Register Load Input. Asserting this signal LOW loads the mask register with the external address available on the address lines. MKLD operation has higher priority over CNTLD operation. CNTLDP1 CNTLDP2 CNTLDP3 CNTLDP4 Counter Load Input. Asserting this signal LOW loads the burst counter with the external address present on the address pins. CNTINCP1 CNTINCP2 CNTINCP3 CNTINCP4 Counter Increment Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. Document #: 38-06027 Rev. *B Page 6 of 37 CY7C0430BV CY7C0430CV Pin Definitions (continued) Port 1 Port 2 Port 3 Port 4 Description CNTRDP1 CNTRDP2 CNTRDP3 CNTRDP4 Counter Readback Input. When asserted LOW, the internal address value of the counter will be read back on the address lines. During CNTRD operation, both CNTLD and CNTINC must be HIGH. Counter readback operation has higher priority over mask register readback operation. Counter readback operation is independent of port chip enables. If address readback operation occurs with chip enables active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os) will be three-stated. The readback timing will be valid after one no-operation cycle plus tCD2 from the rising edge of the next cycle. MKRDP1 MKRDP2 MKRDP3 MKRDP4 Mask Register Readback Input. When asserted LOW, the value of the mask register will be readback on address lines. During mask register readback operation, all counter and MKLD inputs must be HIGH (see Counter and Mask Register Operations truth table). Mask register readback operation is independent of port chip enables. If address readback operation occurs with chip enables active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os) will be three-stated. The readback will be valid after one no-operation cycle plus tCD2 from the rising edge of the next cycle. CNTINTP1 CNTINTP2 CNTINTP3 CNTINTP4 Counter Interrupt Flag Output. Flag is asserted LOW for one clock cycle when the counter wraps around to location zero. INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output. Interrupt permits communications between all four ports. The upper four memory locations can be used for message passing. Example of operation: INTP4 is asserted LOW when another port writes to the mailbox location of Port 4. Flag is cleared when Port 4 reads the contents of its mailbox. The same operation is applicable to ports 1, 2, and 3. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. TCK JTAG Test Clock Input. This can be CLK of any port or an external clock connected to the JTAG TAP. TDI JTAG Test Data Input. This is the only data input. TDI inputs will shift data serially in to the selected register. TDO JTAG Test Data Output. This is the only data output. TDO transitions occur on the falling edge of TCK. TDO normally three-stated except when captured data is shifted out of the JTAG TAP. CLKBIST BIST Clock Input. GND Thermal Ground for Heat Dissipation. VSS Ground Input. VDD Power Input. VSS1 Address Lines Ground Input. VDD1 Address Lines Power Input. VSS2 Data Lines Ground Input. VDD2 Data Lines Power Input. Document #: 38-06027 Rev. *B Page 7 of 37 CY7C0430BV CY7C0430CV Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................–55°C to + 125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2200V Latch-up Current..................................................... > 200 mA Operating Range Supply Voltage to Ground Potential .............. –0.5V to + 4.6V Range DC Voltage Applied to Outputs in High-Z State..........................–0.5V to VCC + 0.5V Ambient Temperature VDD 0°C to +70°C 3.3V ± 150 mV –40°C to +85°C 3.3V ± 150 mV Commercial Industrial DC Input Voltage....................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range Quadport DSE Family –133 Parameter Description Min. Typ. –100 Max. 2.4 Min. Typ. Max. Unit 2.4 VOH Output HIGH Voltage (VCC = Min., IOH = –4.0 mA) VOL Output LOW Voltage (VCC = Min., IOH = +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled, CE = VIL, f = fmax 350 700 ISB1 Standby Current (four ports toggling at TTL Levels,0 active) CE1-4 ≥ VIH, f = fMAX 80 ISB2 Standby Current (four ports toggling at TTL Levels, 1 active) CE1 | CE2 | CE3 | CE4 < VIL, f = fMAX ISB3 ISB4 V 0.4 2.0 0.4 V 2.0 V 0.8 0.8 V 10 µA 300 550 mA 200 60 150 mA 150 300 125 250 mA Standby Current (four ports CMOS Level, 0 active) CE1–4 ≥ VIH, f = 0 1.5 15 1.5 15 mA Standby Current (four ports CMOS Level, 1 active and toggling) CE1 | CE2 | CE3 | CE4 < VIL, f = fMAX 110 290 85 240 mA Min. Max. Unit –10 10 –10 JTAG TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH1 Output HIGH Voltage IOH = −4.0 mA VOL1 Output LOW Voltage IOL = 4.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IX Input Leakage Current 2.4 V 0.4 V 2.0 GND ≤ VI ≤ VDD –100 V 0.8 V 100 µA Capacitance Parameter Description CIN (All Pins) Input Capacitance COUT (All Pins) Output Capacitance CIN (CLK Pins) Input Capacitance COUT (CLK Pins) Output Capacitance Document #: 38-06027 Rev. *B Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF 10 pF 15 pF 15 pF Page 8 of 37 CY7C0430BV CY7C0430CV AC Test Load Z0 = 50Ω OUTPUT R = 50Ω OUTPUT C [5] Z0 = 50Ω R = 50Ω 5 pF VTH = 1.5V VTH = 1.5V (a) Normal Load OUTPUT Z0 = 50Ω R = 50Ω 5 pF VTH = 3.3V 1.5V (b) Three-State Delay 50Ω TDO Z0 =50Ω C = 10 pF 3.0V GND GND (c) TAP Load 10% 90% 90% 10% tF tR All Input Pulses Note: 5. Test conditions: C = 10 pF. Document #: 38-06027 Rev. *B Page 9 of 37 CY7C0430BV CY7C0430CV Switching Characteristics Over the Industrial Operating Range [6] CY7C0430BV and CY7C0430CV –133 Parameter Description Min. –100 Max. Min. Max. Unit 100 MHz fMAX2[7] tCYC2[7] Maximum Frequency Clock Cycle Time 7.5 10 ns tCH2 Clock HIGH Time 3 4 ns tCL2 Clock LOW Time 3 tR Clock Rise Time 2 3 ns tF Clock Fall Time 2 3 ns tSA Address Set-up Time 2.3 3 ns tHA Address Hold Time 0.7 0.7 ns tSC Chip Enable Set-up Time 2.3 3 ns tHC Chip Enable Hold Time 0.7 0.7 ns tSW R/W Set-up Time 2.3 3 ns tHW R/W Hold Time 0.7 0.7 ns tSD Input Data Set-up Time 2.3 3 ns tHD Input Data Hold Time 0.7 0.7 ns tSB Byte Set-up Time 2.3 3 ns tHB Byte Hold Time 0.7 0.7 ns tSCLD CNTLD Set-up Time 2.3 3 ns tHCLD CNTLD Hold Time 0.7 0.7 ns tSCINC CNTINC Set-up Time 2.3 3 ns tHCINC CNTINC Hold Time 0.7 0.7 ns tSCRST CNTRST Set-up Time 2.3 3 ns tHCRST CNTRST Hold Time 0.7 0.7 ns tSCRD CNTRD Set-up Time 2.3 3 ns tHCRD CNTRD Hold Time 0.7 0.7 ns tSMLD MKLD Set-up Time 2.3 3 ns tHMLD MKLD Hold Time 0.7 0.7 ns tSMRD MKRD Set-up Time 2.3 3 ns tHMRD MKRD Hold Time 0.7 0.7 ns tOE Output Enable to Data Valid tOLZ[8] OE to Low-Z 1 tOHZ[8] OE to High-Z 1 tCD2 Clock to Data Valid tCA2 Clock to Counter Address Readback Valid tCM2 Clock to Mask Register Readback Valid tDC Data Output Hold After Clock HIGH 1 tCKHZ[9] Clock HIGH to Output High-Z 1 133 4 6.5 ns 8 1 6 1 ns ns 7 ns 4.2 5 ns 4.7 5 ns 4.7 5 ns 6.8 ns 1 4.8 1 ns Notes: 6. If data is simultaneously written and read to the same address location and tCCS is violated, the data read from the address, as well as the subsequent data remaining in the address is undefined. 7. fMAX2 for commercial is 135 MHz. tCYC2 Min. for commercial is 7.4 ns. 8. This parameter is guaranteed by design, but it is not production tested. 9. Valid for both address and data outputs. Document #: 38-06027 Rev. *B Page 10 of 37 CY7C0430BV CY7C0430CV Switching Characteristics Over the Industrial Operating Range (continued)[6] CY7C0430BV and CY7C0430CV –133 Parameter Description Min. –100 Max. Min. Max. Unit tCKLZ[9] Clock HIGH to Output Low-Z 1 tSINT Clock to INT Set Time 1 7.5 tRINT Clock to INT Reset Time 1 7.5 1 10 ns tSCINT Clock to CNTINT Set Time 1 7.5 1 10 ns tRCINT Clock to CNTINT Reset Time 1 7.5 1 10 ns 1 ns 1 10 ns Master Reset Timing tRS Master Reset Pulse Width 7.5 10 ns tRSR Master Reset Recovery Time 7.5 10 ns tROF Master Reset to Output Flags Reset Time 6.5 8 ns Port to Port Delays tCCS[6] Clock to Clock Set-up Time (time required after a write before you can read the same address location) 6.5 9 ns JTAG Timing and Switching Waveforms Quadport DSE Family –133/–100 Parameter Description Min. Max. Unit 10 MHz fJTAG Maximum JTAG TAP Controller Frequency tTCYC TCK Clock Cycle Time 100 ns tTH TCK Clock High Time 40 ns tTL TCK Clock Low Time 40 ns tTMSS TMS Set-up to TCK Clock Rise 20 ns tTMSH TMS Hold After TCK Clock Rise 20 ns tTDIS TDI Set-up to TCK Clock Rise 20 ns tTDIH TDI Hold after TCK Clock Rise 20 tTDOV TCK Clock Low to TDO Valid tTDOX TCK Clock Low to TDO Invalid fBIST Maximum CLKBIST Frequency tBH CLKBIST High Time 6 ns tBL CLKBIST Low Time 6 ns Document #: 38-06027 Rev. *B ns 20 ns 50 MHz 0 ns Page 11 of 37 CY7C0430BV CY7C0430CV tTH tTL Test Clock TCK tTCYC tTMSH tTMSS Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Switching Waveforms Master Reset[10] tCH2 tCYC2 tCL2 CLK tRS MRST ALL ADDRESS/ DATA LINES tRSF ALL OTHER INPUTS tRSR INACTIVE tS ACTIVE TMS[11] CNTINT INT TDO Notes: 10. tS is the set-up time required for all input control signals. 11. To Reset the test port without resetting the device, TMS must be held low for five clock cycles. Document #: 38-06027 Rev. *B Page 12 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Read Cycle[12, 13, 14, 15, 16] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSB tHB tSW tSA tHW tHA tSC tHC LB UB R/W ADDRESS An DATAOUT An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes: 12. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge. 13. CNTLD = VIL, MKLD = VIH, CNTINC = x, and MRST = CNTRST = VIH. 14. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 15. Addresses do not have to be accessed sequentially. Note 13 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference only. 16. CE is internal signal. CE = VIL if CE0 = VIL and CE1 = VIH. Document #: 38-06027 Rev. *B Page 13 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Bank Select Read[17, 18] tCH2 tCYC2 tCL2 CLK tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE(B1) tCD2 tHC tSC tCD2 tHA tSA A0 ADDRESS(B2) tDC A1 tCKHZ Q3 Q1 Q0 DATAOUT(B1) tCD2 tCKHZ tDC tCKLZ A3 A2 A4 A5 tHC tSC CE(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 Q4 Q2 tCKLZ tCKLZ Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 An+2 tHA DATAIN An+3 An+4 tSD tHD tCD2 tCKHZ Dn+2 tCD2 Qn DATAOUT Qn+3 tCKLZ Read No Operation Write Read Notes: 17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each bank consists of one QuadPort DSE device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 18. LB = UB = OE = CNTLD = VIL; MRST = CNTRST= MKLD = VIH. 19. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 20. LB = UB = CNTLD = VIL; MRST = CNTRST = MKLD = VIH. 21. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference only. 22. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06027 Rev. *B Page 14 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W ADDRESS tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAIN Dn+3 tCD2 tCD2 DATAOUT Qn Qn+4 tOHZ tCKLZ OE Read Write Read Read with Address Counter Advance[23, 24] tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSCLD tHCLD CNTLD tSCINC tHCINC CNTINC tCD2 DATAOUT Qx–1 Qx Read External Address tDC Qn Read with Counter Qn+1 Qn+2 Counter Hold Qn+3 Read with Counter Notes: 23. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH. 24. The “Internal Address” is equal to the “External Address” when CNTLD = VIL. Document #: 38-06027 Rev. *B Page 15 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Write with Address Counter Advance [24, 25] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSCLD tHCLD tSCINC tHCINC An+1 An+2 An+3 An+4 CNTLD CNTINC Dn DATAIN tSD tHD Write External Address Dn+1 Dn+1 Write with Counter Dn+2 Write Counter Hold Dn+3 Dn+4 Write with Counter Note: 25. CE0 = LB = UB = R/W = VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH. Document #: 38-06027 Rev. *B Page 16 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Counter Reset [21, 26, 27] tCH2 tCYC2 tCL2 CLK tSA An ADDRESS INTERNAL ADDRESS tHA AX A0 tSW An+1 A1 An An+1 tHW R/W tHCLD tSCLD CNTLD CNTINC tSCRST An+2 tHCRST CNTRST tSD DATAIN tHD D0 DATAOUT Q0 Counter Reset Write Address 0 Read Address 0 Read Address 1 Q1 Qn Read Address n Notes: 26. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH. 27. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06027 Rev. *B Page 17 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Load and Read Address Counter[28] tCH2 tCYC2 tCL2 Note 29 CLK tHA tSA A0–A15 tCKLZ Note 30 tCA2 tCKHZ An+2[31] An tSCLD tHCLD CNTLD CNTINC tSCINC tHCINC tSCRD tHCRD CNTRD INTERNAL ADDRESS An An+1 Qx–1 Qx Load External Address An+2 tDC tCD2 DATAOUT An+2 Qn An+2 tCKHZ Qn+1 Read Data with Counter Qn+2 tCKLZ Qn+2 Read Internal Address Notes: 28. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH. 29. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle. 30. Address in input mode. Host can drive address bus after tCKHZ. 31. This is the value of the address counter being read out on the address lines. Document #: 38-06027 Rev. *B Page 18 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Load and Read Mask Register [32] tCH2 tCYC2 tCL2 Note 29 CLK tHA tSA A0–A15 tCKLZ Note 30 tCA2 tCKHZ An [33] An tSMLD tHMLD MKLD tSMRD tHMRD MKRD MASK INTERNAL VALUE An An An Load Mask Register Value An An Read Mask Register Value Notes: 32. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =VIH. 33. This is the value of the Mask Register read out on the address lines. Document #: 38-06027 Rev. *B Page 19 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Port 1 Write to Port 2 Read[34, 35, 36] tCH2 tCYC2 tCL2 CLKP1 tHA tSA PORT-1 ADDRESS An tSW tHW R/WP1 tCKHZ tSD PORT-1 tCKLZ Dn DATAIN CLKP2 tHD tCYC2 tCL2 tCCS tCH2 PORT-2 ADDRESS tSA tHA An R/WP2 tCD2 PORT-2 Qn DATAOUT tDC Notes: 34. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH. 35. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If tCCS is violated, indeterminate data will be read out. 36. If tCCS< minimum specified value, then Port 2 will read the most recent data (written by Port 1) only (2*tCYC2 + tCD2) after the rising edge of Port 2’s clock. If tCCS > minimum specified value, then Port 2 will read the most recent data (written by Port 1) (tCYC2 + tCD2) after the rising edge of Port 2’s clock. Document #: 38-06027 Rev. *B Page 20 of 37 CY7C0430BV CY7C0430CV Switching Waveforms (continued) Counter Interrupt [37, 38, 39] tCH2 tCYC2 tCL2 CLK EXTERNAL ADDRESS 007Fh xx7Dh tSMLD tHMLD MKLD tSCLD tHCLD CNTLD tHCINC tSCINC CNTINC COUNTER INTERNAL ADDRESS xx7Dh An xx7Eh xx7Fh xx00h xx00h tSCINT CNTINT tRCINT Mailbox Interrupt Timing[40, 41, 42, 43, 44] tCH2 tCYC2 tCL2 CLKP1 tSA PORT-1 ADDRESS tHA An+1 An FFFE An+2 An+3 tSINT tRINT INTP2 tCH2 tCYC2 tCL2 CLKP2 tSA PORT-2 ADDRESS Am tHA Am+1 FFFE Am+3 Am+4 Notes: 37. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH. 38. CNTINT is always driven. 39. CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “Don’t Care.” 40. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH. 41. Address “FFFE” is the mailbox location for Port 2. 42. Port 1 is configured for Write operation, and Port 2 is configured for Read operation. 43. Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox. 44. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock. Document #: 38-06027 Rev. *B Page 21 of 37 CY7C0430BV CY7C0430CV Table 1. Read/Write and Enable Operation (Any Port)[45, 46, 47] Inputs OE CLK Outputs Operation CE0 CE1 R/W I/O0–I/O17 X H X X High-Z Deselected X X L X High-Z Deselected X L H L DIN Write L L H H DOUT Read L H X High-Z Outputs Disabled H X Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)[45, 48, 49] CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD X Mode Operation Counter/Address Register Reset and Mask Register Set (resets entire chip as per reset state table) L X X X X X X MasterReset H L X X X X X Reset Counter/Address Register Reset H H L X X X X Load Load of Address Lines into Mask Register H H H L X X X Load Load of Address Lines into Counter/Address Register H H H H L X X Increment Counter Increment H H H H H L X Readback Readback Counter on Address Lines H H H H H H L Readback Readback Mask Register on Address Lines H H H H H H H Hold Counter Hold Notes: 45. “X” = “Don’t Care,” “H” = VIH, “L” = VIL. 46. OE is an asynchronous input signal. 47. When CE changes state, deselection and read happen after one cycle of latency. 48. CE0 = OE = VIL; CE1 = R/W = VIH. 49. Counter operation and mask register operation are independent of Chip Enables. Document #: 38-06027 Rev. *B Page 22 of 37 CY7C0430BV CY7C0430CV Master Reset The QuadPort DSE device undergoes a complete reset by taking its Master Reset (MRST) input LOW. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). A Master Reset also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH, resets the BIST controller, and takes all registered control signals to a deselected read state.[50] A Master Reset must be performed on the QuadPort DSE device after power-up. Interrupts The upper four memory locations may be used for message passing and permit communications between ports. Table 3 shows the interrupt operation for all ports. For the 1-Mb QuadPort DSE device, the highest memory location FFFF is the mailbox for Port 1, FFFE is the mailbox for Port 2, FFFD is the mailbox for Port 3, and FFFC is the mailbox for Port 4. Table 3 shows that in order to set Port 1 INTP1 flag, a write by any other port to address FFFF will assert INTP1 LOW. A read of FFFF location by Port 1 will reset INTP1 HIGH. When one port writes to the other port’s mailbox, the Interrupt flag (INT) of the port that the mailbox belongs to is asserted LOW. The Interrupt is reset when the owner (port) of the mailbox reads the contents of the mailbox. The interrupt flag is set in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-through mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without resetting the interrupt. If an application does not require message passing, INT pins should be treated as no-connect and should be left floating. When two ports or more write to the same mailbox at the same time INT will be asserted but the contents of the mailbox are not guaranteed to be valid. Table 3. Interrupt Operation Example Port 1 Function Port 2 Port 3 Port 4 A0P1–15P1 INTP1 A0P2–15P2 INTP2 A0P3–15P3 INTP3 A0P4–15P4 INTP4 X L FFFF X FFFF X FFFF X Reset Port 1 INTP1 Flag FFFF H X X X X X X Set Port 2 INTP2 Flag FFFE X X L FFFE X FFFE X X X FFFE H X X X X FFFD X FFFD X X L FFFD X X X X X FFFD H X X FFFC X FFFC X FFFC X X L X X X X X X FFFC H Set Port 1 INTP1 Flag Reset Port 2 INTP2 Flag Set Port 3 INTP3 Flag Reset Port 3 INTP3 Flag Set Port 4 INTP4 Flag Reset Port 4 INTP4 Flag Note: 50. During Master Reset the control signals will be set to a deselected read state: CE0I = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI = CNTINCI = VIH; CE1I = VIL. The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals. Document #: 38-06027 Rev. *B Page 23 of 37 CY7C0430BV CY7C0430CV Address Counter Control Operations Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications. A port’s burst counter is loaded with the port’s Counter Load pin (CNTLD). When the port’s Counter Increment (CNTINC) is asserted, the address counter will increment on each LOW to HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTINC is deasserted. Depending on the mask register state, the counter can address the entire memory array and will loop back to start. Counter Reset (CNTRST) is used to reset the Burst Counter (the Mask Register value is unaffected). When using the counter in readback mode, the internal address value of the counter will be read back on the address lines when Counter Readback Signal (CNTRD) is asserted. Readback Register CNTRD MKRD Figure 1 provides a block diagram of the readback operation. Table 2 lists control signals required for counter operations. The signals are listed based on their priority. For example, Master Reset takes precedence over Counter Reset, and Counter Load has lower priority than Mask Register Load (described below). All counter operations are independent of Chip Enables (CE0 and CE1). When the address readback operation is performed the data I/Os are three-stated (if CEs are active) and one-clock cycle (no-operation cycle) latency is experienced. The address will be read at time tCA2 from the rising edge of the clock following the no-operation cycle. The read back address can be either of the burst counter or the mask register based on the levels of Counter Read signal (CNTRD) and Mask Register Read signal (MKRD). Both signals are synchronized to the port's clock as shown in Table 2. Counter read has a higher priority than mask read. Addr. Readback MKLD = 1 Mask Register Bidirectional Address Lines CNTINC = 1 Memory Array Counter/ Address Register CNTLD = 1 CNTRST = 1 CLK Figure 1. Counter and Mask Register Read Back on Address Lines Document #: 38-06027 Rev. *B Page 24 of 37 CY7C0430BV CY7C0430CV Counter-Mask Register Example: Load Counter-Mask Register = 3F CNTINT H 0 0 0’s 215 214 H X X X’s 215 214 Max Address Register H X X L 1 1 1 X X 215 214 Mask Register bit-0 Counter Address X 0 0 1 0 0 0 26 25 24 23 22 21 20 X’s 215 214 Max + 1 Address Register 1 26 25 24 23 22 21 20 Blocked Address Load Address Counter = 8 0 1 1 X 1 1 1 1 1 1 Address Counter bit-0 26 25 24 23 22 21 20 X’s X 0 0 0 0 0 0 26 25 24 23 22 21 20 Figure 2. Programmable Counter-Mask Register Operation[51] The burst counter has a mask register that controls when and where the counter wraps. An interrupt flag (CNTINT) is asserted for one clock cycle when the unmasked portion of the counter address wraps around from all ones (CNTINC must be asserted) to all zeros. The example in Figure 2 shows the counter mask register loaded with a mask value of 003F unmasking the first 6 bits with bit “0” as the LSB and bit “15” as the MSB. The maximum value the mask register can be loaded with is FFFF. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of XXX8. The “blocked” addresses (in this case, the 6th address through the 15th address) are loaded with an address but do not increment once loaded. The counter address will start at address XXX8. With CNTINC asserted LOW, the counter will increment its internal address value till it reaches the mask register value of 3F and wraps around the memory block to location XXX0. Therefore, the counter uses the mask-register to define wrap-around point. The mask register of every port is loaded when MKLD (mask register load) for that port is LOW. When MKRD is LOW, the value of the mask register can be read out on address lines in a manner similar to counter read back operation (see Table 2 for required conditions). When the burst counter is loaded with an address higher than the mask register value, the higher addresses will form the masked portion of the counter address and are called blocked addresses. The blocked addresses will not be changed or affected by the counter increment operation. The only exception is mask register bit 0. It can be masked to allow the address counter to increment by two. If the mask register bit 0 is loaded with a logic value of “0,” then address counter bit 0 is masked and can not be changed during counter increment operation. If the loaded value for address counter bit 0 is “0,” the counter will increment by two and the address values are even. If the loaded value for address counter bit 0 is “1,” the counter will increment by two and the address values are odd. This operations allows the user to achieve a 36-bit interface using any two ports, where the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 36-bit word in even memory locations, and the other half in odd memory locations. CNTINT will be asserted when the unmasked portion of the counter wraps to all zeros. Loading mask register bit 0 with “1” allows the counter to increment the address value sequentially. Table 2 groups the operations of the mask register with the operations of the address counter. Address counter and mask register signals are all synchronized to the port's clock CLK. Master reset (MRST) is the only asynchronous signal listed on Table 2. Signals are listed based on their priority going from left column to right column with MRST being the highest. A LOW on MRST will reset both counter register to all zeros and mask register to all ones. On the other hand, a LOW on CNTRST will only clear the address counter register to zeros and the mask register will remain intact. There are four operations for the counter and mask register: 1. Load operation: When CNTLD or MKLD is LOW, the address counter or the mask register is loaded with the address value presented at the address lines. This value ranges from 0 to FFFF (64K). The mask register load operation has a higher priority over the address counter load operation. 2. Increment: Once the address counter is loaded with an external address, the counter can internally increment the address value by asserting CNTINC LOW. The counter can Note: 51. The “X” in this diagram represents the counter upper-bits. Document #: 38-06027 Rev. *B Page 25 of 37 CY7C0430BV CY7C0430CV address the entire memory array (depend on the value of the mask register) and loop back to location 0. The increment operation is second in priority to load operation. 3. Readback: the internal value of either the burst counter or the mask register can be read out on the address lines when CNTRD or MKRD is LOW. Counter readback has higher priority over mask register readback. A no-operation delay cycle is experienced when readback operation is performed. The address will be valid after tCA2 (for counter readback) or tCM2 (for mask readback) from the following port's clock rising edge. Address readback operation is independent of the port's chip enables (CE0 and CE1). If address readback occurs while the port is enabled (chip enables active), the data lines (I/Os) will be three-stated. 4. Hold operation: In order to hold the value of the address counter at certain address, all signals in Table 2 have to be HIGH. This operation has the least priority. This operation is useful in many applications where wait states are needed or when address is available few cycles ahead of data. The counter and mask register operations are totally independent of port chip enables. IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) The CY7C0430BV and CY7C0430CV incorporate a serial boundary scan test access port (TAP). This port is fully compatible with IEEE Standard 1149.1-2001[52]. The TAP operates using JEDEC standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Memory BIST circuitry will also be controlled through the TAP interface. All MBIST instructions are compliant to the JTAG standard. An external clock (CLKBIST) is provided to allow the user to run BIST at speeds up to 50 MHz. CLKBIST is multiplexed internally with the ports clocks during BIST operation. Disabling the JTAG Feature It is possible to operate the QuadPort DSE device without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. CLKBIST must be tied LOW to disable the MBIST. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram (FSM)). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the QuadPort DSE device and may be performed while the device is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the QuadPort DSE device test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Four-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the following JTAG/BIST Controller diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain devices. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the QuadPort DSE device with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Test Mode Select Boundary Scan Register The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. The boundary scan register is connected to all the input and output pins on the QuadPort DSE device. The boundary scan register is loaded with the contents of the QuadPort DSE device Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. Test Access Port (TAP)–Test Clock (TCK) Note: 52. Master Reset will reset the JTAG controller. Document #: 38-06027 Rev. *B Page 26 of 37 CY7C0430BV CY7C0430CV The EXTEST, and SAMPLE/PRELOAD instructions can be used to capture the contents of the Input and Output ring. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the QuadPort DSE device and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Sixteen different instructions are possible with the 4-bit instruction register. All combinations are listed in Table 6, Instruction Codes. Seven of these instructions (codes) are listed as RESERVED and should not be used. The other nine instructions are described in detail below. The TAP controller used in this QuadPort DSE device is fully compatible[52] with the 1149.1 convention. The TAP controller can be used to load address, data or control signals into the QuadPort DSE device and can preload the Input or output buffers. The QuadPort DSE device implements all of the 1149.1 instructions except INTEST. Table 6 lists all instructions. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST allows circuitry external to the QuadPort DSE device package to be tested. Boundary-scan register cells at output pins are used to apply test stimuli, while those at input pins capture test results. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It also places the identification register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. High-Z The High-Z instruction causes the bypass register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all QuadPort DSE device outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. Document #: 38-06027 Rev. *B The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the QuadPort DSE device clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the QuadPort DSE device signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. If the TAP controller goes into the Update-DR state, the sampled data will be updated. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. CLAMP The optional CLAMP instruction allows the state of the signals driven from QuadPort DSE device pins to be determined from the boundary-scan register while the BYPASS register is selected as the serial path between TDI and TDO. CLAMP controls boundary cells to 1 or 0. CYBIST CYBIST instruction provides the user with a means of running a user-accessible self-test function within the QuadPort DSE device as a result of a single instruction. This permits all components on a board that offer the CYBIST instruction to execute their self-tests concurrently, providing a quick check for the board. The QuadPort DSE device MBIST provides two modes of operation once the TAP controller is loaded with the CYBIST instruction: Non-Debug Mode (Go-NoGo) The non-debug mode is a go-nogo test used simply to run BIST and obtain pass-fail information after the test is run. In addition to that, the total number of failures encountered can be obtained. This information is used to aid the debug mode (explained next) of operation. The pass-fail information and failure count is scanned out using the JTAG interface. An MBIST Result Register (MRR) will be used to store the pass-fail results. The MRR is a 25-bit register that will be connected between TDI and TDO during the internal scan (INT_SCAN) operation. The MRR will contain the total number of fail read cycles of the entire MBIST sequence. MRR[0] (bit 0) is the Pass/Fail bit. A “1” indicates some type of failure occurred, and a “0” indicates entire memory pass. In order to run BIST in non-debug mode, the two-bit MBIST Control Register (MCR) is loaded with the default value “00”, and the TAP controller’s finite state machine (FSM), which is synchronous to TCK, transitions to Run Test/Idle state. The entire MBIST test will be performed with a deterministic Page 27 of 37 CY7C0430BV CY7C0430CV number of TCK cycles depending on the TCK and CLKBIST frequency. t CYC [ CLKBIST ] t CYC = -------------------------------------------- × m + SPC t CYC [ TCK ] tCYC is total number of TCK cycles required to run MBIST. SPC is the Synchronization Padding Cycles (4–6 cycles). m is a constant represents the number of read and write operations required to run MBIST algorithms (31195136). Once the entire MBIST sequence is completed, supplying extra TCK or CLKBIST cycles will have no effect on the MBIST controller state or the pass-fail status. Debug Mode With the CYBIST instruction loaded and the MCR loaded with the value of “01,” and the FSM transitions to RUN_TEST/IDLE state, the MBIST goes into CYBIST-debug mode. The debug mode will be used to provide complete failure analysis information at the board level. It is recommended that the user runs the non-debug mode first and then the debug mode in order to save test time and to set an upper bound on the number of scan outs that will be needed. The failure data will be scanned out automatically once a failure occurs using the JTAG TAP interface. The failure data will be represented by a 100-bit packet given below. The 100-bit Memory Debug Register (MDR) will be connected between TDI and TDO, and will be shifted out on TDO, which is synchronized to TCK. Figure 3 is a representation of the 100-bit MDR packet. The packet follows a two-bit header that has a logic “1” value, and represents two TCK cycles. MDR[97:26] represent the BIST comparator values of all four ports (each port has 18 data lines). A value of “1” indicates a bit failure. The scanned out 99 1 data is from LSB to MSB. MDR[25:10] represent the failing address (MSB to LSB). The state of the BIST controller is scanned out using MDR[9:4]. Bit 2 is the Test Done bit. A “0” in bit 2 means test not complete. The user has to monitor this bit at every packet to determine if more failure packets need to be scanned out at the end of the BIST operations. If the value is “0” then BIST must be repeated to capture the next failing packet. If it is “1,” it means that the last failing packets have been scanned out. A trailer similar to the header represents the end of a packet. MCR_SCAN This instruction will connect the Memory BIST Control Register (MCR) between TDI and TDO. The default value (upon master reset) is “00.” Shift_DR state will allow modifying the MCR to extend the MBIST functionality. MBIST Control States Thirty-five states are listed in Table 7. Four data algorithms are used in debug mode: moving inversion (MIA), march_2 (M2A), checkerboard (CBA), and unique address algorithm (UAA). Only Port 1 can write MIA, M2A, and CBA data to the memory. All four ports can read any algorithm data from the QuadPort DSE device memory. Ports 2, 3, and 4 will only write UAA data. Boundary Scan Cells (BSC) Table 9 lists all QuadPort DSE family I/Os with their associated BSC. Note that the cells have even numbers. Every I/O has two boundary scan cells. Bidirectional signals (address lines, datalines) require two cells so that one (the odd cell) is used to control a three-state buffer. Input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout. 98 1 62 97 P3_IO(17-9) P4_IO(17-9) 61 P4_IO(8-0) 25 P2_IO(17-9) P1_IO(17-9) 26 P3_IO(8-0) P2_IO(8-0) P1_IO(8-0) 10 A(15-0) 9 MBIST_State 4 3 P/F 2 TD 1 0 1 1 Figure 3. MBIST Debug Register Packet Document #: 38-06027 Rev. *B Page 28 of 37 CY7C0430BV CY7C0430CV TAP Controller State Diagram (FSM)[53] 1 TEST-LOGIC RESET 0 0 RUN_TEST/ IDLE 1 1 SELECT DR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 SELECT IR-SCAN 0 UPDATE-IR 1 0 Note: 53. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-06027 Rev. *B Page 29 of 37 CY7C0430BV CY7C0430CV JTAG/BIST TAP Controller Block Diagram 0 Bypass Register (BYR) 1 0 MBIST Control Register (MCR) 3 2 1 0 Instruction Register (IR) 24 23 0 MBIST Result Register (MRR) TDI 31 30 29 TDO 0 Identification Register (IDR) 99 Selection Circuitry (MUX) 0 MBIST Debug Register (MDR) 391 0 Boundary Scan Register (BSR) BIST CONTROLLER TAP CONTROLLER CLKBIST TCK TMS MRST MEMORY CELL Table 4. Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 1h Reserved for version number Cypress Device ID (27:12) C000h Defines Cypress part number Cypress JEDEC ID (11:1) 34h Allows unique identification of QuadPort DSE device vendor ID Register Presence (0) 1 Indicate the presence of an ID register Document #: 38-06027 Rev. *B Page 30 of 37 CY7C0430BV CY7C0430CV Table 5. Scan Registers Sizes Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 Identification (IDR) 32 MBIST Control (MCR) 2 MBIST Result (MRR) 25 MBIST Debug (MDR) 100 Boundary Scan (BSR) 392 Table 6. Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the boundary scan register (BSR) between the TDI and TDO. BYPASS 1111 Places the bypass register (BYR) between TDI and TDO. IDCODE 0111 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. HIGHZ 0110 Places the BYR between TDI and TDO. Forces all QuadPort DSE device output drivers to a High-Z state. CLAMP 0101 Controls boundary to 1/0. Uses BYR. SAMPLE/PRELOAD 0001 Captures the Input/Output ring contents. Places the boundary scan register (BSR) between TDI and TDO. CYBIST 1000 Invokes MBIST. Places the MBIST Debug register (MDR) between TDI and TDO. INT_SCAN 0010 Scans out pass-fail information. Places MBIST Result Register (MRR) between TDI and TDO. MCR_SCAN 0011 Presets CYBIST mode. Places MBIST Control Register (MCR) between TDI and TDO. RESERVED All other codes Seven combinations are reserved. Do not use other than the above. Table 7. MBIST Control States States Code State Name Description 000001 movi_zeros Port 1 write all zeros to the QuadPort DSE device memory using Moving Inversion Algorithm (MIA). 000011 movi_1_upcnt Up count from 0 to 64K (depth of QuadPort DSE device). All ports read 0s, then Port 1 writes 1s to all memory locations using MIA, then all ports read 1s. MIA read0_write1_read1 (MIA_r0w1r1). 000010 movi_0_upcnt Up count from 0 to 64K. All ports read 1s, then Port 1 writes 0s, then all ports read 0s (MIA_r1w0r0). 000110 movi_1_downcnt Down count from 64K to 0. MIA_r0w1r1. 000111 movi_0_downcnt Down count MIA_r1w0r0. 000101 movi_read Read all 0s. 000100 mar2_zeros Port 1 write all zeros to memory using March2 Algorithm (M2A). 001100 mar2_1_upcnt Up count M2A_r0w1r1. 001101 mar2_0_upcnt Up count M2A_r1w0r0. 001111 mar2_1_downcnt Down count M2A_r0w1r1. 001110 mar2_0_downcnt Down count M2A_r1w0r0. 001010 mar2_read Read all 0s. 001011 chkr_w Port 1 writes topological checkerboard data to memory. Document #: 38-06027 Rev. *B Page 31 of 37 CY7C0430BV CY7C0430CV Table 7. MBIST Control States (continued) States Code State Name Description 001001 chkr_r All ports read topological checkerboard data. 001000 n_chkr_w Port 1 write inverse topological checkerboard data. 011000 n_chkr_r All ports read inverse topological checkerboard data. 011001 uaddr_zeros2 Port 2 write all zeros to memory using Unique Address Algorithm (UAA). 011011 uaddr_write2 Port 2 writes every address value into its memory location (UAA). 011010 uaddr_read2 All ports read UAA data. 011110 uaddr_ones2 Port 2 writes all ones to memory. 011111 n_uaddr_write2 Port 2 writes inverse address value into memory. 011101 n_uaddr_read2 All ports read inverse UAA data. 011001 uaddr_zeros3 Port 3 write all zeros to memory using Unique Address Algorithm (UAA). 011011 uaddr_write3 Port 3 writes every address value into its memory location (UAA). 011010 uaddr_read3 All ports read UAA data. 011110 uaddr_ones3 Port 3 writes all ones to memory. 011111 n_uaddr_write3 Port 3 writes inverse address value into memory. 011101 n_uaddr_read3 All ports read inverse UAA data. 011001 uaddr_zeros4 Port 4 write all zeros to memory using Unique Address Algorithm (UAA). 011011 uaddr_write4 Port 4 writes every address value into its memory location (UAA). 011010 uaddr_read4 All ports read UAA data. 011110 uaddr_ones4 Port 4 writes all ones to memory. 011111 n_uaddr_write4 Port 4 writes inverse address value into memory. 011101 n_uaddr_read4 All ports read inverse UAA data. 110010 complete Test complete. Table 8. MBIST Control Register (MCR) MCR[1:0] Mode 00 Non-Debug 01 Debug 10 Reserved 11 Reserved Document #: 38-06027 Rev. *B Page 32 of 37 CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order (continued) Table 9. Boundary Scan Order Cell # Signal Name Bump (Ball) ID Cell # Signal Name Bump (Ball) ID 2 A0_P4 K20 84 A10_P3 T20 4 A1_P4 J19 86 A11_P3 T19 6 A2_P4 J18 88 A12_P3 U19 8 A3_P4 H20 90 A13_P3 U18 A14_P3 V20 10 A4_P4 H19 92 12 A5_P4 G19 94 A15_P3 V19 14 A6_P4 G18 96 CNTINT_P3 R17 16 A7_P4 F20 98 CNTRST_P3 L18 MKLD_P3 N18 18 A8_P4 F19 100 20 A9_P4 F18 102 CNTLD_P3 N17 22 A10_P4 E20 104 CNTINC_P3 P17 24 A11_P4 E19 106 CNTRD_P3 T17 MKRD_P3 T18 26 A12_P4 D19 108 28 A13_P4 D18 110 LB_P3 Y20 30 A14_P4 C20 112 UB_P3 W19 32 A15_P4 C19 114 OE_P3 U17 R/W_P3 V16 34 CNTINT_P4 F17 116 36 CNTRST_P4 K18 118 CE1_P3 V18 38 MKLD_P4 H18 120 CE0_P3 V17 40 CNTLD_P4 H17 122 INT_P3 L19 CLK_P3 M17 42 CNTINC_P4 G17 124 44 CNTRD_P4 E17 126 IO0_P4 Y15 46 MKRD_P4 E18 128 IO1_P4 W15 48 LB_P4 A20 130 IO2_P4 Y16 IO3_P4 W16 50 UB_P4 B19 132 52 OE_P4 D17 134 IO4_P4 Y17 54 R/W_P4 C16 136 IO5_P4 W17 56 CE1_P4 C18 138 IO6_P4 Y18 IO7_P4 W18 58 CE0_P4 C17 140 60 INT_P4 K19 142 IO8_P4 Y19 62 CLK_P4 K17 144 IO0_P3 V12 64 A0_P3 L20 146 IO1_P3 Y11 IO2_P3 W12 66 A1_P3 M19 148 68 A2_P3 M18 150 IO3_P3 Y12 70 A3_P3 N20 152 IO4_P3 W13 72 A4_P3 N19 154 IO5_P3 Y13 IO6_P3 V15 74 A5_P3 P19 156 76 A6_P3 P18 158 IO7_P3 Y14 78 A7_P3 R20 160 IO8_P3 W14 80 A8_P3 R19 162 IO0_P1 Y6 R18 164 IO1_P1 W6 82 A9_P3 Document #: 38-06027 Rev. *B Page 33 of 37 CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order (continued) Cell # Signal Name Bump (Ball) ID Table 9. Boundary Scan Order (continued) Cell # Signal Name Bump (Ball) ID 166 IO2_P1 Y5 248 OE_P2 U4 168 IO3_P1 W5 250 R/W_P2 V5 170 IO4_P1 Y4 252 CE1_P2 V3 172 IO5_P1 W4 254 CE0_P2 V4 174 IO6_P1 Y3 256 INT_P2 L2 176 IO7_P1 W3 258 CLK_P2 M4 178 IO8_P1 Y2 260 A0_P1 K1 180 IO0_P2 V9 262 A1_P1 J2 182 IO1_P2 Y10 264 A2_P1 J3 184 IO2_P2 W9 266 A3_P1 H1 186 IO3_P2 Y9 268 A4_P1 H2 188 IO4_P2 W8 270 A5_P1 G2 190 IO5_P2 Y8 272 A6_P1 G3 192 IO6_P2 V6 274 A7_P1 F1 194 IO7_P2 Y7 276 A8_P1 F2 196 IO8_P2 W7 278 A9_P1 F3 198 A0_P2 L1 280 A10_P1 E1 200 A1_P2 M2 282 A11_P1 E2 202 A2_P2 M3 284 A12_P1 D2 204 A3_P2 N1 286 A13_P1 D3 206 A4_P2 N2 288 A14_P1 C1 208 A5_P2 P2 290 A15_P1 C2 210 A6_P2 P3 292 CNTINT_P1 F4 212 A7_P2 R1 294 CNTRST_P1 K3 214 A8_P2 R2 296 MKLD_P1 H3 216 A9_P2 R3 298 CNTLD_P1 H4 218 A10_P2 T1 300 CNTINC_P1 G4 220 A11_P2 T2 302 CNTRD_P1 E4 222 A12_P2 U2 304 MKRD_P1 E3 224 A13_P2 U3 306 LB_P1 A1 226 A14_P2 V1 308 UB_P1 B2 228 A15_P2 V2 310 OE_P1 D4 230 CNTINT_P2 R4 312 R/W_P1 C5 232 CNTRST_P2 L3 314 CE1_P1 C3 234 MKLD_P2 N3 316 CE0_P1 C4 236 CNTLD_P2 N4 318 INT_P1 K2 238 CNTINC_P2 P4 320 CLK_P1 K4 240 CNTRD_P2 T4 322 IO9_P2 A6 242 MKRD_P2 T3 324 IO10_P2 B6 244 LB_P2 Y1 326 IO11_P2 A5 246 UB_P2 W2 328 IO12_P2 B5 Document #: 38-06027 Rev. *B Page 34 of 37 CY7C0430BV CY7C0430CV Table 9. Boundary Scan Order (continued) Cell # Signal Name Bump (Ball) ID 330 IO13_P2 A4 332 IO14_P2 B4 334 IO15_P2 A3 336 IO16_P2 B3 338 IO17_P2 A2 340 IO9_P1 C9 342 IO10_P1 A10 344 IO11_P1 B9 346 IO12_P1 A9 348 IO13_P1 B8 350 IO14_P1 A8 352 IO15_P1 C6 354 IO16_P1 A7 356 IO17_P1 B7 358 IO9_P3 A15 360 IO10_P3 B15 362 IO11_P3 A16 364 IO12_P3 B16 366 IO13_P3 A17 368 IO14_P3 B17 370 IO15_P3 A18 372 IO16_P3 B18 374 IO17_P3 A19 376 IO9_P4 C12 378 IO10_P4 A11 380 IO11_P4 B12 382 IO12_P4 A12 384 IO13_P4 B13 386 IO14_P4 A13 388 IO15_P4 C15 390 IO16_P4 A14 392 IO17_P4 B14 Ordering Information 10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K × 18) Speed (MHz) 133 100 Ordering Code Package Name Package Type Operating Range CY7C0430BV-133BGI BG272 272-ball Grid Array (BGA) Industrial CY7C0430CV-133BGI BG272 272-ball Grid Array (BGA) Industrial CY7C0430BV-100BGC BG272 272-ball Grid Array (BGA) Commercial CY7C0430BV-100BGI BG272 272-ball Grid Array (BGA) Industrial Document #: 38-06027 Rev. *B Page 35 of 37 CY7C0430BV CY7C0430CV Package Diagram 272-Lead PBGA (27 x 27 x 2.33 mm) BG272 51-85130-*A QuadPort is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06027 Rev. *B Page 36 of 37 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C0430BV CY7C0430CV Document History Page Document Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38-06027 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109906 09/10/01 SZV Change from Spec number: 38-01052 to 38-06027 *A 115042 05/23/02 FSG Remove Preliminary, TM from DSE Change RUNBIST to CYBIST Updated ISB values Added notes 7 and 9 Increased commercial prime bin to 135 MHz *B 464083 SEE ECN YDT Part numbers updated to reflect the recent die revisions Removed 1/2M and 1/4M parts Changed title of data sheet Document #: 38-06027 Rev. *B Page 37 of 37