Am49DL6408H Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 30879 Revision A Amendment +3 Issue Date March 12, 2004 THIS PAGE LEFT INTENTIONALLY BLANK. ADVANCE INFORMATION Am49DL6408H Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features ■ Minimum 1 million erase cycles guaranteed per sector ■ Power supply voltage of 2.7 to 3.3 volt ■ 20 year data retention at 125°C — Reliable operation for the life of the system ■ High performance — Access time as fast as 55 ns ■ Package SOFTWARE FEATURES ■ Data Management Software (DMS) — 73-Ball FBGA — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations ■ Operating Temperature — –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank. — Zero latency between read and write operations ■ Flexible Bank™ architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. ■ Manufactured on 0.13 µm process technology ■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Sector is one-time programmable. Once sector is locked, data cannot be changed. ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Boot sectors — Top and bottom boot sectors in the same device ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard ■ Supports Common Flash Memory Interface (CFI) ■ Program/Erase Suspend/Erase Resume — Suspends program/erase operations to allow programming/erasing in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode ■ WP#/ACC input pin — Write protect (WP#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system PERFORMANCE CHARACTERISTICS Pseudo SRAM Features ■ High performance ■ Power dissipation — Access time as fast as 55 ns — Program time: 4 µs/word typical utilizing Accelerate function ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode — Operating: 30 mA maximum — Standby: 100 µA maximum ■ CE1s# and CE2s Chip Select ■ Power down features using CE1s# and CE2s ■ Data retention supply voltage: 2.7 to 3.3 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 30879 Rev: A Amendment/+3 Issue Date: March 12, 2004 Refer to AMD’s Website (www.amd.com) for the latest information. A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION Am29DL640H Features The Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 55, 70 or 85 ns and is offered in a 73-ball FBGA package. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors only. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host sy stem to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640H can be organized as both a top and bottom boot sector configuration. Bank Megabits Bank 1 8 Mb Bank 2 Bank 3 24 Mb 24 Mb Bank 4 8 Mb Sector Sizes Eight 4 Kword, Fifteen 32 Kword Forty-eight 32 Kword Forty-eight 32 Kword Eight 4 Kword, Fifteen 32 Kword The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Customer Indicator Bit (DQ7) is permanently set to a 1 if the part has been customer locked permanently set to 0 if the part has been factory locked, and is 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. 2 Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as a one-time programmable area. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This i s a n a d va n ta g e c o m pa r e d t o s ys te m s w h e r e user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash memory Block Diagram . . . . . . . . . . . . . . . 5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6 Special Package Handling Instructions .................................... 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 MCP Device Bus Operations . . . . . . . . . . . . . . . . . 8 Requirements for Reading Array Data ................................... 10 Writing Commands/Command Sequences ............................ 10 Accelerated Program Operation .......................................... 10 Autoselect Functions ........................................................... 10 Simultaneous Read/Write Operations with Zero Latency ....... 10 Automatic Sleep Mode ........................................................... 11 RESET#: Hardware Reset Pin ............................................... 11 Output Disable Mode .............................................................. 11 Table 2. Am29DL640H Sector Architecture ....................................11 Table 3. Bank Address ....................................................................14 Table 4. SecSi™ Sector Addresses ...............................................14 Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Protection/Unprotection ........................................................................15 Write Protect (WP#) ................................................................ 16 Table 6. WP#/ACC Modes ..............................................................16 Temporary Sector Unprotect .................................................. 16 Figure 1. Temporary Sector Unprotect Operation........................... 16 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 17 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 18 Figure 3. SecSi Sector Protect Verify.............................................. 19 Hardware Data Protection ...................................................... 19 Low VCC Write Inhibit ........................................................... 19 Write Pulse “Glitch” Protection ............................................ 19 Logical Inhibit ...................................................................... 19 Power-Up Write Inhibit ......................................................... 19 Common Flash Memory Interface (CFI) . . . . . . . 19 Flash Command Definitions . . . . . . . . . . . . . . . . 23 Reading Array Data ................................................................ 23 Reset Command ..................................................................... 23 Autoselect Command Sequence ............................................ 23 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 23 Word Program Command Sequence ..................................... 24 Unlock Bypass Command Sequence .................................. 24 Figure 4. Program Operation .......................................................... 25 Chip Erase Command Sequence ........................................... 25 Sector Erase Command Sequence ........................................ 25 Erase Suspend/Erase Resume Commands ........................... 26 Figure 5. Erase Operation............................................................... 26 Flash Write Operation Status . . . . . . . . . . . . . . . . 28 DQ7: Data# Polling ................................................................. 28 Figure 6. Data# Polling Algorithm ................................................... 28 DQ6: Toggle Bit I .................................................................... 29 Figure 7. Toggle Bit Algorithm......................................................... 29 DQ2: Toggle Bit II ................................................................... 30 March 12, 2004 Reading Toggle Bits DQ6/DQ2 ............................................... 30 DQ5: Exceeded Timing Limits ................................................ 30 DQ3: Sector Erase Timer ....................................................... 30 Table 12. Write Operation Status ................................................... 31 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32 Figure 8. Maximum Negative Overshoot Waveform ...................... 32 Figure 9. Maximum Positive Overshoot Waveform........................ 32 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33 CMOS Compatible .................................................................. 33 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 34 Figure 11. Typical ICC1 vs. Frequency ............................................ 34 Pseudo SRAM DC and Operating Characteristics . . . . . . . . . . . . . . . . . . 35 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 12. Test Setup.................................................................... 36 Figure 13. Input Waveforms and Measurement Levels ................. 36 Figure 14. ...................................................................................... 36 Read-Only Operations ........................................................... 37 Figure 15. Read Operation Timings ............................................... 37 Hardware Reset (RESET#) .................................................... 38 Figure 16. Reset Timings ............................................................... 38 Erase and Program Operations .............................................. 39 Figure 17. Program Operation Timings.......................................... Figure 18. Accelerated Program Timing Diagram.......................... Figure 19. Chip/Sector Erase Operation Timings .......................... Figure 20. Back-to-back Read/Write Cycle Timings ...................... Figure 21. Data# Polling Timings (During Embedded Algorithms). Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... Figure 23. DQ2 vs. DQ6................................................................. 40 40 41 42 42 43 43 Temporary Sector Unprotect .................................................. 44 Figure 24. Temporary Sector Unprotect Timing Diagram .............. 44 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 45 Alternate CE#f Controlled Erase and Program Operations .... 46 Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings.......................................................................... 47 Pseudo SRAM AC Characteristics . . . . . . . . . . . 48 Power Up Time ....................................................................... 48 Read Cycle ............................................................................. 48 Figure 27. Pseudo SRAM Read Cycle—Address Controlled......... 48 Figure 28. Pseudo SRAM Read Cycle........................................... 49 Write Cycle ............................................................................. 50 Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 50 Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................ 51 Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control.................................................................. 52 Flash Erase And Programming Performance . . 53 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 53 Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 53 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 53 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 54 FLJ073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .............. 54 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55 Am49DL6408H 3 A D V A N C E I N F O R M A T I O N PRODUCT SELECTOR GUIDE Part Number Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Am49DL6408H Flash Memory Pseudo SRAM 55 70 85 55 70, 85 Max Access Time (ns) 55 70 85 55 70 CE#f Access (ns) 55 70 85 55 70 OE# Access (ns) 25 30 40 30 35 MCP BLOCK DIAGRAM VCCf A21 to A0 VSS A21 to A0 WP#/ACC RY/BY 64 MBit Flash Memory RESET# CE#f DQ15 to DQ0 VCCS/VCCQ VSS/VSSQ A18 to A0 LB#s UB#s WE# OE# CE1#s CE2s 4 DQ15 to DQ0 RY/BY# 8 MBit Flash Memory pSRAM Am49DL6408H DQ15 to DQ0 March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH MEMORY BLOCK DIAGRAM VCC VSS OE# Mux Bank 1 Bank 2 X-Decoder A21–A0 RESET# WE# CE# WP#/ACC STATE CONTROL & COMMAND REGISTER Status DQ15–DQ0 Control Mux DQ15–DQ0 DQ15–DQ0 Bank 3 Address Bank 3 X-Decoder Bank 4 Address Y-gate A0–A21 X-Decoder A21–A0 DQ15–DQ0 Bank 2 Address DQ15–DQ0 RY/BY# DQ15–DQ0 A21–A0 X-Decoder Y-gate Bank 1 Address A21–A0 Bank 4 Mux March 12, 2004 Am49DL6408H 5 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAM 73-Ball FBGA Top View A1 A10 NC NC B1 B5 B6 B10 NC NC NC NC C5 C3 C4 C6 C7 C8 NC A7 LB# WP#/ACC WE# A8 A11 D2 D3 D4 D7 D8 D9 A3 A6 UB# A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RY/BY# A20 A9 A13 A21 F1 F2 F3 F4 F7 F8 F9 F10 NC A1 A4 A17 A10 A14 NC NC G1 G2 G3 G4 G7 G8 G9 G10 NC A0 VSS DQ1 DQ6 NC A16 NC H2 H3 H4 H5 H6 H7 H8 H9 CE#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 NC J2 J3 J4 J5 J6 J7 J8 J9 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS K3 K4 K5 K6 K7 K8 DQ8 DQ2 DQ11 NC DQ5 DQ14 L1 L5 L6 L10 NC NC NC NC D6 RESET# CE2s M1 M10 NC NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be 6 Pseudo SRAM only Shared C1 D5 Flash only compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N PIN DESCRIPTION LOGIC SYMBOL A18–A0 = 19 Address Inputs (Common) A21–A19 = 3 Address Inputs (Flash) SA = Lowest Order Address Pin (PSRAM) Byte mode A21–A19 DQ15–DQ0 = 16 Data Inputs/Outputs (Common) SA CE#f = Chip Enable (Flash) CE#1s = Chip Enable 1 (PSRAM) CE2s = Chip Enable 2 (PSRAM) OE# = Output Enable (Common) 19 A18–A0 CE#f DQ15–DQ0 CE1#s CE2s OE# WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (PSRAM) LB#s = Lower Byte Control (PSRAM) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = PSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally March 12, 2004 16 RY/BY# WE# WP#/ACC RESET# UB#s LB#s Am49DL6408H 7 A D V A N C E I N F O R M A T I O N ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49DL640 8 H 70 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE AND PACKAGE TYPE I = Industrial (–40°C to +85°C) and Pb-free compliant package (FLJ073) F = Industrial (–40°C to +85°C) and Pb-free package (FLJ073) SPEED OPTION See Product Selector Guide and Valid Combinations PROCESS TECHNOLOGY H = 0.13 µm Pseudo SRAM DEVICE DENSITY 8 = 8 Mbits AMD DEVICE NUMBER/DESCRIPTION Am49DL6408H Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL640H 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM Valid Combinations Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD or Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. Order Number Package Marking Am49DL6408H55I M49000003X Am49DL6408H70I M49000003F Am49DL6408H85I M49000003G T, S MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information 8 Am49DL6408H55F M49000003Y Am49DL6408H70F M49000003H Am49DL6408H85F M49000003I needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-3 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am49DL6408H March 12, 2004 A D V A N C E Table 1. Operation (Notes 1, 2) CE#f Device Bus Operations—Flash Word Mode; PSRAM Word Mode CE1#s CE2s OE# WE# H X X L H X X L VCC ± 0.3 V H X X L Output Disable L L H Flash Hardware Reset X H X X L H X X L H X X L H X X L Read from Flash L Write to Flash L Standby Sector Protect (Note 5) L Sector Unprotect (Note 5) L Temporary Sector Unprotect X Read from PSRAM Write to PSRAM H H I N F O R M A T I O N L L H H Addr. LB#s UB#s RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 L H AIN X X H L/H DOUT DOUT H L AIN X X H (Note 4) DIN DIN X X X X X VCC ± 0.3 V H High-Z High-Z H H X L X H H X X L H L/H High-Z High-Z X X X X X L L/H High-Z High-Z L SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X H L SADD, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X X X X X X VID (Note 6) DIN High-Z L L DOUT DOUT H L X H L AIN AIN H L High-Z DOUT L H DOUT High-Z L L DIN DIN H L High-Z DIN L H DIN High-Z H H X X Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. March 12, 2004 Am49DL6408H 9 A D V A N C E I N F O R M A T I O N Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to VIL. CE#f is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table for timing specifications and to Figure 15 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Flash Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The Flash AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass 10 mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page 16 for related information. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6f and ICC7f in the table represent the current specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE#f and RESET# are held at V IH , but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N ICC3f in the table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5f in the table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Table 2. Bank Bank 1 March 12, 2004 Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (I CC4 f). If RESET# is held at VIL but not within V SS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the Flash DC characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29DL640H Sector Architecture Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range SA0 0000000000 4 00000h–00FFFh SA1 0000000001 4 01000h–01FFFh SA2 0000000010 4 02000h–02FFFh SA3 0000000011 4 03000h–03FFFh SA4 0000000100 4 04000h–04FFFh SA5 0000000101 4 05000h–05FFFh SA6 0000000110 4 06000h–06FFFh SA7 0000000111 4 07000h–07FFFh SA8 0000001xxx 32 08000h–0FFFFh SA9 0000010xxx 32 10000h–17FFFh SA10 0000011xxx 32 18000h–1FFFFh SA11 0000100xxx 32 20000h–27FFFh SA12 0000101xxx 32 28000h–2FFFFh SA13 0000110xxx 32 30000h–37FFFh SA14 0000111xxx 32 38000h–3FFFFh SA15 0001000xxx 32 40000h–47FFFh SA16 0001001xxx 32 48000h–4FFFFh SA17 0001010xxx 32 50000h–57FFFh SA18 0001011xxx 32 58000h–5FFFFh SA19 0001100xxx 32 60000h–67FFFh SA20 0001101xxx 32 68000h–6FFFFh SA21 0001101xxx 32 70000h–77FFFh SA22 0001111xxx 32 78000h–7FFFFh Am49DL6408H 11 A D V A N C E Table 2. Bank Bank 2 12 I N F O R M A T I O N Am29DL640H Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kwords) SA23 0010000xxx 32 80000h–87FFFh SA24 0010001xxx 32 88000h–8FFFFh SA25 0010010xxx 32 90000h–97FFFh SA26 0010011xxx 32 98000h–9FFFFh SA27 0010100xxx 32 A0000h–A7FFFh SA28 0010101xxx 32 A8000h–AFFFFh SA29 0010110xxx 32 B0000h–B7FFFh SA30 0010111xxx 32 B8000h–BFFFFh SA31 0011000xxx 32 C0000h–C7FFFh SA32 0011001xxx 32 C8000h–CFFFFh SA33 0011010xxx 32 D0000h–D7FFFh SA34 0011011xxx 32 D8000h–DFFFFh SA35 0011000xxx 32 E0000h–E7FFFh SA36 0011101xxx 32 E8000h–EFFFFh SA37 0011110xxx 32 F0000h–F7FFFh SA38 0011111xxx 32 F8000h–FFFFFh SA39 0100000xxx 32 F9000h–107FFFh SA40 0100001xxx 32 108000h–10FFFFh SA41 0100010xxx 32 110000h–117FFFh SA42 0101011xxx 32 118000h–11FFFFh SA43 0100100xxx 32 120000h–127FFFh SA44 0100101xxx 32 128000h–12FFFFh SA45 0100110xxx 32 130000h–137FFFh SA46 0100111xxx 32 138000h–13FFFFh SA47 0101000xxx 32 140000h–147FFFh SA48 0101001xxx 32 148000h–14FFFFh SA49 0101010xxx 32 150000h–157FFFh SA50 0101011xxx 32 158000h–15FFFFh SA51 0101100xxx 32 160000h–167FFFh SA52 0101101xxx 32 168000h–16FFFFh SA53 0101110xxx 32 170000h–177FFFh SA54 0101111xxx 32 178000h–17FFFFh SA55 0110000xxx 32 180000h–187FFFh SA56 0110001xxx 32 188000h–18FFFFh SA57 0110010xxx 32 190000h–197FFFh SA58 0110011xxx 32 198000h–19FFFFh SA59 0100100xxx 32 1A0000h–1A7FFFh SA60 0110101xxx 32 1A8000h–1AFFFFh SA61 0110110xxx 32 1B0000h–1B7FFFh SA62 0110111xxx 32 1B8000h–1BFFFFh SA63 0111000xxx 32 1C0000h–1C7FFFh SA64 0111001xxx 32 1C8000h–1CFFFFh SA65 0111010xxx 32 1D0000h–1D7FFFh SA66 0111011xxx 32 1D8000h–1DFFFFh SA67 0111100xxx 32 1E0000h–1E7FFFh SA68 0111101xxx 32 1E8000h–1EFFFFh SA69 0111110xxx 32 1F0000h–1F7FFFh SA70 0111111xxx 32 1F8000h–1FFFFFh Am49DL6408H (x16) Address Range March 12, 2004 A D V A N C E Table 2. Bank Bank 3 March 12, 2004 I N F O R M A T I O N Am29DL640H Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range SA71 1000000xxx 32 200000h–207FFFh SA72 1000001xxx 32 208000h–20FFFFh SA73 1000010xxx 32 210000h–217FFFh SA74 1000011xxx 32 218000h–21FFFFh SA75 1000100xxx 32 220000h–227FFFh SA76 1000101xxx 32 228000h–22FFFFh SA77 1000110xxx 32 230000h–237FFFh SA78 1000111xxx 32 238000h–23FFFFh SA79 1001000xxx 32 240000h–247FFFh SA80 1001001xxx 32 248000h–24FFFFh SA81 1001010xxx 32 250000h–257FFFh SA82 1001011xxx 32 258000h–25FFFFh SA83 1001100xxx 32 260000h–267FFFh SA84 1001101xxx 32 268000h–26FFFFh SA85 1001110xxx 32 270000h–277FFFh SA86 1001111xxx 32 278000h–27FFFFh SA87 1010000xxx 32 280000h–28FFFFh SA88 1010001xxx 32 288000h–28FFFFh SA89 1010010xxx 32 290000h–297FFFh SA90 1010011xxx 32 298000h–29FFFFh SA91 1010100xxx 32 2A0000h–2A7FFFh SA92 1010101xxx 32 2A8000h–2AFFFFh SA93 1010110xxx 32 2B0000h–2B7FFFh SA94 1010111xxx 32 2B8000h–2BFFFFh SA95 1011000xxx 32 2C0000h–2C7FFFh SA96 1011001xxx 32 2C8000h–2CFFFFh SA97 1011010xxx 32 2D0000h–2D7FFFh SA98 1011011xxx 32 2D8000h–2DFFFFh SA99 1011100xxx 32 2E0000h–2E7FFFh SA100 1011101xxx 32 2E8000h–2EFFFFh SA101 1011110xxx 32 2F0000h–2FFFFFh SA102 1011111xxx 32 2F8000h–2FFFFFh SA103 1100000xxx 32 300000h–307FFFh SA104 1100001xxx 32 308000h–30FFFFh SA105 1100010xxx 32 310000h–317FFFh SA106 1100011xxx 32 318000h–31FFFFh SA107 1100100xxx 32 320000h–327FFFh SA108 1100101xxx 32 328000h–32FFFFh SA109 1100110xxx 32 330000h–337FFFh SA110 1100111xxx 32 338000h–33FFFFh SA111 1101000xxx 32 340000h–347FFFh SA112 1101001xxx 32 348000h–34FFFFh SA113 1101010xxx 32 350000h–357FFFh SA114 1101011xxx 32 358000h–35FFFFh SA115 1101100xxx 32 360000h–367FFFh SA116 1101101xxx 32 368000h–36FFFFh SA117 1101110xxx 32 370000h–377FFFh SA118 1101111xxx 32 378000h–37FFFFh Am49DL6408H 13 A D V A N C E Table 2. Bank Bank 4 Am29DL640H Sector Architecture (Continued) Sector Address A21–A12 Sector I N F O R M A T I O N Sector Size (Kwords) (x16) Address Range SA119 1110000xxx 32 380000h–387FFFh SA120 1110001xxx 32 388000h–38FFFFh SA121 1110010xxx 32 390000h–397FFFh SA122 1110011xxx 32 398000h–39FFFFh SA123 1110100xxx 32 3A0000h–3A7FFFh SA124 1110101xxx 32 3A8000h–3AFFFFh SA125 1110110xxx 32 3B0000h–3B7FFFh SA126 1110111xxx 32 3B8000h–3BFFFFh SA127 1111000xxx 32 3C0000h–3C7FFFh SA128 1111001xxx 32 3C8000h–3CFFFFh SA129 1111010xxx 32 3D0000h–3D7FFFh SA130 1111011xxx 32 3D8000h–3DFFFFh SA131 1111100xxx 32 3E0000h–3E7FFFh SA132 1111101xxx 32 3E8000h–3EFFFFh SA133 1111110xxx 32 3F0000h–3F7FFFh SA134 1111111000 4 3F8000h–3F8FFFh SA135 1111111001 4 3F9000h–3F9FFFh SA136 1111111010 4 3FA000h–3FAFFFh SA137 1111111011 4 3FB000h–3FBFFFh SA138 1111111100 4 3FC000h–3FCFFFh SA139 1111111101 4 3FD000h–3FDFFFh SA140 1111111110 4 3FE000h–3FEFFFh SA141 1111111111 4 3FF000h–3FFFFFh Note: The address range is A21:A0. Table 3. Bank Address Bank 1 2 3 4 A21–A19 000 001, 010, 011 100, 101, 110 111 Table 4. 14 SecSi™ Sector Addresses Device Sector Size (x16) Address Range Am29DL640H 256 bytes 00000h–0007Fh Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N Sector/Sector Block Protection and Unprotection Sector A21–A12 Sector/ Sector Block Size (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 5). SA63–SA66 01110XXXXX 256 (4x64) Kbytes SA67–SA70 01111XXXXX 256 (4x64) Kbytes SA71–SA74 10000XXXXX 256 (4x64) Kbytes SA75–SA78 10001XXXXX 256 (4x64) Kbytes SA79–SA82 10010XXXXX 256 (4x64) Kbytes The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. SA83–SA86 10011XXXXX 256 (4x64) Kbytes SA87–SA90 10100XXXXX 256 (4x64) Kbytes SA91–SA94 10101XXXXX 256 (4x64) Kbytes SA95–SA98 10110XXXXX 256 (4x64) Kbytes SA99–SA102 10111XXXXX 256 (4x64) Kbytes Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21–A12 Sector/ Sector Block Size SA0 0000000000 8 Kbytes SA103–SA106 11000XXXXX 256 (4x64) Kbytes SA107–SA110 11001XXXXX 256 (4x64) Kbytes SA111–SA114 11010XXXXX 256 (4x64) Kbytes SA115–SA118 11011XXXXX 256 (4x64) Kbytes SA119–SA122 11100XXXXX 256 (4x64) Kbytes SA123–SA126 11101XXXXX 256 (4x64) Kbytes SA127–SA130 11110XXXXX 256 (4x64) Kbytes SA131–SA133 1111100XXX, 1111101XXX, 1111110XXX 192 (3x64) Kbytes SA1 0000000001 8 Kbytes SA2 0000000010 8 Kbytes SA3 0000000011 8 Kbytes SA4 0000000100 8 Kbytes SA134 1111111000 8 Kbytes SA5 0000000101 8 Kbytes SA135 1111111001 8 Kbytes SA6 0000000110 8 Kbytes SA136 1111111010 8 Kbytes SA7 0000000111 8 Kbytes SA137 1111111011 8 Kbytes SA138 1111111100 8 Kbytes SA8–SA10 0000001XXX, 0000010XXX, 0000011XXX, SA139 1111111101 8 Kbytes SA140 1111111110 8 Kbytes SA141 1111111111 8 Kbytes 192 (3x64) Kbytes SA11–SA14 00001XXXXX 256 (4x64) Kbytes SA15–SA18 00010XXXXX 256 (4x64) Kbytes SA19–SA22 00011XXXXX 256 (4x64) Kbytes SA23–SA26 00100XXXXX 256 (4x64) Kbytes SA27-SA30 00101XXXXX 256 (4x64) Kbytes SA31-SA34 00110XXXXX 256 (4x64) Kbytes SA35-SA38 00111XXXXX 256 (4x64) Kbytes SA39-SA42 01000XXXXX 256 (4x64) Kbytes SA43-SA46 01001XXXXX 256 (4x64) Kbytes SA47-SA50 01010XXXXX 256 (4x64) Kbytes SA51-SA54 01011XXXXX 256 (4x64) Kbytes SA55–SA58 01100XXXXX 256 (4x64) Kbytes SA59–SA62 01101XXXXX 256 (4x64) Kbytes March 12, 2004 The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 25 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See “Temporary Sector Unprotect”. Am49DL6408H 15 A D V A N C E I N F O R M A T I O N The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See the Sector/Sector Block Protection and Unprotection section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting without using VID. This function is one of two provided by the WP#/ACC pin. Temporary Sector Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 5). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 24 shows the timing diagrams, for this feature. If the WP#/ACC pin is at VIL , sectors 0, 1, 140, and 141 will remain protected during the Temporary sector Unprotect mode. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. START If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. RESET# = VID (Note 1) Perform Erase or Program Operations Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Table 6. WP# Input Voltage RESET# = VIH WP#/ACC Modes Temporary Sector Unprotect Completed (Note 2) Device Mode VIL Disables programming and erasing in SA0, SA1, SA140, and SA141 VIH Enables programming and erasing in SA0, SA1, SA140, and SA141 VHH Enables accelerated programming (ACC). See “Accelerated Program Operation” on page 10. Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 140, and 141 will remain protected). 2. All previously protected sectors are protected once again. Figure 1. 16 Am49DL6408H Temporary Sector Unprotect Operation March 12, 2004 A D V A N C E I N F O R M A T I O N START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 µs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 µs No First Write Cycle = 60h? First Write Cycle = 60h? Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 150 µs Increment PLSCNT Temporary Sector Unprotect Mode Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Reset PLSCNT = 1 Read from sector address with A6 = 0, A1 = 1, A0 = 0 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Increment PLSCNT No No PLSCNT = 25? Yes Yes No Yes Device failed Read from sector address with A6 = 1, A1 = 1, A0 = 0 Data = 01h? Protect another sector? PLSCNT = 1000? No Data = 00h? Yes Yes Remove VID from RESET# Device failed Last sector verified? Write reset command Sector Protect Algorithm Sector Protect complete Set up next sector address No No Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. March 12, 2004 In-System Sector Protect/Unprotect Algorithms Am49DL6408H 17 A D V A N C E I N F O R M A T I O N SecSi™ (Secured Silicon) Sector Flash Memory Region addresses 000008h–00000Fh. The device is available preprogrammed with one of the following: The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. ■ A random, secure ESN only AMD offers the device with the SecSi Sector either factor y locked o r custom er locka ble . Th e factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector Secure through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number will at addresses 000000h–000007h in word mode. The secure ESN will be programmed in the next 8 words at 18 ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. START RESET# = VIH or VID Wait 1 µs Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Figure 3. Logical Inhibit If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle, CE#f and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit Remove VIH or VID from RESET# If WE# = CE#f = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Write reset command COMMON FLASH MEMORY INTERFACE (CFI) SecSi Sector Protect Verify complete The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 11 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. March 12, 2004 This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 7–10. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 7–10. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. Am49DL6408H 19 A D V A N C E Table 7. I N F O R M A T I O N CFI Query Identification String Addresses (Word Mode) Addresses (Byte Mode) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Table 8. Description System Interface String Addresses (Word Mode) Addresses (Byte Mode) Data 1Bh 36h 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0003h Typical timeout per single byte/word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 0009h Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) 20 Description Am49DL6408H March 12, 2004 A D V A N C E Table 9. Addresses (Word Mode) Addresses (Byte Mode) I N F O R M A T I O N Device Geometry Definition Data Description N 27h 4Eh 0017h Device Size = 2 byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 007Dh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) March 12, 2004 Am49DL6408H 21 A D V A N C E Table 10. I N F O R M A T I O N Primary Vendor-Specific Extended Query Addresses (Word Mode) Addresses (Byte Mode) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 8Ah 0004h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Description Silicon Revision Number (Bits 7-2) 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode 4Ah 94h 0077h Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1) 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 0085h 4Eh 9Ch 0095h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 22 4Fh 9Eh 0001h 50h A0h 0001h 57h AEh 0004h 58h B0h 0017h 59h B2h 0030h 5Ah B4h 0030h 5Bh B6h 0017h 00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 11 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever happens first. Refer to the Flash AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The Read-Only Operations table provides the read parameters, and Figure 15 shows the timing diagram. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset c o m m an d re t ur n s t h at b a nk t o t he e ra s e- s us pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Reset Command Table 11 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SADD). Table 2 shows the address range and bank number associated with each sector. Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. March 12, 2004 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Am49DL6408H 23 A D V A N C E I N F O R M A T I O N Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 11 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 11 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Flash Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- 24 ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 11 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. START Write Program Command Sequence Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Data Poll from System Embedded Program algorithm in progress Sector Erase Command Sequence Verify Data? No Yes Increment Address No Last Address? The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Yes Programming Completed Note: See Table 11 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 11 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Flash Write Operation Status section for information on these status bits. March 12, 2004 Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 11 shows the address and data requirements for the sector erase command sequence. After the command sequence is written, a sector erase time-out of 80 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e ct o r E ra se o r E ra s e S u s p en d d u r i n g th e time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read Am49DL6408H 25 A D V A N C E I N F O R M A T I O N data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Flash Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Erase Suspend/Erase Resume Commands program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the Flash Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. START Write Erase Command Sequence (Notes 1, 2) When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Flash Write Operation Status section for information on these status bits. Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Yes Erasure Completed Notes: 1. See Table 11 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the 26 Data = FFh? Am49DL6408H Figure 5. Erase Operation March 12, 2004 A D V A N C E Autoselect (Note 8) Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Manufacturer ID Word Device ID (Note 9) Word SecSi Sector Factory Word Protect (Note 10) Sector/Sector Block Protect Verify Word (Note 11) Enter SecSi Sector Region Word Exit SecSi Sector Region Word Program Word Unlock Bypass Word Unlock Bypass Program (Note 12) Unlock Bypass Reset (Note 13) Chip Erase Word Sector Erase Word Erase Suspend (Note 14) Erase Resume (Note 15) CFI Query (Note 16) Word Cycles Table 11. 1 1 4 6 First Addr Data RA RD XXX F0 555 AA 555 AA I N F O R M A T I O N Am29DL640H Command Definitions Second Addr Data 2AA 2AA 55 55 (BA)555 (BA)555 90 90 (BA)X00 (BA)X01 01 7E 4 555 AA 2AA 55 (BA)555 90 (BA)X03 80/00 4 555 AA 2AA 55 (BA)555 90 (SADD) 00/01 X02 3 4 4 3 2 2 6 6 1 1 1 555 555 555 555 XXX XXX 555 555 BA BA 55 AA AA AA AA A0 90 AA AA B0 30 98 2AA 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 55 PD 00 55 55 555 555 555 555 88 90 A0 20 XXX PA 00 PD 555 555 80 80 555 555 AA AA Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. Notes: 1. See Tables 1 to 3 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A21–A12 are don’t cares for unlock and command cycles, unless SADD or PA is required. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. March 12, 2004 Bus Cycles (Notes 2–5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data (BA)X0E 02 (BA)X0F 01 2AA 2AA 55 55 555 SADD 10 30 PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SADD = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A12 uniquely select any sector. Refer to Table 2 for information on sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Address bits A21–A19 select a bank. Refer to Table 3 for information on sector addresses. 9. 10. 11. 12. 13. 14. 15. 16. The device ID must be read across the fourth, fifth, and sixth cycles. The data is 80h for factory locked, 40h for customer locked and 00h for not factory locked. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. The Unlock Bypass command is required prior to the Unlock Bypass Program command. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. Command is valid when device is ready to read array data or when device is in autoselect mode. Am49DL6408H 27 A D V A N C E I N F O R M A T I O N FLASH WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm. Figure 21 in the Flash AC Characteristics section shows the Data# Polling timing diagram. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. START Read DQ7–DQ0 Addr = VA DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. 28 DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ8 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has com- Yes DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am49DL6408H Figure 6. Data# Polling Algorithm March 12, 2004 A D V A N C E I N F O R M A T I O N RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 22 in the “Flash AC Characteristics” section shows the toggle bit timing diagrams. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. START Table 12 shows the outputs for RY/BY#. Read Byte (DQ7–DQ0) Address =VA DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#f to control the read cycles. When the operation is complete, DQ6 stops toggling. Read Byte (DQ7–DQ0) Address =VA Toggle Bit = Toggle? Yes No After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. DQ5 = 1? Yes Read Byte Twice (DQ7–DQ0) Address = VA The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 7. March 12, 2004 No Am49DL6408H Toggle Bit Algorithm 29 A D V A N C E I N F O R M A T I O N DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE#f to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 22 shows the toggle bit timing diagram. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for byte mode) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0 for byte mode) on the following read cycle. not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has Table 12 shows the status of DQ3 relative to the other status bits. 30 Am49DL6408H March 12, 2004 A D V A N C E Table 12. Standard Mode Erase Suspend Mode Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program I N F O R M A T I O N Write Operation Status DQ7 (Note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle RY/BY# 0 0 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 DQ7# Toggle 0 N/A N/A 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. March 12, 2004 Am49DL6408H 31 A D V A N C E I N F O R M A T I O N ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C 20 ns Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +85°C +0.8 V Voltage with Respect to Ground –0.5 V VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V 20 ns –2.0 V WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V 20 ns All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 8. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pins RESET#, and WP#/ACC is –0 .5 V. During voltage transitions, WP#/ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. Figure 8. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 20 ns 20 ns Figure 9. Maximum Positive Overshoot Waveform Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C VCCf/VCCs Supply Voltages VCCf/VCCs for standard voltage range . . 2.7 V to 3.3 V Operating ranges define those limits between which the functionality of the device is guaranteed. 32 Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions ILI Input Load Current VIN = VSS to VCC, VCC = VCC max Min Typ Max Unit ±1.0 µA ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V 35 µA ILIT RESET# Input Load Current VCC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max, WP#/ACC = VACC max 35 µA ICC1f ICC2f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Byte Mode 5 MHz 10 1 MHz 2 4 CE#f = VIL, OE# = VIH, Word Mode 5 MHz 10 16 1 MHz 2 4 Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL 16 mA 15 30 mA 0.2 5 µA ICC3f Flash VCC Standby Current (Note 2) VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf ± 0.3 V ICC4f Flash VCC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ± 0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 5 µA ICC5f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCCf = VCC max, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = VIL, OE# = VIH Word 21 45 mA ICC7f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH Word 21 45 mA ICC8f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH 17 35 mA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 VCC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 11.5 12.5 V VOL Output Low Voltage 0.45 V VOH1 Output High Voltage VOH2 VLKO IOL = 2.0 mA, VCCf = VCCs = VCC min IOH = –2.0 mA, VCCf = VCCs = VCC min IOH = –100 µA, VCC = VCC min Flash Low VCC Lock-Out Voltage (Note 5) 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. V VCC–0.4 2.0 Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. March 12, 2004 0.85 x VCC 2.5 V 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Am49DL6408H 33 A D V A N C E I N F O R M A T I O N FLASH DC CHARACTERISTICS Zero-Power Flash Supply Current in mA 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note: Addresses are switching at 1 MHz Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 12 3.3 V 10 2.7 V Supply Current in mA 8 6 4 2 0 1 2 3 4 5 Frequency in MHz Note: T = 25 °C Figure 11. Typical ICC1 vs. Frequency 6. 34 Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N PSEUDO SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC1s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V, VCC = 3.3 V 3 5 mA ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL or VIH, VCC = 3.3 V 12 23 mA VIL Input Low Voltage –0.2 (Note 3) 0.4 V VIH Input High Voltage 2.2 VCC+0.2 (Note 2) V VOL Output Low Voltage IOL = 2.0 mA 0.4 V VOH Output High Voltage IOH = –1.0 mA ISB Standby Current (TTL) CE1#s = VIH, CE2 = VIL, Other inputs = VIH or VIL 0.3 mA ISB1 Standby Current (CMOS) CE1#s=VIH, CE2= VIL: Other inputs = VIH or VIL: tA = 85°C, VCC = 3.0 V 60 µA ISB2 Standby Current (CMOS) CE1#s=VIH, CE2= VIL: Other inputs = VIH or VIL: tA = 85°C, VCC = 3.3 V 85 µA 2.2 V Notes: 1. TA= –40° to 85°C, otherwise specified. 2. 3. 4. 5. Overshoot: VCC+1.0V if pulse width ≤ 20 ns. Undershoot: –1.0V if pulse width ≤ 20 ns. Overshoot and undershoot are sampled, not 100% tested. Stable power supply required 200 µs before device operation. March 12, 2004 Am49DL6408H 35 A D V A N C E I N F O R M A T I O N TEST CONDITIONS Table 13. 3.3 V Test Condition 55, 70, 85 Output Load 2.7 kΩ Device Under Test Test Specifications 1 TTL gate Output Load Capacitance, CL (including jig capacitance) CL 30 Input Rise and Fall Times 6.2 kΩ Figure 12. 100 pF 5 ns 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Input Pulse Levels Note: Diodes are IN3064 or equivalent Unit Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) KS000010-PAL 3.0 V Input 1.5 V Measurement Level 1.5 V Output 0.0 V Figure 13. Input Waveforms and Measurement Levels Figure 14. 36 Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Read-Only Operations Parameter Speed JEDEC Std. Description Test Setup 55 70 85 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 70 85 ns tAVQV tACC Address to Output Delay CE#f, OE# = VIL Max 55 70 85 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 85 ns tGLQV tOE Output Enable to Output Delay Max 25 30 40 ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min 0 ns Read Min 0 ns tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling Min 10 ns Notes: 1. Not 100% tested. 2. See Figure 12 and Table 13 for test specifications 3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF . tRC Addresses Stable Addresses tACC CE#f tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 15. March 12, 2004 Read Operation Timings Am49DL6408H 37 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#f, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#f, OE# RESET# tRP Figure 16. 38 Reset Timings Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Erase and Program Operations Parameter Speed JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min tAHT Address Hold Time From CE#f or OE# high during toggle bit polling Min tDVWH tDS Data Setup Time Min tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns tELWL tCS CE#f Setup Time Min 0 ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns tWHEH tCH CE#f Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns Typ 7 µs tWLAX 70 85 Unit 55 70 85 ns 30 40 45 0 30 25 40 30 ns ns 45 35 ns ns tWHWH1 tWHWH1 Programming Operation (Note 2) tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Max 90 ns tBUSY Word 55 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. March 12, 2004 Am49DL6408H 39 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE#f tCH tGHWL OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status tBUSY DOUT tRB RY/BY# VCCf tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. Program Operation Timings VHH WP#/ACC VIL or VIH VIL or VIH tVHH Figure 18. 40 tVHH Accelerated Program Timing Diagram Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SADD VA 555h for chip erase tAH CE#f tGHWL tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCCf Notes: 1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”. 2. These waveforms are for the word mode. Figure 19. March 12, 2004 Chip/Sector Erase Operation Timings Am49DL6408H 41 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Addresses tWC tWC tRC Valid PA Valid RA tWC Valid PA Valid PA tAH tCPH tACC tCE CE#f tCP tOE OE# tOEH tGHWL tWP WE# tDF tWPH tDS tOH tDH Valid Out Valid In Data Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle Figure 20. CE#f Controlled Write Cycles Back-to-back Read/Write Cycle Timings tRC Addresses VA VA VA tACC tCE CE#f tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data True Valid Data High Z True Valid Data tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. 42 Data# Polling Timings (During Embedded Algorithms) Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS tAHT tAS Addresses tAHT tASO CE#f tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data Valid Data RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 22. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to toggle DQ2 and DQ6. Figure 23. March 12, 2004 DQ2 vs. DQ6 Am49DL6408H 43 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min 4 µs Note: Not 100% tested. VID RESET# VID VSS, VIL, or VIH VSS, VIL, or VIH tVIDR tVIDR Program or Erase Command Sequence CE#f WE# tRRB tRSP RY/BY# Figure 24. 44 Temporary Sector Unprotect Timing Diagram Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS VID VIH RESET# SADD, A6, A1, A0 Valid* Valid* Sector/Sector Block Protect or Unprotect Data 60h 60h Valid* Verify 40h Status Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs CE#f WE# OE# * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address. Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram March 12, 2004 Am49DL6408H 45 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter Speed JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 30 40 45 ns tDVEH tDS Data Setup Time Min 30 40 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE#f Pulse Width Min 25 tEHEL tCPH CE#f Pulse Width High Min 25 tWHWH1 tWHWH1 Programming Operation (Note 2) tWHWH1 tWHWH1 tWHWH2 tWHWH2 Word 55 70 85 Unit 55 70 85 ns 0 ns 40 45 30 ns ns Typ 7 µs Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs Sector Erase Operation (Note 2) Typ 0.4 sec Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. 46 Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE#f tWS tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SADD = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 26. March 12, 2004 Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings Am49DL6408H 47 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS Power Up Time When powering up the SRAM, maintain VCCs for 100 µs minimum with CE#1s at VIH. Read Cycle Parameter Symbol Speed Description Unit 55 70, 85 tRC Read Cycle Time Min 55 70 ns tAA Address Access Time Max 55 70 ns tCO1, tCO2 Chip Enable to Output Max 55 70 ns tOE Output Enable Access Time Max 30 35 ns tBA LB#s, UB#s to Access Time Max 55 70 ns Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min 5 ns tBLZ UB#, LB# Enable to Low-Z Output Min 5 ns tOLZ Output Enable to Low-Z Output Min 5 ns tHZ1, tHZ2 Chip Disable to High-Z Output Max 20 25 ns tBHZ UB#s, LB#s Disable to High-Z Output Max 20 25 ns tOHZ Output Disable to High-Z Output Max 20 25 ns tOH Output Data Hold from Address Change Min tLZ1, tLZ2 10 ns tRC Address tOH Data Out tAA Data Valid Previous Data Valid Notes: 1. CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL 2. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs. Figure 27. 48 Pseudo SRAM Read Cycle—Address Controlled Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS Read Cycle tRC Address tAA tCO1 CE#1s CE2s tOH tCO2 tHZ tOE OE# tOLZ tBLZ Data Out High-Z tLZ tOHZ Data Valid Notes: 1. WE# = VIH. 2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. 4. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs. Figure 28. March 12, 2004 Pseudo SRAM Read Cycle Am49DL6408H 49 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS Write Cycle Parameter Symbol Speed Description Unit 55 70, 85 tWC Write Cycle Time Min 55 70 ns tCw Chip Enable to End of Write Min 45 55 ns tAS Address Setup Time Min tAW Address Valid to End of Write Min 45 55 ns tBW UB#s, LB#s to End of Write Min 45 55 ns tWP Write Pulse Time Min 45 55 ns tWR Write Recovery Time Min 0 Min 0 tWHZ Write to Output High-Z Max 25 tDW Data to Write Time Overlap Min 40 ns tDH Data Hold from Write Time Min 0 ns tOW End Write to Output Low-Z Min 5 ns 0 ns ns ns tWC Address tWR tCW (See Note 1) CE1#s tAW CE2s tCW (See Note 1) tWP (See Note 4) WE# Data In tAS (See Note 3) tDW High-Z High-Z Data Valid tWHZ Data Out tDH tOW Data Undefined Notes: 1. WE# controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 29. 50 Pseudo SRAM Write Cycle—WE# Control Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS tWC Address tAS (See Note 2 ) tCW (See Note 3) tWR (See Note 4) CE1#s tAW CE2s tBW UB#s, LB#s tWP (See Note 5) WE# tDW tDH Data Valid Data In Data Out High-Z High-Z Notes: 1. CE1#s controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 30. March 12, 2004 Pseudo SRAM Write Cycle—CE1#s Control Am49DL6408H 51 A D V A N C E I N F O R M A T I O N PSEUDO SRAM AC CHARACTERISTICS tWC Address tCW (See Note 2) CE1#s tWR (See Note 3) tAW tCW (See Note 2) CE2s UB#s, LB#s tBW tAS (See Note 4) WE# tWP (See Note 5) tDW Data In Data Out tDH Data Valid High-Z High-Z Notes: 1. UB#s and LB#s controlled. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control 52 Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Chip Erase Time 56 Excludes 00h programming prior to erasure (Note 4) Byte Program Time 5 150 µs Accelerated Byte/Word Program Time 4 120 µs Word Program Time 7 210 µs 28 84 sec Chip Program Time (Note 3) Word Mode sec Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Parameter Symbol CIN Parameter Description Input Capacitance Test Setup Typ Max Unit VIN = 0 11 14 pF VOUT = 0 12 16 pF COUT Output Capacitance CIN2 Control Pin Capacitance VIN = 0 14 16 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 17 20 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time March 12, 2004 Am49DL6408H 53 A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS FLJ073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm D1 A D eD 0.15 C 10 (2X) 9 8 SE 7 7 6 E E1 5 4 eE 3 2 1 M INDEX MARK PIN A1 CORNER L K B 10 TOP VIEW J H G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 0.08 C SIDE VIEW 6 b 73X 0.15 0.08 M C A B M C NOTES: PACKAGE FLJ 073 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 11.60 mm x 8.00 mm 2. ALL DIMENSIONS ARE IN MILLIMETERS. PACKAGE 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. JEDEC N/A SYMBOL MIN NOM MAX A --- --- 1.40 A1 0.25 --- --- A2 0.95 --- 1.13 NOTE PROFILE BODY SIZE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION 73 0.30 0.35 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.40 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = 0.000. BALL DIAMETER WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 eE 0.80 BSC. BALL PITCH eD 0.80 BSC. BALL PITCH 0.40 BSC. SOLDER BALL PLACEMENT SD / SE SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT 11.60 BSC. n e REPRESENTS THE SOLDER BALL GRID PITCH. 5. BODY THICKNESS D φb 4. A2,A3,A4,A5,A6,A7,A8,A9,B2,B3,B4,B7,B8,B9 C2,C9,C10,D1,D10,E1,E10,F5,F6,G5,G6,H1,H10 DEPOPULATED SOLDER BALLS J1,J10,K1,K2,K9,K10,L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. NOT USED. 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3232 \ 16-038.14b 54 Am49DL6408H March 12, 2004 A D V A N C E I N F O R M A T I O N REVISION SUMMARY Revision A (September 29, 2003) Revision A+2 (February 11, 2004) Initial release. Ordering Information Revision A+1 (November 24, 2003) Corrected a misidentified order number designator. MCP Block Diagram Revision A+3 (March 12, 2004) Updated Diagram and reconfigured product selector guide table. Connection Diagram Changed G8 and K6 to NC. CMOS Compatible Table 1 Changed the VOL test conditions to IOL = 2.0 mA. Removed SA column and updated title and Legend. Valid Combinations Word Program Command Sequence Updated package markings. Removed reference to byte programming. Read Cycle and Write Cycle Added 85 ns speed option to table. Trademarks Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. March 12, 2004 Am49DL6408H 55