Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 ADS79xx 12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs 1 Features 3 Description • • • • • • • The ADS79xx is a 12/10/8-bit multichannel analog-todigital converter family. The following table shows all twelve devices from this product family. 1 • • • • • • • • 1-MHz Sample Rate Serial Devices Product Family of 12/10/8-Bit Resolution Zero Latency 20-MHz Serial Interface Analog Supply Range: 2.7 to 5.25 V I/O Supply Range: 1.7 to 5.25 V Two SW Selectable Unipolar, Input Ranges: 0 to 2.5 V and 0 to 5 V Auto and Manual Modes for Channel Selection 12, 8, 4-Channel Devices can Share 16 Channel Device Footprint Two Programmable Alarm Levels per Channel Four Individually Configurable GPIOs for TSSOP package devices. One GPIO for QFN devices Typical Power Dissipation: 14.5 mW (+VA = 5 V, +VBD = 3V) at 1 MSPS Power-Down Current (1 μA) Input Bandwidth (47 MHz at 3 dB) 38-,30-Pin TSSOP and 32-,24-Pin QFN Packages 2 Applications • • • • • • • PLC / IPC Battery Powered Systems Medical Instrumentation Digital Power Supplies Touch Screen Controllers High-Speed Data Acquisition Systems High-Speed Closed-Loop Systems The devices include a capacitor based SAR A/D converter with inherent sample and hold. The devices accept a wide analog supply range from 2.7 V to 5.25 V. Very low power consumption makes these devices suitable for battery-powered and isolated power supply applications. A wide 1.7-V to 5.25-V I/O supply range facilitates a glue-less interface with the most commonly used CMOS digital hosts. The serial interface is controlled by CS and SCLK for easy connection with microprocessors and DSP. The input signal is sampled with the falling edge of CS. It uses SCLK for conversion, serial data output, and reading serial data in. The devices allow auto sequencing of preselected channels or manual selection of a channel for the next conversion cycle. There are two software selectable input ranges (0 V to 2.5 V and 0 V to 5 V), four individually configurable GPIOs ( in case of TSSOP package devices), and two programmable alarm thresholds per channel. These features make the devices suitable for most data acquisition applications. The devices offer an attractive power-down feature. This is extremely useful for power saving when the device is operated at lower conversion speeds. The 16/12-channel devices from this family are available in a 38-pin TSSOP and 32 pin VQFN package and the 4/8-channel devices are available in a 30-pin TSSOP and 24 pin VQFN packages. Detailed Block Diagram Device Information(1) PGA Gain Control High input impedance PGA (or non inverting buffer such as THS4031) PART NUMBER GPIO1 GPIO2 GPIO3 MXO AINP ADS79xx GPIO0 high-alarm low-alarm Ch0 Ch1 Ch2 ADC SDO To Host PACKAGE BODY SIZE (NOM) TSSOP (30) 7.80 mm × 4.40 mm VQFN (24) 4.00 mm × 4.00 mm TSSOP (38) 9.70 mm × 4.40 mm VQFN (32) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SDI SCLK Chn CS (1) REF 10 µF REF5025 o/p 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 8 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Absolute Maximum Ratings ...................................... 8 ESD Ratings.............................................................. 8 Recommended Operating Conditions....................... 8 Thermal Information: TSSP ...................................... 9 Thermal Information: VQFN...................................... 9 Electrical Characteristics: ADS7950/51/52/53 ........ 10 Electrical Characteristics, ADS7954/55/56/57 ........ 12 Electrical Characteristics, ADS7958/59/60/61 ........ 13 Timing Requirements .............................................. 15 Typical Characteristics (all ADS79xx Family Devices) ................................................................... 18 7.11 Typical Characteristics (12-Bit Devices Only)....... 19 7.12 Typical Characteristics (12-Bit Devices Only)....... 25 8 Detailed Description ............................................ 26 8.1 8.2 8.3 8.4 8.5 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... 26 27 27 27 37 Application and Implementation ........................ 42 9.1 Application Information............................................ 42 9.2 Typical Applications ................................................ 44 10 Power Supply Recommendations ..................... 47 11 Layout................................................................... 48 11.1 Layout Guidelines ................................................. 48 11.2 Layout Example .................................................... 48 12 Device and Documentation Support ................. 49 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 49 49 49 49 49 49 13 Mechanical, Packaging, and Orderable Information ........................................................... 50 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (April 2010) to Revision B • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Original (June 2008) to Revision A Page • Added QFN information to Features....................................................................................................................................... 1 • Added QFN information to Description................................................................................................................................... 1 • Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinout ..................................................................................... 4 • Added QFN pinout .................................................................................................................................................................. 4 • Added QFN pinout .................................................................................................................................................................. 4 • Added QFN pinout .................................................................................................................................................................. 4 • Added QFN pinout .................................................................................................................................................................. 5 • Added terminal functions for QFN packages.......................................................................................................................... 7 • Changed ADS7950/4/8 QFN package MXO pin from 7 to 3.................................................................................................. 7 • Changed thermal impedance for DBT package in absolute maximum ratings ...................................................................... 8 • Changed thermal impedance for RHB package in absolute maximum ratings...................................................................... 8 • Changed thermal impedance for RGE package in absolute maximum ratings...................................................................... 8 • Added Vref = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7950/51/52/53....................................................................... 10 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions........................................................................... 10 • Added while 2Vref ≤ +VA to Absolute input range span range 2 test conditions................................................................. 10 • Added Total unadjusted error (TUE) specification ............................................................................................................... 10 • Changed reference voltage at REFP min and max values .................................................................................................. 11 2 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 • Added Note to Electrical Characteristics, ADS7950/51/52/53 ............................................................................................. 11 • Added Vref = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7954/55/56/57 test conditions............................................... 12 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions........................................................................... 12 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions........................................................................... 12 • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 12 • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 12 • Added Vref = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7958/59/60/61 test conditions............................................... 13 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions........................................................................... 13 • Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions........................................................................... 13 • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 14 • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 14 • Changed tsu1 values from max to min................................................................................................................................... 15 • Changed tsu2 values from max to min................................................................................................................................... 15 • Added TOTAL UNADJUSTED ERROR (TUE Max) graph................................................................................................... 23 • Added TOTAL UNADJUSTED ERROR (TUE Min) graph.................................................................................................... 23 • Changed GPIO pins description ........................................................................................................................................... 26 • Added device powerdown through GPIO in the case of the TSSOP packaged devices ..................................................... 26 • Added note to Table 1 .......................................................................................................................................................... 31 • Added note to Table 2 .......................................................................................................................................................... 33 • Added note to Table 5 .......................................................................................................................................................... 36 • Added note to Programming GPIO Registers description.................................................................................................... 38 • Added QFN information to Table 11..................................................................................................................................... 39 • Changed DI12 = 1? from No or No to Yes or No in Figure 56............................................................................................. 40 • Added note to Figure 57 ....................................................................................................................................................... 42 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 3 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 5 Device Comparison Table RESOLUTION NUMBER OF CHANNELS 12 BIT 10 BIT 8 BIT 16 ADS7953 ADS7957 ADS7961 12 ADS7952 ADS7956 ADS7960 8 ADS7951 ADS7955 ADS7959 4 ADS7950 ADS7954 ADS7958 6 Pin Configuration and Functions DBT Package 38-Pin TSSOP Top View 4 35 BDGND 4 35 BDGND +VA 5 34 SDO REFP +VA 5 34 SDO AGND MXO 6 33 6 33 7 32 SDI SCLK AGND AINP 8 31 AINM 9 30 26 CS AINP AINM 9 30 AINM 29 AGND +VA 29 +VA 28 CH0 27 CH1 CH2 ADS7953 ADS7957 ADS7961 AGND CH15 10 28 CH0 CH14 12 27 CH1 CH13 13 26 CH2 11 NC 14 25 CH3 25 15 24 CH4 CH12 CH11 14 CH11 CH10 15 24 CH3 CH4 16 23 CH5 CH10 16 23 CH5 CH9 17 22 CH6 CH9 17 22 CH6 CH8 AGND 18 21 CH7 CH8 18 21 CH7 19 20 AGND AGND 19 20 AGND AGND ADS7952/ ADS7956/ ADS7960 NC NC NC CH10 CH0 17 16 8 9 REFP SDI SDO +VBD BDGND GPIO REFM REFP +VA 32 AINP AGND AINP +VA AINM ADS7953/ ADS7957/ ADS7961 CH0 1 ADS7951/ ADS7955/ ADS7959 MXO CH7 SDI SCLK AGND CS CH14 CS AGND +VA 6 13 12 7 CH0 Submit Documentation Feedback CH5 CH6 CH7 CH8 CH9 CH10 CH11 9 CH1 CH2 CH3 CH4 CH3 CH4 8 CH6 CH2 17 16 CH5 CH1 CH13 4 SCLK MXO CH12 19 18 24 25 24 1 CH15 CH1 RGE Package 32-Pin VQFN Top View +VA AINM NC CH11 RGE Package 32-Pin VQFN Top View AGND +VA SDO 13 AINP AGND SCLK CS BDGND NC CS 31 +VBD 12 11 32 8 GPIO NC 7 MXO REFM 10 MXO 25 24 1 CH9 ADS7952 ADS7956 ADS7960 AGND NC 32 AGND SDI SCLK SDI +VBD REFP SDO 36 CH2 3 CH3 REFM BDGND 36 +VBD GPIO0 3 CH4 GPIO1 37 GPIO 38 2 CH5 1 GPIO3 REFM GPIO2 GPIO0 +VBD CH6 GPIO1 37 CH7 38 2 CH8 1 GPIO3 REFM +VA GPIO2 REFP RGE Package 24-Pin VQFN Top View Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 19 18 24 +VA SDO BDGND +VBD GPIO REFM REFP RGE Package 32-Pin VQFN Top View 1 SCLK AGND ADS7950/ ADS7954/ ADS7958 MXO AINP CS AGND +VA AINM CH1 CH0 CH2 NC NC 13 12 7 NC 6 CH3 NC SDI Pin Functions: TSSOP Packages PIN ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 I/O REFP 4 4 4 4 I Reference input REFM 3 3 3 3 I Reference ground NAME DESCRIPTION REFERENCE ADC ANALOG INPUT AINP 8 8 8 8 I Signal input to ADC AINM 9 9 9 9 I ADC input ground Multiplexer output MULTIPLEXER MXO 7 7 7 7 O Ch0 28 28 20 20 I Ch1 27 27 19 18 I Ch2 26 26 18 14 I Ch3 25 25 17 12 I Ch4 24 24 14 — I Ch5 23 23 13 — I Ch6 22 22 12 — I Ch7 21 21 11 — I Ch8 18 18 — — I Ch9 17 17 — — I Ch10 16 16 — — I Ch11 15 15 — — I Ch12 14 — — — I Ch13 13 — — — I Ch14 12 — — — I Ch15 11 — — — I Analog channels for multiplexer DIGITAL CONTROL SIGNALS CS 31 31 23 23 I Chip select input SCLK 32 32 24 24 I Serial clock input SDI 33 33 25 25 I Serial data input SDO 34 34 26 26 O Serial data output Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 5 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Pin Functions: TSSOP Packages (continued) PIN ADS7953 ADS7957 ADS7961 NAME ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 I/O DESCRIPTION GENERAL PURPOSE INPUTS / OUTPUTS (1) GPIO0 High alarm or High/Low alarm GPIO1 Low alarm GPIO2 37 37 29 29 38 38 30 30 1 Range GPIO3 1 2 PD 1 1 2 2 2 I/O General purpose input or output O Active high output indicating high alarm or high/low alarm depending on programming I/O General purpose input or output O Active high output indicating low alarm I/O General purpose input or output I I/O I Selects range: High -> Range 2 / Low -> Range 1 General purpose input or output Active low power-down input POWER SUPPLY AND GROUND +VA 5, 29 5, 29 5, 21 5, 21 — Analog power supply AGND 6, 10, 19, 20, 30 6, 10, 19, 20, 30 6, 10, 22 6, 10, 22 — Analog ground +VBD 36 36 28 28 — Digital I/O supply BDGND 35 35 27 27 — Digital ground — 11, 12, 13, 14 15, 16 11, 13, 15, 16, 17, 19 — Pins internally not connected, do not float these pins NC PINS — (1) 6 These pins have programmable dual functionality. Refer to Table 12 for functionality programming Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Pin Functions: VQFN Packages PIN ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 I/O REFP 31 31 24 24 I Reference input REFM 30 30 23 23 I Reference ground PIN NAME DESCRIPTION REFERENCE ADC ANALOG INPUT AINP 3 3 4 4 I Signal input to ADC AINM 4 4 5 5 I ADC input ground Multiplexer output MULTIPLEXER MXO 2 2 3 3 O Ch0 20 18 13 11 I Ch1 19 17 12 10 I Ch2 18 16 11 9 I Ch3 17 15 10 8 I Ch4 16 14 9 — I Ch5 15 13 8 — I Ch6 14 12 7 — I Ch7 13 11 6 — I Ch8 12 10 — — I Ch9 11 9 — — I Ch10 10 8 — — I Ch11 9 7 — — I Ch12 8 — — — I Ch13 7 — — — I Ch14 6 — — — I Ch15 5 — — — I Analog-input channels for multiplexer DIGITAL CONTROL SIGNALS CS 23 23 16 16 I Chip select input SCLK 24 24 17 17 I Serial clock input SDI 25 25 18 18 I Serial data input SDO 26 26 19 19 O Serial data output I/O General purpose input or output O Active high output indicating high alarm or high/low alarm depending on programming GENERAL PURPOSE INPUT / OUTPUT (1) GPIO0 High alarm or High/Low alarm 29 29 22 22 POWER SUPPLY AND GROUND +VA 21, 32 21, 32 1, 14 1, 14 — Analog power supply AGND 1, 22 1, 22 2, 15 2, 15 — Analog ground +VBD 28 28 21 21 — Digital I/O supply BDGND 27 27 20 20 — Digital ground — 5, 6, 19, 20 — 6, 7, 12, 13 — Pins internally not connected, do not float these pins NC PINS — (1) This pin has programmable dual functionality. Refer to Table 12 for functionality programming. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 7 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT AINP or CHn to AGND –0.3 VA +0.3 V +VA to AGND, +VBD to BDGND –0.3 7 V Digital input voltage to BDGND –0.3 7 V Digital output to BDGND –0.3 VA + 0.3 V Power dissipation (TJ Max–TA)/θJA θJA thermal impedance, DBT Package 100.6 °C/W θJA thermal impedance, RHB Package 34 °C/W θJA thermal impedance, RGE Package Operating temperature –40 Junction temperature (TJ Max) Storage temperature (Tstg) (1) (2) –65 38 °C/W 125 °C 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DBT packaged versions of ADS79xx family devices are rated for MSL2 260°C per the JSTD-020 specifications and the RGE and RHB packaged versions of ADS79xx family devices are rated for MSL3 260C per JSTD-020 specifications 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V(+VA) Analog power-supply voltage 2.7 3.3 5.25 V V(+VBD) Digital I/O-supply voltage 1.7 3.3 V(+VA) V V(REF) Reference voltage 2 2.5 3 V ƒ(SCLK) SCLK frequency 20 MHz TA Operating temperature range 125 °C 8 Submit Documentation Feedback –40 Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 7.4 Thermal Information: TSSP ADS795x THERMAL METRIC (1) DBT (TSSP) DBT (TSSP) 38 PINS 30 PINS UNIT RθJA Junction-to-ambient thermal resistance 83.6 89.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.8 22.9 °C/W RθJB Junction-to-board thermal resistance 44.7 43.1 °C/W ψJT Junction-to-top characterization parameter 2.9 0.8 °C/W ψJB Junction-to-board characterization parameter 44.1 42.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Thermal Information: VQFN ADS7953, ADS7957, ADS7961 THERMAL METRIC (1) RHB (VQFN) RGE (VQFN) 32 PINS 24 PINS UNIT RθJA Junction-to-ambient thermal resistance 40.6 36.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.1 39.3 °C/W RθJB Junction-to-board thermal resistance 13.1 14.7 °C/W ψJT Junction-to-top characterization parameter 0.8 0.7 °C/W ψJB Junction-to-board characterization parameter 13 14.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.7 5.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 9 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 7.6 Electrical Characteristics: ADS7950/51/52/53 VA = 2.7 V to 5.25 V, VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Range 1 0 Vref Range 2 while 2Vref ≤ +VA 0 2*Vref –0.2 VREF +0.2 –0.2 2*VREF +0.2 Range 1 Absolute input range Range 2 while 2Vref ≤ +VA Input capacitance Input leakage current TA = 125°C V V 15 ρF 61 nA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes Integral linearity Differential linearity ADS795XSB (2) ADS795XS (2) ADS795XSB (2) ADS795XS (2) Bits 11 –1 ±0.5 1 –1.5 ±0.75 1.5 ADS795XSB (2) –1 ±0.5 1 ADS795XS (2) –2 ±0.75 1.5 –3.5 ±1.1 3.5 –2 ±0.2 2 Offset error (4) Range 1 Gain error 12 Range 2 ±0.2 Total unadjusted error (TUE) ±2 LSB (3) LSB LSB LSB LSB SAMPLING DYNAMICS Conversion time 20 MHz sclk Acquisition time Maximum throughput rate 800 325 ns ns 20 MHz sclk 1 MHz Aperture delay 5 ns Step response 150 ns Overvoltage recovery 150 ns (1) (2) (3) (4) 10 Ideal input span; does not include gain or offset error. ADS795X, where X indicates 0, 1, 2, or 3 LSB means Least Significant Bit. Measured relative to an ideal full-scale input Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Electrical Characteristics: ADS7950/51/52/53 (continued) VA = 2.7 V to 5.25 V, VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS Total harmonic distortion (5) 100 kHz –82 dB Signal-to-noise ratio 100 kHz, ADS795XSB (2) 70 71.7 dB 100 kHz, ADS795XS (2) 70 71.7 100 kHz, ADS795XSB (2) 69 71.3 100 kHz, ADS795XS (2) 68 71.3 Signal-to-noise + distortion dB Spurious free dynamic range 100 kHz 84 dB Small signal bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input (isolation crosstalk). –95 From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input (memory crosstalk). –85 dB EXTERNAL REFERENCE INPUT Vref reference voltage at REFP (6) 2 Reference resistance 2.5 3 V 100 kΩ ALARM SETTING Higher threshold range 0 FFC Hex Lower threshold range 0 FFC Hex DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD ) VIL +VBD = 5 V 0.8 VIL +VBD = 3 V 0.4 VOH At Isource = 200 μA VOL At Isink = 200 μA V Vdd-0.2 0.4 Data format MSB first MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 V +VBD supply voltage 1.7 3.3 5.25 V At +VA = 2.7 to 3.6 V and 1 MHz throughput Supply current (normal mode) 1.8 At +VA = 2.7 to 3.6 V static state mA At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA Power-down state supply current +VBD supply current mA 1.05 +VA = 5.25 V, fs = 1MHz 1 μA 1 mA Power-up time 1 μs Invalid conversions after power up or reset 1 Numbers TEMPERATURE RANGE Specified performance (5) (6) –40 125 °C Calculated on the first nine harmonics of the input frequency. Device is designed to operate over Vref = 2 V to 3 V. However one can expect lower noise performance at Vref < 2.4 V. This is due to SNR degradation resulting from lowered signal range. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 11 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 7.7 Electrical Characteristics, ADS7954/55/56/57 +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Range 1 0 Vref Range 2 while 2Vref ≤ +VA 0 2*Vref Range 1 –0.20 VREF +0.20 Range 2 while 2Vref ≤ +VA –0.20 2*VREF +0.20 Absolute input range Input capacitance Input leakage current TA = 125°C V V 15 ρF 61 nA 10 Bits SYSTEM PERFORMANCE Resolution No missing codes 10 Bits Integral linearity –0.5 ±0.2 0.5 LSB (2) Differential linearity –0.5 ±0.2 0.5 LSB Offset error (3) –1.5 ±0.5 1.5 LSB –1 ±0.1 1 Range 1 Gain error Range 2 ±0.1 LSB SAMPLING DYNAMICS Conversion time 20 MHz SCLK 800 Acquisition time Maximum throughput rate 325 ns ns 20 MHz SCLK 1 MHz Aperture delay 5 ns Step response 150 ns Overvoltage recovery 150 ns –80 dB DYNAMIC CHARACTERISTICS Total harmonic distortion (4) 100 kHz Signal-to-noise ratio 100 kHz 60 Signal-to-noise + distortion 100 kHz 60 Spurious free dynamic range 100 kHz 82 dB Full power bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk dB Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input. –95 From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input. –85 dB EXTERNAL REFERENCE INPUT Vref reference voltage at REFP 2 Reference resistance 2.5 3 100 V kΩ ALARM SETTING Higher threshold range 000 FFC Hex Lower threshold range 000 FFC Hex (1) (2) (3) (4) 12 Ideal input span; does not include gain or offset error. LSB means Least Significant Bit. Measured relative to an ideal full-scale input Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Electrical Characteristics, ADS7954/55/56/57 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD ) VIL +VBD = 5 V 0.8 VIL +VBD = 3 V 0.4 VOH At Isource = 200 μA VOL At Isink = 200 μA Data format MSB first V Vdd-0.2 0.4 MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage +VBD supply voltage 2.7 3.3 5.25 1.7 3.3 5.25 At +VA = 2.7 to 3.6 V and 1MHz throughput Supply current (normal mode) V 1.8 At +VA = 2.7 to 3.6 V static state mA 1.05 1 mA At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA Power-down state supply current +VBD supply current V +VA = 5.25V, fs = 1MHz 1 μA 1 mA Power-up time 1 μs Invalid conversions after power up or reset 1 Numbers TEMPERATURE RANGE Specified performance –40 125 °C 7.8 Electrical Characteristics, ADS7958/59/60/61 +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Range 1 0 Vref Range 2 while 2Vref ≤ +VA 0 2*Vref Range 1 –0.20 VREF +0.2 Range 2 while 2Vref ≤ +VA –0.20 2*VREF +0.2 Absolute input range Input capacitance Input leakage current TA = 125°C V V 15 ρF 61 nA 8 Bits SYSTEM PERFORMANCE Resolution No missing codes 8 Bits Integral linearity –0.3 ±0.1 0.3 LSB (2) Differential linearity –0.3 ±0.1 0.3 LSB –0.5 ±0.2 0.5 LSB Offset error (1) (2) (3) (3) Ideal input span; does not include gain or offset error. LSB means Least Significant Bit. Measured relative to an ideal full-scale input Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 13 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Electrical Characteristics, ADS7958/59/60/61 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS Range 1 Gain error MIN TYP MAX –0.6 ±0.1 0.6 Range 2 ±0.1 UNIT LSB SAMPLING DYNAMICS Conversion time 20 MHz SCLK 800 Acquisition time 325 Maximum throughput rate ns ns 20 MHz SCLK 1 MHz Aperture delay 5 ns Step response 150 ns Overvoltage recovery 150 ns –75 dB DYNAMIC CHARACTERISTICS Total harmonic distortion (4) 100 kHz Signal-to-noise ratio 100 kHz 49 Signal-to-noise + distortion 100 kHz 49 Spurious free dynamic range 100 kHz –78 dB Full power bandwidth At –3 dB 47 MHz Channel-to-channel crosstalk dB Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input. –95 From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input. –85 dB ETERNAL REFERENCE INPUT Vref reference voltage at REFP 2 Reference resistance 2.5 3 100 V kΩ ALARM SETTING Higher threshold range 000 FF Hex Lower threshold range 000 FF Hex DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level 0.7*(+VBD) VIL +VBD = 5 V 0.8 VIL +VBD = 3 V 0.4 V VOH At Isource = 200 μA VOL At Isink = 200 μA V Data format Vdd-0.2 0.4 MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 +VBD supply voltage 1.7 3.3 5.25 At +VA = 2.7 to 3.6 V and 1 MHz throughput Supply current (normal mode) At +VA = 2.7 to 3.6 V static state 14 1.05 mA 2.3 3 mA At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA +VA = 5.25V, fs = 1MHz Power-up time (4) V mA At +VA = 4.7 to 5.25 V and 1 MHz throughput Power-down state supply current +VBD supply current 1.8 1 μA 1 mA 1 μs Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Electrical Characteristics, ADS7958/59/60/61 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Invalid conversions after power up or reset MAX UNIT 1 Numbers TEMPERATURE RANGE Specified performance –40 125 °C 7.9 Timing Requirements All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified) (1) (2) (see Figure 1, Figure 2, Figure 3, and Figure 4) MIN tconv tq td1 tsu1 td2 th1 td3 tsu2 Conversion time Minimum quiet sampling time needed from bus 3state to start of next conversion Delay time, CS low to first data (DO–15) out Setup time, CS low to first rising edge of SCLK Delay time, SCLK falling to SDO next data bit valid Hold time, SCLK falling to SDO data bit valid th Delay time, 16 SCLK falling edge to SDO 3-state Setup time, SDI valid to rising edge of SCLK Hold time, rising edge of SCLK to SDI valid +VBD = 3 V 16 +VBD = 5 V 16 +VBD = 1.8 V 40 +VBD = 3 V 40 +VBD = 5 V 40 38 +VBD = 3 V 27 +VBD = 5 V 17 +VBD = 1.8 V 8 +VBD = 3 V 6 +VBD = 5 V 4 35 +VBD = 3 V 27 +VBD = 5 V 17 7 +VBD = 3 V 5 +VBD = 5 V 3 26 +VBD = 3 V 22 +VBD = 5 V 13 2 +VBD = 3 V 3 td4 (1) (2) Pulse duration CS high Delay time CS high to SDO 3-state ns ns ns +VBD = 1.8 V +VBD = 1.8 V SCLK ns +VBD = 1.8 V +VBD = 1.8 V UNIT ns +VBD = 1.8 V ns ns 4 +VBD = 1.8 V 12 +VBD = 3 V 10 +VBD = 5 V tw1 MAX 16 +VBD = 5 V th2 NOM +VBD = 1.8 V ns 6 +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 ns +VBD = 1.8 V 24 +VBD = 3 V 21 +VBD = 5 V 12 ns 1.8V specifications apply from 1.7 V to 1.9 V, 3 V specifications apply from 2.7 V to 3.6 V, 5 V specifications apply from 4.75 V to 5.25 V. With 50-pF load Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 15 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Timing Requirements (continued) All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)(1)(2) (see Figure 1, Figure 2, Figure 3, and Figure 4) MIN twh Pulse duration SCLK high twl Pulse duration SCLK low Frequency SCLK +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 NOM MAX ns ns +VBD = 1.8 V 20 +VBD = 3 V 20 +VBD = 5 V 20 Frame n UNIT MHz Frame n + 1 CS 1 3 5 9 7 11 13 15 16 1 3 5 9 7 11 13 15 16 SCLK SDO Top 4 Bit SDI Top 4 Bit 12-Bit Conversion Result 16-Bit I/P Word 12-Bit Conversion Result 16-Bit I/P Word Mux Chan Change Mux Chan Change Analog I/P Settling After Chan Change MUX Sampling Instance Acquisition Acquisition Phase tacq Conversion Conversion Phase Data Written (through SDI) in Frame n – 1 GPO Conversion Phase tcnv Data Written (through SDI) in Frame n GPI GPI status is latched in on CS falling edge and transferred to SDO frame n Figure 1. Device Operation Timing Diagram 16 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 a 1/t Throughput (Single Frame) CS tw1 tsu1 SCLK 1 3 2 th1 td1 DO15 SDO 4 5 6 15 14 16 td3 td2 DO-14 DO-13 DO-12 DO-11 MSB DO-10 MSB-1 DO-2 LSB+2 DO-1 LSB+1 DO-0 LSB tq tsu2 SDI DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-2 DI-1 DI-0 th2 Figure 2. Serial Interface Timing Diagram for 12-Bit Devices (ADS7950/51/52/53) a 1/t Throughput (Single Frame) CS tw1 tsu1 SCLK 1 3 2 th1 td1 DO15 SDO 4 5 6 15 14 16 td3 td2 DO-14 DO-13 DO-12 DO-11 MSB DO-10 MSB-1 DO-2 LSB DO-1 DO-0 tq tsu2 SDI DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-2 DI-1 DI-0 th2 Figure 3. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954/55/56/57) a 1/t Throughput (Single Frame) CS tw1 tsu1 SCLK 1 td1 SDO 3 2 th1 DO15 DO-14 4 5 6 12 13 16 td3 td2 DO-13 DO-12 DO-11 MSB DO-10 MSB-1 DO-4 LSB DO-3 DO-0 tq tsu2 SDI DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-4 DI-3 DI-0 th2 Figure 4. Serial Interface Timing Diagram for 8-Bit Devices (ADS7958/59/60/61) Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 17 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 7.10 Typical Characteristics (all ADS79xx Family Devices) 1.5 3.5 TA = 25°C 1.4 3 +VA - Supply Current - mA +VA - Supply Current - mA fS = 1 MSPS, TA = 25°C 2.5 2 1.5 1 2.7 1.3 1.2 1.1 1 3.4 4.1 4.8 +VA - Supply Voltage - V 0.9 2.7 5.5 Figure 5. Supply Current vs Supply Voltage 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 6. Static Supply Current vs Supply Voltage 1.115 1.11 3.2 +VA - Supply Current - mA +VA - Supply Current - mA VDD = 5.5 V fS = 1 MSPS, VDD = 5.5 V 3.4 3 2.8 2.6 2.4 2.2 1.105 1.1 1.095 1.09 1.085 1.08 1.075 2 -40 15 70 TA - Free-Air Temperature - °C 1.07 -40 125 Figure 7. Supply Current vs Free-Air Temperature 2.5 No Powerdown, TA = 25°C With Powerdown, TA = 25°C 5V 2 +VA - Supply Current - mA +VA - Supply Current - mA 125 Figure 8. Static Supply Current vs Free-Air Temperature 2.5 2.7 V 1.5 1 0.5 2 5V 1.5 2.7 V 1 0.5 0 0 0 200 400 600 800 fS - Sample Rate - KSPS 1000 Figure 9. Supply Current vs Sample Rate 18 15 70 TA - Free-Air Temperature - °C Submit Documentation Feedback 0 100 200 300 400 fS - Sample Rate - KSPS 500 Figure 10. Supply Current vs Sample Rate Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 7.11 Typical Characteristics (12-Bit Devices Only) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 1 fS = 1 MSPS, TA = 25°C 0.6 INL - Integral Nonlinearity - LSBs DNL - Differential Nonlinearity - LSBs 1 0.8 DNL max 0.4 0.2 0 -0.2 DNL min -0.4 -0.6 -0.8 -1 2.7 3.2 4.2 4.7 3.7 +VA - Supply Voltage - V 5.2 0.6 DNL max 0 -0.2 DNL min -0.4 -0.6 15 70 TA - Free-Air Temperature - °C 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 0.6 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 5.2 INL max 0.4 0.2 0 -0.2 INL min -0.4 -0.6 -1 -40 125 15 70 TA - Free-Air Temperature - °C 125 Figure 14. Integral Nonlinearity vs Free-Air Temperature 2 2 +VBD = 1.8 V, fS = 1 MSPS, TA = 25°C 1.8 1.6 Offset Error - LSBs Offset Error - LSBs -0.6 -0.8 Figure 13. Differential Nonlinearity vs Free-Air Temperature 1.4 1.2 1 0.8 0.6 1.2 1 0.8 0.6 0.4 0.2 0.2 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 15. Offset Error vs Supply Voltage Copyright © 2008–2015, Texas Instruments Incorporated +VA = 5.5 V, fS = 1 MSPS, TA = 25°C 1.4 0.4 0 2.7 INL min -0.4 Figure 12. Integral Nonlinearity vs Supply Voltage -0.8 1.6 0 -0.2 0.8 0.2 1.8 0.2 1 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.4 -1 -40 INL max 0.4 -1 2.7 5.5 INL - Integral Nonlinearity - LSBs DNL - Differential Nonlinearity - LSBs 0.8 0.6 fS = 1 MSPS, TA = 25°C -0.8 Figure 11. Differential Nonlinearity vs Supply Voltage 1 0.8 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 +VBD - Interace Supply - V 5.3 5.5 Figure 16. Offset Error vs Interface Supply Voltage Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 19 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Typical Characteristics (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 1 1 +VBD = 1.8 V, fS = 1 MSPS, TA = 25°C 0.8 0.6 0.4 Gain Error - LSBs Gain Error - LSBs 0.6 0.2 0 -0.2 -0.4 0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V -1 1.8 5.5 Figure 17. Gain Error vs Supply Voltage 0.8 1.4 1.2 1 0.8 0.6 0 -40 15 70 TA - Free-Air Temperature - °C 0.4 0.3 71 70.5 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 21. Signal-to-Noise Ratio vs Supply Voltage Submit Documentation Feedback 15 70 TA - Free-Air Temperature - °C 125 Figure 20. Gain Error vs Free-Air Temperature SINAD - Signal-to-Noise and Distortion - dB 71.5 69 2.7 0.5 0 -40 125 72 69.5 0.6 0.1 Figure 19. Offset Error vs Free-Air Temperature 70 0.7 0.2 0.2 SNR - Signal-to-Noise Ratio - dB 5.3 5.5 +VA = 5.5 V, +VBD = 1.8 V, fS = 1 MSPS 0.9 0.4 20 2.8 3.3 3.8 4.3 4.8 +VBD - Interace Supply - V 1 +VA = 5.5 V, +VBD = 1.8 V, fS = 1 MSPS Gain Error - LSBs Offset Error - LSBs 1.6 2.3 Figure 18. Gain Error vs Interface Supply Voltage 2 1.8 +VA = 5.5 V, fS = 1 MSPS, TA = 25°C 0.8 72 71.5 71 70.5 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 70 69.5 69 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 22. Signal-to-Noise + Distortion vs Supply Voltage Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Typical Characteristics (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves SFDR - Spurious Free Dynamic Range - dB -80 THD - Total Harmonic Distortion - -81 -82 -83 -84 -85 -86 -87 -88 -89 -90 2.7 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 Figure 23. Total Harmonic Distortion vs Supply Voltage 71.5 71 70.5 70 69.5 69 -40 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 15 70 TA - Free-Air Temperature - °C 125 Figure 25. Signal-To-Noise Ratio vs Free-Air Temperature -81 -82 -83 -84 -85 -86 -87 -88 -89 -90 -40 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 15 70 TA - Free-Air Temperature - °C 125 Figure 27. Total Harmonic Distortion vs Free-Air Temperature Copyright © 2008–2015, Texas Instruments Incorporated 88 87 +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz TA = 25°C 86 85 84 83 82 81 80 2.7 3.4 4.1 4.8 +VA - Supply Voltage - V 5.5 72 71.5 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 71 70.5 70 69.5 69 -40 15 70 TA - Free-Air Temperature - °C 125 Figure 26. Signal-to-Noise + Distortion vs Free-Air Temperature SFDR - Spurious Free Dynamic Range - dB THD - Total Harmonic Distortion - dB -80 89 Figure 24. Spurious Free Dynamic Range vs Supply Voltage SINAD - Signal-to-Noise and Distortion - dB SNR - Signal-to-Noise Ratio - dB 72 90 90 89 88 87 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, fIN = 100 kHz 86 85 84 83 82 81 80 -40 15 70 TA - Free-Air Temperature - °C 125 Figure 28. Spurious Free Dynamic Range vs Free-Air Temperature Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 21 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Typical Characteristics (12-Bit Devices Only) (continued) Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves SINAD - Signal-to-Noise and Distortion - dB SNR - Signal-to-Noise Ratio - dB 73 72.5 72 71.5 71 70.5 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 70 69.5 69 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 Figure 29. Signal-to-Noise Ratio vs Input Frequency -72 -74 -76 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP -78 -80 -82 -84 -86 -88 -90 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 72 71.5 1000 W 71 10 W 70 69.5 69 20 100 W +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP 40 60 80 fIN - Input Frequency - KHz 100 Figure 33. Signal-to-Noise + Distortion vs Input Frequency (Across Different Source Resistance Values) 22 71.5 71 70.5 70 69.5 69 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 100 +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 95 90 85 80 75 70 10 30 50 70 90 110 130 fIN - Input Frequency - KHz 150 -70 500 W 70.5 72 Figure 32. Spurious Free Dynamic Range vs Input Frequency THD - Total Harmonic Distortion - dB SINAD - Signal-to-Noise and Distortion - dB Figure 31. Total Harmonic Distortion vs Input Frequency +VA = 5 V +VBD = 3 V, fS = 1 MSPS, TA = 25°C, MXO Shorted to AINP 72.5 Figure 30. Signal-to-Noise + Distortion vs Input Frequency SFDR - Spurious Free Dynamic Range - dB THD - Total Harmonic Distortion - dB -70 73 Submit Documentation Feedback +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP -72 -74 -76 1000 W -78 500 W -80 -82 10 W -84 100 W -86 -88 -90 20 40 60 80 fIN - Input Frequency - KHz 100 Figure 34. Total Harmonic Distortion vs Input Frequency (Across Different Source Resistance Values) Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Typical Characteristics (12-Bit Devices Only) (continued) 1 90 DNL - Differential Nonlinearity - LSBs SFDR - Spurious Free Dynamic Range - dB Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 88 10 W 86 100 W 84 82 80 1000 W 500 W 78 76 +VA = 5 V +VBD = 5 V, fS = 1 MSPS, TA = 25°C, Buffer Between MXO and AINP 74 72 70 20 40 60 80 fIN - Input Frequency - KHz 0.6 0.2 0 -0.2 -0.6 -0.8 -1 0 1.6 EO - Offset Error - LSBs INL - Integral Nonlinearity - LSBs 0.6 0 -0.2 INL min -0.4 -0.6 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS -0.8 -1 0 15 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 1.4 INL max 0.2 5 10 Channel Number Figure 36. Differential Nonlinearity Variation Across Channels 1 1.2 1 0.8 0.6 0.4 0.2 0 5 10 Channel Number 15 Figure 37. Integral Nonlinearity Variation Across Channels 0 5 10 15 Channel Number 20 Figure 38. Offset Error Variation Across Channels 73 0.25 SNR - Signal-to-Noise Ratio - dB +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.2 EG - Gain Error - LSBs DNL min -0.4 0.8 0.4 DNL max 0.4 100 Figure 35. Spurious Free Dynamic Range vs Input Frequency (Across Different Source Resistance Values) +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 0.8 0.15 0.1 0.05 0 0 5 10 15 Channel Number 20 Figure 39. Gain Error Variation Across Channels Copyright © 2008–2015, Texas Instruments Incorporated 72.5 72 71.5 71 70.5 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS 70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Channel Number Figure 40. Signal-to-Noise Ratio Variation Across Channels Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 23 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Typical Characteristics (12-Bit Devices Only) (continued) 120 73 72.5 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS Isolation 100 72 Crosstalk - dB SINAD - Signal-to-Noise and Distortion - dB Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves 71.5 71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Channel Number Figure 41. Signal-to-Noise + Distortion Variation Across Channels 40 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, CH0, CH1 50 100 150 200 fIN - Input Frequency - KHz 250 Figure 42. Crosstalk vs Input Frequency 100 25 +VA = 5 V, +VBD = 5 V 80 20 70 Number of Devices AINP - Leakage Current - nA 60 0 0 70 60 50 VI = 0 V 40 VI = 1.25 V 30 20 Memory 20 70.5 90 80 VI = 2.5 V 15 10 5 10 0 -40 -25 -10 5 0 20 35 50 65 80 95 110 125 0.25 0.5 0.75 1 1.25 1.5 1.75 TUE Max - LSB TA - Free-Air Temperature - °C Figure 43. Input Leakage Current vs Free-Air Temperature 2 Figure 44. Total Unadjusted Error (TUE Maximum) 25 Number of Devices 20 15 10 5 1 0.5 0.75 0 0.25 -0.5 -0.25 -1 -0.75 -1.5 -1.25 -1.75 0 TUE Min- LSB Figure 45. Total Unadjusted Error (TUE Minimum) 24 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 7.12 Typical Characteristics (12-Bit Devices Only) INL DNL 1 1 +VA = 5 V +VBD = 5 V, 0.8 0.6 fS = 1 MSPS, +VA = 5 V +VBD = 5 V, 0.6 fS = 1 MSPS 0.4 TA = 25°C INL - LSBs DNL - LSBs 0.4 0.8 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 0 1024 2048 3072 4096 0 1024 2048 4096 Figure 47. Typical INL for All Codes Figure 46. Typical DNL for All Codes FFT 0 Amplitude - dB 3072 Code Code -20 +VA = 5 V +VBD = 5 V, -40 fS = 1 MSPS, -60 fIN = 100 kHz Npoints = 16384 -80 -100 -120 -140 -160 0 100000 200000 300000 400000 500000 f - Frequency - Hz Figure 48. Typical FFT Plot Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 25 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 8 Detailed Description 8.1 Overview The ADS7950 to ADS7961 are 12/10/8-bit multichannel devices. Figure 1, Figure 2, Figure 3, and Figure 4 show device operation timing. Device operation is controlled with CS, SCLK, and SDI. The device outputs its data on SDO. Each frame begins with the falling edge of CS. With the falling edge of CS, the input signal from the selected channel is sampled, and the conversion process is initiated. The device outputs data while the conversion is in progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion result in MSB first format. There is an option to read the GPIO status instead of the channel address. (Refer to Table 1, Table 2, and Table 5 for more details.) The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase starts on the fourteenth SCLK rising edge. On the next CS falling edge the acquisition phase will end, and the device starts a new frame. The TSSOP packaged device has four General Purpose IO (GPIO) pins, QFN versions have only one GPIO. These four pins can be individually programmed as GPO or GPI. It is also possible to use them for preassigned functions, refer to Table 11. GPO data can be written into the device through the SDI line. The device refreshes the GPO data on the CS falling edge as per the SDI data written in previous frame. Similarly the device latches GPI status on the CS falling edge and outputs the GPI data on the SDO line (if GPI read is enabled by writing DI04=1 in the previous frame) in the same frame starting with the CS falling edge. The falling edge of CS clocks out DO-15 (first bit of the four bit channel address), and remaining address bits are clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for 12/10/8-bit devices. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge of SCLK. The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched on every rising edge of SCLK starting with the 1st clock as shown in Figure 2, Figure 3, and Figure 4. CS can be asserted (pulled high) only after 16 clocks have elapsed. The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits; the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register settings (refer to Table 11). The alarm is asserted (under the alarm conditions) on the 12th falling edge of SCLK in the same frame when a data conversion is in progress. The alarm output is reset on the 10th falling edge of SCLK in the next frame. The device offers a power-down feature to save power when not in use. There are two ways to powerdown the device. It can be powered down by writing DI05 = 1 in the mode control register (refer to Table 1, Table 2, and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another way to powerdown the device is through GPIO in the case of the TSSOP packaged devices. GPIO3 can act as the PD input (refer to Table 11, to assign this functionality to GPIO3). This is an asynchronous and active low input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will power up again on the CS falling edge with DI05 = 0 in the mode control register and GPIO3 (PD) = 1. 26 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 8.2 Functional Block Diagram REF MXO AINP Ch0 Ch1 +VA AGND ADC Ch2 SDO Compare Alarm Threshold Ch n* Control Logic & Sequencing GPIO BDGND SDI SCLK CS VBD NOTE: n* is number of channels (16,12,8, or 4) depending on the device from the ADS79xx product family. NOTE: 4 number of GPIO are available in TSSOP package devices only, QFN package devices offer only one GPIO. 8.3 Feature Description 8.3.1 Reference The ADS79xx can operate with an external 2.5-V ± 10-mV reference. A clean, low noise, well-decoupled reference voltage on the REF pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF5025 can be used to drive this pin. A 10-μF ceramic decoupling capacitor is required between the REF and GND pins of the converter. The capacitor should be placed as close as possible to the pins of the device. 8.3.2 Power Saving The ADS79xx devices offer a power-down feature to save power when not in use. There are two ways to power down the device. It can be powered down by writing DI05 = 1 in the Mode Control register (refer to Table 1, Table 2 and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another way to powerdown the device is through GPIO. GPIO3 can act as a PD input (refer to Table 11, for assigning this functionality to GPIO3). This is an asynchronous and active low input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will powerup again on the CS falling edge while DI05 = 0 in the Mode Control register and GPIO3 (PD) = 1. 8.4 Device Functional Modes 8.4.1 Channel Sequencing Modes There are three modes for channel sequencing, namely Manual mode, Auto-1 mode, Auto-2 mode. Mode selection is done by writing into the control register (refer to Table 1, Table 2, and Table 5). A new multiplexer channel is selected on the second falling edge of SCLK (as shown in Figure 1) in all three modes. Manual mode: When configured to operate in Manual mode, the next channel to be selected is programmed in each frame and the device selects the programmed channel in the next frame. On powerup or after reset the default channel is 'Channel-0' and the device is in Manual mode. Auto-1 mode: In this mode the device scans pre-programmed channels in ascending order. A new multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for pre-programming the channel sequence. Table 3 and Table 4 show Auto-1 ‘program register’ settings. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 27 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Device Functional Modes (continued) Once programmed the device retains ‘program register’ settings until the device is powered down, reset, or reprogrammed. It is allowed to exit and re-enter the Auto-1 mode any number of times without disturbing ‘program register’ settings. The Auto-1 program register is reset to FFFF/FFF/FF/F hex for the 16/12/8/4 channel devices respectively upon device powerup or reset; implying the device scans all channels in ascending order. Auto-2 mode: In this mode the user can configure the program register to select the last channel in the scan sequence. The device scans all channels from channel 0 up to and including the last channel in ascending order. The multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for pre-programming of the last channel in the sequence (multiplexer depth). Table 6 lists the ‘Auto-2 prog’ register settings for selection of the last channel in the sequence. Once programmed the device retains program register settings until the device is powered down, reset, or reprogrammed. It is allowed to exit and re-enter Auto-2 mode any number of times, without disturbing the ‘program register’ settings. On powerup or reset the bits D9-D6 of the Auto-2 program register are reset to F/B/7/3 hex for the 16/12/8/4 channel devices respectively; implying the device scans all channels in ascending order. 8.4.2 Device Programming and Mode Control The following section describes device programming and mode control. These devices feature two types of registers to configure and operate the devices in different modes. These registers are referred as ‘Configuration Registers’. There are two types of ‘Configuration Registers’ namely ‘Mode control registers’ and ‘Program registers’. 8.4.2.1 Mode Control Register A ‘Mode control register’ is configured to operate the device in one of three channel sequencing modes, namely Manual mode, Auto-1 Mode, Auto-2 Mode. It is also used to control user programmable features like range selection, device power-down control, GPIO read control, and writing output data into the GPIO. 8.4.2.2 Program Registers The 'Program registers’ are used for device configuration settings and are typically programmed once on powerup or after device reset. There are different program registers such as ‘Auto-1 mode programming’ for preprogramming the channel sequence, ‘Auto-2 mode programming’ for selection of the last channel in the sequence, ‘Alarm programming’ for all 16 channels (or 12,8,4 channels depending on the device) and GPIO for individual pin configuration as GPI or GPO or a pre-assigned function. 8.4.3 Device Power-Up Sequence The device power-up sequence is shown in Figure 49. Manual mode is the default power-up channel sequencing mode and Channel-0 is the first channel by default. As explained previously, these devices offer Program Registers to configure user programmable features like GPIO, Alarm, and to pre-program the channel sequence for Auto modes. At ‘power up or on reset’ these registers are set to the default values listed in Table 1 to Table 11. TI recommends programming these registers on power up or after reset. Once configured; the device is ready to use in any of the three channel sequencing modes namely Manual, Auto-1, and Auto-2. 28 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Device Functional Modes (continued) Device power up or reset Device operation in manual mode, Channel 0; SDO Invalid in first frame CS First frame CS Auto 1 register program (note 1) CS Auto 2 register program (note 1) CS Alarm register program (note 1) CS GPIO register program (note 1) CS CS Operation in Auto 1 mode Operation in manual mode CS Operation in Auto 2 mode (1) The device continues its operation in Manual mode channel 0 through out the programming sequence and outputs valid conversion results. It is possible to change channel, range, GPIO by inserting extra frames in between two programming blocks. It is also possible to bypass any programming block if the user does not intent to use that feature. (2) It is possible to reprogram the device at any time during operation, regardless of what mode the device is in. During programming the device continues its operation in whatever mode it is in and outputs valid data. Figure 49. Device Power-Up Sequence 8.4.4 Operating in Manual Mode The details regarding entering and running in Manual channel sequencing mode are illustrated in Figure 50. Table 1 lists the Mode Control Register settings for Manual mode in detail. There are no Program Registers for manual mode. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 29 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Device Functional Modes (continued) CS Frame: n-1 Device operation in Auto 1 or Auto 2 mode No Change to Manual mode? Yes CS Frame: n Request for Manual mode CS Frame: n+1 Entry into Manual Mode CS Frame: n+2 Operation in Manual mode * Sample: Samples and converts channel selected in ‘frame n-1’ * Mux : Selects channel incremented from previous frame as per auto sequence this channel will be acquired in this frame and sampled at start of ‘frame n+1’ * Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +1’ DI15..12 = 0001 binary …. Selects manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n-1’ I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects channel programmed in ‘frame n’(Manual mode) this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame .* SDI : Programming for ‘frame n+2’ DI15..12 = 0001 binary …. To continue in manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n+1’ * Mux : Selects channel programmed in ‘frame n+1’ (Manual mode), this channel will be acquired in this frame and sampled at start of ‘frame n+3’ * Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0001 binary …. Selects manual mode DI11=1 enables programming of ‘range and GPIO’ DI10..7 = binary address of channel DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n+1’ I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same frame CS Continue operation in manual mode Figure 50. Entering and Running in Manual Channel Sequencing Mode 30 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Device Functional Modes (continued) Table 1. Mode Control Register Settings for Manual Mode RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0001 Selects Manual Mode DI11 0 1 Enables programming of bits DI06-00. 0 Device retains values of DI06-00 from the previous frame. DI10-07 0000 This four bit data represents the address of the next channel to be selected in the next frame. DI10: MSB and DI07: LSB. For example, 0000 represents channel- 0, 0001 represents channel-1 and so forth. DI06 0 0 Selects 2.5V i/p range (Range 1) 1 Selects 5V i/p range (Range 2) 0 Device normal operation (no powerdown) 1 Device powers down on 16th SCLK falling edge 0 SDO outputs current channel address of the channel on DO15..12 followed by 12 bit conversion result on DO11..00. DI05 0 DI04 0 1 DI03-00 (1) 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel. DOI5 DOI4 DOI3 DOI2 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 31 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 8.4.5 Operating in Auto-1 Mode The details regarding entering and running in Auto-1 channel sequencing mode are illustrated in the flowchart in Figure 51. Table 2 lists the Mode Control Register settings for Auto-1 mode in detail. CS Frame: n-1 Device operation in Manual or Auto-2 mode No Change to Auto -1 mode? Yes CS Frame: n Request for Auto-1 mode CS Frame: n+1 Entry into Auto-1 Mode CS Frame: n+2 Operation in Auto-1 mode * Sample: Samples and converts channel selected in ‘frame n -1’ * Mux : Selects channel incremented from previous frame as per Auto -2 sequence, or channel programmed in previous frame in case of manual mode. This channel will be acquired in this frame and sampled at start of ‘frame n +1’ * Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n+1’ DI15..12 = 0010 binary …. Selects Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 = x, Device automatically resets channel to lowest number in Auto -1 sequence. DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n-1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects lowest channel# in Auto-1 sequence; this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +2’ DI15..12 = 0010 binary …. To continue in Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0, not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n+1’ (ie. Lowest channel# in Auto-1 sequence) * Mux : Selects next higher channel in Auto -1 sequence, this channel will be acquired in this frame and sampled at start of ‘frame n +3’ * Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0010 binary …. To continue in Auto-1 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0 not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI3..0 written in frame n+1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Continue operation in Auto -1 mode Figure 51. Entering and Running in Auto-1 Channel Sequencing Mode 32 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Table 2. Mode Control Register Settings for Auto-1 Mode RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0010 Selects Auto-1 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from previous frame. 1 The channel counter is reset to the lowest programmed channel in the Auto-1 Program Register DI10 0 0 The channel counter increments every conversion (No reset) DI09-07 000 xxx Do not care DI06 0 0 Selects 2.5V i/p range (Range 1) 1 Selects 5V i/p range (Range 2) DI05 0 0 Device normal operation (no powerdown) 1 Device powers down on the 16th SCLK falling edge 0 SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion result on DO11..00. DI04 0 1 DI03-00 (1) 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 33 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com The Auto-1 Program Register is programmed (once on powerup or reset) to pre-select the channels for the Auto1 sequence. Auto-1 Program Register programming requires two CS frames for complete programming. In the first CS frame the device enters the Auto-1 register programming sequence and in the second frame it programs the Auto-1 Program Register. Refer to Table 2, Table 3, and Table 4 for complete details. CS Device in any operation mode No Program Auto 1 register? Yes SDI: DI15..12 = 1000 (Device enters Auto 1 programming sequence) CS Entry into Auto 1 register programming sequence CS SDI: DI15..0 as per tables 4,5 Auto 1 register programming End of Auto 1 register programming NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 52. Auto-1 Register Programming Flowchart Table 3. Program Register Settings for Auto-1 Mode BITS RESET STATE LOGIC STATE FUNCTION FRAME 1 DI15-12 NA 1000 DI11-00 NA Do not care Device enters Auto-1 program sequence. Device programming is done in the next frame. All 1s 1 (individual bit) FRAME 2 DI15-00 A particular channel is programmed to be selected in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; for example, DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00 A particular channel is programmed to be skipped in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; for example DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00 0 (individual bit) Table 4. Mapping of Channels to SDI Bits for 16,12,8,4 Channel Devices Device (1) SDI BITS DI15 DI14 DI13 DI12 DI11 DI10 DI09 DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 DI00 16 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 12 Chan X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 8 Chan X X X X X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 4 Chan X X X X X X X X X X X X 1/0 1/0 1/0 1/0 (1) 34 When operating in Auto-1 mode, the device only scans the channels programmed to be selected. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 8.4.6 Operating in Auto-2 Mode The details regarding entering and running in Auto-2 channel sequencing mode are illustrated in Figure 53. Table 5 lists the Mode Control Register settings for Auto-2 mode in detail. CS Frame: n-1 Device operation in Manual or Auto -1 mode No Change to Auto- 2 mode ? Yes CS Frame: n Request for Auto-2 mode CS Frame: n+1 Entry into Auto-2 Mode CS Frame: n+2 Operation in Auto-2 mode * Sample: Samples and converts channel selected in ‘frame n-1’ * Mux : Selects channel incremented from previous frame as per Auto-1 sequence, or channel programmed in previous frame in case of manual mode. . This channel will be acquired in this frame and sampled at start of ‘frame n +1’ * Range: As programmed in ‘frame n-1’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n+1’ DI15..12 = 0011 binary …. Selects Auto-2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 = x, Device automatically resets to channel 0. DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n -1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n -1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel selected in ‘frame n’ * Mux : Selects channel0 (Auto-2 sequence always starts with Ch -0); this channel will be acquired in this frame and sampled at start of ‘frame n+2’ * Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame . * SDI : Programming for ‘frame n +2’ DI15..12 = 0011 binary …. To continue in Auto -2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0, not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame * Sample: Samples and converts channel 0 * Mux : Selects next higher channel in Auto -2 sequence, this channel will be acquired in this frame and sampled at start of ‘frame n+3’ * Range: As programmed in ‘frame n+1’. Applies to channel selected for acquisition in current frame.* SDI : Programming for ‘frame n+3’ DI15..12 = 0011 binary …. To continue in Auto -2 mode DI11=1 enables programming of ‘range and GPIO’ DI10 =0 not to reset channel sequence DI6.. As per required range for channel to be selected DI5=0 .. No power down DI4..0… as per GPIO settings *SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n+1’ * GPIO : O/P: latched on CS falling edge as per DI 3..0 written in frame n+1’ I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Continue operation in Auto-2 mode Figure 53. Entering and Running in Auto-2 Channel Sequencing Mode Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 35 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Table 5. Mode Control Register Settings for Auto-2 Mode RESET STATE BITS LOGIC STATE FUNCTION DI15-12 0001 0011 Selects Auto-2 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from the previous frame. 1 Channel number is reset to Ch-00. DI10 0 0 Channel counter increments every conversion.(No reset). DI09-07 000 xxx Do not care DI06 0 0 Selects 2.5V i/p range (Range 1) 1 Selects 5V i/p range (Range 2) DI05 0 0 Device normal operation (no powerdown) 1 Device powers down on the 16th SCLK falling edge 0 SDO outputs the current channel address of the channel on DO15..12 followed by the 12-bit conversion result on DO11..00. DI04 0 1 DI03-00 (1) 0000 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO data for the channels configured as output. Device ignores data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. The Auto-2 Program Register is programmed (once on powerup or reset) to pre-select the last channel (or sequence depth) in the Auto-2 sequence. Unlike Auto-1 Program Register programming, Auto-2 Program Register programming requires only 1 CS frame for complete programming. See Figure 54 and Table 6 for complete details. CS Device in any operation mode No Program Auto 2 register? Yes CS SDI: Di15..12 = 1001 DI9..6 = binary address of last channel in the sequence refer tables 6 Auto 2 register programming End of Auto 2 register programming NOTE: The device continues its operation in the selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 54. Auto-2 Register Programming Flowchart 36 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Table 6. Program Register Settings for Auto-2 Mode BITS RESET STATE LOGIC STATE FUNCTION DI15-12 NA 1001 Auto-2 program register is selected for programming DI11-10 NA Do not care DI09-06 NA aaaa DI05-00 NA Do not care This 4-bit data represents the address of the last channel in the scanning sequence. During device operation in Auto-2 mode, the channel counter starts at CH-00 and increments every frame until it equals “aaaa”. The channel counter roles over to CH-00 in the next frame. 8.4.7 Continued Operation in a Selected Mode Once a device is programmed to operate in one of the modes, the user may want to continue operating in the same mode. Mode Control Register settings to continue operating in a selected mode are detailed in Table 7. Table 7. Continued Operation in a Selected Mode BITS RESET STATE LOGIC STATE FUNCTION DI15-12 0001 0000 The device continues to operate in the selected mode. In Auto-1 and Auto-2 modes the channel counter increments normally, whereas in the Manual mode it continues with the last selected channel. The device ignores data on DI11-DI00 and continues operating as per the previous settings. This feature is provided so that SDI can be held low when no changes are required in the Mode Control Register settings. DI11-00 All '0' Device ignores these bits when DI15-12 is set to 0000 logic state 8.5 Programming 8.5.1 Digital Output As discussed previously in Overview, the digital output of the ADS79xx devices is SPI compatible. The following tables list the output codes corresponding to various analog input voltages. Table 8. Ideal Input Voltages for 12-Bit Devices and Output Codes for 12-Bit Devices (ADS7950/51/52/53) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → Vref Range 2 → 2×Vref Least significant bit (LSB) Vref/4096 2Vref/4096 Full scale Vref – 1 LSB 2Vref – 1 LSB 1111 1111 1111 FFF Midscale Vref/2 Vref 1000 0000 0000 800 Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 0111 1111 1111 7FF Zero 0V 0V 0000 0000 0000 000 STRAIGHT BINARY BINARY CODE HEX CODE Table 9. Ideal Input Voltages for 10-Bit Devices and Digital Output Codes for 10-Bit Devices (ADS7954/55/56/57) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → Vref Range 2 → 2×Vref Least significant bit (LSB) Vref/1024 2Vref/1024 Full scale Vref – 1 LSB 2Vref – 1 LSB 1111 1111 1111 3FF Midscale Vref/2 Vref 1000 0000 0000 200 Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 0111 1111 1111 1FF Zero 0V 0V 0000 0000 0000 000 Copyright © 2008–2015, Texas Instruments Incorporated STRAIGHT BINARY BINARY CODE HEX CODE Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 37 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Table 10. Ideal Input Voltages for 10-Bit Devices and Digital Output Codes for 10-Bit Devices (ADS7954/55/56/57) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range Range 1 → Vref Range 2 → 2×Vref Least significant bit (LSB) Vref/256 2Vref/256 Full scale Vref – 1 LSB 2Vref – 1 LSB 1111 1111 FF Midscale Vref/2 Vref 1000 0000 80 Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 0111 1111 7F Zero 0V 0V 0000 0000 00 STRAIGHT BINARY BINARY CODE HEX CODE 8.5.2 GPIO Registers NOTE GPIO 1 to 3 are available only in TSSOP packaged devices. The QFN device offers 'GPIO 0' only. As a result, all references related to 'GPIO 0' only are valid in the case of QFN package devices. The device has four General Purpose Input and Output (GPIO) pins. Each of the four pins can be independently programmed as General Purpose Output (GPO) or General Purpose Input (GPI). It is also possible to use the GPIOs for some pre-assigned functions (refer to Table 11 for details). GPO data can be written into the device through the SDI line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in the previous frame. Similarly, the device latches GPI status on the CS falling edge and outputs it on SDO (if GPI is read enabled by writing DI04 = 1 during the previous frame) in the same frame starting on the CS falling edge. The details regarding programming the GPIO registers are illustrated in the flowchart in Figure 55. Table 11 lists the details regarding GPIO Register programming settings. CS Device in any operation mode No Program GPIO register? Yes CS SDI: DI15..12 = 0100 Refer table 9 for DI11..00 data GPIO register programming End of GPIO register programming NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 55. GPIO Program Register Programming Flowchart 38 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Table 11. GPIO Program Register Settings RESET STATE BITS LOGIC STATE FUNCTION DI15-12 NA 0100 Device selects GPIO Program Registers for programming. DI11-10 00 00 Do not program these bits to any logic state other than ‘00’ DI09 0 1 Device resets all registers in the next CS frame to the reset state shown in the corresponding tables (it also resets itself). 0 Device normal operation DI08 0 1 Device configures GPIO3 as the device power-down input. 0 GPIO3 remains general purpose I or O. Program 0 for QFN packaged devices. 1 Device configures GPIO2 as device range input. 0 GPIO2 remains general purpose I or O. Program 0 for QFN packaged devices. 000 GPIO1 and GPIO0 remain general purpose I or O. Valid setting for QFN packaged devices. xx1 Device configures GPIO0 as ‘high or low’ alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 010 Device configures GPIO0 as high alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 100 Device configures GPIO1 as low alarm output. This is an active high output. GPIO0 remains general purpose I or O. Setting not allowed for QFN packaged devices. 110 Device configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high outputs. Setting not allowed for QFN packaged devices. DI07 0 DI06-04 000 Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI08..04 DI03 0 DI02 0 DI01 0 DI00 0 1 GPIO3 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO3 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO2 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO2 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO1 pin is configured as general purpose output. Program 1 for QFN packaged devices. 0 GPIO1 pin is configured as general purpose input. Setting not allowed for QFN packaged devices. 1 GPIO0 pin is configured as general purpose output. Valid setting for QFN packaged devices. 0 GPIO0 pin is configured as general purpose input. Valid setting for QFN packaged devices. 8.5.3 Alarm Thresholds for GPIO Pins Each channel has two alarm program registers, one for setting the high alarm threshold and the other for setting the low alarm threshold. For ease of programming, two alarm programming registers per channel, corresponding to four consecutive channels, are assembled into one group (a total eight registers). There are four such groups for 16 channel devices and 3/2/1 such groups for 12/8/4 channel devices respectively. The grouping of the various channels for each device in the ADS79xx family is listed in Table 12. The details regarding programming the alarm thresholds are illustrated in the flowchart in Figure 56. Table 13 lists the details regarding the Alarm Program Register settings. Table 12. Grouping of Alarm Program Registers GROUP NO. REGISTERS APPLICABLE FOR DEVICE 0 High and low alarm for channel 0, 1, 2, and 3 ADS7953..50, ADS7957..54, ADS7961..58 1 High and low alarm for channel 4, 5, 6, and 7 ADS7953..51, ADS7957..55, ADS7961..59 2 High and low alarm for channel 8, 9, 10, and 11 ADS7953 and 52, ADS7957 and 56, ADS7961 and 60 3 High and low alarm for channel 12, 13, 14, and 15 ADS7953, ADS7957, ADS7961 Each alarm group requires 9 CS frames for programming their respective alarm thresholds. In the first frame the device enters the programming sequence and in each subsequent frame it programs one of the registers from the group. The device offers a feature to program less than eight registers in one programming sequence. The device exits the alarm threshold programming sequence in the next frame after it encounters the first ‘Exit Alarm Program’ bit high. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 39 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 CS www.ti.com Device in any operation mode No Program alarm thresholds? Yes CS Entry into alarm register programming sequence CS SDI: DI15..12 = 11XX (xx indicates group of four channels; refer table 8) Device enters alarm register programming sequence SDI: DI15..0 as per table 8 (program alarm thresholds) Alarm register programming sequence No Yes DI12 = 1? Yes Program another group of four channels? No End of alarm programing NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming. Figure 56. Alarm Program Register Programming Flowchart 40 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Table 13. Alarm Program Register Settings BITS RESET STATE LOGIC STATE FUNCTION FRAME 1 DI15-12 NA 1100 Device enters ‘alarm programming sequence’ for group 0 1101 Device enters ‘alarm programming sequence’ for group 1 1110 Device enters ‘alarm programming sequence’ for group 2 1111 Device enters ‘alarm programming sequence’ for group 3 Note: DI15-12 = 11bb is the alarm programming request for group bb. Here ‘bb’ represents the alarm programming group number in binary format. DI11-14 NA Do not care FRAME 2 AND ONWARDS DI15-14 NA cc Where “cc” represents the lower two bits of the channel number in binary format. The device programs the alarm for the channel represented by the binary number “bbcc”. “bb” is programmed in the first frame. DI13 NA 1 High alarm register selection 0 Low alarm register selection 0 Continue alarm programming sequence in next frame 1 Exit Alarm Programming in the next frame. Note: If the alarm programming sequence is not terminated using this feature then the device will remain in the alarm programming sequence state and all SDI data will be treated as alarm thresholds. Do not care DI12 NA DI11-10 NA xx DI09-00 All ones for high alarm register and all zeros for low alarm register This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (High Alarm) or lower (Low Alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09 to DI02 and DI00, 01 are 'do not care'. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 41 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information In general applications, when the internal multiplexer is updated, the previously converted channel charge is stored in the 15-pF internal input capacitance that disturbs the voltage at the newly selected channel. This disturbance is expected to settle to 1 LSB during sampling (acquisition) time to avoid degrading converter performance. The initial absolute disturbance error at the channel input must be less than 0.5 V to prevent source current saturation or slewing that causes significantly long settling times. Fortunately, significantly reducing disturbance error is easy to accomplish by simply placing a large enough capacitor at the input of each channel. Specifically, with a 150-pF capacitor, instantaneous charge distribution keeps disturbance error less than 0.46 V because the internal input capacitance can only hold up to 75 pC (or 5 V × 15 pF). The remaining error must be corrected by the voltage source at each input, with impedance low enough to settle within 1 LSB. The following application examples explain the considerations for the input source impedance (RSOURCE). 9.1.1 Analog Input The ADS79xx device family offers 12/10/8-bit ADCSs with 16/12/8/4 channel multiplexers for analog input. The multiplexer output is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a system designer as both signals are accessible externally. Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be processed independently. In this condition, TI recommends limiting source impedance to 50 Ω or less. Higher source impedance may affect the signal settling time after a multiplexer channel change. This condition can affect linearity and total harmonic distortion. MXO AINP GPIO 0, H Alarm Ch0 Ch1 GPIO 1, L Alarm Ch2 GPIO 2, Range GPIO 3, PD From sensors, INA etc. There is a restriction on source impedance. RSOURCE £ 50 W ADC SDO To Host SDI SCLK CS Chn* REF 10 mF REF5025 o/p GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all references related to 'GPIO 0' only are valid in case of QFN package devices. Figure 57. Typical Application Diagram Showing MXO Shorted to AINP 42 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Application Information (continued) Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the restriction on source impedance to a large extent. Refer to Typical Characteristics (all ADS79xx Family Devices) for the effect of source impedance on device performance. The typical characteristics show that the device has respectable performance with up to 1kΩ source impedance. This topology (including a common ADC driver) is useful when all channel signals are within the acceptable range of the ADC. In this case the user can save on signal conditioning circuit for each channel. High input impedance PGA (or non inverting buffer such as THS4031) PGA Gain Control GPIO1 GPIO2 GPIO3 MXO AINP GPIO0 high-alarm low-alarm Ch0 Ch1 Ch2 See note A. ADC SDO To Host SDI SCLK CS Chn* REF 10 µF REF5025 o/p Figure 58. Typical Application Diagram Showing Common Buffer/PGA for All Channels When the converter samples an input, the voltage difference between AINP and AGND is captured on the internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS79xx charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 .. Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 43 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Application Information (continued) MXO Ch0 200 3 pF 80 5 pF AINP 7 pF Chn 20 M 3 pF Ch0 assumed to be on Chn assumed to be off Figure 59. ADC and MUX Equivalent Circuit 9.2 Typical Applications 9.2.1 Unbuffered Multiplexer Output (MXO) This application is the most typical application, but requires the lowest RSOURCE for good performance. In this configuration, the 2xREF range allows larger source impedance than the 1xREF range because the 1xREF range LSB size is smaller, thus making it more sensitive to settling error. MXO RSOURCE AINP GPIO 0 GPIO 1 Ch0 150 pF RSOURCE See Note A GPIO 2 GPIO 3 Ch1 150 pF RSOURCE ADC Chn 150 pF To Host REF REF5025 A. SDO SDI SCLK CS o/p 10 PF A restriction on the source impedance exists. RSOURCE ≤ 100 Ω for the 1xREF 12-bit settling at 1 MSPS or RSOURCE ≤ 250 Ω for the 1xREF 12-bit settling at 1 MSPS . Figure 60. Application Diagram for an Unbuffered MXO 9.2.1.1 Design Requirements The design is optimized to show the input source impedance (RSOURCE) from the 100 Ω to 10000 Ω required to meet the 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xREF (2.5-V) and 2xREF (5-V) input ranges. 9.2.1.2 Detailed Design Procedure Although the required input source impedance can be estimated assuming a 0.5-V initial error and exponential recovery during sampling (acquisition) time, this estimation over-simplifies the complex interaction between the converter and source, thus yielding inaccurate estimates. Thus, this design uses an iterative approach with the converter itself to provide reliable impedance values. To determine the actual maximum source impedance for a particular resolution and sampling rate, two subsequent channels are set at least 95% of the full-scale range apart. With a 1xREF range and 2.5 Vref, the channel difference is at least 2.375 V. With 2xREF and 2.5 Vref, the difference is at least 4.75 V. With a source impedance from 100 Ω to 10,000 Ω, the conversion runs at a constant rate and a channel update is issued that captures the first couple samples after the update. This process is repeated at least 100 times to remove any noise and to show a clear settling error. The first sample after the channel update is then compared against the second one. If the first and second samples are more than 1 LSB apart, throughput rate is reduced until the settling error becomes 1 LSB, which then sets the maximum throughput for the selected impedance. The whole process is repeated for nine different impedances from 100 Ω to 10000 Ω. 44 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Typical Applications (continued) 9.2.1.3 Application Curves These curves show the RSOURCE for an unbuffered MXO. 1000 1000 12-bit 10-bit 8-bit 800 12-bit 10-bit 8-bit 900 MAX Throughput (KSPS) MAX Throughput (KSPS) 900 700 600 500 400 300 200 100 800 700 600 500 400 300 200 100 0 100 1000 Rsource (:) 10000 D100 D101 Figure 61. 2xREF Input Range Settling without an MXO Buffer Copyright © 2008–2015, Texas Instruments Incorporated 0 100 1000 Rsource (:) 10000 D101 Figure 62. 1xREF Input Range Settling without an MXO Buffer Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 45 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com Typical Applications (continued) 9.2.2 OPA192 Buffered Multiplexer Output (MXO) The use of a buffer relaxes the RSOURCE requirements to an extent. Charge from the sample-and-hold capacitor no longer dominates as a residual charge from a previous channel. Although having good performance is possible with a larger impedance using the OPA192, the output capacitance of the MXO also holds the previous channel charge and cannot be isolated, which limits how large the input impedance can finally be for good performance. In this configuration, the 1xREF range allows slightly higher impedance because the OPA192 (20 V/µs) slews approximately 2.5 V in contrast to the 2xREF range that requires the OPA192 to slew approximately 5 V. 5V + OPA192 - RSOURCE 100 MXO 150pF AINP GPIO 0 GPIO 1 Ch0 150 pF RSOURCE See Note A GPIO 2 GPIO 3 Ch1 150 pF RSOURCE ADC Chn 150 pF To Host REF REF5025 A. SDO SDI SCLK CS o/p 10 PF Restriction on the source impedance exists. R(SOURCE) ≤ 500 Ω for a 12-bit settling at 1 MSPS with both 1xREF and 2xREF ranges. Figure 63. Application Diagram for an OPA192 Buffered MXO 9.2.2.1 Design Requirements The design is optimized to show the input source impedance (RSOURCE) from the 100 Ω to 10000 Ω required to meet a 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xREF (2.5 V) and 2xREF (5 V) input ranges. 9.2.2.2 Detailed Design Procedure The design procedure is similar to the unbuffered-MXO application, but includes an operation amplifier in unity gain as a buffer. The most important parameter for multiplexer buffering is slew rate. The amplifier must finish slewing before the start of sampling (acquisition) to keep the buffer operating in small-signal mode during sampling (acquisition) time. Also, between the buffer output and converter input (INP), there must be a capacitor large enough to keep the buffer in small-signal operation during sampling (acquisition) time. Because 150 pF is large enough to protect the buffer form hold charge from internal capacitors, this value selected along with the lowest impedance that allows the op amp to remain stable. The converter allows the MXO to settle approximately 600 ns before sampling. During this time, the buffer slews and then enters small-signal operation. For a 5-V step change, slew rate stays constant during the first 4 V. The last 1 V includes a transition from slewing and non-slewing. Thus, the buffer cannot be assumed to keep a constant slew during the 600 ns available for MXO settling. Assuming that the last 1-V slew is reduced to half is recommended. For this reason, slew is 10 V/µs or (5 Vref + 1 V) / 0.6 µs to account for the 1-V slow slew. The OPA192 has a 20-V/us slew, and is capable of driving 150 pF with more than a 50° phase margin with a 50-Ω or 100-Ω Riso, making the OPA192 an ideal selection for the ADS79xx-Q1 family of converters. 46 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 Typical Applications (continued) 9.2.2.3 Application Curves These curves show the RSOURCE for an OPA192 buffered MXO. 1000 1000 12-bit 10-bit 8-bit 800 12-bit 10-bit 8-bit 900 MAX Throughput (KSPS) MAX Throughput (KSPS) 900 700 600 500 400 300 200 800 700 600 500 400 300 200 100 100 0 100 1000 Rsource (:) 10000 D102 Figure 64. 2xREF Input Range Settling with an OPA192 MXO Buffer 0 100 1000 Rsource (:) 10000 D103 Figure 65. 1xREF Input Range Settling with an OPA192 MXO Buffer 10 Power Supply Recommendations The devices are designed to operate from an analog supply voltage (V(+VA)) range from 2.7 V to 5.25 V and a digital supply voltage (V(+VBD)) range from 1.7 V to 5.25 V. Both supplies must be well regulated. The analog supply is always greater than or equal to the digital supply. A 1-µF ceramic decoupling capacitor is required at each supply pin and must be placed as close as possible to the device. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 47 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 11 Layout 11.1 Layout Guidelines • • • • A copper fill area underneath the device ties the AGND, BDGND, AINM, and REFM pins together. This copper fill area must also be connected to the analog ground plane of the PCB using at least four vias. The power sources must be clean and properly decoupled by placing a capacitor close to each of the three supply pins, as shown in Figure 66. To minimize ground inductance, ensure that each capacitor ground pin is connected to a grounding via by a very short and thick trace. The REFP pin requires a 10-μF ceramic capacitor to meet performance specifications. Place the capacitor directly next to the device. This capacitor ground pin must be routed to the REFM pin by a very short trace, as shown in Figure 66. Do not place any vias between a capacitor pin and a device pin. NOTE The full-power bandwidth of the converter makes the ADC sensitive to high frequencies in digital lines. Organize components in the PCB by keeping digital lines apart from the analog signal paths. This design configuration is critical to minimize crosstalk. For example, in Figure 66, input drivers are expected to be on the left of the converter and the microcontroller on the right. 1 µF REFP Analog Inputs +VA 11.2 Layout Example 10 µF Pin 1 GPIO Analog Ground 1 µF +VBD GPIO SPI 1 µF +VA Analog Inputs Figure 66. Recommended Layout 48 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 www.ti.com SLAS605B – JUNE 2008 – REVISED JULY 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • REF5025 Data Sheet, SBOS410 • OPA192 Data Sheet, SBOS620 12.2 Related Links The following below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 14. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADS7950-Q1 Click here Click here Click here Click here Click here ADS7951-Q1 Click here Click here Click here Click here Click here ADS7952-Q1 Click here Click here Click here Click here Click here ADS7953-Q1 Click here Click here Click here Click here Click here ADS7954-Q1 Click here Click here Click here Click here Click here ADS7956-Q1 Click here Click here Click here Click here Click here ADS7957-Q1 Click here Click here Click here Click here Click here ADS7958-Q1 Click here Click here Click here Click here Click here ADS7959-Q1 Click here Click here Click here Click here Click here ADS7960-Q1 Click here Click here Click here Click here Click here ADS7961-Q1 Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 49 ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955 ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 SLAS605B – JUNE 2008 – REVISED JULY 2015 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 50 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 PACKAGE OPTION ADDENDUM www.ti.com 14-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS7950SBDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 B ADS7950SBDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 B ADS7950SBDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 B ADS7950SBRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 B ADS7950SBRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 B ADS7950SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7950 ADS7950SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 ADS7950SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7950 ADS7951SBDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 B ADS7951SBDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 B ADS7951SBDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 B ADS7951SBRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 B ADS7951SBRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Jul-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) B ADS7951SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 ADS7951SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 ADS7951SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7951 ADS7951SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 ADS7951SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS 7951 ADS7952SBDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B ADS7952SBDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B ADS7952SBDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 B ADS7952SBRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 B ADS7952SBRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 B ADS7952SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 ADS7952SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 ADS7952SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7952 ADS7952SRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 ADS7952SRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7952 ADS7953SBDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 B ADS7953SBDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 B Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Jul-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS7953SBDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 B ADS7953SBRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 B ADS7953SBRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 B ADS7953SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 ADS7953SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 ADS7953SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7953 ADS7953SRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 ADS7953SRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7953 ADS7954SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 ADS7954SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7954 ADS7954SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7954 ADS7954SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7954 ADS7955SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 ADS7955SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 ADS7955SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7955 ADS7955SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7955 ADS7955SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7955 Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Jul-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS7956SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 ADS7956SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7956 ADS7956SRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7956 ADS7956SRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7956 ADS7957SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 ADS7957SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7957 ADS7957SRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7957 ADS7957SRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7957 ADS7958SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 ADS7958SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 ADS7958SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7958 ADS7958SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7958 ADS7958SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7958 ADS7959SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 ADS7959SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 ADS7959SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7959 ADS7959SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7959 ADS7959SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7959 Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Jul-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS7960SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 ADS7960SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 ADS7960SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7960 ADS7960SRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7960 ADS7960SRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7960 ADS7961SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS7961 ADS7961SRHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7961 ADS7961SRHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 7961 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Jul-2015 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955, ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961 : • Automotive: ADS7950-Q1, ADS7951-Q1, ADS7952-Q1, ADS7953-Q1, ADS7954-Q1, ADS7955-Q1, ADS7956-Q1, ADS7957-Q1, ADS7958-Q1, ADS7959-Q1, ADS7960-Q1, ADS7961-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 6 PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7950SBDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7950SBRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7950SBRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7950SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7950SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7950SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SBDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7951SBRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SBRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7951SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7951SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7952SBDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7952SBRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7952SBRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7952SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7952SRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7952SRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2015 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7953SBDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7953SBRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7953SBRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7953SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7953SRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7953SRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7954SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7954SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7954SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7955SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7955SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7955SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7956SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7956SRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7956SRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7957SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7957SRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7957SRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7958SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7958SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7958SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7959SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS7959SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7959SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS7960SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7960SRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7960SRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7961SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 ADS7961SRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS7961SRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7950SBDBTR ADS7950SBRGER TSSOP DBT 30 2000 367.0 367.0 38.0 VQFN RGE 24 3000 367.0 367.0 35.0 ADS7950SBRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7950SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7950SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7950SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7951SBDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7951SBRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7951SBRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7951SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7951SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7951SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7952SBDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7952SBRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS7952SBRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS7952SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7952SRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS7952SRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS7953SBDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7953SBRHBR VQFN RHB 32 3000 367.0 367.0 35.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2015 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7953SBRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS7953SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7953SRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS7953SRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS7954SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7954SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7954SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7955SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7955SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7955SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7956SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7956SRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS7956SRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS7957SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7957SRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS7957SRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS7958SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7958SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7958SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7959SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0 ADS7959SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS7959SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS7960SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7960SRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS7960SRHBT VQFN RHB 32 250 210.0 185.0 35.0 ADS7961SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0 ADS7961SRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS7961SRHBT VQFN RHB 32 250 210.0 185.0 35.0 Pack Materials-Page 4 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue 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