ELMOS E98103A38B Autonomous mac and individual physical address Datasheet

E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Key Features
Included power supplies:
ÿÿ
ÿÿ
ÿÿ
ÿÿ
ÿÿ 20V supply, up to 20mA
ÿÿ 3.3V (70mA) / 5V (70mA) DC/DC converter
Certified with KNX® TP1-256 application
Autonomous MAC and individual physical address
Included protocol handling
Included power supply for bus powered
applications with selectable bus current limitation
The E981.03 combines the TP1-256 physical layer, the
communication controller and two DC supply outputs
for bus powered applications. The internal power management assures KNX conformance under all load conditions.
KNX® Interface
ÿÿ
ÿÿ
ÿÿ
ÿÿ
ÿÿ
General Description
Extended frames with up to 254 byte payload
Analog Mode (direct RX / TX interface)
Autonomous Telegram trigger
Alarm Telegram
Autonomous poll data transfer
The connection between the E981.03 and the host processor can be established by either UART or SPI compatible interfaces, or in direct Analog Mode.
UART host interface
Applications
ÿÿ Supports 9.6 k, 19.2 k, 115.2 k
ÿÿ 9 bit mode for easy data stream interpretation
ÿÿ Optional CRC (at 19.2kBd and 115.2 kBd)
ÿÿ Sensors, actuators, routers, gateways,
Bus-powered or externally supplied
ÿÿ Security applications
SPI™ host interface
Ordering Information
ÿÿ if not used 4 GPIOs are available
Ordering-No.:
Temp Range
Package
E98103A38B
-25°C to +85°C
QFN32L7
is a Konnex Association registered trademark.
SPI™ is a Motorola Inc. trademark.
Typical Application Circuit
Typical Application Circuit **1
V20
CREC
RTXH
U1
RXD
TXD
C20
RTX
µC
20V
CREC
UART
D1 BUSP
Q
BUSN
EXTAL
E981.03
SET_VCC RSET
XTAL
GND
+ BUS
TP1-256
Coupling
Module
VIO
V33I
VST
SW
VCC
VCC
LSPS
C33I
CCST
CST
DSPS
CVCC
Application
RTXL
RTXL
CCVCC CVIO
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
Minimal Function of E981.03 **3
1/51
C33I
QM-No.: 25DS0046E.03
TP1-
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Functional Diagram
Functional
D1
Diagram **2
E981.03
(19) VIO
(31) MISO / GPIO
(30) MOSI / GPIO
(29) SCK / GPI
(28) SCS / GPI
(26) RXD
(25) TXD
(21) BS1
(20) BS0
(32) SAVE
(2) RESET
(1) OTEMP
(4) AOUT
(22) INT
(7) WK / GPI
(12) BUSP
CREC
SPI host
interface
(8) CREC
(11) RTXH
U1
ADC/DAC
UART host
interface
KNX / EIB
Interface
RTX
(10) RTXL
RTXL
Internal
Logic
Monitoring
Unit
(9) BUSN
(23) EXTAL
Q
clock
system
(24) XTAL
+ TP1-256
(27) GND
(3) i.c.
(13) i.c.
Mode
Control
(16) i.c.
(5) SETVCC
20V
Switched
Current
Supply Limiter Power supply
IC supply
IC start-up
(6)
V33I
(14)
V20
(15) (17) (18)
VST SW VCC
RVCC
V20
VCC
CV20
LSPS
C33I
CCST CST
DSPS
CVCC
CCVCC
Full Normal Mode Application **4
8
Optional
Isolation
amplifier
28
27
26
25
EXTAL 23
XTAL 24
SW 17
VCC 18
VIO 19
BS0 20
BS1 21
INT 22
Note: Not to scale, EP Exposed die pad
CCST CST
29
GPIO / ResetN
GPIO
SPI
Option
7
host processor
Optional
Optocoupler
6
Analog IN
GPIO
Optional Optocoupler
5
GPIO
VCC= 5V
VCC= 3.3V
OPEN= Alarm
i.c.
SAVE
BUSP
MOSI
RTXH
MISO
RTXL
SCK
BUSN
SCS
GND
RXD
TXD
Optional
Optocoupler
OTEMP
1
2
4
CREG
3
V20
13
9
WK
E981.03
2
14
10
30
V33I
1
VST
11
31
SETVCC
32
15
Optional
Optocoupler
EP
E981.03
31
i.c.
32
12
33
AOUT
30
16
Optional
Optocoupler
SW
VCC
VIO
BS0
AOUT
i.c.
3
RESET
4
5
CREC
WK
6 V33I
SETVCC
7
E981.03
IC1
29
i.c.
D1
RTX
28
ELA-0120
RTXL
27
RESET
U1
BUSN
SCK9
RTXL
MISO10
RTXH
MOSI11
SAVE
BUSP
12
i.c.
13
V20
14
Pin 1
VST
15
i.c. 16
26
OTEMP
SCS
RSET
24 23 22 21 20 19 18 17
25
8
BUS
TXD
Coupling RXD
Module GND
BS1
CREC
VVIO
Bottom Side
INT
XTAL
Top View
EXTAL
C33I
UART
Pin Configuration
GPIO
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
RVCC
Data Sheet
LSPS
2/51
CVIO
VVCC= 3.3V (50mA)
SETVCC=GND
VVCC= 5V (30mA)
SETVCC=VVIO
QM-No.: 25DS0046E.03
Q
VVIO
VVCC
DVIO
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Pin Description
Pin
Name
Type 1)
Pull
Description
1
OTEMP
D_O
-
Over-temperature warning
2
RESET
D_IO
Up
Bidirectional reset pin (low active)
3
i.c.
-
-
Reserved for factory use, connect to GND during operation.
4
AOUT
A_O
-
Analog multiplexer output
5
SETVCC
D_I
2)
Combination of
- selection of the VCC output voltage and
- alarm function activation
6
V33I
S
-
3.3V internal supply: Connect to external capacitor
7
WK
HV_D_IO -
Output with tri-state capability; used for KNX telegram trigger
Output [default]: VIO related output levels
Input: VST tolerant. Thresholds V V33i related
8
CREC
HV_A_I
-
Receive pin for KNX bus communication
9
BUSN
S
-
Connection to the negative bus line
10
RTXL
HV_A_IO -
Ground connection of external resistor RTX
11
RTXH
HV_A_IO -
KNX send output pin - upper connection of external resistor RTX
12
BUSP
HV_S
-
Connection to positive KNX bus via external diode for reverse polarity protection
13
i.c.
-
-
Reserved for factory use, connect to GND during operation.
14
V20
HV_S
-
20V DC supply output
15
VST
HV_S
-
Connection to external storage capacitor CST
16
i.c.
-
-
Do not connect externally
17
SW
HV_A_IO -
Switched output of DC/ DC converter
18
VCC
A_I
-
DC/ DC converter output voltage control input
19
VIO
S
-
Supply for digital IO pins (connect to VCC if no external supply is
used)
20
BS0
D_I
Down
Baud rate select pin 0
21
BS1
D_I
Down
Baud rate select pin 1
22
INT
D_O
-
Used for KNX collision trigger (low active)
23
EXTAL
D_O
-
External crystal terminal 2
24
XTAL
D_I
-
External crystal terminal 1 or clock input if no crystal is connected
25
TXD
D_O
-
UART transmit signal: from E981.03 to host processor (push/pull)
26
RXD
D_I
Down
UART receive signal: from host processor to E981.03
27
GND
S
-
GND pin
28
SCS
D_I
Up
SPI chip select (low active) or General Purpose Input if SPI is disabled
29
SCK
D_I
Down
SPI clock or GPI if SPI is disabled
30
MISO
D_IO
-
SPI master in slave out data line or GPIO if SPI is disabled
31
MOSI
D_IO
-
SPI master out slave in data line or GPIO if SPI is disabled
32
SAVE
D_O
Up
VST under voltage pre alarm signal (low active)
33
EP
Exposed Die Pad
1) D = digital, A = analog, S = supply, I = input, O = output, HV = high voltage
2) Internally weak pulled to V33I/2. A open pin is the alarm condition. To select a VCC voltage push it to VIO or pull it to GND.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
3/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
1 Absolute Maximum Ratings
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages
with respect to ground. Currents flowing into terminals are positive, those drawn out of a terminal are negative.
Description
Symbol
Min
Max
Unit
BUSP voltage
VBUSP
-0.3
55
V
BUSP voltage during surge pulse (t < 150µs)
VBUSP_surge
-0.3
65
V
Junction temperature
TJ
-45
150
°C
Storage temperature
TS
-45
150
°C
ESD immunity (human body model, this test can be applied between any two pins of the IC)
VESD,hbm
-2
2
kV
Voltage at digital and analog VIO pins:
RESET, SAVE, XTAL, INT, SETVCC, OTEMP, SCS, SCK, MOSI,
MISO, RXD, TXD, BS0, BS1, AOUT
V
-0.3 V
VIO + 0.3 V
Voltage at WK pin
VWK
-0.3
40
V
Voltage at VST pin
V VST
-0.3
40
V
Voltage at SW pin
VSW
-5 V
VST + 0.3 V
Voltage at VCC pin
V VCC
-0.3
8
V
Voltage at VIO pin
V VIO
-0.3
7
V
Overall current through digital and analog VIO pins
(latch up immunity):
RESET, SAVE, XTAL, INT, SETVCC, OTEMP, SCS, SCK, MOSI,
MISO, RXD, TXD, BS0, BS1, WK, AOUT
I
-100
100
mA
Current through digital and analog VIO pins
(latch up immunity):
RESET, SAVE, XTAL, INT, SETVCC, OTEMP, SCS, SCK, MOSI,
MISO, RXD, TXD, BS0, BS1, WK
I
-70
70
mA
Voltage at pin EXTAL
VEXTAL
-0.3
+3.6
V
Input voltage at CREC pin
VCREC
-15 V
VBUSP
Voltage at pins RTXH, RTXL
VRTX
-0.3 V
VBUSP
Current through RTXL pin
IRTXL
0
800
mA
Current through AOUT pin
IAOUT
-10
10
mA
Voltage at pin V33I pin
V V33I
-0.3
+3.6
V
Voltage at pin V20
V V20
-0.3 V
VST + 0.3 V
2 Recommended Operation Conditions
Description
Condition
Symbol
Min
Typ
Max
Unit
Tamb
-25
25
85
°C
CST
270
330
1000
µF
CST equivalent series resistance
RESR,CST
0.1
1
Ω
CST voltage capability
VCST
35
Parallel ceramic capacitance VST to GND
CCER,ST
80
100
120
nF
Average bus idle voltage
VBUSP
20
30
33
V
C20
10
22
R
0.1
Ambient temperature
External storage capacitance
4)
20V supply external capacitance
7)
C20 equivalent series resistance
V
ESR,C20
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
4/51
µF
1
Ω
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Description
Condition
20V load current, this current is positive from
the supply to the output
Symbol
Min
IV20 8)
0
CVCC,L330µ
10
Typ
Max
Unit
20
mA
47
0.6 · CST
µF
VCC output capacitance
LSPS=330µH
VCC output capacitance
LSPS=1000µH
CVCC,L1000µ
68
100
0.6 · CST
µF
CVCC equivalent series resistance
LSPS=330µH
RESR,CVCC,L330µ
0.2
0.5
0.8
Ω
CVCC equivalent series resistance
LSPS=1000µH R
1
2)
ESR,CVCC, L1000µ
1.25
1.5
Ω
2)
Ceramic capacitance VCC to ground
CCVCC
80
100
120
nF
DC / DC converter inductance
LSPS
270
330
1200
µH
3
10
Ω
LSPS series resistance
Saturation current of LSPS
Maximum forward voltage of the external
diode
RL,SPS
1
3)
Isat,SPS
160
I=150mA
Vf,DSPS
Reverse recovery time of the external diode
mA
0.6
trr,DSPS
1
V
50
ns
VCC load current in 3.3 V mode, this current is
positive from the supply to the output
LSPS=330µH
IVCC3.3,L330µ 8)
0
50
mA
VCC load current in 3.3 V mode, this current is
positive from the supply to the output
LSPS=1000µH
IVCC3.3,L1000µ 8) 0
70
mA
VCC load current in 5V mode, this current is
positive from the supply to the output
LSPS=330µH
IVCC5,L330µ 8)
0
30
mA
VCC load current in 5V mode, this current is
positive from the supply to the output
LSPS=1000µH
IVCC5,L1000µ 8)
0
70
mA
Digital IO interface voltage 6)
VIO,norm=5V
VIO,5
4.75
5.25
V
Digital IO interface voltage
VIO,norm=3.3V
VIO,33
3.15
3.45
V
6)
Crystal frequency (+- 50 ppm)
fQ
Synchronization clock frequency applied at
pin XTAL
no crystal in- f
XTAL,sync
stalled
Receiver decoupling capacitance
External send resistance
External send resistor power dissipation
System level ESD protection resistance
1)
CCREC
50
56
62
nF
RTX
44.5
47
49.4
Ω
PRTX
1
W
1
VzDiode
5)
MHz
126.537 126.562 126.588 Hz
RSET; RVCC
5)
System level ESD protection zener-diode
7.3728
Analog monitor (AOUT - pin) current
IAOUT
-50
External send pull-down
RTXL
9
10
kΩ
6.2
V
50
µA
11
kΩ
1) For telegram rates > 50% PRTX = 2 W is recommended.
2) The lower limit is necessary for DC/ DC control.
The upper limit is a result of ripple considerations: voltage ripple is ESR * current ripple of LSPS.
To guarantee this over lifetime it is useful to use a low ESR capacitor and realize the lower limit with a series resistor.
3) Isat,SPS is the DC current that causes an inductance drop of 20 %.
4) Smaller CST down to 47 µF can be used, however the load step capability has to be proved experimentally.
5) Only necessary in case of the E981.03 being connected to a separate application module.
These components only ensuring to meet the absolute maximum rating in case of connecting and disconnecting the
application module. If the connector guarantees to connect GND potential first, the ESD protection is not needed.
6) For better elaboration of the ADC results a stable VIO is highly recommended.
7) High capacitance may affect the Reset / Power up Sequence time, as it is loaded with current limitation IV20(max).
8) To use the maximum current capability on VCC and V20 it is needed to change MAX_BUS_CURR settings before switching on
high current consumption. Additionally a continuous under voltage condition on BUSP could reduce available current. To
prevent unexpected under voltage conditions it is strongly recommended to observe VVST and implement a power
management system. The voltage VVST could be observed ADC converted trough UART or SPI.
For details read chapter 6.3 and 10.2.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
5/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
3 Electrical Characteristics
(VBUSP = 19V … 33V, TAMB = -25°C … +85°C, unless otherwise noted. Positive currents are flowing into the device pins.
Typical values are at TAMB = +25°C, unless otherwise noted.)
Description
Condition
Symbol
Min
Typ
Max
Unit
E981.03 Modes, Sequences and Functions - DC Characteristics
Voltage level at V33I pin for
activating hard reset mode
V V33I,reset,act
Voltage level at V33I pin for leaving hard reset mode
V V33I,reset,deact
First voltage level at VST pin for
switching VCC supply on
VST,VCC,on,abs
Second voltage level at VST pin for
switching VCC supply on
V VST,VCC,on,rel
-
VBUSP,mean
-6V
-
V
Voltage level for switching
KNX IC current from BUSP to VST
V VST,V33ana
-
12
-
V
Voltage level for switching VST
load current in soft start mode
to maximum level
V VST,V33dig
15
Current at BUSP during soft
start
IBUSP,SS
9
Voltage level at VST pin for
switching VCC supply off
V VST,VCC,off
9
2.6
3.0
16
V
V
10
mA
V
Voltage level at VCC pin for RESET
deactivation (3.3 V)
V VCC = 3.3 V
VRESET,LH,3
2.8
3.05
V
Voltage level at VCC pin for RESET
deactivation (5V)
V VCC = 5 V
VRESET,LH,5
4.20
4.5
V
Voltage hysteresis at VCC pin for
RESET generation
VRESET,VCC,hyst
0.095
Voltage level at VST pin for activation of SAVE pin
V VST,SAVE,HL
13
15
V
Absolute V VST level for
deactivation of SAVE pin
V VST,SAVE,LH,abs 14
16
V
Relative V VST level for
deactivation of SAVE pin
V VST,SAVE,LH,rel
VBUSP,mean
-6V
V
VBUSP level for deactivation of SAVE
pin
VBUSP,SAVE,LH
18.5
V
Hysteresis of SAVE pin
activation / deactivation levels
VST,SAVE,hyst
V
1
V
ISAVE = 5 mA
VIO = 5 V
VSAVE,low,5
0.7
V
ISAVE = 2 mA
VSAVE,low,2
0.4
V
VSAVE = 0 V
VIO = 5 V
ISAVE,pu
-500
Absolute V20 supply activation
threshold
V V20,on,abs
V VST,SAVE,LH
+1 V
Relative V20 supply activation
threshold
V V20,on,rel
VBUSP,mean
-5V
Absolute V20 supply deactivation
threshold
V V20,off,abs
V VST,SAVE,HL
+1 V
SAVE output voltage at logic-level
low
Pull up current at pin SAVE
µA
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
6/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Electrical Characteristics (continued)
(VBUSP = 19V … 33V, TAMB = -25°C … +85°C, unless otherwise noted. Positive currents are flowing into the device pins.
Typical values are at TAMB = +25°C, unless otherwise noted.)
Description
Condition
Symbol
Min
Typ
Max
Unit
VBUSP,mean
-6V
Relative V20 supply deactivation
threshold
V V20,off,rel
High threshold at pin WK. 1)
VWK,high
2.0
2.5
V
Low threshold at pin WK.
VWK,low
1.1
1.6
V
1)
Pull down current at pin
WK (active in input mode) 1)
VWK = V VIO/2,
V VIO = 5V
IWK,pd
High level at pin WK
IWK = -2mA
VWK,OUT,high2
V VIO -1V
V
High level at pin WK
IWK = -0.5mA
VWK,OUT,high5
V VIO
-0.5V
V
Low level at pin WK
IWK = 5mA
VWK,OUT,low
0.7
V
t33I,on
20
ms
60
µA
E981.03 mode parameters - AC Characteristics
Maximum duration of hard reset
mode
VBUSP > 20 V
C33I = 100 nF
Wait time between KNX bus communication free and sending Reset
indication to the host processor
tw,ri
40
Duration of an active driven wakeup pulse to MCU causes by a valid
trigger telegram
tTRIGGER,pw
80
Debounce time of alarm condition
at pin SETVCC
tALARM,deb
bit
times
100
120
ms
100
120
ms
0.4
V
Reset Concept - DC Characteristics
Actively driven low level on pin
RESET
IRESET < 5 mA
V VIO > 3 V
VRESET,low, out
Pull up current at pin RESET
VRESET = 0 V
V VIO = 5 V
IRESET,pu
2)
-500
µA
Low level at pin RESET input path
VRESET, low,in
High level at pin RESET input path
VRESET, high,in
0.8
0.2
VIO
VIO
Minimum voltage at pin VIO for interpreting the input path of
RESET 3)
VIO,min, RESET
2.0
V
Debounce time of input pin RESET
for activation soft reset mode
tRESET,deb
10
µs
Minimum active time of RESET 4)
tRESET,min
10
VST_drop
2
IBUSP(max)
11.4
Reset Concept - AC Characteristics
20
ms
2.4
3
V
12
12.6
mA
Power Supply – DC Characteristics
Voltage drop between BSUP and
VST PIN
Maximum DC BUSP current
MAX_BUS_CURR
(0x20F) = 0xBF
1) The WK pin is configurable as input or as output which sent a trigger pulse on received trigger telegram. To configure this change bit EN_OUT to “0” in Register TRIGGER (0x214). Default configuration is output.
2) The RESET pin is an open drain input/output with pull current source to VIO
3) The input at pin RESET is not active in reset and startup modes and in case of low VIO
4) In case of RESET activation by E981.03.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
7/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Electrical Characteristics (continued)
(VBUSP = 19V … 33V, TAMB = -25°C … +85°C, unless otherwise noted. Positive currents are flowing into the device pins.
Typical values are at TAMB = +25°C, unless otherwise noted.)
Description
Condition
Symbol
Min
Typ
Max
Unit
Maximum DC BUSP current
MAX_BUS_CURR
(0x20F) = 0xFF
IBUSP(max)
17.1
18
18.9
mA
Maximum DC BUSP current
MAX_BUS_CURR
(0x20F) = 0x3F
IBUSP(max)
22.8
24
25.2
mA
Maximum DC BUSP current
MAX_BUS_CURR
(0x20F) = 0x7F
IBUSP(max)
28.5
30
31.5
mA
Maximum bus current slope
in 0.25 mA/ms mode
CURRENT_SLOPE
(0x210) = 0x00
slope,
lim025_di/
dt
0.17
0.2
0.23
mA /
ms
Maximum bus current slope
in 0.5 mA/ms mode (default)
(0x210) = 0x01
slope,
1)
lim05_di/dt 0.35
0.4 1)
0.45 1)
mA /
ms
Maximum bus current slope
in 1.25 mA/ms mode
(0x210) = 0x02
slope,
lim125_di/
dt
1 1)
1.13 1)
mA /
ms
Maximum bus current slope
in 2.5 mA/ms mode
(0x210) = 0x03
slope,
lim25_di/dt 1.75
2
2.25
mA /
ms
Output voltage at pin V20
V VST > 20V,
IV20 = 0 ... IV20(max)
(positive output
current)
V V20
20
21.5
V
Voltage drop linear voltage
regulator at under-voltage
V VST<20V,
IV20 =0...20mA
(positive output
current)
V V20,DROP
0.5
0.8
V
Short circuit current
(positive output current)
IV20(SC)
25
50
mA
Output voltage in 3.3V mode
ILOAD,VCC <= 50 mA
(positive output current)
SETVCC = GND
V VCC3.3
3.15
3.3
3.45
V
Output voltage in 5V mode
ILOAD,VCC <= 30 mA (positive output current) V VCC5
SETVCC = VIO
4.75
5
5.25
V
0.87 1)
18.5
CVCC = 47µF
Voltage ripple in 3.3V mode. This
ESR = 0.5Ω
ripple is already included in output LSPS = 330µH
voltage tolerance.
RLSPS = 3 Ω
SETVCC = GND
V VCC,PP3.3
70
mV
CVCC = 47µF
Voltage ripple in 5V mode. This rip- ESR = 0.5Ω
ple is already included in output
LSPS = 330µH
voltage tolerance.
RLSPS = 3 Ω
SETVCC = VIO
V VVC,PP5
70
mV
Voltage at pin SETVCC for
selection of VCC = 3.3 V and no
active alarm condition
VSETVCC,low
Voltage at pin SETVCC for an
active alarm condition
VSETVCC,alarm
0.4
0.6
V
0.6
V V33I
1) guaranteed by design
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
8/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Electrical Characteristics (continued)
(VBUSP = 19V … 33V, TAMB = -25°C … +85°C, unless otherwise noted. Positive currents are flowing into the device pins.
Typical values are at TAMB = +25°C, unless otherwise noted.)
Description
Condition
Symbol
Min
Voltage at pin SETVCC for
selection of VCC = 5 V and no
active alarm condition
VSETVCC,high
0.8
Pull resistance at pin SETVCC to
V33I
Rp33,SETVCC
200
kΩ
Pull resistance at pin SETVCC to
GND
Rp0,SETVCC
200
kΩ
Voltage at pin V33I
V V33I
3.22
Typ
Max
Unit
V V33I
3.3
3.38
V
Clock System - AC Characteristics
Crystal frequency (±50ppm)
CLK_FAC L/H (0x20A
/ 0x20B) = 0xE330
(reset value)
fQ
Synchronization clock frequency
applied at pin XTAL
no crystal installed
EXTAL is n.c.
f XTAL,sync
7.3728
126.537 126.562
MHz
126.588 Hz
Host UART Interface - DC Characteristics
Input low voltage at pin RXD
VRXD,low
Input high voltage at pin RXD
VRXD,high
Pull down current at pin RXD
Low level on TXD pin
High level on TXD pin
VIO
IRXD,pd
ITXD = 5 mA, VIO = 5
V TXD,low,5
0.7
V
ITXD = 2 mA
V TXD,low,2
0.4
V
ITXD = -5 mA, VIO = 5
V TXD,high,5
VIO-0.7 V
ITXD = -2 mA
V TXD,high,2
VIO-0.4 V
0.2
VIO
VBS0,low
High level on pin BS0
VBS0,high
VIO=5 V, VBS0=5 V
VBS1,low
High level on pin BS1
VBS1,high
VIO=5 V, VBS0=5 V
100
µA
0.8
IPD,BS0
Low level on pin BS1
Pull down current on pin BS1
VIO
VRXD = 5 V, VIO = 5 V
Low level on pin BS0
Pull down current on pin BS0
0.2
0.8
VIO
30
µA
0.2
0.8
IPD,BS1
VIO
VIO
30
µA
Host UART Interface - AC Characteristics
UART receiver timeout between
subsequent byte of a service
tUART,IBG,RX
2.5
Baud rate deviation
ΔfUART
-3%
Input high voltage at pin SCS, SCK,
MOSI, MISO
VSPI,high
0.8
Input low voltage at pin SCS, SCK,
MOSI, MISO
VSPI,low
ms
3%
Host SP Interface - DC Characteristics
VIO
0.2
VIO
Pull down current on pin SCS
VSCS=5 V, VIO=5 V
IPU,SCS
-30
µA
Pull down current on pin SCK
VSCK=5 V, VIO=5 V
IPU,SCK
-30
µA
High output level on MISO, MOSI
pin
IMISO = -5mA, VIO= 5V
VMISO,high,5
VIO -0.7V
IMISO = -2 mA
VMISO,high,2
VIO-0.4 V
Low output level on MISO, MOSI
pin
IMISO = 5mA, VIO= 5V
VMISO,low,5
0.7
V
IMISO = 2 mA
VMISO,low,2
0.4
V
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
9/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Electrical Characteristics (continued)
(VBUSP = 19V … 33V, TAMB = -25°C … +85°C, unless otherwise noted. Positive currents are flowing into the device pins.
Typical values are at TAMB = +25°C, unless otherwise noted.)
Description
Condition
Symbol
Min
Typ
Max
Unit
Time between falling SCS edge
and first rising SCK edge
tLS1
30
ns
Time between last falling SCK
edge and rising SCS edge
tLS2
30
ns
Inter byte gap - time between last
falling SCK edge of a byte
transmission and first rising SCK
edge of subsequent byte within a
SPI transfer relevant especially for
read accesses between address
and data bytes
tIBG
1
µs
Period of SPI clock
tP_SCK
250
ns
MOSI data setup time (time between MOSI data valid and falling
edge of SCK
tsetup
30
ns
Input low voltage at pin MOSI data
hold time (time between falling
edge of SCK and MOSI data invalidation)
thold
20
ns
Host SP Interface - AC Characteristics
MISO data valid time (time between rising edge of SCK and
MISO data valid)
CMISO < 20 pF
tvalid
Time between rising edge of SCS
and high impedance at MISO
35
tMISO_Z
100
ns
ns
Monitoring Functions
ADC scaling factor for low voltage
VBUSP signal used for measurement
(VADC / VBUSP)
ScaleVBUSP,
ADC scaling factor for low voltage
V20 signal used for measurement
(VADC / V20)
1/16.1
1/15
1/13.9
ScaleV20,ADC
1/8.4
1/8
1/7.6
ADC scaling factor for low voltage
VCC signal used for measurement
(VADC / VCC)
ScaleVCC,ADC
1/2.14
1/2
1/1.86
ADC scaling factor for low voltage
VCC signal used for measurement
(VADC / VST)
ScaleVST,ADC
1/10.7
1/10.05
1/9.4
ADC scaling factor for low voltage
VIO signal used for ADC
measurement (VADC / VIO)
ScaleVIO,ADC
1/2.36
1/2.2
1/2.04
Averaging time for mean value of
VBUSP
tVBUSP(AV)
Temperature limit for activating
temperature warning
Twarn,on
Temperature limit for
deactivating temperature
warning
Twarn,off
Twarn,on
-10°C
°C
Temperature limit for reducing
power consumption
Tshutoff,on
Twarn,on
+30°C
°C
ADC
5
110
ms
120
140
°C
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
10/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Electrical Characteristics (continued)
(VBUSP = 19V … 33V, TAMB = -25°C … +85°C, unless otherwise noted. Positive currents are flowing into the device pins.
Typical values are at TAMB = +25°C, unless otherwise noted.)
Description
Condition
Symbol
Temperature limit for switching
on power consuming functions
High level at pin OTEMP
Low level at pin OTEMP
Min
Typ
Max
Twarn,on
+20°C
Tshutoff,off
Unit
°C
IOTEMP = -5 mA,
V VIO=5V
VOTEMP,high,5
VIO-0.7V
IOTEMP = -2 mA
VOTEMP,high,2
VIO-0.4V
IOTEMP = 5 mA,
V VIO=5V
VOTEMP,low,5
0.7
V
IOTEMP = 2 mA
VOTEMP,low,2
0.4
V
Temperature step per LSB
ΔTLSB
Aout scaling factor for low voltage
VBUSP signal used for measurement (VAOUT / VBUSP)
ScaleVBUSP,
Aout scaling factor for low voltage
VBUSP signal used for measurement (VAOUT / VBUSP)
ScaleVBUSP,
2.5
K
1/12.2
1/12
1/11.8
1/8.1
1/8
1/7.9
AOUT,3V3
AOUT,5V
4 Hardware Configuration
Pins of SPI and UART interfaces, SAVE, RESET, WK, INT and OTEMP are prepared for galvanic insulation with optical
coupler. MISO, TXD, SAVE, RESET, WK, INT and OTEMP can provide a current of 5 mA for driving a diode of an optical coupler in case of VIO = 5 V.
For lower power consumption set VIO_SW bit in PS_CTRL register.
4.1 PCB Design Rules
Figure 1. PCB Layout
Remark! The layout example is incomplete! The layout only gives an example about the placement of the DC/DC
converter components, the external capacitors and GND routing.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
11/51
QM-No.: 25DS0046E.03
E981.03
BUSN
EXTAL
Applicati
Q
VIO
SET_VCC RSET
XTAL
GND
+ TP1-256 BUS
Coupling
KNX/ EIB TRANSCEIVER Module
PRODUCTION DATA - JAN 15, 2015
V33I
VST
SW
VCC
VCC
LSPS
C33I
CCST
CST
DSPS
CVCC
(9) BUSN
(23) EXTAL
Q
(24) XTAL
+ TP1-256
(27) GND
(3) i.c.
(13) i.c.
E981.03
CCVCC CVIO
4.2 Minimal Function of E981.03
Minimal Function of E981.03 **3
Full Normal Mode
C33I
C3
RSET
CREC
RVCC
CCST CST
DVIO
C20
OTEMP not used:
WK not used:
SAVE not used:
RESET not used:
AOUT not used:
open
open
open
open
open
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
12/51
5
CREC
WK
V33I
SETVCC
6
7
20
19
LSPS
VVIO = VVCC
(50mA)
SETVCC=VIO
Figure 2. Schematic Example (minimal application)
DC/ DC converter active (3.3 V): Imax=50 mA
SETVCC = GND:
VCC = 3.3 V
BS1 = BS0 = GND:
UART 19.2 k baud
V20 not used:
V20 = VST
UART optional with optical coupler
SPI not used
MOSI = GND
MISO = open
SCK = GND
SCS = VIO
8
RVCC
Q
DSPS CVCC CCVCC CVIO
E981
17
Application
Module
VVIO
LSPS
IC
18
25
RTX
BUSN
9
RTXL 10
RTXH 11
BUSP
12
i.c.
13
V20
14
VST
15
i.c. 16
SW
VCC
VIO
BS0
26
RTXL
UART
27
U1
D1
Optional
Optocoupler
29
28
22
host processor
OTEMP
E981.03
30
EXTAL 23
XTAL 24
CCST CST
1
2
AOUT
i.c.
3
RESET
4
5
CREC
WK
V33I
SETVCC
6
7
IC1
E981.03
31
SAVE
MOSI
MISO
SCK
SCS
GND
RXD
TXD
BUS
Coupling
Module
ELA-0120
D1
33
ELA-0120
RTXL
RTX
VVIO
32
SW 17
VCC 18
VIO 19
BS0 20
BS1 21
INT
U1
BUSN
9
RTXL 10
RTXH 11
BUSP
12
i.c.
13
V20
14
VST
15
i.c. 16
8
BUS
Coupling
Module
CREC
QM-No.: 25DS0046E.03
DSPS CVCC CCVC
VIO
VCC
(27) GND
(3) i.c.
(13) i.c.
(16) i.c.
(5) SETVCC
20V
Switched
Current
Supply Limiter Power supply
IC supply
IC start-up
KNX/ EIB TRANSCEIVER
CCVCC CVIO
Mode
Control
(6)
V33I
(14)
V20
PRODUCTION DATA - JAN 15, 2015
(15) (17) (18)
VST SW VCC
E981.03
RVCC
V20
VCC
CV20
LSPS
C33I
CCST CST
DSPS
CVCC
CCVCC
4.3 Full Normal Mode Application
Full Normal Mode Application **4
VVIO
RSET
Application
Module
CCST CST
VVIO
Optional
Isolation
amplifier
Optional
Optocoupler
29
28
27
26
25
LSPS
DVIO
Q
SPI
GPIO
DVIO
DSPS CVCC CCVCC CVIO
C20
GPIO / ResetN
GPIO
VVCC= 3.3V (50mA)
SETVCC=GND
VVIO VVCC= 5V (30mA)
VVCC SETVCC=VVIO
RVCC
VVIO = VVCC
(50mA)
SETVCC=VIO
Analog IN
GPIO
Optional Optocoupler
30
E981.03
SAVE
MOSI
MISO
SCK
SCS
GND
RXD
TXD
Optional
Optocoupler
OTEMP
1
2
AOUT
i.c.
RESET
3
4
5
WK
V33I
SETVCC
6
7
CREC
8
IC1
31
Optional
Optocoupler
Optional
Optocoupler
UART
D1
32
33
EXTAL 23
XTAL 24
RTXL
RTX
BUSN
9
RTXL 10
RTXH 11
BUSP
12
i.c.
13
V20
14
VST
15
i.c. 16
E981.03
U1
SW 17
VCC 18
VIO 19
BS0 20
BS1 21
INT 22
VVIO
SAVE
MOSI
MISO
SCK
SCS
GND
RXD
TXD
BUS
Coupling
Module
ELA-0120
host processor
CREC
GPIO
VCC= 5V
VCC= 3.3V
OPEN= Alarm
host processor
Optional
Optocoupler
C33I
Option
3 **3
UART
C
clock
system
(24) XTAL
+ TP1-256
(4) AOUT
(22) INT
(7) WK / GPI
Unit
(23) EXTAL
Q
Applic
SET_VCC RSET
VV20=20V / 20mA
Figure 3. Schematic Example (full application)
DC/DC converter active (3.3 V/5 V):
SETVCC = GND:
SETVCC = VIO:
BS1 = BS0 = GND:
V20 used:
UART optional with optical coupler
SPI optional with optical coupler
Imax = 50/ 30 mA
VCC = 3 V
VCC = 5 V
UART 19.2 k baud
additional CV20,
Imax = 20 mA
OTEMP used
WK used
SAVE used
RESET used
AOUT used
optional with optocoupler
optional with optocoupler
optional with optocoupler
optional with optocoupler
optional with insulation
amplifier for analog Signal
In Normal Mode alarm functionality is usable. Alarm is detected in case of an open SETVCC pin.
For other schematics read application notes.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
13/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 1. Recommended Components
Component Recommended value
Remarks
U1
model: SMAJ43CA, SMBJ43CA
D1
model: BYG21
CST
330 µF / 35 V
ESR < 1 Ω
CCST
ceramic 100 nF / 35 V
±20%
C20
22 μF / 35 V
ESR < 1 Ohm
LSPS
330 µH, RLSPS,typ = 3 Ω,RLSPS,max = 10 Ω, Isat,SPS = 160 mA, Tamb < 85 °C ±20%
CVCC
47 µF / 6 V
0.2 Ω < ESR < 0.8 Ω
CCVCC
ceramic 100 nF / 8V
±20%
CCVIO
ceramic 100 nF / 8V
±20%
DSPS
40 V, 200 mA, trr < 15 ns
e.g. BAT64
C33I
ceramic 100 nF
±20%
RTX
47 Ω
±5 % / 1 W
CREC
Ceramic 56 nF
±10 %
Q
f = 7.3728 MHz, tolerance 50 ppm
Do not use external capacitors or crystals with internal
capacitors.
RSET 1)
1 kΩ
RVCC 1)
1 kΩ
DVIO
6.2 V, 500 mW
RTXL
1)
10 kΩ
±1%
1) Only necessary in case of the E981.03 being connected to a separate application module. These components only ensuring to
meet the absolute maximum rating in case of connecting and disconnecting the application module. If the connector guarantees
to connect GND potential first, the ESD protection is not needed.
5 Interfaces Description
5.1 KNX/ EIB – Interface
The KNX/ EIB - Interface is a full compatible KNX TP1
transceiver with autonomous Medium Access Control
and individual physical Address. The telegram on KNX
bus is analyzed and dependent on its contents and
communication mode, the data will be processed.
In Analog Mode, the signals SEND and REC are directly
bypassed to the host UART interface pins RXD and TXD.
5.2 UART – Interface
The E981.03 has a full duplex UART interface to transmit and receive bytes asynchronously. The protocol between E981.03 and host controller is a two-wire protocol with software handshake.
The UART host interface consists of the following three
parts
• UART physical layer realizes media access and bit
decoding / encoding or output driver for KNX bypass in Analog Mode
•
UART logical layer provides byte framing capabilities
•
UART service layer defines control and data access
sequences
To secure UART communication, a CRC calculation for
receive and transmit path can be activated separately.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
14/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 2. Baud rate configuration
BS1
GND
GND
VIO
VIO
BS0
VIO
GND
GND
VIO
Description
9.6 k baud
19.2 k baud
115.2 k baud
Analog Mode
CRC check useable
No
Yes
Yes
No
Remark
8 bit, even parity, 1 stop-bit
8 bit, even parity, 1 stop-bit
9 bit, even parity, 1 stop-bit
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
P
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
Sp
104µs • 11Bit = 1,042ms
52µs • 11Bit = 0,521ms
8,7 µs • 12 Bit = 0,104ms
9.600 Baud
19.200 Baud
115.200 Baud
ST
D0..D8
P
Sp
Start Bit
Data Bits
Parity Bit
Stop Bit
Sp
Low
LSB first
even
High
Figure 4. UART Bit
The bit D8 in 9-bit UART has the following meaning:
0: data byte
1: service byte
5.3 SPI compatible – Interface
E981.03 has a slave SPI compatible - interface to transmit and receive data. The interface can be used alternatively for E981.03 configuration and KNX communication. In analog mode the interface is the only possibility
to configure parameters like bus current.
To secure SPI compatible communication, a CRC calculation can also be activated.
The user could switch off the SPI compatible - Interface
by setting ON0 and ON1 to zero (Register SPI_CTRL ). In
this case 4 GPIOS could be used trough the UART – Interface. The GPIOs have VIO related I/O levels.
The pins MOSI and MISO are useable as general purpose
inputs or outputs. The pins SCS and SCK can be used as
input pins. For read and write
5.4 Telegram Transmission
After successful upload of the frame E981.03 sends the
frame on KNX bus after the KNX specified bus
idle time detected.
The repeat flag of the frame transmitted is handled by
the E981.03.
• In first transmission the repeat flag is set to 1.
• In repeated frames the repeat bit is cleared to 0.
The acknowledge frame sent by the receivers of the
frame is checked and
• In case of BUSY acknowledged frames E981.03
waits for at least 150 bit times after the BUSY acknowledge before starting a new transmission attempt. These 150 bit times refer to the end of the
BUSY acknowledged frame independent from other
communication on the EIB bus. In case of bus com-
munication between the two (BUSY) repetitions the
time between the interposed frame and the BUSY
repetition is 50 bit times.
• In case of NACK acknowledged frames E981.03
starts a new transmission attempt.
• No acknowledge and corrupted acknowledge will
be handled as NACK.
• BUSY and NACK acknowledge will be handled as
BUSY.
If the repeat flag in the uploaded frame is not set,
E981.03 will send the frame only once even in case of
not ACK acknowledgment.
The maximum number of repetitions is defined in the
register MAX_RST_CNT and can be modified e.g.
by a host UART service or SPI.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
15/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 3. KNX frame timing
Description
Condition
Symbol
Time between end of telegram
upload from host processor to
E981.03 and start of telegram
transmission on EIB bus
(in case of idle EIB bus)
bit TXDEL of
register
UART_CTRL = 0
L_Data or
L_PollData
frame
ttr,delay,var
Time between end of telegram
upload from host processor to
E981.03 and start of telegram
transmission on EIB bus
(in case of idle EIB bus)
bit TXDEL of
register
UART_CTRL = 0
L_ExtData frame
Wait time after BUSY acknowledge
Min
tBUSY,rep
Typ
Max
Unit
104
μs
250
μs
104
μs
5.5 AOUT
The pin AOUT is used to monitor several voltages. The
source can be selected by a register value. The analog
monitor signal is not filtered by the E981.03. Especially
the scaled analog bus voltage is not the mean value of
the bus voltage but follows the BUSP line immediately.
Between AOUT buffer and AOUT pin a series resistor of
approximately 10 k is implemented in E981.03. It can be
VIO = 3.3 V
VIO = 5 V
used to realize a first order RC filter by connecting AOUT
to an external capacitor Cext. Measurement of AOUT
voltage needs to take the intern resistor value into account (high impedance measurement input use).
Measurement values are:
• Temperature voltage
• Band gap voltage 1)
• Bus voltage
VBUS / 12
VBUS / 8
other multiplexer configuration are invalid
1) The band gap voltage can be used to increase the precision of the ADC.
VBUS/12
VBUS/8
0
1
AOUT_CTRL[0]
VTemp
VBG
1
2
3
E981.03
Approx.
10kΩ
+
external µC
AOUT
-
Analog IN
AOUT_SRC[0:1]
Figure 5. Analog Monitoring
AOUT is controlled by Register AOUT_CTRL and Register AOUT_SRC.
5.6 WK
The WK pin is configurable as output for remote wake-up with trigger telegram or as general purpose input. To configure as a input change bit EN_OUT to “0” in Register TRIGGER (0x214). Default configuration is output. To read
input state read bit WK in the Register PINS.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
16/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
5.7 E981.03 System Functions
5.8 Power Supply
GND
BUSP
VBUSP
Switch A:
Switch to 0:
Switch to 1:
bus current
source
IREF<= IBUSP,MAX
VVST_drop
D
01
2
Switch to 2:
Switch A
ILOAD_SUM
Switch C
V20
supply
V33I
supply
2
1
Switch B
IV33I
VST
(15)
IVST
CST
V20
(14)
VVST
IV20
CV20
VV20
VCC buck
converter
V33I
(6)
VCC IVCC
(18)
VIO
(19)
C33I
VV33I
CVIO
CVCC
Only after PON until end of soft-start
(VVIO is in valid range >~3.1 … <~3.4V) and (VVCC is 3.3V or
(VVCC=5V and PFCTRL (0x20e) Bit 7 is set))
Otherwise
Switch B:
Switch to 1:
(VVIO is in valid range >~3.1 … <~3.4V) and (VVCC is 3.3V or
(VVCC=5V and PFCTRL (0x20e) Bit 7 is set))
Switch to 2: Otherwise
Switch C:
Open: When VVST is below VV20,off,abs or VV20,off,rel
VVST < VV20,off,abs,typ = VVST,SAVE,HL,typ+1 V=14V+1V=15V
VVST > VBUSP,mean- 6 V
Close: When VVST is above either VV20,on,abs and VV20,on,rel
VVST > VV20,on,abs,typ = VVST,SAVE,LH,abs,typ+1 V=15V+1V=16V
VVST > VVBUSP,mean- 5 V
VVCC
Option 1: VVIO supplied by VVCC
Option 2: VVIO supplied by external
If the ILOAD_SUM is higher then IBUSP,MAX the CVST discharges and the voltage VVST drops down.
Figure 6. Configurable Power Management
The supply blocks generates a 20V application voltage VV20, a variable storage voltage VST, a configurable
5V/3.3V output voltage V VCC and a 3.3V voltage V V33I used
by internal components of the E981.03. The voltages V V20
and V VCC can be used to supply external components.
The voltages V V33I is externally blocked but the strictly
recommendation is not use this pin for other supplies!
The voltage V VST is externally blocked. Usage of this voltage for external supplies is not recommended because it
disturb the autonomous power management of the IC!
To prevent a overload and a fast load slope on the bus
the power management of the IC generates a variable
storage voltage VVST. This voltage has a limited input current IREF and a limited slope of IREF. The maximum current
IREF and the maximum slope are configurable through SPI
or UART – Service. The value of V VST in normal operation
without an overload condition is VBUSP – V VST_DROP. The
power which is continuously useable is (VBUSP – VVST_DROP)
* IREF. If more power is used the CST is discharging, VVST
drops below VBUSP – VVST_DROP.
To prevent a unpredictable crash the supplies have the
following prioritization:
3rd : V20
Is generated by a linear voltage regulator out of the VST.
It is the supply for additional circuits and has the lowest priority. V20 is the first one drops down, to prevent
a dropping down of VCC with the consequence of a microcontroller reset. If a continuous overload is applied a
pulsing V20 is possible.
2nd : VCC
Is generated by a step down DC/DC converter and could
supply a microcontroller with its peripheral. The output
voltage is selectable 5V or 3.3V. The supply could deliver up to 30mA at 5V and 50mA at 3.3V. Before it drops
down V20 is switched of. If a continues overload condition is active V VST drops below VVST,SAVE,HL and the SAFE signal flags a overload condition before VCC drops down.
1st : V33I
Supplies the IC and is the last one which drops down.
Please refer the Application Note for more details.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
17/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
fXTAL,sync
e.g. from host
optional:
opto coupler
E981.03
1
XTAL
XTAL
Q1
CXTAL
EXTAL
CLK source
PLL
OSCRC
CEXTAL
CLKSPI
0
OSCQ
processor
CLKUART
sync
divider
DQ
CLKKNX
CLKMemory
CLKin
ACLK
crystal
Figure 7. Clock Generation
5.9 Clock System
The main clock is generated by an internal RC oscillator. An external clock reference / crystal can be used to
achieve a system clock accuracy of approx 0.05%.
Two different synchronization clocks are useable:
The sync - signal source could be a crystal oscillator (OSCQ) or an external VIO related digital clock on
XTAL(remark: absolute maximum rating “V”). The IC automatically detects the used mode and selects the correct internal signal path.
1) Crystal at fQ = 7.3728 MHz
• default configuration
• foot point capacitors are incl
In Analog Mode no crystal and no external clock are required. To increase the robustness to EMI the input XTAL
shall be connected to GND if not used.
2) Clock reference at f XTAL,sync= 126.562 Hz
• the crystal oscillator should be switched off
- EXT_Q to 1 in CLK_CTRL Register
6 Mode Depending Device Functions
V33I not ok
Hard
reset
V33I ok
Soft
start
Soft start
finished
Reset
condition
Voltage
VST
not ok
Save
Communication
Mode
Voltage
VST ok
Receive Trigger
Telegram
Met alarm
condition
End of alarm
telegram transmition
No condition
Trigger
Alarm
2)
1)
Figure 8. Device Modes
1) Trigger mode only available from Normal Mode
2) Alarm mode not available in Analog Mode see chapter 6.5 Analog Mode
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
18/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
6.1 Reset / Power Up-&Down Sequence
6.2 Overall
To ensure a stable function under all conditions the E981.03 supports several power up and power down scenarios.
The status of the configurable supply management/ monitoring can be queried via UART and digital SAVE pin at any
time.
Properties
Power Up Sequence
• Hard Reset Mode
• Start Up Mode
• Soft Reset
V33I not ok
external supply voltage switch on dependent on capacitance the Power Up Sequence stays longer in this mode
E981.03 will be set to soft reset value.
Power Down Sequence
• Save Mode
• Internal Reset
SAVE pin is active (low)
Hard Reset Mode
6.3 Undervoltage Condition
With falling bus voltage (data point 1) VST falls, too.
When V VST is below either V V20,off,abs or V V20,off,rel (whichever is higher) V20 is switched off (data point 2). V VST will
rise in typical case of high V20 load resulting in pulsed
activation of V20.
When V VST falls below V VST,save,HL the SAVE signal is activated to initiate the save routines of host processor
(data point 3). The DC/DC converter continues its normal operation until V VST falls below the minimum converter input voltage V VCC switch off and the V V33I input
(or output compare Figure 6 Configurable Power Management) make a switchover to V VST without a fail time
(data point 4). To avoid bus overload soft start phase
with bus current reduction is activated in case of active SAVE.
The RESET signal is activated when V VCC falls below the
threshold VRESET,HL (short after data point 4). If the BUSP
recovers now (data point 5) the IC come back without internal reset. SAVE will be deactivated, when V VST
achieves the value V VST,save,LH (data point 6). V VCC will be
activated, when V VST achieves the value V VST,VCCon (data
point 7). The IC is back on regular condition after V VST
achieves VBUSP - V VST_drop (data point 8). With the returning V VCC the V33I output (compare Figure 6 Configurable
Power Management) make a switchover to V VCC if V VCC
is in a valid range for 3.3V otherwise the Input of the
internal V33I regulator switch to V VST and the output of
V33I regulator switch to V V33I output. And finally V20 recovers.
The 2nd case with data point 10 to 14 is like the case before, but now the V VST drop deeper and finally E981.03
will be reset when V33I is lower than V33I, reset, act (data
point 14).
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
19/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
V
VBUSP
VVST,VCCon
VV20,off
VVST,SAVE,LH
VVST,SAVE,HL
VVST,VCCoff
VVST
VRESET_N,HL
VV33I,reset,act
VV20
VV33I
VVCC
2
10
t
11
I
SoftStart
Phase 2
IBUSP,MAX
IBUSP
IBUSP,SS
IBUSP,SSpu
IVST
7
8
t
IV33I
1
3
4
5
6
9
12
13
14
IV33I,VCC
IV33I,VST
SAVE_N
t
RESET_N
t
t
Figure 9. Undervoltage Condition
6.4 Communication Mode
CMOD = Busy
CMOD = Normal
Normal Mode
Bus Monitoring Mode
Analog Mode
CMOD = Bus
Monitoring
Busy Mode
Communication Mode
BS1 = 1
BS0 = 1
In figure 10 the four communication sub modes are
shown. The mode controlling registers can be modified
through UART or SPI commands.
For mode controlling registers see registers “DEVMODE”
und “CMODE”.
{optional}
Addressed Mode
Figure 10. E981.03 Communication Mode
Mode
Hard reset
Start-up
Soft reset
Analog
Normal
Bus monitor
Busy
Prioritization
1
2
3
4
5
5
4
The Prioritization is higher with a lower value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
20/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
6.5 Analog Mode
Activation
Analog Mode is activated if
• no higher prioritize mode is active (e.g. reset,
starup) and the baud rate select pins BS0 and BS1
have both high level
Deactivation
Analog Mode will be left for
• a higher prior mode (e.g. reset) if the activation
condition for that modes holds or
• Normal Mode if any of the baud rate select pins has
low level
Properties
• IC is fully functional (all supplies active)
• host UART interface is switched off.
No UART service is available
• bypass from KNX transceiver to UART transceiver
is active
• host SPI interface is active (may be switched off by
host processor)
comparable to 'Medium Attachment Unit (MAU)'
KNX standard: Volume 3 System Specifications: Physical Layer
General
6.6 Monitoring Mode
Activation
Monitor mode can be activated if
• no higher prioritize mode is active (e.g. reset,
startup, busy) and
• the CMODE register has the Bus monitor mode
value
The CMODE register can be modified by
• sending a U_ActivateBusmon service request via
UART or
• writing to the CMODE register via SPI or UART
Deactivation
Bus monitor mode can be left for any higher prioritize
mode (e.g. reset) if the activation condition for that
modes holds.
Switching to Busy Mode is not possible in Bus monitor
mode.
Properties
• The data link layer of the UART is in bus monitor
mode. Only the local L_Busmon service is available
for the host processor. All L_Data host to E981.03
services including L_Poll_Data service are not available and will be ignored.
• Each byte received on the KNX / EIB is sent to the
host as well as illegal control bytes and all acknowledge frames.
•
•
E981.03 is quiet (not sending) on the KNX bus.
Writing to the telegram buffers in Bus Monitoring
Mode is possible.
• The transmit frame buffer content will not be transmitted to the KNX bus in Bus Monitoring Mode.
• U_Reset.request clears the transmit buffer ready
flag (Flag READY in Register KNX_TR_BUF_STAT).
Leaving Bus Monitoring Mode without clearing this
flag results in transmission of the transmit buffer
content on KNX bus.
• Alarm telegrams can be transmitted even in Bus
Monitor Mode.
All received telegrams are sent byte-wise from E981.03
to the host.
Switching to Busy Mode is not allowed in Bus Monitoring Mode. Bus Monitoring Mode will be deactivated on
activation of Busy Mode.
It is recommended to activate and deactivate Bus Monitoring Mode using UART service requests. Activation
using direct register access will be described in an application note.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
21/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
6.7 Busy Mode
If the host controller is temporarily not able to receive
telegrams from the bus (e.g. due to no code execution
during flash erase), the Busy Mode can be estimated to
reject frames from the bus with BUSY acknowledges
independently from host acknowledge information in
KNX Busy Mode.
Activation
Busy Mode can be activated if
• no higher prior mode is active (e.g. reset, startup)
and
• the CMODE register has the Busy Mode value
Busy Mode activation during active Busy Mode is ignored. The Busy Mode duration is not prolongated.
Busy Mode activation in active Bus monitor mode is
not supported.
The CMODE register can be modified by
• sending a U_ActivateBusyMode service request via
UART or
• writing to the CMODE register via SPI or UART
Deactivation
Busy Mode can be left for
• any higher prior mode (e.g. reset) if the activation
condition for that modes holds or
• another CMODE controlled mode in case of CMODE
value change
•
the CMODE register can be modified by
- sending an U_Ackinfo or an U_ResetBusyMode
service request via UART or
- writing to the CMODE register via SPI or UART or
- internal logic when reaching timeout defined by
register BUSY_REG
- after timeout of defined in Register BUSY_REG.
Properties
• the IC is in full function (all supplies may be
switched on)
• KNX/ EIB, UART and SPI interfaces are active (dependent on their control register contents)
but E981.03 rejects following telegrams from the bus
with BUSY acknowledges
1) individually addressed telegrams with their destination address matching the individual address stored in
the registers (Addressed Mode only)
2) all group telegrams including broadcast
All other frames will not be acknowledged with BUSY.
All received telegrams are sent byte-wise from E981.03
to the host.
Remark
Busy Mode activation in active Bus Monitoring Mode is
not supported. The IC would switch from Bus Monitoring Mode to Busy Mode but BUSY acknowledging will
be delayed.
6.8 Normal Mode
Activation
The Normal Mode is active if
• no higher prioritized mode is active (e.g. reset,
start-up) and
• the CMOD register has the Normal Mode value
Deactivation
The Normal Mode will be left for
• any higher prior mode (e.g. reset) if the activation
condition for that modes holds or
• another CMOD controlled mode in case of CMOD
value change
Properties
• the IC is in full function (all supplies may be
switched on)
• KNX/ EIB, UART and SPI compatible interfaces are
active (dependent on their control register contents)
• UART is in normal (full) mode as long as UART is not
switched off by SPI access
• all UART services are available
All received telegrams are sent byte-wise from E981.03
to the host.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
22/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
6.9 Addressed Mode
Each KNX / EIB device has it's own unique individual address in a network. The E981.03 can be configured with
an individual node (physical) address. In this mode, the
processor load will be reduced by the autonomous KNX
protocol handling.
Activation
• after a complete address upload
• activated VALID bit in KNX_ADR_STAT register
Properties
• incoming Frames will be analyzed
• frames with a physical address will be answered
with an acknowledge automatically, if the stored
address matched
• all frames with a group address will be answered
automatically with an acknowledge.
• the host can suppress an automatic acknowledge
generation
Deactivation
• Reset / Power up Sequence
• deactivated VALID bit in KNX_ADR_STAT register
6.10 Trigger Functionality
Activation
• after upload of a trigger frame to E981.03 and upload of a trigger telegram mask to E981.03
• entering busy or Normal Mode.
Deactivation
• deactivated BUF bit in TRIGGER register.
Properties
WK pin is a tristate pin (tristate push pull) the E981.03
forces in Reset / Power up sequence WK to ground level.
E981.03 applies high level at pin WK after either
• a trigger telegram was received correctly or
• a broadcast telegram was received or
• an individually addressed telegram was received
•
with address equals node address (optional if configured)
the generated trigger pulse has a length of tTRIGGER,pw.
The received telegram can be read from telegram receive buffer until the next telegram arrives on the KNX/
EIB bus. Thus the host processor can get information
about trigger telegram contents after restarting the
node.
Attention: To be able to get the trigger message in all
conditions use the communication interface UART with
115.2KBd or SPI.
Trigger Function is not available in Bus Monitoring
Mode and Analog Mode.
6.11 Alarm Functionality
During any Communication Mode (but not in Analog
Mode) an alarm sequence can be used to signal improper node state to the system via KNX / EIB bus by sending an alarm telegram.
Activation
• after a complete alarm telegram upload and alarm
condition (SETVCC pin open or forced to V V33I/2 =
V VSETVCC,ALARM) is pending
Deactivation
• deactivated BUF bit in ALARM_STAT register
Properties
• an alarm telegram is send on KNX bus
• active RESET will be delay transmission, both alarm
telegram buffer and alarm state register are not
changed
The KNX/ EIB to UART receive path remains active during alarm sequence.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
23/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
6.12 Save Mode
To enlarge the V VCC operation time during low bus voltage supply the E981.03 switches some power devices off.
Properties
• KNX/ EIB transmitter is switched off
• The SAVE pin is active low
• KNX/ EIB receiver, UART host and SPI host
interfaces remain active
• V20 is switched off to allow longer VCC active times
7 Data Communication
The general communication between E981.03 and host is realized by using UART services. Furthermore the IC can
be configured via SPI interface.
7.1 UART-Service Host -> UART
Any service sent from host to E981.03 consists of one or more bytes. The first byte is the UART control field which
identifies the type of the requested service. The E981.03 can handle the following service requests:
Table 4. UART Service - Host to E981.03
UART control field
Service Name
Hex
U_Reset.request
0x01
U_State.request
0x02
U_ActivateBusmon
0x05
U_AckInformation
0x10
...
0x17
U_ProductID.request
0x20
U_ActivateBusyMode
0x21
U_ResetBusyMode
0x22
U_MxRstCnt
0x24
U_ActivateCRC
0x25
Remarks / Description
Bin
7
followed by n bytes
6 5 4 3 2 1 0
After receiving a U_Reset.
0000 0001 request the IC transits to
its soft reset state.
The IC answers an U_State.
request service by sending
0000 0010 its communication state
using State.response
service.
0000 0101
n: NACK
b: BUSY
0001 0nba a: ADDRESSED
0: inactive
1: active
0010 0000
The service activates the
0010 0001 KNX Busy Mode in the
E981.03
The host shall synchronize
0010 0010 its receiver before sending
the U_ResetBusyMode.
0010 0100
0010 0101
number of busy and nack
counts (in one byte)
- 0..7 times
B2 B1 B0
Busy
0
0
0
0
N2 N1 N0
Nack
KNX control field
Only with baud rates
19.200 or 115.200
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
24/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
UART control field
Service Name
U_SetAddress
Hex
0x28
Remarks / Description
Bin
0010 1000
Set KNX physical address
- individual KNX address
(high byte)
- individual KNX address
(low byte)
7
followed by n bytes
6 5 4 3 2 1 0
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
F1 F0
U_SetAlarmTelegramm
0x29
0010 1001
KNX control field which is
sent in alarm condition
R
1
frame Reformat peat
flag
P1 P2
0
0
0
0
priority
KNX control field
U_SetTriggerTelegram
0x2A
0010 1010
U_SetTriggerTelegramMask
0x2B
0010 1011
U_ReadReg.request
0x2E
0010 1110
U_WriteReg
0x2F
0010 1111
KNX control field which is
reason for a event detection
KNX control field mask
make it possible to detect a
event with several combinations
read access to the E981.03
internal memories
- address (high byte)
- address (low byte)
write access to the E981.03
internal memories
- address (high byte)
- address (low byte)
- data byte
U_L_DataStart
0x80
data telegram up1000 0000 Begin
load with KNX control field
U_L_DataContinue
0x81
...
0xBE
10xx xxxx
Upload data byte with index x
x: index (1 ... 62)
U_L_DataEnd
0x47
...
0x7F
01xx xxxx
Upload check sum with last
index x+1
x: last index+1 (7 ... 63)
U_PollingState
U_L_LongDataContinue
U_L_LongDataEnd
0xE0
...
0xEF
1110 xxxx
0xC0
0xC1
1100 000x
0xD0
0xD1
1101 000x
Upload polling state in to
the expecting slot x
x: slot number (0 ... 14)
- PollAddrHigh
- PollAddrLow
- State
Upload data byte with index x(bit 8 .. 0)
(1 ... 263)
x: MSB (bit 8) of index
- index x(bit 7 ... 0)
- data byte
Upload check sum with last
index x+1
(bit 8 .. 0) (1 ... 264)
x: MSB (bit 8) of index
- index x(bit 7 ... 0)
- data byte
F1 F0
R
1
P1 P2
KNX control field
M7 M6 M5 M4 M3 M2 M1 M0
0
0
0
0
0
0
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
F1 F0
R
1
P1 P0
0
0
KNX control field
D7 D6 D5 D4 D3 D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
It is calculated as logical NOT XOR
function over the individual bits of
the preceding bytes of the frame.
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
S7 S6 S5 S4 S3 S2 S1 S0
I7
I6
I5
I4
I3
I2
I1
I0
D7 D6 D5 D4 D3 D2 D1 D0
I7
I6
I5
I4
I3
I2
I1
I0
D7 D6 D5 D4 D3 D2 D1 D0
It is calculated as logical NOT XOR
function over the individual bits of
the preceding bytes of the frame.
An U_State.indication as a result of faulty UART control field is sent to the host as soon as possible in the following cases:
• protocol error flag set: undefined UART control field
• receiver error flag set: time between subsequent bytes of a service longer than the defined timeout
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
25/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
7.2 UART Service UART -> Host
Any service sent from E981.03 to host consists of one or more bytes. The first byte is the control field which identifies UART service. The E981.03 can handle the following three different UART services:
• KNX data link layer services are complete
• immediate acknowledge service include information about sending state
• UART control services are used to send requested information to the host controller or, in case of failures, a
state indication
Table 5. UART Service - E981.03 to Host
UART control field
Service Name
Hex
acknowledge
(BUSY and NACK)
0x00
Reset.indication
0x03
L_Data.confirm
(negative)
0x0B
acknowledge
(NACK)
0x0C
L_Data telegram
(L_ExtData frame)
0x10
0x14
0x18
0x1C
0x30
0x34
0x38
0x3C
Remarks / Description
Bin
0001 0000
0001 0100
0001 1000 First Byte (Control field of
0001 1100 an frame which is received
0011 0000 on KNX bus. 3)
0011 0100
0011 1000
0011 1100
0x8B
1000 1011
L_Data telegram
(L_Data frame)
0x90
0x94
0x98
0x9C
0xB0
0xB4
0xB8
0xBC
1001 0000
1001 0100
1001 1000
1001 1100
1011 0000
1011 0100
1011 1000
1011 1100
0xC0
acknowledge
(ACK)
0xCC
6
1 0
the preceding data teleis negative and busy
0000 0000 gram
acknowledged by a combination of receiving nodes. 1)
a Reset of the
0000 0011 indicate
E981.03
L_Data telegram negative
confirm:
the preceding data telwas either nega0000 1011 egram
tive acknowledged (either
NACK or BUSY) by receiving node(s) or not acknowledged at all.
the preceding data teleis negative acknowl0000 1100 gram
edged by any of the receiving nodes. 1)
L_Data.confirm
(positive)
acknowledge
(BUSY)
7
followed by
5 4 3 2
an extended data frame (L_
ExtData)
Each complete received
byte of the frame will be
transmitted. (End of Frame
indication will be a time gap
above tUART,IBG,RX = 2.5ms.) The
frame length is between 2
and 264 byte.
L_Data telegram positive
confirm:
the preceding data telegram was positive acknowledged (ACK) by the
receiving node
First Byte (Control field)
of an frame which is received on KNX bus. 3)
a data frame (L_Data)
Each complete received
byte of the frame will be
transmitted. (End of Frame
indication will be a time gap
above tUART,IBG,RX = 2.5ms.) The
frame length is between 2
and 64 byte.
the preceding data telis busy acknowl1100 0000 egram
edged by any of the receiving nodes. 1)
the preceding data telis positive acknowl1100 1100 egram
edged by all of the receiving nodes. 1)
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
26/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
UART control field
Service Name
Hex
Remarks / Description
Bin
L_PollData.request
0xF0
1111 0000
U_ReadReg.response
0xF1
1111 0001
U_ProductID.response
0xFE
1111 1110
abcd e111
State.response
State.indication
0x_7
and
0x_F
a: [SC]
b: [RE]
c: [TE]
d: [PE]
e: [TW]
7
6
followed by
5 4 3 2
1 0
a data frame (L_PollData.
request)
Each complete received
E981.03 is Poll_Master:
byte of the frame will be
uploaded L_PollData.retransmitted. (End of Frame
quest telegram
indication will be a time gap
above tUART,IBG,RX = 2.5ms.) The
frame length is 7 byte.
E981.03 is Poll_Slave:
write host to UART service
a Poll_Master can also be a U_PollingState with the corPoll_Slave
responding data
answer of U_ReadReg.reD7 D6 D5 D4 D3 D2 D1 D0
quest
answer of
I7 I6 I5 I4 I3 I2 I1 I0
U_ProductID.request
answer of
- U_State.request
- Indication of any state
chance:
[1] activation
[0] deactivation
see table below
1) note: all acknowledge frames are transmitted to the host in Bus Monitor Mode only
2) each L_Data telegram is transmitted completely to the host controller.
3) Each correctly received byte is immediately transferred to the host processor.
Table 6. E981.03 State Indication
Name
SC: slave collision
Bit is set in case of
- an other polling slave uses same slot (and has higher "priority")
- check-sum error in uploaded telegram
- parity error on UART
RE: receiver error
- frame error on UART (stop bit wrong)
- timeout violation between received service bytes
TE: transmitter error
- KNX transmitter sends "0", KNX receiver receives "1"
- illegal control byte in a service of telegram upload
- transmit telegram buffer overrun (upload during telegram transmission on KNX
PE: protocol error
bus)
- U_L_DataContinue service with index 0 or greater than 263
TW: temperature warning - temperature monitor signals too high temperature
7.3 SPI Logical Layer
Several bytes transferred subsequently during active
chip select form a SPI access. The first byte of a SPI access is the command byte. It contains the following information:
1. distinction between read and write
2. decision whether to transmit a xor check-sum or
3. read accesses information about short or long access
4. upper part of address
If the XOR bit in the command byte is set a check-sum is
calculated over the bytes of the access and transferred
as last byte in master --> slave and slave --> master directions. Thus both master and slave have information
about potentially incorrect transfer of command, address and data bytes.
In short form of read access the inter byte gap has to
be regarded between byte 2 (address) and byte 3 (data).
Otherwise the transmitted byte may not be correct.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
27/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Figure 11. SPI read accesses
Figure 12. SPI write accesses
Via SPI the host is able to read all addresses in the ranges 0x000 ... 0x27F and 0x300-3FF.
Write access is allowed in the address range 0x000 ... 0x17F and 0x200 to 0x27F, except:
• UART_STAT (0x2A0)
• UART_RX (0x2A3)
• UART_TX (0x2A4)
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
28/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
7.4 SPI Timing
Figure 13. SPI timing
8 Monitoring Functions
For measurement reasons the voltages are scaled to low voltage domain V33I. For scaling factors please read Table
Electrical Characteristics section Monitoring Functions.
For error calculations refer following tolerances: Divider, ADC, V33I Supply (tolerance depend on configuration and
Mode).
8.1 Analog Monitoring Functions
As described in section 5.5 AOUT the AOUT is an analog monitoring pin with a high impedance. Possible sources are:
• Temperature voltage
• Band gap voltage
• Bus voltage
8.2 Digital Monitoring Functions
ADC unit converts a configurable count of analog signals
to 8 bit resolution digital numbers. The signal conversion
time of a selected channel is typical 5 µs at a clock frequency of 4 MHz. The input channels are converted in a
continuously running conversion cycle. The ADC embedded system consists of:
8 bit SAR ADC Core
• high and low level reference generator
• conversion channel mux with input buffer
• channel sequence control unit
• result registers
In E981.03 ADC converts
• bus voltage VBUSP
• VST
• V20
• VCC
• VIO
• temperature (for details read chapter 8.3 Temperature Supervision)
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
29/51
QM-No.: 25DS0046E.03
ductor AG
KNX/ EIB TRANSCEIVER
E981.03
PRODUCTION DATA - JAN 15, 2015
E981.03
RAM
VST
0x397
ADC_VSTRES
V20
0x398
ADC_V20RES
VCC
VIO
VBUSP,mean
VTemp
M
U
X
0x399
ADC_VCCRES
A
D
0x39A
ADC_VIORES
0x39D
ADC_VBUSP_MEAN
VBUS,current
0x39E
ADC_TEMPRES
ACLK
INTERNAL
0x3B1
BUS_CURR_STAT
shift pattern
Figure 14. Digital Monitoring Functions
For measurement reasons the voltages are scaled to low
voltage domain V33I. The scaled voltages are converted
by the on chip ADC. For scaling factor look at chapter
Electrical Functions section Monitoring Functions. The
conversion results can be read by access to the result
registers. The VBUSP is an average value (tVBUSP(AV) = 5 ms).
ADC control cycle consists of two conversion cycles. The
bus voltage is converted in the first conversion cycle of
every control cycle. All other analog channels are con-
1/1
verted in the second slot of the control cycle. The resulting conversion rate is approximately
• 70 k samples for bus voltage
• 10 .. 20 k samples for all other sources
Note: From VST supervision an active SAVE_N signal is generated in case of falling supply voltages. This allows the host processor to stop the application program and to save its data before the reset pin RESET_N becomes active.
PRELIMINARY INFORMATION
Jan. 2012
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
30/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
8.3 Temperature Supervision
The temperature supervision is necessary for protection in case of high power dissipation in failure cases, for example
short circuit of supply outputs.
Figure 15. Over-temperature scenario
In case of over temperature
• the warning signal OTEMP for the host controller is
generated
• in Normal Mode a State.indication service is sent
to the host controller once at the beginning of over
temperature situation
In case of further temperature rising power consuming
blocks are switched off (shutoff phase):
• no further transmission at KNX (KNX transmitter is
disabled) in both Analog and Normal Modes
•
•
•
V20 and VCC supplies are switched off
SAVE is activated
RESET is activated when VCC is lower than the reset
limit – not depending on temperature.
When E981.03 temperature is lower than the limit:
• VCC and V20 supplies are switched on again
• SAVE_N is deactivated
• KNX transmitter is enabled
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
31/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
9 E981.03 security functions
The E981.03 has two security functions featuring an external digital interface.
SAVE
OTEMP
In case of an invalid VST voltage, the E981.03 activates the Save Mode to expand an active VCC time.
The SAVE pin gives this status of the Save Mode to an external device (host processor).
The temperature supervision is necessary for protection in case of higher power dissipation in failure
cases, for example short circuit of supply outputs. The OTEMP pin gives an over-temperature warning
10 RAM and register table
10.1 RAM table
Table 7. RAM address ranges
Address
0x000 ... 0x107
0x108 ... 0x109
0x10A ... 0x10B
0x10C
0x10D
0x10E ... 0x10F
0x110 ... 0x128
0x129 ... 0x12F
0x130 ... 0x148
0x149 ... 0x14F
0x150 ... 0x168
0x169 ... 0x16A
0x16B ... 0x16C
0x16D ... 0x1BF
0x1C0 ... 0x1FF
0x200 ... 0x2FF
0x300 ... 0x3FF
Bytes
264
2
2
1
1
2
25
7
25
7
25
2
2
82
64
256
256
Content
transmit frame buffer
individual KNX address of the KNX/EIB node
polling address 1)
polling slot 1)
polling data 1)
reserved for E981.03 internal use 2)
alarm telegram buffer
reserved for E981.03 internal use 2)
trigger telegram buffer
reserved for E981.03 internal use 2)
trigger mask buffer
length of alarm telegram
length of trigger telegram
reserved for E981.03 internal use 2)
received frame buffer 2)
registers table 3)
registers table 2) 3)
App. note
1) May be written by the host during a L_PollData.request frame.
2) Writing to these addresses is not allowed
3) Only allowed access to the named registers, see table below (register table).
10.2 Register table
Table 8. Register Table
Register Name
CMODE
RESET_CTRL
BUSY_REG
SPI_CTRL
SPI_PINS
UART_CTRL
CLK_CTRL
CLK_FAC0
CLK_FAC1
PS_CTRL
Address
0x200
0x201
0x202
0x205
0x206
0x208
0x209
0x20A
0x20B
0x20E
Description
communication mode
Reset control register
Busy Mode register
SPI control register
SPI pin access
UART control register
host clock control register
lower 8 bit of the clock divider register
upper 8 bit of the clock divider register
power supply control register
App. note
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
32/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Register Name
MAX_BUS_CURR
CURRENT_SLOPE
AOUT_CTRL
AOUT_SRC
ALARM_STAT
TRIGGER
KNX_TR_BUF_STAT
KNX_ADR_STAT
MAX_RST_CNT
KNX_TX_LEN1
KNX_TX_LEN0
ACK_HOST
POLL_CONF
UART_STAT
UART_RX
UART_TX
DEVMODE
RES_SOURCE
PINS
SPI_STAT
PROD_ID
ADC_VSTRES
ADC_V20RES
ADC_VCCRES
ADC_VIORES
ADC_VBUSP_MEAN
ADC_TEMPRES
BUS_CURR_STAT
PS_STAT
ACK_KNXIC
Address
0x20F
0x210
0x211
0x212
0x213
0x214
0x215
0x216
0x217
0x218
0x219
0x21A
0x21B
0x2A0
0x2A3
0x2A4
0x300
0x302
0x306
0x310
0x371
0x397
0x398
0x399
0x39A
0x39D
0x39E
0x3B0
0x3BF
0x3E9
Description
set the maximum DC bus current
set up the maximum bus current slope
AOUT control register
AOUT source select register
alarm status register
trigger register
status of the transmit telegram buffer
status of the address
number of retries in case of not acknowledge and busy
length of the frame in the transmit buffer (bits 8)
length of the frame in the transmit buffer (bits 7 ... 0)
acknowledge information from host
status of a polling slave
UART status register
previous received byte
UART transmitter data register
active device mode
binary coded reset source
mode control and baud rate select pin values
SPI status register
Product ID (read only)
ADC result for the (scaled) voltage on VST
ADC result for the (scaled) voltage on V20
ADC result for the (scaled) voltage on pin VCC
ADC result for the (scaled) voltage on VIO
mean value for VBUSP voltage
ADC result temperature scan
actual value of DC bus current
power supply status register
acknowledge information from E981.03
Address
0x302
Description
binary coded reset source
App. note
Table 9. Reset register
Register Name
RES_SOURCE
back to Table 8 Register Table
Table 10. Binary coded reset source
RES_SOURCE
content
hard reset value
soft reset value
access
bit description
MSB
0
0
LSB
SRC0
0
0
SRC2
SRC1
0
0
0
0
value of reset source
R 1)
R 1)
R 1)
R 1)
R 1)
R 1)
R 1)
R 1)
SRC : binary coded reset source (see following table for valid values, reset value is “startup
reset” value)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
33/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 11. Reset source
RES_SOURCE value
0x00
0x01
0x02
0x03
0x04
0x05
0x07
reset source
start-up reset (this is the only reset source that corresponds to register hard reset values)
the previous reset was initiated by an externally driven active RESET
the previous reset was initiated by a Reset.request service
the previous reset was initiated by a write access to the RESET_CTRL register
E981.03 intern watchdog
the previous reset was initiated by a low VCC
E981.03 internal error
Table 12. Busy timeout register
Register Name
BUSY_REG
Address
0x202
Description
Busy Mode register
back to Table 8 Register Table
Table 13. BUSY_REG
BUSY_REG
content
hard reset value
soft reset value
access
MSB
T7
0
0
R/W 1)
T6
0
0
R/W 1)
T5
0
0
R/W 1)
T4
1
1
R/W 1)
T3
1
1
R/W 1)
T2
0
0
R/W 1)
T1
1
1
R/W 1)
LSB
T0
0
0
R/W 1)
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Table 14. Timeout examples
BUSY_REG value
255
175
26 (default)
0
timeout value
1.02 s
0.7 s
0.1 s
0s
Timebase is 4 ms per digit.
Table 15. Device mode registers
Register Name
DEVMODE
CMODE
PROD_ID
PINS
Address
0x300
0x200
0x371
0x306
Description
active device mode
communication mode
IC product ID (read only)
mode control and baud rate select pin values
Register CMODE is used for IC control and is intended to be written by host controller. Register DEVMODE reflects
the state of the IC.
back to Table 8 Register Table
Table 16. Active device mode
DEVMODE
content
hard reset value
soft reset value
access
bit description
MSB
LSB
M7
M6
M5
M4
M3
M2
M1
M0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
R 1)
R 1)
R 1)
R 1)
R 1)
R 1)
R 1)
R 1)
This register holds the value of the currently active mode. This mode may differ from the
communication mode selected by the CMODE register for several reasons. Especially during mode changes the DEVMODE register reflects the currently active mode.
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
34/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
back to Table 8 Register Table
Table 17. Communication mode
CMODE
content
hard reset value
soft reset value
access
MSB
0
R 1)
0
R 1)
0
R 1)
0
R 1)
0
R 1)
CM2
1
1
R/W 1)
CM1
0
0
R/W 1)
LSB
CM0
0
0
R/W 1)
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Table 18. E981.03 mode register values
1
3
4
5
Register
CMODE
don't care
don't care
don't care
don't care
Register
DEVMODE
0x00
0x01
0x02
0x03
Normal
5
0x04
0x04
Bus monitor
Busy
5
4
0x05
0x06
0x05
0x06
Mode
Priority
hard reset
start-up
soft reset
Analog
Remarks
reset state is active if internal power supply is down
0x04 is the reset value of register CMODE
Normal Mode is active in case of CMODE values that
do not define an other communication mode.
back to Table 8 Register Table
Table 19. IC product ID (read only)
PROD_ID
content
hard reset value
soft reset value
access
bit description
MSB
ID7
0
ID6
0
ID5
0
ID4
ID3
0
0
never changed
R 1)
R 1)
R 1)
R 1)
R 1)
product ID will be changed in case of feature change.
ID2
1
ID1
0
LSB
ID0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
The state of several pins are accessible via register address PINS. The read value changes with pin voltages without respect to IC state.
back to Table 8 Register Table
Table 20. Mode control and baud rate select pin values
PINS
content
access
bit description
MSB
SETVCC
R
SETVCC
BS1 BS0 ALARM
WK RESET SAVE LSB
BS1
BS0
ALARM
0
WK
RESET
SAVE
R
R
R
R
R
R
R
: this bits reflects the value of the SETVCC pin information
: this bits reflects the value of the BS1 pin
: this bits reflects the value of the BS0 pin
: this bits reflects the value of the ALARM condition (SETVCC=VSETVCC,ALARM)
: this bits reflects the value of the WK pin
: this bits reflects the value of the RESET pin
: this bits reflects the value of the SAVE pin
1) Access via UART service and SPI possible.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
35/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 21. Overview trigger register
Register Name
TRIGGER
TRIGGER_BUF
TRIGGER_MASK
TRIGGER_LEN1
TRIGGER_LEN0
Address
0x214
0x130 ...
0x148
0x150 ...
0x168
0x16B
0x16C
Description
wake-up register
25 byte trigger telegram buffer
25 byte trigger telegram mask buffer
length of trigger telegram (high byte)
length of trigger telegram (low byte)
back to Table 8 Register Table
Table 22. Trigger register
TRIGGER
content
hard reset value
soft reset value
access
bit description
MSB
LSB
EVENT
EN_OUT MASK_BUF BUF
0
0
0
0
0
1
0
0
1
0
0
R 1)
R 1)
R 1)
R 1)
R/W 1)
R/W 1)
R/W 1)
R/W 1)
EVENT :
"1": a trigger event was detected
"0": no trigger event detected
The EVENT bit is initially cleared. If the IC receives a triggering telegram on KNX bus it acknowledges this telegram by sending a BUSY acknowledge on KNX bus and sets the EVENT
bit. Any further incoming triggering telegram will not be BUSY acknowledged by the IC as
long as the host does not clear the EVENT bit by writing a "0".
Acknowledge generation based on auto address mode is not affected by the EVENT bit
state.
EN_OUT :
"1": enable output stage (pull down disabled)
"0": disable output stage (output tri-state, pull down enabled)
MASK_BUF :
"1": the trigger mask buffer was written completely
"0": the trigger buffer was not written completely yet
BUF :
"1": the trigger buffer was written completely
"0": the trigger buffer was not written completely yet
Bits MASK_BUF and BUF are set by the E981.03 after successful upload using host UART
interface. They may be written by the host directly.
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Table 23. Alarm state register
Register Name
ALARM_STAT
ALARM_BUF
ALARM_LEN1
ALARM_LEN0
Address
0x213
0x110...
0x128
0x169
0x16A
Description
alarm status register
25 byte alarm telegram buffer
length of alarm telegram (high byte)
length of alarm telegram (low byte)
The alarm state register is used to signal the state of the alarm functionality and to control sending of the alarm
telegram. Reading the register is allowed any time using any interface. Writing to the register is only recommended
to clear the SENT bit and allow resending of the alarm telegram. A successful alarm telegram transmission is confirmed to the host by sending a L_Data.confirm service on host UART interface.
back to Table 8 Register Table
Table 24. Alarm status register Power supply registers
ALARM_STAT
content
hard reset value
MSB
0
0
0
0
0
PEND
0
BUF
0
LSB
SENT
0
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
36/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
ALARM_STAT
soft reset value
external access
bit description
MSB
LSB
1)
1)
1)
1)
1)
1)
1)
R
R
R
R
R
R/(W)
R/W
R/W 1)
PEND :
"1": an alarm transmission is either pending, under transmission or sent
(e.g. in case of alarm pin activation during transmission of a "normal" telegram)
"0": no alarm is pending or sent
Writing to the register using UART U_WriteReg service clears the PEND bit independent of
the value that is written to that bit.
Writing using SPI shall not change the value of the PEND bit which is not controlled by the
E981.03 but is in the responsibility of the host controller.
BUF :
"1": the alarm buffer was written completely
"0": the alarm buffer was not written completely yet
The bit is set by the E981.03 after successful upload using host UART interface services.
It may be written by the host directly to activate alarm functionality without using upload
procedure via host UART interface or after uploading a alarm telegramm by SPI. The alarm
telegram buffer is not checked for correctness in this case.
SENT :
"1": an alarm telegram was sent
"0": no alarm telegram was sent
The bit is set after sending of an alarm telegram.
It can be reset by the host processor by writing a "0". The host should never write an “1” to
the SENT bit. If the bit SENT is set no alarm telegram is transmitted regardless of the alarm
condition. An ongoing alarm telegram transmission on EIB bus (states AlarmTelegramWait
and AlarmTelegramTransmit) is not interrupted by writing a “0” to the SENT bit.
A reading by UART Interface delete this bit. A SPI read do not delete this and the User have
to do this.
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard reset the
register is reset to the hard reset value.
Table 25. Power supply registers
Register Name
PS_CTRL
PS_STAT
Address
0x20E
0x3BF
Description
power supply control register
power supply status register
back to Table 8 Register Table
Table 26. Power supply control register
PS_CTRL
content
hard reset value
soft reset value
external access
bit description
MSB
LSB
VIO_SW
VCC_ON1 1) VCC_ON0 1) V20_ON1 1) V20_ON0 1)
0
0
1
1
0
0
1
1
0
1
1
1
1
R/W 2)
R
R/W 2)
R/W 2)
R
R
R/W 2)
R/W 2)
VCC_ON :
“00”: VCC is to switch off 1)
“01”,”10”,”11”: VCC is to switch on
The bits do not reflect the state of the VCC supply.
The actual state is reflected by PS_STAT register.
V20_ON :
"00": V20 is to switch off 1)
“01”,”10”,”11”: V20 is to switch on
The bits do not reflect the state of the V20 supply.
The actual state is reflected by PS_STAT register.
VIO_SW:
When VCC = 5 V and VIO = 3.3 V: write “1” to VIO_SW bit to reduce power consumption of
E981.03. In all other cases this bit has no effect.
1) The bits VCC_ON and V20_ON are doubled for safety reasons. VCC and V20 supplies are switched off only if both ON bits have
value "0". Otherwise the supply is switched on and the ON bits are set to value "1" by the E981.03 itself.
2) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
37/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
In case VCC supply is switched off and either register
PS_CTRL access or U_Reset.request UART service are
used to switch VCC on the following will occur:
• VCC is switched on
• VCC is below its reset limit
• RESET will be activated
• soft reset will be performed
Remark:
As a result the E981.03 will restart with soft reset in
these cases. Especially V20 will be switched on too.
back to Table 8 Register Table
Table 27. Power supply status register
PS_STAT
content
hard reset value
soft reset value
access
bit description
MSB
0
0
0
0
0
0
- (not reset)
R 1)
R 1)
R 1)
R 1)
R 1)
R 1)
VCC_ON : this bit represents the actual state of the VCC supply.
"1": VCC is switched on.
"0": VCC is switched off.
V20_ON : this bit represents the actual state of the V20 supply.
"1": V20 is switched on.
"0": V20 is switched off.
VCC_ON
0
LSB
V20_ON
0
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Table 28. Bus current source registers
Register Name
MAX_BUS_CURR
BUS_CURR_STAT
CURRENT_SLOPE
Address
0x20F
0x3B0
0x210
Description
set the maximum DC bus current
actual ADC value of DC bus current
set up the maximum bus current slope
back to Table 8 Register Table
Table 29. Maximum DC bus current
MAX_BUS_CURR
content
hard reset value
soft reset value
access
bit description
MSB
MAXCURR7 MAXCURR6 1
1
0
0
1
1
R/W 1)
R/W 1)
R 1)
R 1)
MAXCURR : maximum DC bus current selection
0
R 1)
0
R 1)
0
R 1)
LSB
0
R 1)
1) For write access read the remarks of every bit carefully. In case of hard or soft reset the register is reset to the hard reset value
or soft reset value respectively.
Table 30. Maximum DC bus current selection
MAXCURR7
MAXCURR6
1
1
0
0
0
1
0
1
Maximum DC bus current
typ
max
12 mA
12.6 mA
18 mA
18.9 mA
24 mA
25.2 mA
30 mA
31.5 mA
min
11.4 mA
17.1 mA
22.8 mA
28.5 mA
back to Table 8 Register Table
Table 31. Actual value of DC bus current
BUS_CURR_STAT
content
hard reset value
soft reset value
access
MSB
CURR7
0
CURR6
0
CURR5
0
R 1)
R 1)
R 1)
CURR4
CURR3
0
0
- (not reset)
R 1)
R 1)
CURR2
0
CURR1
0
LSB
CURR0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
38/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
back to Table 8 Register Table
Table 32. Set up the maximum bus current slope
CURRENT_SLOPE
content
hard reset value
soft reset value
access
bit description
MSB
0
0
0
R
R
R
see following table for SL values.
0
R
0
R
0
R
SL1
0
0
R/W 1)
LSB
SL0
1
1
R/W 1)
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset the
register is reset to the hard reset value or soft reset value respectively.
Table 33. Bus current slope selection values
SL1
0
0
1
1
SL0
0
1
0
1
Slope limitation mode, mA/ms
0.25
0.5 (default)
1.25
2.5
Table 34. Clock registersSet up the maximum bus current slope
Register Name
CLK_CTRL
CLK_FAC0
CLK_FAC1
Address
0x209
0x20A
0x20B
Description
host clock control register
lower 8 bit of the clock divider register
upper 8 bit of the clock divider register
back to Table 8 Register Table
Table 35. Host clock control register
CLK_CTRL
content
hard reset value
soft reset value
access
bit description
MSB
0
-
0
R
0
R
0
R
0
R
EXT_Q
0
0
W 1)
0
R
LSB
ENQ
1
1
R/W 1)
R
EXT_Q :
„1“: XTAL is used as clock input from external clock source, EXTAL is left open and internal
capacitors are disconnected
„0“: a quartz is connected to XTAL and EXTAL
ENQ :
„1“: crystal or clock enabled
„0“: crystal or clock disabled and XTAL grounded useful e.g. for analog mode
1) For write access read the remarks of every bit carefully. In case of soft and hard reset the state machine writes mentioned values.
back to Table 8 Register Table
Table 36. Clock divider register (low part)
CLK_FAC0
content
hard reset value
soft reset value
access
MSB
F7
0
0
R/W 1)
F6
0
0
R/W 1)
F5
1
1
R/W 1)
F4
1
1
R/W 1)
F3
0
0
R/W 1)
F2
0
0
R/W 1)
F1
0
0
R/W 1)
LSB
F0
0
0
R/W 1)
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset the
register is reset to the hard reset value or soft reset value respectively.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
39/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
back to Table 8 Register Table
Table 37. Clock divider register (high part)
CLK_FAC1
content
hard reset value
soft reset value
access
MSB
F7
1
1
R/W 1)
F6
1
1
R/W 1)
F5
1
1
R/W 1)
F4
0
0
R/W 1)
F3
0
0
R/W 1)
F2
0
0
R/W 1)
F1
1
1
R/W 1)
LSB
F0
1
1
R/W 1)
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset the
register is reset to the hard reset value or soft reset value respectively.
The clock divider has a total reset value of 58.254.
When using other quartz frequencies than 7.3728 MHz
the value has to be changed to
DQ = fQuartz / 126.76532 Hz - 1
Before changing the clock divider register values the
timing unit of the E981.03 runs with the accuracy of
the RC oscillator. Communication using the host UART
interface has to take that accuracy into account. Specified UART and KNX communication parameter ranges
are not guaranteed before adaption of the clock divider
register.
The PLL has a tolerance of approximately 10% to input
frequency for locking. As a result quartz frequencies
in the range between fQuartz, nom – 10% and fQuartz, nom +
10% may be regarded as the nominal quartz frequency resulting in incorrect timing at the KNX and UART
interfaces. It is highly recommended not to use quartz
frequencies in that range or to change the CLK_FAC registers using SPI after each reset of the E981.03.
Individual Node Address
Each KNX device has a unique individual address in a
network. The individual address is a 2 byte value that
consists of an 8 bit subnetwork address and an 8 bit
device address. The device address may have any value
between 0 and 255.
The individual node address can be uploaded to the
E981.03 from host using
• service request U_SetAddress on UART interface
(see chapter 7.1 UART-Service Host -> UART ) or writing to the appropriate RAM addresses (see chapter
7.3 SPI Logical Layer for details) and validate the address by writing to the KNX_ADR_STAT register.
After upload address evaluation in E981.03 is activated.
After both hard and soft reset the address evaluation of
E981.03 is deactivated.
The device address shall be unique within a sub-network.
The device address in E981.03 is not initialized to a defined value.
KNX subnet adress
high byte (0x108)
MSB
A3
LSB
A2
A1
A0
L3
area adress
KNX subnet adress
low byte (0x109)
D7
D6
D5
L2
L1
L0
line adress
D4
D3
D2
D1
D0
device adress
Figure 16. KNX individual address
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
40/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 38. KNX address register
Register Name
KNX_ADR_STAT
KNX_ADR_HIGH
KNX_ADR_LOW
Address
0x216
0x108
0x109
Description
status of the address
KNX subnet adress high byte
KNX subnet adress low byte
back to Table 8 Register Table
Table 39. Status of the KNX address
KNX_ADR_STAT
content
hard reset value
soft reset value
access
bit description
MSB
LSB
VALID
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R/W 1)
VALID :
"1": the stored address is valid
"0": the stored address is invalid
the bit is set by the host by writing to the register or by using U_SetAddress service request
it is reset. If the Address is configured by SPI the User have to set this bit too.
- by the host by writing to the register and
- during soft reset
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Table 40. Telegram transmission register
Register Name
MAX_RST_CNT
KNX_TR_BUF_STAT
KNX_TX_LEN1
KNX_TX_LEN0
KNX_TR_BUF
KNX_RC_BUF
Address
0x217
0x215
0x218
0x219
0x000 …
0x107
0x1C0…
0x1FF
Description
number of retries in case of not acknowledge and busy
status of the transmit telegram buffer
length of the frame in the transmit buffer (bit 8) 1)
length of the frame in the transmit buffer (bits 7 ... 0) 1)
264 Byte transmit buffer
64 Byte receiving frame buffer
1) The length of the frame gives the number of bytes stored in the frame transmit buffer including all frame overhead.
back to Table 8 Register Table
Table 41. MAX_RST_CNT
MAX_RST_CNT
content
hard reset value
soft reset value
access
bit description
MSB
LSB
BUSY2
BUSY1
BUSY0
NACK2
NACK1
NACK0
0
0
1
1
0
0
1
1
0
1
1
0
1
1
R
R/W 1)
R/W 1)
R/W 1)
R
R/W 1)
R/W 1)
R/W 1)
ACK : number of retries in case of not acknowledge (either NACK on no ack frame)
BUSY : number of retries in case of busy (BUSY or simultaneously BUSY and NACK)
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
41/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
back to Table 8 Register Table
Table 42. Status of the transmit telegram buffer
KNX_TR_BUF_
STAT
content
hard reset value
soft reset value
access
bit description
MSB
LSB
READY
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R/W 1)
READY :
"1": the RAM buffer is ready for transmission
"0": the RAM buffer is not yet ready for transmission
The bit is set by either the host processor or internal logic and reset after successful transmission. A manual write is only necessary if the frame is uploaded by SPI
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset
the register is reset to the hard reset value or soft reset value respectively.
Table 43. Length of the frame in the transmit buffer (bit 8)
KNX_TX_LEN1
content
hard reset value
soft reset value
access
MSB
0
R
0
R
0
R
back to Table 8 Register Table
0
R
0
R
0
R
0
R
LSB
LEN8
0
0
R/W 1)
1) Access via UART service and SPI possible. If a frame is uploaded by SPI the host controller have to set the LEN bits. In case of hard
or soft reset the register is reset to the hard reset value or soft reset value respectively.
Table 44. Length of the frame in the transmit buffer (bits 7 ... 0)
KNX_TX_LEN0
content
hard reset value
soft reset value
access
MSB
LEN7
0
0
R/W 1)
LEN6
0
0
R/W 1)
LEN5
0
0
R/W 1)
LEN4
0
0
R/W 1)
back to Table 8 Register Table
LEN3
0
0
R/W 1)
LEN2
0
0
R/W 1)
LEN1
0
0
R/W 1)
LSB
LEN0
0
0
R/W 1)
1) Access via UART service and SPI possible. If a frame is uploaded by SPI the host controller have to set the LEN bits. In case of hard
or soft reset the register is reset to the hard reset value or soft reset value respectively.
Table 45. Acknowledge state register
Register Name
ACK_HOST
ACK_KNXIC
Address
0x21A
0x3E9
Description
acknowledge information from host
acknowledge information from E981.03
back to Table 8 Register Table
Table 46. Acknowledge information from host
ACK_HOST
content
hard reset value
soft reset value
external access
bit description
MSB
RX_ACK NACK
BUSY
0
0
0
0
0
0
0
1)
1)
R
R
R
R
R/W
R/W
R/W 1)
RX_ACK:„1": acknowledge information from host for frame currently received
"0": no acknowledge information from host for frame currently received
Bit is set by host access via SPI or UART and reset by internal logic at
start of a frame on KNX line.
NACK : not acknowledge flag
BUSY : busy flag
ADR : addressed flag
all flags are reset by the E981.03 at the beginning of a received frame.
LSB
ADR
0
R/W 1)
1) Access via UART service and SPI possible. If a frame is uploaded by SPI the host controller have to set the LEN bits. In case of hard
reset the register is reset to the hard reset value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
42/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 47. Acknowledge information used by E981.03 for previous received telegram
ACK_KNXIC
content
hard reset value
soft reset value
access
bit description
back to Table 8 Register Table
MSB
NACK
BUSY
0
0
0
0
0
0
0
1)
R
R
R
R
R
R
R 1)
NACK : not acknowledge flag
BUSY : busy flag
ADR : addressed flag
all flags are reset by the E981.03 at the beginning of a received frame.
LSB
ADR
0
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
POLLconf
Register POLL_CONF is completely handled by E981.03 when using host UART interface for communication. When
using host SPI interface the host has to handle POLL_CONF register itself.
Table 48. Polling slave register
Register Name
POLL_CONF
POLL_ADR_HIGH
POLL_ADR_LOW
POLL_SLOT
POLL_DATA
Address
0x21B
0x10A
0x10B
0x10C
0x10D
Description
status of a polling slave
high byte
low byte
polling slot
polling data
back to Table 8 Register Table
Table 49. Status of a polling slave
POLL_CONF
content
hard reset value
soft reset value
access
bit description
MSB
LSB
VALID
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R/W 1)
VALID :
"1": the data in the polling slave RAM area is valid for transmission
"0": the data in the polling slave RAM area is invalid
This bit is set by either the U_PollingState UART service request or direct writing to the
register by the host. If the configuration is don by SPI the User have to set this bit too.
It is reset by the E981.03 at the begin of a L_PollData.request frame reception on KNX bus
(KNX control field 0xF0 was received).
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Table 50. UART registers
Register Name
UART_CTRL
UART_STAT
Address
0x208
0x2A0
Description
UART control register
UART status register
The UART_CTRL register is used to control properties of the UART by host processor software. It is not modified by
the E981.03. The UART_STAT register is used to signal UART state to the host processor software. The host is not
allowed to modify the UART_STAT register.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
43/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
back to Table 8 Register Table
Table 51. UART control register
UART_CTRL
content
hard reset value
soft reset value
access
bit description
MSB
LSB
TXDEL
CRC
ON1
ON0
0
0
0
0
0
0
1
1
0
0
1
1
1)
1)
1)
R
R
R
R/W
R/W
R
R/W
R/W 1)
TXDEL:
"1": activate constant transmission delay between end of UART service and start of transmission on KNX bus
"0": transmission delay between end of UART service and start of transmission on EIB bus
is variable (faster)
CRC:
"1": the UART CRC is enabled (not available in analog mode and not at 9.6kBd)
"0": the UART CRC is disabled
ON1 :
ON0 :
"-1" or "1-": the UART is switched on
"00": the UART is switched off
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
1. The bit ON is doubled for safety reasons.
UART interface is switched off only if both ON bits have value "0".
Otherwise UART interface is switched on and the ON bits are set to value "1" by the E981.03 itself.
2. Bits ON1 and ON0 can not be modified using U_WriteReg service request.
Use SPI to switch UART on and off.
Bits TXDEL and CRC can be modified using either U_WriteReg service request or SPI.
3. Bit CRC is used to activate CRC calculation on UART to host communication. CRC is not used in case of KNX
bus monitor mode or 9.6 k baud UART speed, independent on the value of the CRC bit of register UART_CTRL.
back to Table 8 Register Table
Table 52. UART status register
UART_STAT
content
hard reset value
soft reset value
access
bit description
MSB
0
0
0
0
0
- (not reset)
R
R
0
0
LSB
ON
0
R
R
R
R
R
R 1)
ON :
"1": the UART interface is currently on
"0": the UART interface is currently off. This may be because of Analog Mode activation or
because of a host write access to the UART_CTRL register
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
UART Byte Receiver
The parity bit of every received byte from the host will be checked by the E981.03. Errors will be reported to the
host controller by sending a State.indication service with receiver error flag set to the host as soon as possible.
The UART receiver accepts frames up to a maximum baud rate deviation of 3%. The signals can be transmitted
without a break.
Table 53. UART receiver registers
Register Name
UART_RX
Address
0x2A3
Description
previous received byte
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
44/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
back to Table 8 Register Table
Table 54. Previous received byte
UART_RX
content
hard reset value
soft reset value
access
MSB
D7
0
D6
0
D5
0
D4
0
R 1)
R 1)
R 1)
R 1)
D3
0
-(not reset)
R 1)
D2
0
D1
0
LSB
D0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
UART Byte Transmitter
TXD idle-level in any other mode but KNX Analog Mode is "1".
The UART transmitter has a baud rate deviation of less than 1% during byte frame transmission. Subsequent
bytes may be transmitted without a break.
Table 55. UART transmitter registers
Register Name
UART_TX
Address
0x2A4
Description
UART transmitter data register
back to Table 8 Register Table
Table 56. UART transmitter data register
UART_TX
content
hard reset value
soft reset value
access
MSB
D7
0
D6
0
D5
0
D4
0
R 1)
R 1)
R 1)
R 1)
D3
0
-(not reset)
R 1)
D2
0
D1
0
LSB
D0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Table 57. SPI registers
Register Name
SPI_CTRL
SPI_STAT
SPI_PINS
Address
0x205
0x310
0x206
Description
SPI control register
SPI status register
SPI pin access
Table 58. SPI control register
SPI_CTRL
content
hard reset value
soft reset value
access
bit description
back to Table 8 Register Table
MSB
0
0
0
R
R
R
ON1 :
ON0 :
"-1" or "1-": the SPI is switched on
"00": the SPI is switched off
0
R
0
R
0
R
ON1
1
1
R/W 1)
LSB
ON0
1
1
R/W 1)
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Table 59. SPI status register
SPI_STAT
content
hard reset value
soft reset value
access
bit description
MSB
0
back to Table 8 Register Table
0
0
R
R
R
XERR : XOR error detected
0
0
- (not reset)
R
R
0
0
LSB
XERR
0
R
R
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
45/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Register SPI_PINS is used for SPI pin value accesses. Bits SCS and SCK reflect the state of IC pins in any case of operation mode.
When SPI is switched off (bits ON1 and ON0 of register SPI_CTRL are both „0“) MOSI and MISO are used as general purpose input / output of the E981.03 that can be controlled by host processor. Pins SCS and SCK can be
used as general purpose input pin.
Table 60. SPI pin access
SPI_PINS
content
hard reset value
soft reset value
SPI switched on
SPI switched off
access
bit description
back to Table 8 Register Table
MSB
-
-
0
0
R
R
MOSIEN MISOEN MISO
MOSI
SCSN
register bits reflect always the state of the physical pins
defining reset values makes no sense
0
1
pin values
R/W 1)
R/W 1)
R/W 1)
R/W 1)
R 1)
LSB
SCK
R 1)
MOSIEN : this bit set the pin direction 0 means high ohmic input 1 mean output.
MISOEN : this bit set the pin direction 0 means high ohmic input 1 mean output.
(enable for tri-state output)
MISO : if the pin is used as a input this bit reflects the input state and
if the pin is used as a output the user write the output level.
MOSI : if the pin is used as a input this bit reflects the input state and
if the pin is used as a output the user write the output level.
SCSN : this bit reflects the input state of the SCS pin
SCK : this bit reflects the input state of the SCK pin
1) Access via UART service and SPI possible.
Table 61. RESET_CTRL
Register Name
RESET_CTRL
Address
0x201
Description
RESET_CTRL control register
Table 62. RESET_CTRL control register
RESET_CTRL
content
hard reset value
soft reset value
access
bit description
back to Table 8 Register Table
MSB
LSB
RST
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R/W 1)
RST :
Writing a “1” to bit RST results in a transition to soft reset state. Writing to the RESET_CTRL
register is the way to initiate a soft reset via either host SPI or host UART interfaces.
1) Access via UART service and SPI possible. In case of hard or soft reset the register is reset to the hard reset value or soft reset
value respectively.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
46/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Digital monitoring registers
The measurement values are scaled to limit them below the supply voltage (V33I) of the ADC and analog to digital converted. For scaling values look at chapter Electrical Charecteristics section Monitoring Functions.
Table 63. Voltage supervision registers
Register Name
Address
Description
ADC_VBUSP_MEAN 0x39D
mean value for VBUSP voltage
1 LSB=VBUSP,mean*scaleVBUSP,ADC/V33I +- 5%
ADC_VSTRES
0x397
ADC result for the (scaled) voltage on VST
1 LSB=V VST*scaleVST,ADC/V33I +- 5%
ADC_V20RES
0x398
ADC result for the (scaled) voltage on V20
1 LSB=V20*scaleV20,ADC/V33I +- 5%
ADC_VCCRES
0x399
ADC result for the (scaled) voltage on pin VCC
1 LSB=VCC*scaleVCC,ADC/V33I +- 5%
ADC_VIORES
0x39A
ADC result for the (scaled) voltage on VIO
1 LSB=VIO*scaleVIO,ADC/V33I +- 5%
Table 64. Mean value for VBUSP voltage
ADC_VBUSP_MEAN
content
hard reset value
soft reset value
access
back to Table 8 Register Table
MSB
V7
0
V6
0
V5
0
R 1)
R 1)
R 1)
V4
0
V3
0
- (not reset)
R 1)
R 1)
V2
0
V1
0
LSB
V0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Table 65. ADC result for the (scaled) voltage on VST
ADC_VSTRES
content
hard reset value
soft reset value
access
MSB
V7
0
V6
0
V5
0
R 1)
R 1)
R 1)
back to Table 8 Register Table
V4
0
V3
0
- (not reset)
R 1)
R 1)
V2
0
V1
0
LSB
V0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Table 66. ADC result for the (scaled) voltage on V20
ADC_V20RES
content
hard reset value
soft reset value
access
MSB
V7
0
V6
0
V5
0
R 1)
R 1)
R 1)
back to Table 8 Register Table
V4
0
V3
0
- (not reset)
R 1)
R 1)
V2
0
V1
0
LSB
V0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Table 67. ADC result for the (scaled) voltage on pin VCC
ADC_VCCRES
content
hard reset value
soft reset value
access
MSB
V7
0
V6
0
V5
0
R 1)
R 1)
R 1)
back to Table 8 Register Table
V4
0
V3
0
- (not reset)
R 1)
R 1)
V2
0
V1
0
LSB
V0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
47/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 68. ADC result for the (scaled) voltage on VIO
ADC_VIORES
content
hard reset value
soft reset value
access
MSB
V7
0
V6
0
V5
0
R 1)
R 1)
R 1)
back to Table 8 Register Table
V4
0
V3
0
- (not reset)
R 1)
R 1)
V2
0
V1
0
LSB
V0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Temperature Supervision Register
The temperature supervision is necessary for protection in case of high power dissipation in failure cases, for example short circuit of supply outputs. For details read chapter 8.3 Temperature Supervision.
Table 69. Temperature supervision registers
Register Name
ADC_TEMPRES
Address
0x39E
Description
ADC result temperature scan
Table 70. ADC result temperature scan
ADC_TEMPRES
content
hard reset value
soft reset value
access
back to Table 8 Register Table
MSB
T7
0
T6
0
T5
0
R 1)
R 1)
R 1)
T4
0
T3
0
- (not reset)
R 1)
R 1)
T2
0
T1
0
LSB
T0
0
R 1)
R 1)
R 1)
1) Access via UART service and SPI possible. In case of hard reset the register is reset to the hard reset value.
Analog Monitor Pin
The pin AOUT is used to monitor several voltages. For details read chapter 5.5 AOUT.
Table 71. Analog monitor register
Register Name
AOUT_SRC
AOUT_CTRL
Address
0x212
0x211
Description
AOUT source select register
AOUT control register
Table 72. Source selector register for multiplexer on analog monitor pin
AOUT_SRC
content
hard reset value
soft reset value
access
MSB
0
R
0
R
0
R
0
R
back to Table 8 Register Table
0
R
0
R
S1
1
1
R/W 1)
LSB
S0
0
0
R/W 1)
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset
the register is reset to the hard reset value or soft reset value respectively.
Table 73. Analog monitor multiplexer sources
AOUT_SRC value
0x00
0x01
0x02
0x03
Source
none; output is high impedance
temperature voltage
VBUSP / 8 or VBUSP / 12 depending on AOUT_CTRL register setting
bandgap voltage
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
48/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
Table 74. Bus voltage divider selection register
AOUT_CTRL
content
hard reset value
soft reset value
access
MSB
0
R
0
R
back to Table 8 Register Table
0
R
0
R
0
R
0
R
0
R
LSB
DIV
1
1
R/W 1)
1) Access via UART service and SPI possible. For write access read the remarks of every bit carefully. In case of hard or soft reset the
register is reset to the hard reset value or soft reset value respectively.
Table 75. Analog BUSP voltage multiplexer
AOUT_CTRL value
Source
0
VBUSP / 12
1
VBUSP / 8
In case of VIO = 3.3 V and bus voltage divider selection of VBUSP / 12 pin voltage AOUT will not be higher than VIO
even if VBUSP / 12 is higher.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
49/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
PACKAGE OUTLINE SPECIFICATION
11 Package Information
Date : 05.01.2012
The E981.03 is available in a Pb free, RoHS compliant, QFN32L7 plastic package according to JEDEC MO-220 K, variant VKKC-2. The package is classified
to Moisture
3 (MSL
3) according to JEDEC J-STD-020D with a
32 Lead
QuadSensitivity
Flat NonLevel
Leaded
Package
QM-No.: 08SP0677.04
Author:
ASto
soldering
peak temperature
of (260±5) °C.
(QFN32L7)
Package Outline and Dimensions are according JEDEC MO-220 K, variant VKKC-2
Description
Symbol
min
mm
typ
max
min
inch
typ
max
Package height
A
0.80
0.90
1.00
0.031
0.035
0.039
Stand off
A1
0.00
0.02
0.05
0.000
0.00079
0.002
Thickness of terminal leads, including lead finish
A3
--
0.20 REF
--
--
0.0079 REF
--
Width of terminal leads
b
0.25
0.30
0.35
0.010
0.012
0.014
Package length / width
D/E
--
7.00 BSC
--
--
0.276 BSC
-0.229
D2 / E2
5.50
5.65
5.80
0.217
0.223
Lead pitch
e
--
0.65 BSC
--
--
0.026 BSC
--
Length of terminal for soldering to substrate
L
0.35
0.40
0.45
0.014
0.016
0.018
Number of terminal positions
N
Length / width of exposed pad
32
32
Note: the mm values are valid, the inch values contains rounding errors
Note 1: for assembler specific pin1 identification please see QM-document 08SP0363.xx (Pin 1 Specification)
Page 1 of 1
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
50/51
QM-No.: 25DS0046E.03
E981.03
KNX/ EIB TRANSCEIVER
PRODUCTION DATA - JAN 15, 2015
WARNING – Life Support Applications Policy
Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products,
to observe standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor
AG Product could cause loss of human life, body injury or damage to property. In the development of your design,
please ensure that Elmos Semiconductor AG products are used within specified operating ranges as set forth in
the most recent product specifications.
General Disclaimer
Information furnished by Elmos Semiconductor AG is believed to be accurate and reliable. However, no responsibility is assumed by Elmos Semiconductor AG for its use, nor for any infringements of patents or other rights of third
parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Elmos Semiconductor AG. Elmos Semiconductor AG reserves the right to make changes to this document
or the products contained therein without prior notice, to improve performance, reliability, or manufacturability.
Application Disclaimer
Circuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as
means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is believed
to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does
not convey to the purchaser of the semiconductor devices described any license under the patent rights of Elmos
Semiconductor AG or others.
Contact Information
Headquarters
Elmos Semiconductor AG
Heinrich-Hertz-Str. 1 • D-44227 Dortmund (Germany)
: +492317549100
: [email protected]
Sales and Application Support Office North America
Elmos NA. Inc.
32255 Northwestern Highway • Suite 220 Farmington Hills
MI 48334 (USA)
: +12488653200
: [email protected]
Sales and Application Support Office China
Elmos Semiconductor Technology (Shanghai) Co., Ltd.
Unit 16B, 16F Zhao Feng World Trade Building,
No. 369 Jiang Su Road, Chang Ning District,
Shanghai, PR China, 200050
: +86216210 0908
: [email protected]
Sales and Application Support Office Korea
Elmos Korea
B-1007, U-Space 2, #670 Daewangpangyo-ro,
Sampyoung-dong, Bunddang-gu, Sungnam-si
Kyounggi-do 463-400 Korea
: +82317141131
: [email protected]
Sales and Application Support Office Japan
Elmos Japan K.K.
BR Shibaura N Bldg. 7F
3-20-9 Shibaura, Minato-ku,
Tokyo 108-0023 Japan
: +81334517101
: [email protected]
Sales and Application Support Office Singapore
Elmos Semiconductor Singapore Pte Ltd.
3A International Business Park
#09-13 ICON@IBP • 609935 Singapore
: +65 6908 1261
: [email protected]
 : www.elmos.com
© Elmos Semiconductor AG, 2014. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor AG, is prohibited.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
51/51
QM-No.: 25DS0046E.03