43 CY7C441 CY7C443 Clocked 512 x 9, 2K x 9 FIFOs Features lutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. • High-speed, low-power, first-in first-out (FIFO) memories • 512 x 9 (CY7C441) • 2,048 x 9 (CY7C443) • 0.65 micron CMOS for optimum speed/power • High-speed 83-MHz operation (12 ns read/write cycle time) • Low power — ICC=70 mA • Fully asynchronous and simultaneous read and write operation • Empty, Almost Empty, and Almost Full status flags • TTL compatible • Parity generation/checking • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Center power and ground pins for reduced noise • Width Expansion Capability • Available in PLCC packages Both FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a free-running read clock (CKR) and a read enable pin (ENR). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are acceptable. Functional Description The CY7C441 and CY7C443 clocked FIFOs provide two status flag pins (F1 and F2). These flags are decoded to determine one of four states: Empty, Almost Empty, Intermediate, and Almost Full (Table 1). The flags are synchronous; i.e., change state relative to either the read clock (CKR) or the write clock (CKW). The Empty and Almost Empty states are updated exclusively by the CKR while Almost Full is updated exclusively by CKW. The synchronous flag architecture guarantees that the flags maintain their status for some minimum time. The CY7C441 and CY7C443 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a 512 word by 9 bit memory array, while the CY7C443 has a 2048 word by 9 bit memory array. These devices provide so- The CY7C441 and the CY7C443 use center power and ground for reduced noise. Both configurations are fabricated using an advanced.65µm CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by reliable layout techniques and guard rings. Logic Block Diagram CKW ENW Pin Configuration D0– 8 PLCC Top View D 1 D 2 D 3 NCD 4 D 5 D 6 INPUT REGISTER FLAG LOGIC WRITE CONTROL LOGIC WRITE POINTER MR RAM ARRAY 512 x 9 2048x 9 F1 F2 READ POINTER RESET LOGIC D0 ENW CKW VCC VSS F1 F2 NC Q0 READ CONTROL LOGIC 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 7C441 25 7C443 24 23 22 21 14 15 16 17 1819 20 Q1 Q 2 Q 3 NC Q 4 Q5 Q 6 D7 D8 NC MR VSS CKR ENR Q8 Q7 C441-2 OUTPUT REGISTER CKR C441-1 Q0– 8 Cypress Semiconductor Corporation Document #: 38-06032 Rev. *A ENR • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 26, 2002 CY7C441 CY7C443 Selection Guide 7C441–12 7C443–12 7C441–14 7C443–14 7C441–20 7C443–20 7C441–30 7C443–30 83.3 71.4 50 33.3 Maximum Access Time (ns) 9 10 15 20 Minimum Cycle Time (ns) 12 14 20 30 Minimum Clock HIGH Time (ns) 5 6.5 9 12 Minimum Clock LOW Time (ns) 5 6.5 9 12 Minimum Data or Enable Set-Up (ns) 4 5 6 7 Minimum Data or Enable Hold (ns) 0 0 0 0 Maximum Frequency (MHz) Maximum Flag Delay (ns) Maximum Current (mA) 9 10 15 20 Commercial 140 140 120 100 Military/Industrial 150 150 130 110 Selection Guide (continued) CY7C441 CY7C443 Density 512 x 9 2,048 x 9 Package 32-Pin PLCC 32-Pin PLCC Maximum Ratings[1](Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage............................................ –3.0V to +7.0V Output Current into Outputs (LOW) .............................20 mA Latch-Up Current.................................................... > 200 mA Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% Industrial Pin Definitions I/O Description D0–8 Signal Name I Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge) writes data (D0 – D8) into the FIFO’s memory Q0–8 O Data Outputs: when the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0 – Q8) out of the FIFO’s memory ENW I Enable Write: enables the CKW input ENR I Enable Read: enables the CKR input CKW I Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and updates the Almost Full flag state CKR I Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW and updates the Almost Empty and Empty flag states F1 O Flag 1: is used in conjunction with Flag 2 to decode which state the FIFO is in (see Table 1) F2 O Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in (see Table 1) MR I Master Reset: resets the device to an empty condition Document #: 38-06032 Rev. *A Page 2 of 15 CY7C441 CY7C443 Electrical Characteristics Over the Operating Range 7C441–12 7C443–12 Parameter Description Test Conditions 7C441–14 7C443–14 7C441–20 7C443–20 7C441–30 7C443–30 Min. Max. Min. Max. Min. Max. Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC 2.2 VCC 2.2 VCC VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 –0.5 IIX Input Leakage Current VCC = Max., GND < VI < VCC –10 +10 –10 +10 –10 IOS[2] Output Short Circuit Current VCC = Max., VOUT = GND –90 ICC1[3] Operating Current VCC = Max., IOUT = 0 mA Com’l 140 140 120 100 mA Mil/Ind 150 150 130 110 mA VCC = Max., IOUT = 0 mA Com’l 70 70 70 70 mA Mil/Ind 80 80 80 80 mA VCC = Max., IOUT = 0 mA Com’l 30 30 30 30 mA Mil/Ind 30 30 30 30 mA ICC2 [4] Operating Current ISB[5] Standby Current 2.4 2.4 0.4 2.4 2.4 0.4 –90 0.4 V 0.4 V 2.2 VCC V 0.8 –0.5 0.8 V +10 –10 +10 µA –90 –90 mA Capacitance[6] Parameter Description CIN Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF AC Test Loads and Waveform[7,8] R1 500Ω 5V ALL INPUT PULSES OUTPUT 3.0V CL INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT 200Ω OUTPUT R2 333Ω GND ≤ 3 ns C441-4 90% 10% 90% 10% ≤ 3 ns C441-5 2V Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Test no more than one output at a time and do not test any output for more than one second. 3. Input signals switch from 0V to 3V with a rise/fall time of 3 ns or less, clocks and clock enables switch at maximum frequency (fMAX), while data inputs switch at fMAX/2. Outputs are unloaded. 4. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 5. All inputs signals are connected to VCC. All outputs are unloaded. Read and write clocks switch at maximum frequency (fMAX). 6. Tested initially and after any design or process changes that may affect these parameters. 7. CL = 30 pF for all AC parameters. 8. All AC measurements are referenced to 1.5V. Document #: 38-06032 Rev. *A Page 3 of 15 CY7C441 CY7C443 Switching Characteristics Over the Operating Range[9] 7C441–12 7C443–12 Parameter Description Min. Max. 7C441–14 7C443–14 Min. Max. 7C441–20 7C443–20 Min. Max. 7C441–30 7C443–30 Min. Max. Unit tCKW Write Clock Cycle 12 14 20 30 ns tCKR Read Clock Cycle 12 14 20 30 ns tCKH Clock HIGH 5 6.5 9 12 ns tCKL Clock LOW 5 6.5 9 12 ns tA[10] Data Access Time tOH Previous Output Data Hold After Read HIGH 0 0 0 0 ns tFH Previous Flag Hold After Read/Write HIGH 0 0 0 0 ns tSD Data Set-Up 4 5 6 7 ns tHD Data Hold 0 0 0 0 ns tSEN Enable Set-Up 4 5 6 7 ns tHEN Enable Hold 0 0 0 0 ns tFD tSKEW1 9 Flag Delay [11] 10 9 15 10 20 15 20 ns ns Opposite Clock After Clock 0 0 0 0 ns tSKEW2[12] Opposite Clock Before Clock 12 14 20 30 ns tPMR Master Reset Pulse Width (MR LOW) 12 14 20 30 ns tSCMR Last Valid Clock LOW Set-Up to MR LOW 0 0 0 0 ns tOHMR Data Hold From MR LOW 0 0 0 0 ns tMRR Master Reset Recovery (MR HIGH Set-Up to First Enabled Write/Read) 12 14 20 30 ns tMRF MR HIGH to Flags Valid 12 14 20 30 ns tAMR MR HIGH to Data Outputs LOW 12 14 20 30 ns Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in the AC Test Loads and Waveforms and capacitance as in Note 7, unless otherwise specified. 10. Access time includes all data outputs switching simultaneously. 11. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full flag. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Almost Full flag, CKR is the clock for Empty and Almost Empty flags. 12. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEW2 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. See Note 11 for definition of clock and opposite clock. Document #: 38-06032 Rev. *A Page 4 of 15 CY7C441 CY7C443 Switching Waveforms Write Clock Timing Diagram tCKW tCKH CKW tCKL ENABLED WRITE tSD D0 – 8 DISABLED WRITE tHD VALID DATA IN tSEN tHEN ENW tSEN tFH tHEN F1 tFH tFD tFD C441-6 Read Clock Timing Diagram tCKR tCKH CKR ENABLED READ DISABLED READ tA tOH Q0 – 8 tCKL PREVIOUS WORD NEW WORD tSEN tHEN ENR tSEN tFH tHEN F1, F2 tFD Document #: 38-06032 Rev. *A tFH tFD C441-7 Page 5 of 15 CY7C441 CY7C443 Switching Waveforms (continued) Master Reset Timing Diagram[13, 14, 15, 16] tPMR MR tSCMR tMRR tSCMR tMRR CKW ENW CKR ENR tOHMR Q0 – 8 tAMR ALL DATA OUTPUTS LOW VALID DATA tMRF F1, F2 C441-8 [17, 18, 19] Read to Empty Timing Diagram COUNT 3 2 1 0 1 1 (no change) 0 LATENT CYCLE CKR R1 ENABLED READ R2 ENABLED READ R3 ENABLED READ R4 FLAG UPDATE READ R5 ENABLED READ ENR tSKEW1 W1 ENABLED WRITE CKW ENW tSKEW2 LOW tFD tFD tFD F1 F2 LOW C441-10 Notes: 13. ENW or CKW must be inactive while MR is LOW. 14. ENR or CKR must be inactive while MR is LOW. 15. All data outputs (Q0 – 8) go LOW as a result of the rising edge of MR. 16. In this example, Q0 – 8 will remain valid until tOHMR if the first read shown did not occur or if the read occurred soon enough such that the valid data was caused by it. 17. “Count” is the number of words in the FIFO. 18. CKR is clock and CKW is opposite clock. 19. R3 updates the flags to the Empty state by bringing F1 LOW. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating flag status. But because W1 occurs greater than tSKEW2 before R4, R4 includes W1 in the flag update and therefore updates the FIFO to the Almost Empty state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status, regardless of the state of ENR. It does not change the count or the FIFO’s data outputs. Document #: 38-06032 Rev. *A Page 6 of 15 CY7C441 CY7C443 Switching Waveforms (continued) [17, 18, 20] Read to Empty Timing Diagram with Free-Running Clocks COUNT 1 CKR 0 1 R1 ENABLED READ R2 IGNORED READ 0 LATENT CYCLE R3 IGNORED READ tSKEW2 tSKEW2 R4 FLAG UPDATE READ R5 ENABLED READ R6 IGNORED READ ENR tSKEW1 W1 CKW tSKEW2 W2 W3 ENABLED WRITE W4 W5 W6 ENW tFD tFD tFD F F11 F2 F2 LOW C441-9 Read to Almost Empty Timing Diagram with Free-Running Clocks[17, 18] COUNT 17 CKR 16 17 R1 ENABLED READ 18 R2 17 R3 16 R4 ENABLED READ 15 R5 ENABLED READ R6 ENABLED READ ENR tSKEW1 CKW tSKEW2 W2 ENABLED WRITE W1 W3 ENABLED WRITE W4 W5 W6 ENW F1 HIGH tFD tFD tFD F2 C441-11 Note: 20. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than tSKEW2 before R4, R4 includes W3 in the flag update. Document #: 38-06032 Rev. *A Page 7 of 15 CY7C441 CY7C443 Switching Waveforms (continued) Read to Almost Empty Timing Diagram with Read Flag Update Cycle and Free-Running Clocks[17, 18, 21, 22] 18 (no change) COUNT CKR 17 16 17 R1 ENABLED READ FLAG UPDATE CYCLE 18 R2 R4 FLAG UPDATE READ R3 17 16 15 R5 ENABLED READ R6 ENABLED READ R7 ENABLED READ W5 W6 W7 ENR tSKEW1 CKW W1 tSKEW2 W2 ENABLED WRITE W3 ENABLED WRITE W4 ENW F1 HIGH tFD tFD tFD F2 C441-12 [17, 23, 24, 25, 26] Write to Almost Full Timing Diagram COUNT 2030 [494] CKW 2031 [495] W1 ENABLED WRITE 2032 [496] 2031 [495] 2030 [494] W2 ENABLED WRITE 2031 [497] 2032 [498] 2033 [497] 2030 [494] 2031 [495] 2032 [498] W3 ENABLED WRITE W4 ENABLED WRITE W5 ENABLED WRITE FLAG UPDATE ENW LOW tSKEW1 CKR ENR tSKEW2 R1 ENABLED READ R2 ENABLED READ LOW tFD tFD tFD tFD F1 F2 HIGH C441-14 Notes: 21. R4 only updates the flag status. It does not affect the count because ENR is HIGH. 22. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 Á18; two enabled writes: W2, W3) before a read (R4) can update flags to the Intermediate state. 23. CKW is clock and CKR is opposite clock. 24. Count = 2032 indicates Almost Full for CY7C443 and count = 496 indicates Almost Full for CY7C441. Values for the CY7C441 count are shown in brackets. 25. The dashed lines show W3 as flag update write rather than an enabled write because ENW is deasserted. 26. W2 updates the flags to the Almost Full state by bringing F1 LOW. Because R1 occurs greater than tSKEW1 after W2, W2 does not recognize R1 when updating the flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does not have to be enabled to update flags. Document #: 38-06032 Rev. *A Page 8 of 15 CY7C441 CY7C443 Switching Waveforms (continued) Write to Almost Full COUNT 2031 [495] CKW Timing Diagram with Free-Running Clocks 2032 [496] 2030 [494] 2031 [495] W1 ENABLED WRITE W2 [17, 23, 24] 2032 [496] 2031 [495] W3 2033 [497] W4 ENABLED WRITE W5 ENABLED WRITE R4 R5 W6 ENABLED WRITE ENW tSKEW1 R1 CKR tSKEW2 R2 ENABLED READ R3 ENABLED READ R6 ENR tFD tFD tFD F1 F2 HIGH C441-13 Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks[17, 23, 24, 27] COUNT 2031 [495] CKW 2032 [496] 2030 [494] 2031 [495] W1 ENABLED WRITE 2030 (no change) [494] FLAG UPDATE CYCLE W2 W3 W4 FLAG UPDATE WRITE 2031 [495] W5 ENABLED WRITE 2032 [496] 2033 [497] W6 ENABLED WRITE W7 ENABLED WRITE ENW tSKEW1 CKR tSKEW2 R2 ENABLED READ R1 R3 ENABLED READ R4 R5 R6 R7 ENR tFD tFD tFD F1 F2 HIGH C441-15 Note: 27. When making the transition from Almost Full to Intermediate, the count must decrease by two (2032 Á 2030; two enabled reads: R2, R3) before a write (W4) can update flags to Intermediate state. Architecture Resetting the FIFO The CY7C441/443 consist of an array of 512/2048 words of 9 bits each (implemented by an array of dual-port RAM cells), a read pointer, a write pointer, control signals (CKR, CKW, ENR, ENW, MR), and flags (F1, F2). Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the Empty condition signified by both flags F1 and F2 being LOW. All data outputs (Q0–8) go LOW at the rising edge of MR. In order for the FIFO to reset to its default state, a falling edge must occur on MR and the user must not read or write while MR is LOW (unless Document #: 38-06032 Rev. *A Page 9 of 15 CY7C441 CY7C443 ENR and ENW are HIGH). Upon completion of the Master Reset cycle, all data outputs will go LOW tAMR after MR is deasserted. F1 and F2 are guaranteed to be valid tMRF after MR is taken HIGH. FIFO Operation When the ENW signal is active (LOW), data on the D0–8 pins is written into the FIFO on each rising edge of the CKW signal. Similarly, when the ENR signal is active, data in the FIFO memory will be presented on the Q0–8 outputs. New data will be presented on each rising edge of CKR while ENR is active. ENR must set up tSEN before CKR for it to be a valid read. ENW must occur tSEN before CKW for it to be a valid write. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0–8 outputs even after additional reads occur. Flag Operation The CY7C441/3 provide two flags, F1 and F2, which are used to decode four FIFO states (see Table 1). All flags are synchronous, meaning that the change of states is relative to one of the clocks (CKR or CKW, as appropriate; see Figure 1). The synchronous architecture guarantees some minimum valid time for the flags. The Empty and Almost Empty flag states are exclusively updated by each rising edge of the read clock (CKR). For example, when the FIFO contains 1 word, the next read (rising edge of CKR while ENR=LOW) causes the F1 and F2 pins to output a state signifying the Empty condition. The Almost Full flag is updated exclusively by the write clock (CKW). For example, if the CY7C443 FIFO contains 2031 words (2032 words or greater indicates Almost Full in the CY7C443), the next write (rising edge of CKW while ENW=LOW) causes the F1 and F2 pins to output the Almost Full state. Table 1. Flag Truth Table State CY7C441 Number of Words in FIFO CY7C443 Number of Words in FIFO F1 F2 0 0 Empty 0 0 1 0 Almost Empty 1 – 16 1 – 16 1 1 Intermediate Range 17 – 495 17 – 2031 0 1 Almost Full or Full 496 – 512 2032 – 2048 E CKR F1 AF CKW F2 AE CKR INTERNAL LOGIC PINS C441-16 Figure 1. Flag Logic Diagram Flag Operation (continued) Since the flags denoting emptiness (Empty, Almost Empty) are only updated by CKR and the Almost Full flag is only updated by the CKW, careful attention must be given to the flag operation. The user must be aware that if a flag boundary (Empty, Almost Empty, and Almost Full) is crossed due to an operation from a clock that the flag is not synchronized to (i.e.,CKR does not effect Almost Full), a flag update is necessary to represent the FIFO’s new state. This signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty and Almost Empty flags; CKR is the opposite clock for the Almost Full flag). Until the flag update cycle is executed, the synchronous flags do not show the true state of the FIFO. For example, if 2,040 Document #: 38-06032 Rev. *A writes are performed to an empty CY7C443 without a single read, F1 and F2 will still exhibit an Empty flag. This is because F2 is exclusively updated by the CKR, therefore, a single read (flag update cycle) is necessary to update flags to Almost Full state. It should be noted that this flag update read does not require ENR = LOW, so a free-running read clock will initiate the flag update cycle. When updating the flags, the CY7C441/443 decide whether or not the opposite clock was recognized when a clock updates the flag. For example, if a write occurs at least tSKEW1 after a read when updating the Empty flag, the write is guaranteed not to be included when CKR updates the flag. If a write occurs at least tSKEW2 before a read, the write is guaranteed to be included when CKR updates the flag. If a write occurs within tSKEW1/tSKEW2 after or before CKR, then the decision of Page 10 of 15 CY7C441 CY7C443 whether or not to include the write when the flag is updated by CKR is arbitrary. The update cycle for non-boundary flags (Almost Empty, Almost Full) is different from that used to update the boundary flag (Empty). Both operations are described below. Boundary Flag (Empty) The Empty flag is synchronized to the CKR signal. The Empty flag can only be updated by a clock pulse on the CKR pin. An empty FIFO that is written to will be described with an Empty flag state until a clock pulse is presented on the CKR pin. When making the transition from Empty to Almost Empty (or Empty to Intermediate or Empty to Almost Full), a clock cycle on the CKR is necessary to update the flags to the current state. Such a state (flags displaying empty even though data has been written to the FIFO) would require two read cycles to read data out of FIFO. The first read serves only to update the flags to the Almost Empty, Intermediate, or Almost Full state, and the second read outputs the data. This first read cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number of words in FIFO). It simply deasserts the Empty flag. The flags are updated regardless of the ENR state. Therefore the update occurs even when ENR is deasserted (HIGH) so that a valid read is not necessary to update the flags to correctly describe the FIFO. With a free-running clock connected to CKR, the flag updates with each cycle. Table 2 shows sample operations that update the Empty flag. Although a Full flag is not supplied externally on the CY7C441/CY7C443, a Full flag exists internally. The operation of the FIFO at the Full boundary is analogous to its operation at the Empty boundary. See the text section “Boundary Flags (Full)” in the CY7C451/CY7C453 datasheet. Non-Boundary Flags (Almost Empty, Almost Full) The flag status pins, F1 and F2, exhibit the Almost Empty status when both the CY7C441 and the CY7C443 contain 16 words or less. The Almost Full Flag becomes active when the FIFO contains 16 or less empty locations. The CY7C441 becomes Almost Full when it contains 496 words. The CY7C443 becomes Almost Full when it contains 2032 words. The Almost Empty flag (like the Empty flag) is synchronous to the CKR signal, whereas the Almost Full flag is synchronous to the CKW signal. Non-boundary flags employ flag update cycles similar to the boundary flag latent cycles in order to update the FIFO state. For example, if the FIFO just reaches the Almost Document #: 38-06032 Rev. *A Empty state (16 words) and then two words are written, a read clock (CKR) will be required to update the flags to the Intermediate state. However, unlike the boundary (Empty) flag’s update cycle, the state of the enable pin (ENR in this case) affects the operation. Therefore, ENR set-up (tSEN) and hold (tHEN) times must be met. If ENR is asserted (ENR=LOW) during the latent cycle, the count and data update in addition to F1 and F2. If ENR is not active (ENR=1) during the flag update cycle, only the flag is updated. The same principles apply for updating the flags when a transition from the Almost Full to the Intermediate state occurs. If the CY7C443 just reaches the Almost Full state (2032 words) and then two words are read, a write clock (CKW) will be required to update the flag to the Intermediate state. If ENW is LOW during the flag update cycle, the count and data update in addition to the flags. If ENW is HIGH, only the flag is updated. Therefore, ENW set-up (tSEN) and hold (tHEN) times must be met. Tables 3 and 4 show examples for a sequence of operations that affect the Almost Empty and Almost Full flags, respectively. Width Expansion The CY7C441/3 can be expanded in width to provide word width greater than 9 in increments of 9. During width expansion mode, all control inputs are common. When the FIFO is being read near the Empty boundary, it is important to note that both sets of flags should be checked to see if they have been updated to the Not Empty condition on all devices. Checking all sets of flags is critical so that data is not read from the FIFOs “staggered” by one clock cycle. This situation could occur when the first write to an empty FIFO and a read are very close together. If the read occurs less than tSKEW2 after the first write to two width expanded devices (A and B), device A may go Almost Empty (read recognized as flag update) while device B stays Empty (read ignored).The first write occurs because a read within tSKEW2 of the first write is only guaranteed to be either recognized or ignored, but which of the two is not guaranteed. The next read cycle outputs the first half of the first word on device A while device B updates its flags to Almost Empty. Subsequent reads will continue to output “staggered” data assuming more data has been written to the FIFOs. In the width expansion configuration, any of the devices’ flags may be monitored for the composite Almost Full status. Page 11 of 15 CY7C441 CY7C443 Table 2. Empty Flag Operation Example [28] Status Before Operation Status After Operation F1 F2 Number of Words in FIFO F1 F2 Number of Words in FIFO Empty 0 0 0 Write (ENW = LOW) Empty 0 0 1 Write Empty 0 0 1 Write (ENW = LOW) Empty 0 0 2 Write Empty 0 0 2 Read (ENR = HIGH) AE 1 0 2 Flag Update AE 1 0 2 Read (ENR = LOW) AE 1 0 1 Read AE 1 0 1 Read (ENR = LOW) Empty 0 0 0 Read (Transition for Almost Empty to Empty) Empty 0 0 0 Write (ENW = LOW) Empty 0 0 1 Write Empty 0 0 1 Read (ENR = X) AE 1 0 1 Flag Update AE 1 0 1 Read (ENR = LOW) Empty 0 0 0 Read (Transition from Almost Empty to Empty) Current State of FIFO Operation Next State of FIFO Table 3. Almost Empty Flag Operation Example[28] Status Before Operation Current State of FIFO F1 F2 Number of Words in FIFO AE 1 0 16 Write (ENW = LOW) AE 1 0 17 AE 1 0 Intermediate 1 AE 1 Comments Status After Operation F1 F2 Number of Words in FIFO AE 1 0 17 Write Write (ENW = LOW) AE 1 0 18 Write 18 Read (ENR = LOW) Intermediate 1 1 17 Flag Update and Read 1 17 Read (ENR = LOW) AE 1 0 16 Read (Transition from Intermediate to Almost Empty) 0 16 Read (ENR = HIGH) AE 1 0 16 Ignored Read Operation Next State of FIFO Comments Note: 28. Applies to both the CY7C441 and CY7C443 operations. Document #: 38-06032 Rev. *A Page 12 of 15 CY7C441 CY7C443 Table 4. Almost Full Flag Operation Example[29,30] Status Before Operation Status After Operation Number Number of Words of Words Current State in FIFO in FIFO of FIFO F1 F2 CY7C441 CY7C443 Number of Number of Words in Words in FIFO FIFO F1 F2 CY7C441 CY7C443 Comments Operation Next State of FIFO AF 0 1 496 2032 Read (ENR=LOW) AF 0 1 495 2031 Read AF 0 1 495 2031 Read (ENR=LOW) AF 0 1 494 2030 Read AF 0 1 494 2030 Write Intermediate (ENW=HIGH) 1 1 494 2030 Flag Update Intermediate 1 1 494 2030 Write (ENW=LOW) Intermediate 1 1 495 2031 Write Intermediate 1 1 495 2031 Write (ENW=LOW) AF 0 1 496 2032 Write (Transition from Intermediate toAlmost Full) Note: 29. The CY7C441 Almost Full state is represented by 496 or more words. 30. The CY7C443 Almost Full state is represented by 2032 or more words. Ordering Information 512x9 Clocked FIFO Speed (ns) 12 14 20 30 Ordering Code Package Name Package Type Operating Range CY7C441–12JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C441–12JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C441–14JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C441–14JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C441–20JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C441–20JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C441–30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C441–30JI J65 32-Lead Plastic Leaded Chip Carrier Industrial 2Kx9 Clocked FIFO Speed (ns) 12 14 20 30 Ordering Code Package Name Package Type Operating Range CY7C443–12JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C443–12JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C443–14JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C443–14JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C443–20JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C443–20JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C443–30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C443–30JI J65 32-Lead Plastic Leaded Chip Carrier Industrial Document #: 38-06032 Rev. *A Page 13 of 15 CY7C441 CY7C443 Package Diagrams 32-Lead Plastic Leaded Chip Carrier J65 Document #: 38-06032 Rev. *A Page 14 of 15 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C441 CY7C443 Document Title: CY7C441 / CY7C443 Clocked 512 x 9, 2K x 9 FIFOs Document Number: 38-06032 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110173 09/29/01 SZV Change from Spec number: 38-00124 to 38-06032 *A 122283 12/26/02 RBI Power up requirements added to Maximum Ratings Information Document #: 38-06032 Rev. *A Page 15 of 15