APW7506A 1.5MHz, 1A Synchronous Buck Regulator Features General Description • 1A Output Continuous Current • 1.2A Output Peak Current APW7506A is a 1.5MHz high efficiency monolithic synchronous buck regulator. Design with current mode • Wide 3V~5.5V Input Voltage • Fixed 1.5MHz Switching Frequency • Low Dropout Operating at 100% Duty Cycle • Integrate Synchronous Rectifier • 0.6V Reference Voltage • Current-Mode Operation with Internal scheme, the APW7506A is stable with ceramic output capacitor. Input voltage from 3V to 5.5V makes the APW7506A ideally suited for single Li-Ion battery powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable electrical devices. The internally fixed 1.5MHz operating frequency allows the using of small surface mount inductors and capacitors. The synchronous switches included inside Compensation - Stable with Ceramic Output Capacitors increase the efficiency and eliminate the need of an external Schottky diode. - Fast Line Transient Response • Short-Circuit Protection • Over-Temperature Protection with Hysteresis • Available in SOT-23-5/TSOT-23-5A Packages • Lead Free and Green Devices Available The APW7506A is available in SOT-23-5/TSOT-23-5A packages. (RoHS Compliant) Applications Pin Configuration • HD STB • BT Mouse RUN 1 • PND Instrument GND 2 • Portable Instrument APW7506A SW 3 C1 4.7µF (MLCC) L1 2.2µH 4 VIN VOUT SW 3 C3 APW7506A 1 RUN FB 5 GND 2 4 VIN SOT-23-5/TSOT-23-5A (Top View) Simplified Application Circuit VIN 5 FB R1 C2 10µF (MLCC) R2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 1 www.anpec.com.tw APW7506A Ordering and Marking Information Package Code BT : TSOT-23-5A B : SOT-23-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7506A Assembly Material Handling Code Temperature Range Package Code APW7506A BT : W6AX X - Date Code APW7506A B : W6AX X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Sym bol VIN P arameter Input Bias Sup ply Voltage (V IN to GND) RUN, FB, SW to GND Voltage PD Po we r Dissipation Maximum Junctio n Tempe rature T STG TSD R Storag e Tempe rature Maximum Lead S olde ring Temperature , 10 Se co nds Ra ting Unit -0 .3 ~ 6 V - 0.3 ~ V IN+0 .3 V In te rnally Limited W 150 o -6 5 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) TSOT-23-5A SOT-23-5 Unit o C/W 220 250 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 2 www.anpec.com.tw APW7506A Recommended Operating Conditions (Note 3) S ymbol V IN Pa ra mete r Range Unit 3 ~ 5.5 V Co nverter Outpu t Voltage 0.6 ~ VIN V Co nverter Outpu t Curren t 0~ 1 In put B ias S uppl y Voltage (VIN to GND) VOUT I OUT Co nverter Outpu t Pea k Curre nt, 10ms pulse, 1 % duty cycle A 1.2 L1 Co nverter Outpu t In ductor 1.0 ~ 10 µH C IN Co nverter In put Ca pacito r 4.7 ~10 0 µF Co nverter Outpu t Capacitor 4.7 ~10 0 µF Ambie nt Tempera tu re -40 ~ 85 o -4 0 ~ 125 o C OU T TA TJ Junctio n Temp erature C C Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=3.3~5V and TA= 25 oC. Sym bol Parame ter APW750 6A Te st Conditions Unit Min. Typ. Max. - - 0.5 µA 2.45 2.7 2.95 V - 0.1 - V 0 .5 88 0.6 0 .6 12 V -2.5 - +2.5 % -50 - 50 nA S UPPLY CURRENT ISD Shutdown Input Current RUN = GND P OWER-ON- RE SET (POR) Risin g POR Thre shold P OR Hysteresis REFERE NCE V OLTAGE VR EF Refer ence Volta ge Output Vo ltag e Accuracy I FB 0A < IOUT < 1 A FB Inpu t Curren t INTERNAL POWER MOSFETS F SW Swi tchin g Fr eque ncy VFB = 0.6 V 1.2 1.5 1.9 MHz Fo ldback Fre quen cy VFB = 0.1 V - 210 - kHz Fo ldback Thr esh old Voltage on FB VFB Falli ng - 0.2 - V mV - 50 - R P-FET Fo ldback Hyste resis Hig h Side P- FET Switch O N Resistan ce ISW =200mA - 0.26 - Ω R N-FET L ow S ide N-FET S witch ON Resistance ISW =200mA - 0.23 - Ω Min imum On-Time - - 1 00 ns Ma ximum Duty Cycl e - - 1 00 % A P ROTECTION IL IM T OTP Ma ximum Inductor Curren t-L imit IP-FET, VIN = 3.3~5 V 1.3 2.3 - Ove r-Tempe rature Protection T J Rising (No te 4) - 150 - Ove r-Tempe rature Protection Hysteresis (Note 4) - 30 - Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 3 °C www.anpec.com.tw APW7506A Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=3.3~5V and TA= 25 oC. Sym bol Parame ter APW750 6A Te st Conditions Unit Min. Typ. Max. - 0.7 - ms - - 1 V 0.4 - - V -1 - 1 µA S TART-UP AND SHUTDOWN tss Soft-Start Dur ati on (Note 4) RUN Inp ut High Thre sh old RUN Inp ut L ow Thresho ld RUN Leakag e Cu rrent VRU N = 5V, VIN = 5V Note 4: Guarantee by design, not production test. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 4 www.anpec.com.tw APW7506A Typical Operating Characteristics Efficiency vs. Load Current Efficiency vs. Load Current 100 100 VOUT = 1.8V VOUT = 1.8V 90 80 80 70 70 Efficiency (%) Efficiency (%) 90 VOUT = 1.2V 60 50 40 30 60 VOUT = 1.2V 50 40 30 20 20 VIN = 5V, Force PWM Mode TA = 25oC 10 0 0.001 0.01 0.1 1 VIN = 3.3V, Force PWM Mode TA = 25oC 10 0 0.001 10 0.01 Load Current, IOUT (A) 10 Load Current, IOUT (A) 1.8 0.606 Switching Frequency, FSW (MHz) VIN = 3.6V 0.605 Reference Voltage, VREF (V) 1 Switching Frequency vs. Junction Temperature Reference Voltage vs. Junction Temperature 0.604 0.603 0.602 0.601 0.600 0.599 0.598 0.597 0.596 0.595 VIN = 3.6V 1.7 1.6 1.5 1.4 1.3 1.2 0.594 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 o o Junction Temperature ( C) Junction Temperature ( C) Maximum Inductor Current-Limit vs. Junction Temperature Switching Frequency vs. Supply Voltage 1.8 3.2 TA = 25oC Switching Frequency, FSW (MHz) Maximum Inductor Current-Limit, ILIM (A) 0.1 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.6 -50 -25 0 25 50 75 100 3.0 125 o 4.0 4.5 5.0 5.5 Supply Voltage, VIN (V) Junction Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 3.5 5 www.anpec.com.tw APW7506A Typical Operating Characteristics Maximum Inductor Current-Limit, ILIM (A) Maximum Inductor Current-Limit vs. Supply Voltage 3.0 TA = 25oC 2.8 2.6 2.4 2.2 2.0 1.8 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 6 www.anpec.com.tw APW7506A Pin Description PIN FUNCTION NO. NAME 1 RUN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V shuts it down. In shutdown, all functions are disabled to decrease the supply current below 0.5µA. Do not leave RUN pin floating. 2 GND Power and Signal Ground. 3 SW Switch Node Connected to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFETs switches. 4 VIN Device and Converter Supply Pin. Must be closely decoupled to GND with a 4.7µF or greater ceramic capacitor. 5 FB Feedback Input Pin. The buck regulator senses feedback voltage via FB and regulates the FB voltage at 0.6V. Connecting FB with a resistor-divider from the output sets the output voltage of the buck converter. Block Diagram Current Sense Amplifier RUN VIN Shutdown Control Logic Control SW OverTemperature Protection Gate Driver Current -Limit Slope Compensation ZeroCrossing Comparator ∑ GND Oscillator ICMP Error Amplifier FB COMP EAMP SoftStart Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 7 VREF 0.6V www.anpec.com.tw APW7506A Typical Application Circuit IIN VIN L1 2.2µH 4 SW VIN VOUT 3 3 ~ 5.5V C1 4.7µF (MLCC) C3 APW7506A 1 RUN FB R1 0.6V~VIN C2 0~1A 10µF (MLCC) 5 GND R1 ≤ 1MΩ is recommended 2 R2 R2 ≤ 200kΩ is recommended C1 closed to IC. Less than 2mm is recommended. C3 ≤ 47pF is recommended(Option) Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 8 www.anpec.com.tw APW7506A Function Description Main Control Loop Slope Compensation and Inductor Peak Current The APW7506A is a constant frequency, synchronous rec- The APW7506A is a peak current mode PWM step down tifier and current-mode switching regulator. In normal operation, the internal P-channel power MOSFET is converter. To prevent sub-harmonic oscillations, the APW7506A sense the peak current and add slope com- turned on each cycle. The peak inductor current at which ICMP turn off the P-FET is controlled by the voltage on the pensation to stable the converter. It is accomplished internally by adding a compensating ramp to the inductor COMP node, which is the output of the error amplifier (EAMP). An external resistive divider connected between current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak cur- VOUT and ground allows the EAMP to receive an output feedback voltage VFB at FB pin. When the load current rent for duty cycles > 40%. However, the APW7506A uses a special scheme that counteracts this compensating increases, it causes a slightly decrease in VFB relative to the 0.6V reference, which in turn causes the COMP volt- ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. age to increase until the average inductor current matches the new load current. Adaptive Shoot-Through Protection The gate driver incorporates adaptive shoot-through pro- Power-On-Reset (POR) tection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. The APW7506A keeps monitoring the voltage on VIN pin to prevent wrong logic operations which may occur when This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to VIN voltage is not high enough for the internal control circuitry to operate. The VIN POR has a rising threshold rise. During turn-off the low-side MOSFET, the internal LGATE of 2.7V (typical) with 0.1V of hysteresis. voltage is monitored until it is below 1.5V threshold, at Soft-Start The APW7506A has a built-in soft-start to control the out- which time the UGATE is released to rise after a constant delay. During turn-off the high-side MOSFET, the UGATE put voltage rise during start-up. During soft-start, an internal ramp voltage, connected to the one of the positive voltage is also monitored until it is above 1.5V threshold, at which time the LGATE is released to rise after a con- inputs of the error amplifier, raises up to replace the reference voltage (0.6V typical) until the ramp voltage stant delay. reaches the reference voltage. Then, the voltage on FB regulated at reference voltage. Enable/Shutdown Driving RUN to the ground places the APW7506A in shutdown mode. When in shutdown, the internal power MOSFETs turn off, all internal circuitry shuts down and the quiescent supply current reduces to 0.5µA maximum. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 9 www.anpec.com.tw APW7506A Function Description (Cont.) Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7506A. When the junction temperature exceeds 150oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and regulate the output voltage again after the junction temperature cools by 30oC. The OTP is designed with a 30oC hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions, increasing the lifetime of the device. Short-Circuit Protection When the output is shortened to the ground, the frequency of the oscillator is reduced to about 210kHz, 1/7 of the nominal frequency. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will progressively increase to 1.5MHz when VFB or VOUT rises above 0V. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 10 www.anpec.com.tw APW7506A Application Information Input Capacitor Selection shown in “Typical Application Circuits”. A suggestion of Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the maximum value of R2 is 200kΩ to keep the minimum current that provides enough noise rejection ability through best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. the resistor divider. The output voltage can be calculated as below: Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For R1 R1 VOUT = VREF ⋅ 1 + = 0.6 ⋅ 1 + R2 R2 good input voltage filtering, usually a 4.7µF input capacitor is sufficient. It can be increased without any limit for VOUT better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and R1≤1MΩ they are less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input FB R2 ≤ 200kΩ APW7506A capacitor as close as possible to the input and GND pin of the device for better performance. GND Inductor Selection Output Capacitor Selection For high efficiencies, the inductor should have a low DC The current-mode control scheme of the APW7506A allows the use of tiny ceramic capacitors. The higher ca- resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a pacitor value provides the good load transients response. higher impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value de- tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the ideal output capacitor. lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient ∆VOUT response. A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current. The rec- V VOUT ⋅ 1 − OUT VIN ≅ FSW ⋅ L 1 ⋅ ESR + 8 ⋅ FSW ⋅ COUT When choosing the input and output ceramic capacitors, ommended inductor value can be calculated as below: choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage char- V VOUT 1 − OUT V IN L≥ FSW ⋅ ∆IL acteristics of all the ceramics for a given value and size. VIN IL(MAX) = IOUT(MAX) + 1/2 x ∆IL IIN IP-FET To avoid the saturation of the inductor, the inductor should IL be rated at least for the maximum output current of the converter plus the inductor ripple current. CIN Output Voltage Setting P-FET VOUT SW N-FET In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is con- IOUT ESR COUT nected to the output, allowing remote voltage sensing as Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 11 www.anpec.com.tw APW7506A Application Information (Cont.) Output Capacitor Selection (Cont.) The maximum power dissipation on the device can be shown as follow figure: IL ILIM 0.8 Maximum Power Disspation (W) IPEAK ∆IL IOUT IP-FET 0.7 TSOT-23-5A TJ=125oC 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 60 70 80 90 o Ambient Temperature ( C) Thermal Consideration 0.8 Maximum Power Disspation (W) In most applications, the APW7506A does not dissipate much heat due to its high efficiency. But, in applications where the APW7506A is running at high ambient temperature with low supply voltage and high duty cycles, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the APW7506A from exceeding the maximum 0.7 SOT-23-5 TJ=125oC 0.6 0.5 0.4 0.3 0.2 0.1 0.0 junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to deter- -40 -30 -20 -10 0 10 20 30 40 50 Ambient Temperature (oC) mine whether the power dissipated exceeds the maximum junction temperature of the part. The power dissipated by the part is approximated: PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D)) The temperature rise is given by: TR = (PD)(θJA) Where PD is the power dissipated by the regulator, D is duty cycle of main switch D = VOUT/VIN The θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR Where TA is the ambient temperature. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 12 www.anpec.com.tw APW7506A Layout Consideration For all switching power supplies, the layout is an important step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND t o c a p a c i t or l e s s t h a n 2m m r e s pe c t i ve ly i s recommended. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the SW pin to minimize the noise coupling into other circuits. 3. The output capacitor should be place closed to converter VOUT and GND. 4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes ground shifts and noise is recommended. Via to GND R2 FB VRUN R1 L1 Via to VOUT VOUT SW COUT CIN VIN GND APW7506A Layout Suggestion Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 13 www.anpec.com.tw APW7506A Package Information TSOT-23-5A D e E E1 SEE VIEW A c b 0.25 A GAUGE PLANE SEATING PLANE A1 A2 e1 L VIEW A TSOT-23-5A S Y M B O L MIN. MAX. MIN. MAX. A 0.70 1.00 0.028 0.039 0.004 MILLIMETERS INCHES A1 0.01 0.10 0.000 A2 0.70 0.90 0.028 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC e1 1.90BSC 0.037 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Followed from JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 14 www.anpec.com.tw APW7506A Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 INCHES MILLIMETERS MIN. MAX. MIN. A MAX. 1.45 0.057 A1 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC 0.037 BSC e1 1.90 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 15 www.anpec.com.tw APW7506A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSOT-23-5A A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 4.0±0.10 4.0±0.10 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 Application SOT-23-5 (mm) Devices Per Unit Package Type Unit Quantity TSOT-23-5A Tape & Reel 3000 SOT-23-5 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 16 www.anpec.com.tw APW7506A Taping Direction Information TSOT-23-5A USER DIRECTION OF FEED SOT-23-5 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 17 www.anpec.com.tw APW7506A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 18 www.anpec.com.tw APW7506A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2016 19 www.anpec.com.tw