H CAT521 EE GEN FR ALO Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications LE FEATURES APPLICATIONS ■ 8-bit DPP configured as a programmable ■ Automated product calibration voltage source in DAC-like applications A D F R E ETM ■ Remote control adjustment of equipment ■ Buffered wiper output ■ Offset, gain and zero adjustments in ■ Non-volatile NVRAM memory wiper storage self-calibrating and adaptive control systems ■ Output voltage range includes both supply rails ■ Tamper-proof calibrations ■ 1 LSB accuracy, high resolution ■ DAC (with memory) substitute ■ Serial Microwire-like interface ■ Single supply operation: 2.7V - 5.5V ■ Setting read-back without effecting outputs DESCRIPTION The CAT521 is a 8-bit digitally-programmable potentiometer (DPP™) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. settings and stored settings can be read back without disturbing the DPP’s output. The CAT521 is controlled with a simple 3-wire, Microwirelike serial interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the CAT521 Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The programmable DPP has an output voltage range which includes both supply rails. The wiper is buffered by a rail to rail op amp. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be dithered to test new output values without effecting the stored The CAT521 is available in 0°C to 70°C commercial and -40°C to 85°C industrial operating temperature ranges. Both 14-pin plastic DIP and surface mount packages are available. FUNCTIONAL DIAGRAM RDY/BSY 3 PROG DI CLK CS 7 PIN CONFIGURATION V DD V REFH 14 1 DIP Package (P, L) 5 2 SOIC Package (J, W) PROGRAM CONTROL SERIAL CONTROL WIPER CONTROL REGISTER AND NVRAM + SERIAL DATA OUTPUT REGISTER 8 GND © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 CLK 2 14 VREFH VDD 1 13 NC CLK 2 12 14 VREFH 13 NC CAT521 CAT521 4 CAT521 VDD RDY/BSY 3 12 VOUT CS 4 11 DI 5 10 DO 6 9 VREFL PROG 7 8 GND RDY/BSY 3 12 VOUT NC CS 4 11 NC NC DI 5 10 NC DO 6 9 VREFL PROG 7 8 GND V OUT 6 DO 9 VREFL 1 Doc. No. 2003, Rev. F CAT521 Operating Ambient Temperature Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C Industrial (‘I’ suffix) ........................ -40°C to +85°C Junction Temperature ..................................... +150°C Storage Temperature ........................ -65°C to +150°C Lead Soldering (10 sec max) .......................... +300°C ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND ...................................... -0.5V to +7V Inputs CLK to GND ............................ -0.5V to VDD +0.5V CS to GND .............................. -0.5V to VDD +0.5V DI to GND ............................... -0.5V to VDD +0.5V RDY/BSY to GND ................... -0.5V to VDD +0.5V PROG to GND ........................ -0.5V to VDD +0.5V VREFH to GND ........................ -0.5V to VDD +0.5V VREFL to GND ......................... -0.5V to VDD +0.5V Outputs D0 to GND ............................... -0.5V to VDD +0.5V VOUT 1– 4 to GND ................... -0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating — 400 600 µA Programming, VDD = 5V — 1600 2500 µA VDD = 3V — 1000 1600 µA 2.7 — 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD — — 10 µA IIL Input Leakage Current VIN = 0V — — -10 µA VIH High Level Input Voltage 2 — VDD V VIL Low Level Input Voltage 0 — 0.8 V Min Typ Max Units VDD -0.3 — — V LOGIC OUTPUTS Symbol Parameter Conditions VOH High Level Output Voltage IOH = -40µA VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V IOL = 0.4 mA, VDD = +3V — — 0.4 V Doc. No. 2003, Rev. F 2 CAT521 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions RPOT Potentiometer Resistance See Note 3 Min Typ Max Units 24 RPOT to RPOT Match — +0.5 Pot Resistance Tolerance kΩ +1 % +20 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin 0V VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 Ω IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance 300 ppm/˚C CH/CL Potentiometer Capacitances 8/8 pF AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 150 100 0 50 50 — — — — — 150 700 500 300 DC — — — — — — — 400 400 4 — — — — — — — — — — 150 150 — — 5 — — — — 1 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz — — 3 6 10 10 µs µs Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL=100pF, see note 1 Analog tDS NOTES: DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3. The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ +20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value. 3 Doc. No. 2003, Rev. F CAT521 A. C. TIMING DIAGRAM to 1 2 3 4 5 t CLK H CLK t CSS t CLK L t CSH CS t CSMIN t DIS DI t DIH t DO0 t LZ DO t HZ t DO1 PROG t PS t PROG RDY/BSY t BUSY to Doc. No. 2003, Rev. F 1 2 3 4 4 5 CAT521 PIN DESCRIPTION Pin DPP addressing is as follows: Name Function 1 2 3 4 5 6 7 VDD CLK RDY/BSY CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL NC NC VOUT NC VREFH Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin EEPROM Programming Enable Input Power supply ground Minimum DAC output voltage No Connect No Connect DPP output No Connect Maximum DPP 1 output voltage DPP OUTPUT A0 A1 VOUT 1 0 DEVICE OPERATION CHIP SELECT The CAT521 is a single 8-bit configured digitally programmable potentiometer (DPP™) whose output can be programmed to any one of 256 individual voltage steps. Once programmed, the output setting is retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPP returns to the setting stored in non-volatile memory. The DPP can be written to and read from without effecting the output voltage during the read or write cycle. The output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. Chip Select (CS) enables and disables the CAT521’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control register will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. DIGITAL INTERFACE CLOCK The CAT521 employs a 3 wire, Microwire-like serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. The CAT521 clock controls both data flow in and out of the device and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT521 internal power-on reset circuitry loads data from non-volatile memory to the DPP without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. 5 Doc. No. 2003, Rev. F CAT521 As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control register. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. single serial data line and simplifies interfacing multiple 521s to a microprocessor. WRITING TO MEMORY Programming the CAT521’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF VREF, the voltage applied between pins VREFH &VREFL, sets the DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH &VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The CAT521 non-volatile memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed. BUSY READY/BUSY When saving data to non-volatile memory, the Ready/ Busy ouput (RDY/BSY) signals the start and duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT521 will ignore any data appearing at DI and no data will be output on DO. READING DATA Data is output serially by the CAT521, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 521s to share a Each time data is transferred into the DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory's setting is reloaded into the DPP wiper control register. Since this value is Figure 1. Writing to Memory Figure 2. Reading from Memory RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT to 1 2 3 4 5 6 7 8 9 10 11 12 N to N+1 N+2 1 2 3 4 5 6 7 8 9 10 11 12 CS CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI D6 D7 DO 1 A0 A1 CURRENT DPP DATA CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 PROG PROG RDY/BSY RDY/BSY DPP OUTPUT Doc. No. 2003, Rev. F CURRENT DPP VALUE NEW DPP VALUE NEW DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE DPP OUTPUT D0 D1 D2 D3 D4 D5 CURRENT DPP VALUE NON-VOLATILE 6 D6 D7 CAT521 Figure 3. Temporary Change in Output the same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle’s conclusion. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA TEMPORARILY CHANGE OUTPUT 1 DI The CAT521 allows temporary changes in the DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA D0 DO D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT Figure 3 shows the control and data signals needed to effect a temporary output change. DPP settings may be changed as many times as required. The temporary setting remains in effect long as CS remains high. When CS returns low the DPP will return to the output value stored in non-volatile memory. CURRENT DPP VALUE NEW DPP VALUE CURRENT DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP wiper control register prior to programming. This is because the CAT521’s internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. APPLICATION CIRCUITS DPP INPUT +5V Ri Vi RF VFS +15V VDD CONTROL & DATA VREFH GND VOUT – + CAT521 ANALOG OUTPUT V (R +R )-V R VOUT = DPP I F I F RI For R I = RF VOUT = 2VDPP -VI = 0.99 V VREF = 5V R I = RF MSB LSB VZERO = 0.01 V 1111 1111 255 (.98 V —— REF) + .01 VREF= .990 VREF 255 VOUT = +4.90V 1000 0000 V = +0.02V OUT 0111 1111 128 (.98 V —— REF) + .01 VREF= .502 VREF 255 127 —— (.98 VREF) + .01 VREF= .498 VREF 255 OP 07 -15V VREFL DPP OUTPUT CODE (V - V VDPP = ——— FS ZERO ) + VZERO 255 0000 0001 1 (.98 V —— REF + .01 VREF = .014 V REF 255 0000 0000 0 (.98 V —— REF) + .01 VREF = .010 VREF 255 V = -0.02V OUT V OUT = -4.86V V = -4.90V OUT Bipolar DPP Output +5V RI RF +15V VDD CONTROL & DATA VREFH – + CAT521 GND VOUT OP 07 -15V VREFL RF VOUT = (1 + –––) V DPP RI Amplified DPP Output 7 Doc. No. 2003, Rev. F CAT521 APPLICATION CIRCUITS (Cont.) 28 - 32V V+ I > 2 mA 15K 10 µF VDD CONTROL & DATA VREFH OPT 515 CAT521 GND VREF = 5.000V 1N5231B VDD LT 1029 VREFH 5.1V 10K CONTROL & DATA VREFL + CAT521 GND VREFL – MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 2003, Rev. F Digitally Controlled Voltage Reference 8 10 µF 35V 0 - 25V @ 1A CAT521 ORDERING INFORMATION Prefix Device # Suffix CAT 521 J Optional Company ID Product Number -TE13 I Package P: PDIP J: SOIC L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) Notes: (1) The device used in the above example is a CAT521JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) 9 Doc. No. 2003, Rev. F REVISION HISTORY Date Rev. Reason 3/16/2004 E Updated Potentiometer Characteristics 7/12/2004 F Updated Functional Diagram Updated Potentiometre Characteristics Added Note 3 under Potentiometer/AC Characteristics tables Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: Type: 2003 F 7/12/04 Final