Features • Utilizes the ARM7TDMI™ ARM Thumb Processor Core • • • • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-circuit Emulation) 2K Bytes Internal RAM Fully-programmable External Bus Interface (EBI) – Maximum External Address Space of 64M Bytes – Up to 8 Chip Selects – Software Programmable 8/16-bit External Data Bus Multi-processor Interface (MPI) – High-performance External Processor Interface – 512 x 16-bit Dual-port RAM 8-channel Peripheral Data Controller 8-level Priority, Individually Maskable, Vectored Interrupt Controller – 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request 58 Programmable I/O Lines 6-channel 16-bit Timer/Counter – 6 External Clock Inputs – 2 Multi-purpose I/O Pins per Channel 3 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART – Support for Up to 9-bit Data Transfers Master/Slave SPI Interface – 2 Dedicated Peripheral Data Controller (PDC) Channels – 8- to 16-bit Programmable Data Length – 4 External Slave Chip Selects Programmable Watchdog Timer Power Management Controller (PMC) – CPU and Peripherals Can Be Deactivated Individually IEEE 1149.1 JTAG Boundary-scan on All Active Pins Fully Static Operation: 0 Hz to 25 MHz (12 MHz at 1.8V) 1.8V to 3.6V Core Operating Voltage Range 2.7V to 5.5V I/O Operating Voltage Range -40°C to +85°C Operating Temperature Range Available in a 176-lead TQFP Package AT91 ARM® Thumb® Microcontrollers AT91M63200 Summary Description The AT91M63200 is a member of the Atmel AT91 16/32-bit microcontroller family which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features Atmel’s high-density, in-system programmable, nonvolatile memory technology. The AT91M63200 has a direct connection to off-chip memory, including Flash, through the External Bus Interface. The Multi-processor Interface (MPI) provides a high-performance interface with an external coprocessor or a high bandwidth peripheral. The AT91M63200 is manufactured using the Atmel high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-processor interface and a wide range of peripheral functions on a monolithic chip, the AT91M63200 provides a highly-flexible and cost-effective solution to many computeintensive multi-processor applications. Rev. 1028DS–06/00 1 Pin Configuration 2 Pin AT91M63200 Pin AT91M63200 Pin AT91M63200 Pin AT91M63200 1 GND 45 GND 89 GND 133 GND 2 GND 46 GND 90 GND 134 GND 3 NCS0 47 D8 91 PA19 / RXD1 135 MPI_D12 4 NCS1 48 D9 92 PA20 / SCK2 136 MPI_D13 5 NCS2 49 D10 93 PA21 / TXD2 137 MPI_D14 6 NCS3 50 D11 94 PA22 / RXD2 138 MPI_D15 7 NLB/A0 51 D12 95 PA23 / SPCK 139 PB0/MPI_NOE 8 A1 52 D13 96 PA24/MISO 140 PB1/MPI_NLB 9 A2 53 D14 97 PA25/MOSI 141 PB2/MPI_NUB 10 A3 54 D15 98 PA26/NPCS0/NSS 142 PB3 11 A4 55 PB19/TCLK0 99 PA27/NPCS1 143 PB4 12 A5 56 PB20/TIOA0 100 PA28/NPCS2 144 PB5 13 A6 57 PB21/TIOB0 101 PA29/NPCS3 145 PB6 14 A7 58 PB22/TCLK1 102 MPI_A1 146 PB7 15 VDDIO 59 VDDIO 103 VDDIO 147 VDDIO 16 GND 60 GND 104 GND 148 GND 17 A8 61 PB23/TIOA1 105 MPI_A2 149 PB8 18 A9 62 PB24/TIOB1 106 MPI_A3 150 PB9 19 A10 63 PB25/TCLK2 107 MPI_A4 151 PB10 20 A11 64 PB26/TIOA2 108 MPI_A5 152 PB11 21 A12 65 PB27/TIOB2 109 MPI_A6 153 PB12 PB13 22 A13 66 PA0/TCLK3 110 MPI_A7 154 23 A14 67 PA1/TIOA3 111 MPI_A8 155 PB14 24 A15 68 PA2/TIOB3 112 MPI_A9 156 PB15 25 A16 69 PA3/TCLK4 113 MPI_NCS 157 PB16 26 A17 70 PA4/TIOA4 114 MPI_RNW 158 PB17/MCKO 27 A18 71 PA5/TIOB4 115 MPI_BR 159 NWDOVF 28 A19 72 PA6/TCLK5 116 MPI_BG 160 MCKI 29 VDDIO 73 VDDIO 117 VDDIO 161 VDDIO 30 GND 74 GND 118 GND 162 GND 31 A20/CS7 75 PA7/TIOA5 119 MPI_D0 163 PB18/BMS 32 A21/CS6 76 PA8/TIOB5 120 MPI_D1 164 JTAGSEL 33 A22/CS5 77 PA9/IRQ0 121 MPI_D2 165 TMS 34 A23/CS4 78 PA10/IRQ1 122 MPI_D3 166 TDI 35 D0 79 PA11/IRQ2 123 MPI_D4 167 TDO 36 D1 80 PA12/IRQ3 124 MPI_D5 168 TCK 37 D2 81 PA13/FIQ 125 MPI_D6 169 NTRST 38 D3 82 PA14/SCK0 126 MPI_D7 170 NRST 39 D4 83 PA15/TXD0 127 MPI_D8 171 NWAIT 40 D5 84 PA16/RXD0 128 MPI_D9 172 NOE/NRD 41 D6 85 PA17/SCK1 129 MPI_D10 173 NWE/NWR0 42 D7 86 PA18/TXD1/NTRI 130 MPI_D11 174 NUB/NWR1 43 VDDCORE 87 VDDCORE 131 VDDCORE 175 VDDCORE 44 VDDIO 88 VDDIO 132 VDDIO 176 VDDIO AT91M63200 AT91M63200 Pin Description Module EBI MPI AIC Timer USART SPI PIO WD Clock Reset Name Function A0 - A23 Address Bus Type Active Level Output – D0 - D15 Data Bus I/O – CS4 - CS7 Chip Select Output High NCS0 - NCS3 Chip Select Output Low NWR0 Lower Byte 0 Write Signal Output Low Comments All valid after reset A23 - A20 after reset Used in Byte Write option NWR1 Lower Byte 1 Write Signal Output Low Used in Byte Write option NRD Read Signal Output Low Used in Byte Write option NWE Write Enable Output Low Used in Byte Select option NOE Output Enable Output Low Used in Byte Select option NUB Upper Byte Select (16-bit SRAM) Output Low Used in Byte Select option NLB Lower Byte Select (16-bit SRAM) Output Low Used in Byte Select option NWAIT Wait Input Input Low BMS Boot Mode Select Input – MPI_NCS Chip Select Input Low MPI_RNW Read Not Write Signal Input – MPI_BR Bus Request From External Processor Input High MPI_BG Bus Grant To External Processor Output High MPI_NOE Output Enable Input Low MPI_NLB Lower Byte Select Input Low Sampled during reset MPI_NUB Upper Byte Select Input Low MPI_A1 - MPI_A9 Address Bus Input – MPI_D0 - MPI_D15 Data Bus I/O – IRQ0 - IRQ3 External Interrupt Request Input – PIO-controlled after reset FIQ Fast External Interrupt Request Input – PIO-controlled after reset TCLK0 - TCLK5 Timer External Clock Input – PIO-controlled after reset TIOA0 - TIOA5 Multipurpose Timer I/O Pin A I/O – PIO-controlled after reset TIOB0 - TIOB5 Multipurpose Timer I/O Pin B I/O – PIO-controlled after reset SCK0 - SCK2 External Serial Clock I/O – PIO-controlled after reset TXD0 - TXD2 Transmit Data Output Output – PIO-controlled after reset RXD0 - RXD2 Receive Data Input Input – PIO-controlled after reset SPCK SPI Clock I/O – PIO-controlled after reset MISO Master In Slave Out I/O – PIO-controlled after reset MOSI Master Out Slave In I/O – PIO-controlled after reset NSS Slave Select NPCS0 - NPCS3 Peripheral Chip Select PA0 - PA29 PB0 - PB27 Input Low PIO-controlled after reset Output Low PIO-controlled after reset Programmable I/O Port A I/O – Input after reset Programmable I/O Port B I/O – Input after reset Output Low Input – NWDOVF Watchdog Timer Overflow MCKI Master Clock Input MCKO Master Clock Output NRST Hardware Reset Input Output – Input Low Open-drain Schmitt trigger Schmitt trigger, internal pull-up 3 Pin Description (Continued) Module JTAG/ICE Power Emulation Name Function Type Comments JTAGSEL Selects between JTAG and ICE Mode Input – High enables IEEE 1149.1 JTAG Boundary-scan Low enables ARM Standard ICE debug TMS Test Mode Select Input – Schmitt trigger, internal pull-up Input – Schmitt trigger, internal pull-up Output – TDI Test Data In TDO Test Data Out TCK Test Clock Input – Schmitt trigger, internal pull-up NTRST Test Reset Input Input Low Schmitt trigger, internal pull-up VDDIO I/O Power Power – 3V or 5V nominal supply VDDCORE Core Power Power – 2.0V or 3V nominal supply GND Ground Ground – NTRI Tri-state Mode Enable Input Low Figure 1. Pin Configuration (Top View) 176 133 132 1 AT91M63X00 176-Lead TQFP 89 44 45 4 Active Level AT91M63200 88 Sampled during reset AT91M63200 Block Diagram Embedded ICE MPI_A1-MPI_A9 ASB PA14/SCK0 PA15/TXD0 PA16/RXD0 PA17/SCK1 PA18/TXD1/NTRI PA19/RXD1 PA20/SCK2 PA21/TXD2 PA22/RXD2 PA23/SPCK PA24/MISO PA25/MOSI PA26/NPCS0/NSS PA27/NPCS1 PA28/NPCS2 PA29/NPCS3 A1-A19 A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0-NCS3 A20/CS7 A21/CS6 A22/CS5 A23/CS4 EBI: External Bus Interface ASB Controller AMBA Bridge P I O EBI User Interface PB18/BMS TC: Timer Counter Block 0 PB19/TCLK0 PB22/TCLK1 PB25/TCLK2 TC0 PB20/TIOA0 PB21/TIOB0 AIC: Advanced Interrupt Controller USART0 2 PDC Channels USART1 2 PDC Channels APB SPI: Serial Peripheral Interface TC1 2 PDC Channels USART2 PMC: Power Management Controller TC2 PIOA: Parallel I/O Controller A P I O PB23/TIOA1 PB24/TIOB1 PB26/TIOA2 PB27/TIOB2 TC: Timer Counter Block 1 PA0/TCLK3 PA3/TCLK4 PA6/TCLK5 TC0 PA1/TIOA3 PA2/TIOB3 TC1 PA4/TIOA4 PA5/TIOB4 TC2 PA7/TIOA5 PA8/TIOB5 Chip ID WD: Watchdog Timer PB0/MPI_NOE PB1/MPI_NLB PB2/MPI_NUB D0-D15 Internal RAM 2/8K Bytes 2 PDC Channels NWDOVF MPI_NCS MPI_RNW MPI_BR MPI_BG P I O Clock MCKI PB17/MCKO PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 MPI_D0-MPI_D15 MPI: MultiProcessor Interface ARM7TDMI Core PA9/IRQ0 PA10/IRQ1 PA11/IRQ2 PA12/IRQ3 PA13/FIQ NRST Reset JTAG NTRST TMS TDO TDI TCK PIOB: Parallel I/O Controller B 5 Architectural Overview The AT91M63200 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The AT91M63200 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16-Kbyte address space allocated in the upper 3M bytes of the 4-Gbyte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modifywrite and complex bit manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Controller. The PIO Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO Controller in order to define which peripheral signals are connected with off-chip logic. 6 AT91M63200 The ARM7TDMI processor operates in little-endian mode in the AT91M63200 microcontroller. The processor’s internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are described in detail in the AT91M63200 datasheet. Electrical and mechanical characteristics are documented in the AT91M63200 Electrical Characteristics datasheet. The ARM Standard In-circuit-Emulation debug interface is supported via the ICE port of the AT91M63200 via the JTAG/ICE port when JTAGSEL is low. IEEE JTAG Boundary-scan is supported via the JTAG/ICE port when JTAGSEL is high. PDC: Peripheral Data Controller The AT91M63200 has an 8-channel PDC dedicated to the three on-chip USARTs and to the SPI. One PDC channel is connected to the receiving channel and one to the transmitting channel of each peripheral. The user interface of a PDC channel is integrated in the memory space of each USART channel and in the memory space of the SPI. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed data is transferred, an end-of-transfer interrupt is generated by the corresponding peripheral. See the USART section and the SPI section for more details on PDC operation and programming. Power Supplies The AT91M63200 has two kinds of power supply pins: • VDDCORE pins, which power the chip core • VDDIO pins, which power the I/O lines This allows core power consumption to be reduced by supplying it with a lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage greater than the supply voltage applied to the VDDIO pins. Typical supported voltage combinations are shown in the following table: Pins VDDCORE VDDIO Typical Supply Voltages 3.0V or 3.3V 3.0V or 3.3V 2.0V 5.0V 3.0V or 3.3V 3.0V or 3.3V AT91M63200 EBI: External Bus Interface The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64M bytes. It has eight chip selects and a 24-bit address bus, the upper four bits of which are multiplexed with a chip select. The 16-bit data bus can be configured to interface with 8or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols, allowing single clock cycle memory accesses. The main features are: • External memory mapping • Up to 8 chip select lines • 8- or 16-bit data bus • Byte write or byte select lines • Remap of boot memory • Two different read protocols • Programmable wait state generation • External wait request • Programmable data float time MPI: Multi-processor Interface The AT91M63200 features a second bus interface that is dedicated to parallel data exchange with an external processing device. The MPI features a 1-Kbyte dual-port RAM memory and memory access arbitration logic. The ARM processor core and the external processor can both read and write to the dual-port RAM memory. AIC: Advanced Interrupt Controller The AT91M63200 has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ3. An 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high- or low-level sensitive. PIO: Parallel I/O Controller The AT91M63200 features 58 programmable I/O lines. 14 pins on the AT91M63200 are dedicated as general-purpose I/O pins. Other I/O lines are multiplexed with on-chip peripheral I/O signals in order to optimize the use of available package pins. The I/O lines are controlled by two separate and identical PIO controllers (PIOA and PIOB). Each PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller (AIC). USART: Universal Synchronous/Asynchronous Receiver/Transmitter The AT91M63200 provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: • Programmable baud rate generator • Parity, framing and overrun error detection • Line break generation and detection • Automatic echo, local loopback and remote loopback channel modes • Multi-drop mode: address detection and generation • Interrupt generation • Two dedicated peripheral data controller channels • 5-, 6-, 7-, 8- and 9-bit character length SPI: Serial Peripheral Interface The AT91M63200 features an SPI, which provides communication with external devices in master or slave mode. The SPI has four external chip selects that can be connected to up to 15 devices. The data length is programmable, from 8- to 16-bit. As for the USART, a 2-channel PDC is used to move data directly between memory and the SPI without CPU intervention for maximum real-time processing throughput. 7 TC: Timer/Counter PMC: Power Management Controller The AT91M63200 features two identical Timer/Counter blocks, each containing three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulsewidth modulation. Each Timer/Counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user. Each channel drives an internal interrupt signal that can be programmed to generate processor interrupts via the Advanced Interrupt Controller (AIC). Each Timer Counter block features two global registers that act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each Timer/Counter channel, allowing them to be chained. The Power Management Controller allows optimization of power consumption. The PMC enables/disables the clock inputs to most of the peripherals as well as to the ARM processor core. When the ARM core clock is disabled, the current instruction is processed before the clock is stopped. The clock can be re-enabled by any enabled interrupt or by a hardware reset. When a peripheral clock is disabled, the clock is immediately stopped. When the clock is re-enabled, the peripheral resumes action where it left off. Due to the static nature of the design, the contents of the on-chip RAM and registers for which the clocks are disabled remain unchanged. WD: Watchdog Timer The AT91M63200 features an internal watchdog timer, which can be used to guard against system lock-up if the software becomes trapped in a deadlock. 8 AT91M63200 SF: Special Function The AT91M63200 provides registers that implement the following special functions: • Chip identification • RESET status AT91M63200 Ordering Information Max Speed (MHz) Operating Power Supply Range 25 2.7V to 3.6V (Core) 2.7V to 5.5V (I/Os) AT91M63200-25AI 12 1.8V to 3.6V (Core) 2.7V to 3.6V (I/Os) AT91M63200-12AI-1.8 Ordering Code RAM (Bytes) Package Operating Temperature Range Industrial (-40°C to 85°C) 2K TQFP 176 Industrial (-40°C to 85°C) 9 Package Outline TQFP 176 Common Dimensions (mm) Symbol Min Nom Max c 0.09 0.2 c1 0.09 0.16 L 0.45 L1 0.6 0.75 1.00 REF R2 0.08 R1 0.08 S 0.2 q 0° θ1 0° θ2 θ3 0.2 3.5° 7° 11° 12° 13° 11° 12° 13° A 1.6 A1 0.05 A2 1.35 0.15 1.4 1.45 Tolerances of form and position aaa 0.2 bbb 0.2 Lead Count Dimensions b b1 Pin Count D/E BSC D1/E1 BSC Min Nom Max Min Nom Max e BSC ccc ddd 176 26.0 24.0 0.17 0.22 0.27 0.17 0.2 0.23 0.50 0.10 0.08 10 AT91M63200 AT91M63200 Package Drawing aaa bbb PIN 1 θ2 S ccc θ3 ddd R2 R1 0.25 θ c c1 θ1 L1 11 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail [email protected] Web Site http://www.atmel.com BBS 1-(408) 436-4309 © Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1028DS–06/00/0M