AD AD9650BCPZ-105 16-bit, 25 msps/65 msps/80 msps/105 msps, 1.8 v dual analog-to-digital converter (adc) Datasheet

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS,
1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
SNR
82 dBFS at 30 MHz input and 105 MSPS data rate
83 dBFS at 9.7 MHz input and 25 MSPS data rate
SFDR
90 dBc at 30 MHz input and 105 MSPS data rate
95 dBc at 9.7 MHz input and 25 MSPS data rate
Low power
328 mW per channel at 105 MSPS
119 mW per channel at 25 MSPS
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
Analog input range of 2.7 V p-p
Optional on-chip dither
Integrated ADC sample-and-hold inputs
Differential analog inputs with 500 MHz bandwidth
ADC clock duty cycle stabilizer
AVDD
Industrial instrumentation
X-Ray, MRI, and ultrasound equipment
High speed pulse acquisition
Chemical and spectrum analysis
Direct conversion receivers
Multimode digital receivers
Smart antenna systems
General-purpose software radios
GENERAL DESCRIPTION
The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/
105 MSPS analog-to-digital converter (ADC) designed for
digitizing high frequency, wide dynamic range signals with
input frequencies of up to 300 MHz.
CSB
DRVDD
SPI
AD9650
ORA
PROGRAMMING DATA
VIN+A
CMOS/LVDS
OUTPUT BUFFER
ADC
VIN–A
16
CLK+
DIVIDE 1
TO 8
VREF
CLK–
SENSE
VCM
DUTY CYCLE
STABILIZER
REF
SELECT
DCO
GENERATION
RBIAS
DCOA
DCOB
ORB
VIN–B
VIN+B
D15A (MSB)
TO
D0A (LSB)
CMOS/LVDS
OUTPUT BUFFER
ADC
16
D15B (MSB)
TO
D0B (LSB)
MULTICHIP
SYNC
AGND
SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
08919-001
APPLICATIONS
SDIO/ SCLK/
DCS
DFS
Figure 1.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9650 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold
analog input amplifiers, and shared integrated voltage reference,
which eases design considerations. A duty cycle stabilizer is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converters to maintain excellent performance.
3.
The ADC output data can be routed directly to the two external
16-bit output ports or multiplexed on a single 16-bit bus. These
outputs can be set to either 1.8 V CMOS or LVDS.
5.
4.
On-chip dither option for improved SFDR performance
with low power analog input.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and test modes.
Pin compatible with the AD9268 and other dual families,
AD9269, AD9251, AD9231, and AD9204. This allows a
simple migration across resolutions and bandwidth.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD9650
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC Architecture ...................................................................... 29
Applications....................................................................................... 1
Analog Input Considerations ................................................... 29
General Description ......................................................................... 1
Voltage Reference ....................................................................... 32
Functional Block Diagram .............................................................. 1
Channel/Chip Synchronization................................................ 34
Product Highlights ........................................................................... 1
Power Dissipation and Standby Mode .................................... 34
Revision History ............................................................................... 2
Digital Outputs ........................................................................... 35
Specifications..................................................................................... 3
Timing ......................................................................................... 35
ADC DC Specifications ............................................................... 3
Built-In Self-Test (BIST) and Output Test .................................. 36
ADC AC Specifications ................................................................. 4
Built-In Self-Test (BIST)............................................................ 36
Digital Specifications ................................................................... 5
Output Test Modes..................................................................... 36
Switching Specifications ................................................................ 7
Serial Port Interface (SPI).............................................................. 37
Timing Specifications .................................................................. 8
Configuration Using the SPI..................................................... 37
Absolute Maximum Ratings.......................................................... 10
Hardware Interface..................................................................... 38
Thermal Characteristics ................................................................ 10
Configuration Without the SPI ................................................ 38
ESD Caution................................................................................ 10
SPI Accessible Features.............................................................. 38
Pin Configurations and Function Descriptions ......................... 11
Memory Map .................................................................................. 39
Typical Performance Characteristics ........................................... 15
Reading the Memory Map Register Table............................... 39
AD9650-25 .................................................................................. 15
Memory Map Register Table..................................................... 40
AD9650-65 .................................................................................. 18
Memory Map Register Descriptions........................................ 42
AD9650-80 .................................................................................. 21
Applications Information .............................................................. 43
AD9650-105 ................................................................................ 24
Design Guidelines ...................................................................... 43
Equivalent Circuits ......................................................................... 28
Outline Dimensions ....................................................................... 44
Theory of Operation ...................................................................... 29
Ordering Guide .......................................................................... 44
REVISION HISTORY
7/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD9650
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1.35 V
Mode)
Load Regulation at 1.0 mA
INPUT REFERRED NOISE
VREF = 1.35 V
ANALOG INPUT
Input Span, VREF = 1.35 V
Input Capacitance 2
Input Common-Mode Voltage
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1 (1.8 V CMOS)
IDRVDD1 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD =
1.8 V CMOS Output Mode)
Sine Wave Input1 (DRVDD =
1.8 V LVDS Output Mode)
Standby Power 3
Power-Down Power
Temp
Full
AD9650BCPZ-25
Min Typ
Max
16
AD9650BCPZ-65
Min Typ
Max
16
Full
Full
Full
Full
25°C
Full
Guaranteed
±0.2
±0.5
±0.4
±2.5
−1
+1.3
±0.7
±3
Guaranteed
±0.2
±0.5
±0.4
±2.5
−1
+1.3
±0.7
±5
AD9650BCPZ-80
Min Typ
Max
16
−1
Guaranteed
±0.4
±0.70
±0.4
±2.5
+1.3
±0.7
±6
Unit
Bits
Guaranteed
±0.4
±0.7
±0.4
±2.5
−1
+1.3
±0.7
±6
% FSR
% FSR
LSB
LSB
LSB
25°C
±1.6
Full
Full
±0.1
±0.5
Full
Full
±2
±15
Full
±7
Full
10
10
10
10
mV
25°C
1.5
1.5
1.5
1.5
LSB
rms
Full
Full
Full
Full
2.7
11
0.9
6
2.7
11
0.9
6
2.7
11
0.9
6
2.7
11
0.9
6
V p-p
pF
V
kΩ
Full
Full
1.7
1.7
±2.5
AD9650BCPZ-105
Min Typ
Max
16
±0.4
±1.3
±0.1
±0.5
±2.5
±0.4
±1.3
±0.1
±0.5
±2
±15
±14
1.8
1.8
1.9
1.9
131
±7
1.7
1.7
±3
±0.4
±1.3
±0.1
±0.5
±2
±15
±14
1.8
1.8
1.9
1.9
202
209
±7
1.7
1.7
LSB
±0.4
±1.3
±2
±15
±14
1.8
1.8
1.9
1.9
267
275
±7
1.7
1.7
% FSR
% FSR
ppm/°C
ppm/°C
±14
1.8
1.8
1.9
1.9
332
340
mV
V
V
Full
125
Full
8
23
29
36
mA
Full
72
86
90
100
mA
Full
Full
237
240
Full
355
Full
Full
50
0.25
254
397
405
408
520
2.5
50
0.25
1
Rev. 0 | Page 3 of 44
537
642
2.5
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK+ and CLK− pins inactive (set to AVDD or AGND).
2
522
533
50
0.25
656
663
675
778
2.5
50
0.25
mA
mW
mW
mW
2.5
mW
mW
AD9650
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz 2
SIGNAL-TO-NOISE-AND-DISTORTION
(SINAD)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz2
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz2
WORST SECOND OR THIRD HARMONIC
fIN =9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz
TWO-TONE SFDR
fIN = 7.2 MHz (−7 dBFS ), 8.4 MHz
(−7 dBFS)
fIN = 25 MHz (−7 dBFS ), 30 MHz
(−7 dBFS)
fIN = 125 MHz (−7 dBFS ), 128 MHz
(−7 dBFS)
CROSSTALK 3
ANALOG INPUT BANDWIDTH
1
2
3
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
AD9650BCPZ-25
Min
Typ
Max
AD9650BCPZ-65
Min Typ
Max
83
81.5
AD9650BCPZ-80
Min Typ
Max
83
82
81.8
AD9650BCPZ-105
Min Typ
Max
83
82
81.5
82.5
82
81.6
dBFS
dBFS
dBFS
dBFS
dBFS
80.5
79.5
81
79.5
81
80
80
80
82.2
80
82
81.2
82
82
82
80.4
Unit
78
79.2
75
78.5
75.1
78.8
75.5
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
13.5
13.0
12.7
13.5
13.2
13.0
12.9
13.5
13.2
13.0
13.0
13.3
13.2
13.0
12.3
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−95
−85
−94
−93
−95.5
−92
−91
−90
−87
−86
−79
−86
−79
−92
−80
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
95
85
94
93
95.5
92
91
90
81.5
81
80.7
−91.5
91.5
80
−88
88
−87
87
−87
87
87
86
79
86
79
92
80
25°C
25°C
Full
25°C
25°C
−110
−102
−105
−105
−105
−105
−100
−101
25°C
87
25°C
84
25°C
Full
25°C
−97
−97
−97
−97
−97
−88
dBc
dBc
dBc
dBc
dBc
90
87
87
dBc
83
83
84
dBc
−105
500
−105
500
−105
500
dBFS
MHz
−97
−97
−105
500
−97
−97
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Measurements made with a divide-by-4 clock rate to minimize the effects of clock jitter on the SNR performance.
Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 4 of 44
dBc
dBc
dBc
dBc
dBc
−94
AD9650
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (OEB, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
CMOS/LVDS/LVPECL
0.9
0.3
AGND
0.9
−100
−100
8
3.6
AVDD
1.4
+100
+100
9
10
12
CMOS
0.9
AGND
1.2
AGND
−100
−100
12
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
AVDD
AVDD
0.6
+100
+100
1
16
20
V
V
V
V
μA
μA
pF
kΩ
V
V
μA
μA
kΩ
pF
2.1
0.6
−135
+10
V
V
μA
μA
kΩ
pF
2.1
0.6
+10
128
V
V
μA
μA
kΩ
pF
2.1
0.6
−134
+10
V
V
μA
μA
kΩ
pF
26
2
26
5
Rev. 0 | Page 5 of 44
V
V p-p
V
V
μA
μA
pF
kΩ
2.1
0.6
+10
132
26
2
26
5
Unit
AD9650
Parameter
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
1
2
Temperature
Min
Full
Full
1.79
1.75
Typ
290
1.15
160
1.15
Pull up.
Pull down.
Rev. 0 | Page 6 of 44
Unit
V
V
Full
Full
Full
Full
Full
Full
Max
345
1.25
200
1.25
0.2
0.05
V
V
400
1.35
230
1.35
mV
V
mV
V
AD9650
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate 1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1
Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS
Enabled
Divide-by-1 Mode, DCS
Disabled
Divide-by-2 Mode
Through Divide-by-8
Mode
Aperture Delay (tA)
Aperture Uncertainty
(Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay
(tPD)
DCO Propagation Delay
(tDCO) 2
DCO to Data Skew (tSKEW)
LVDS Mode
Data Propagation Delay
(tPD)
DCO Propagation Delay
(tDCO)2
DCO to Data Skew (tSKEW)
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay
(Latency) Channel A/
Channel B
Wake-Up Time 3
Out-of-Range Recovery
Time
Temp
AD9650BCPZ-25
Min
Typ
Max
Full
200
Full
Full
Full
20
10
40
Full
12
Full
19
Full
0.8
Full
Full
Full
AD9650BCPZ-65
Min
Typ
Max
520
25
25
20
10
15.4
20
28
4.65
20
21
7.33
Full
3.5
20
10
12.5
7.70
10.75
3.75
7.70
8.07
5.95
2.8
3.1
3.5
2.8
3.1
640
MHz
105
105
MSPS
MSPS
ns
20
10
9.5
6.25
8.75
2.85
4.75
6.65
ns
6.25
6.55
4.5
4.75
5.0
ns
0.8
1.0
0.080
4.2
Unit
80
80
0.8
1.0
0.090
4.2
AD9650BCPZ-105
Min Typ
Max
640
65
65
0.8
1.0
0.100
2.8
AD9650BCPZ-80
Min Typ
Max
3.5
ns
1.0
0.075
4.2
2.8
3.1
3.5
ns
ps rms
4.2
3.1
ns
ns
Full
−0.6
−0.4
0
−0.6
−0.4
0
−0.6
−0.4
0
−0.6
−0.4
0
ns
Full
2.9
3.7
4.5
2.9
3.7
4.5
2.9
3.7
4.5
2.9
3.7
4.5
ns
Full
Full
Full
3.9
−0.1
+0.2
12
3.9
+0.5
−0.1
+0.2
12
3.9
+0.5
−0.1
+0.2
12
3.9
+0.5
−0.1
+0.2
12
ns
+0.5
ns
Cycles
Full
12/12.5
12/12.5
12/12.5
12/12.5
Cycles
Full
Full
500
2
500
2
500
2
500
2
μs
Cycles
1
Conversion rate is the clock rate after the divider.
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
3
Wake-up time is defined as the time required to return to normal operation from power-down mode.
2
Rev. 0 | Page 7 of 44
AD9650
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS 1
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
1
Conditions
Limit
Unit
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
0.3
0.40
ns typ
ns typ
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge
2
2
40
2
2
10
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
10
ns min
See Figure 93.
Timing Diagrams
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
CH A/CH B DATA
N – 13
N – 12
N – 11
N – 10
N–9
N–8
tPD
08919-002
tSKEW
Figure 2. CMOS Default Output Mode Data Output Timing
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
CH A/CH B DATA
CH A CH B CH A
CH B CH A CH B
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10
Figure 3. CMOS Interleaved Output Mode Data Output Timing
Rev. 0 | Page 8 of 44
CH A
N–9
CH B
N–9
CH A
N–8
08919-003
tSKEW
tPD
AD9650
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
CH A CH B CH A CH B CH A CH B
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10
CH A/CH B DATA
CH A
N–9
CH B
N–9
Figure 4. LVDS Mode Data Output Timing
CLK+
tHSYNC
08919-004
tSSYNC
SYNC
Figure 5. SYNC Input Timing Requirements
Rev. 0 | Page 9 of 44
CH A
N–8
08919-003
tSKEW
tPD
AD9650
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical1
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB
PDWN
D0A/D0B Through D15A/D15B to
AGND
DCOA/DCOB to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
1
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−40°C to +85°C
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints and maximizes the
thermal capability of the package.
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces θJA.
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
(CP-64-6)
Airflow
Velocity (m/sec)
0
1.0
2.5
1
θJA1, 2
18.5
16.1
14.5
θJC1, 3
1.0
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-STD 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
ESD CAUTION
150°C
−65°C to +150°C
The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) +
0.2 V but should not exceed 2.1 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 10 of 44
θJB1, 4
9.2
Unit
°C/W
°C/W
°C/W
AD9650
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9650
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D15A
D14A
D13A
D12A
D11A
DRVDD
D10A
D9A
D8A
D7A
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
08919-005
D12B
D13B
DRVDD
D14B
D15B
ORB
DCOB
DCOA
D0A
D1A
D2A
DRVDD
D3A
D4A
D5A
D6A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK+
CLK–
SYNC
D0B
D1B
D2B
D3B
D4B
D5B
DRVDD
D6B
D7B
D8B
D9B
D10B
D11B
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
ADC Power Supplies
10, 19, 28, 37
49, 50, 53, 54, 59,
60, 63, 64
0
ADC Analog
51
52
62
61
55
56
58
57
1
2
Digital Input
3
Digital Outputs
25
26
27
29
30
31
32
Mnemonic
Type
Description
DRVDD
AVDD
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for proper
operation.
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
Input
Input
Input
Input
Input/output
Input
Input/output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
SYNC
Input
Digital Synchronization Pin. Slave mode only.
D0A
D1A
D2A
D3A
D4A
D5A
D6A
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data (LSB).
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Rev. 0 | Page 11 of 44
AD9650
Pin No.
33
34
35
36
38
39
40
41
42
43
4
5
6
7
8
9
11
12
13
14
15
16
17
18
20
21
22
24
23
SPI Control
45
44
46
ADC Configuration
47
48
Mnemonic
D7A
D8A
D9A
D10A
D11A
D12A
D13A
D14A
D15A
ORA
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
D12B
D13B
D14B
D15B
ORB
DCOA
DCOB
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data (MSB).
Channel A Overrange Output.
Channel B CMOS Output Data (LSB).
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data (MSB).
Channel B Overrange Output
Channel A Data Clock Output.
Channel B Data Clock Output.
SCLK/DFS
SDIO/DCS
CSB
Input
Input/output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Rev. 0 | Page 12 of 44
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
AD9650
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9650
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
OR+
OR–
D15+
D15–
D14+
D14–
DRVDD
D13+
D13–
D12+
D12–
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
08919-006
D6–
D6+
DRVDD
D7–
D7+
D8–
D8+
DCO–
DCO+
D9–
D9+
DRVDD
D10–
D10+
D11–
D11+
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK+
CLK–
SYNC
D0–
D0+
D1–
D1+
D2–
D2+
DRVDD
D3–
D3+
D4–
D4+
D5–
D5+
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
ADC Power Supplies
10, 19, 28, 37
49, 50, 53, 54, 59,
60, 63, 64
0
ADC Analog
51
52
62
61
55
56
58
57
1
2
Digital Input
3
Digital Outputs
5
4
7
6
9
8
12
Mnemonic
Type
Description
DRVDD
AVDD
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for proper
operation.
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
Input
Input
Input
Input
Input/output
Input
Input/output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
SYNC
Input
Digital Synchronization Pin. Slave mode only.
D0+
D0−
D1+
D1−
D2+
D2−
D3+
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True (LSB).
Channel A/Channel B LVDS Output Data 0—Complement (LSB).
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Rev. 0 | Page 13 of 44
AD9650
Pin No.
11
14
13
16
15
18
17
21
20
23
22
27
26
30
29
32
31
34
33
36
35
39
38
41
40
43
42
25
24
SPI Control
45
44
46
ADC Configuration
47
48
Mnemonic
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
D10+
D10−
D11+
D11−
D12+
D12−
D13+
D13−
D14+
D14−
D15+
D15−
OR+
OR−
DCO+
DCO−
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Output Data 12—True.
Channel A/Channel B LVDS Output Data 12—Complement.
Channel A/Channel B LVDS Output Data 13—True.
Channel A/Channel B LVDS Output Data 13—Complement.
Channel A/Channel B LVDS Output Data 14—True.
Channel A/Channel B LVDS Output Data 14—Complement.
Channel A/Channel B LVDS Output Data 15—True (MSB).
Channel A/Channel B LVDS Output Data 15—Complement (MSB).
Channel A/Channel B LVDS Overrange Output—True.
Channel A/Channel B LVDS Overrange Output—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
SCLK/DFS
SDIO/DCS
CSB
Input
Input/output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Rev. 0 | Page 14 of 44
AD9650
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS disabled, 1.35 V internal reference, 2.7 V p-p differential input, VIN = −1.0 dBFS,
and 32k sample, TA = 25°C, unless otherwise noted.
AD9650-25
0
–20
25MSPS
9.7MHz @ –6dBFS
–20 SNR = 77.9dB (83.9dBFS)
SFDR = 99dBc
–40
AMPLITUDE (dBFS)
–60
–80
–100
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 8. AD9650-25 Single-Tone FFT with fIN = 9.7 MHz
0
2
4
6
8
10
12
Figure 11. AD9650-25 Single-Tone FFT with fIN = 9.7 MHz at −6 dBFS with
Dither Disabled
0
25MSPS
9.7MHz @ –6dBFS
–20 SNR = 77.4dB (83.4dBFS)
SFDR = 101.3dBc
–40
AMPLITUDE (dBFS)
–60
–80
–100
–40
–60
–80
–100
–120
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 9. AD9650-25 Single-Tone FFT with fIN = 30.3 MHz
0
–140
08919-109
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 12. AD9650-25 Single-Tone FFT with fIN = 9.7 MHz at −6 dBFS with
Dither Enabled
120
25MSPS
70.1MHz @ –1dBFS
SNR = 78.5dB (79.5dBFS)
SFDR = 87.2dBFS
–20
0
08919-112
AMPLITUDE (dBFS)
0
FREQUENCY (MHz)
–120
SFDR (dBFS)
100
SNR (dBFS)
–40
SNR/SFDR
80
–60
–80
60
SFDR (dBc)
40
–100
20
–120
SNR (dB)
–140
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 10. AD9650-25 Single-Tone FFT with fIN = 70.1 MHz
0
–100
08919-110
AMPLITUDE (dBFS)
–100
–140
25MSPS
30.3MHz @ –1dBFS
SNR = 80.6dB (81.6dBFS)
SFDR = 84.6dBc
–20
–140
–80
–120
08919-108
–140
–60
08919-111
–120
–40
–90
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
0
08919-113
AMPLITUDE (dBFS)
0
25MSPS
9.7MHz @ –1dBFS
SNR = 82.4dB (83.4dBFS)
SFDR = 95.8dBc
Figure 13. AD9650-25 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 9.7 MHz
Rev. 0 | Page 15 of 44
AD9650
1400000
120
SFDR (dBFS) DITHER ON
115
1200000
110
1000000
NUMBER OF HITS
SNR/SFDR (dBFS)
105
SFDR (dBFS) DITHER OFF
100
95
90
SNR (dBFS) DITHER OFF
85
800000
600000
400000
SNR (dBFS) DITHER ON
80
200000
95
N–7
08919-118
N–6
N–5
OUTPUT CODE
Figure 17. AD9650-25 Grounded Input Histogram
Figure 14. AD9650-25 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 9.7 MHz with and Without Dither Enabled
100
N–4
INPUT AMPLITUDE (dBFS)
0
N–3
0
N–2
–10
N
–20
N–1
–30
N+1
–40
N+2
–50
N+3
–60
N+4
–70
N+5
–80
N+6
–90
08919-114
70
–100
N+7
75
120
6
100
4
80
2
DITHER DISABLED
DITHER ENABLED
0
50
0
–2
SNR
20
100
150
200
–4
0
300
250
–6
INPUT FREQUENCY (MHz)
0
20000
30000
40000
50000
60000
OUTPUT CODE
Figure 18. AD9650-25 INL with fIN = 9.7 MHz
Figure 15. AD9650-25 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
with 2.7 V p-p Full Scale
105
2.0
1.5
100
1.0
DNL ERROR (LSB)
95
SFDR (dBc)
90
85
SNR (dBFS)
0.5
0
–0.5
–1.0
80
75
10
15
20
25
30
35
40
45
50
SAMPLE RATE (MSPS)
Figure 16. AD9650-25 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 9.7 MHz
–2.0
0
10000
20000
30000
40000
50000
OUTPUT CODE
Figure 19. AD9650-25 DNL with fIN = 9.7 MHz
Rev. 0 | Page 16 of 44
60000
08919-120
–1.5
08919-216
SNR (dBFS), SFDR (dBc)
10000
08919-119
70
65
40
SNR (–40°C)
SNR (+25°C)
SNR (+85°C)
SFDR (–40°C)
SFDR (+25°C)
SFDR (+85°C)
75
SFDR (dBc)
60
80
08919-115
SNR (dBFS)
SFDR
85
INL ERROR (LSB)
90
AD9650
400
350
TOTAL POWER LVDS (mW)
300
250
TOTAL POWER CMOS (mW)
200
LVDS AND CMOS IAVDD (mA)
150
100
LVDS IDRVDD (mA)
50
0
10
CMOS IDRVDD (mA)
15
20
25
30
35
40
45
SAMPLE RATE (MSPS)
50
08919-121
TOTAL POWER (mW), CURRENT (mA)
450
Figure 20. AD9650-25 Power and Current vs. Sample Rate
Rev. 0 | Page 17 of 44
AD9650
AD9650-65
0
–20
–40
–60
–80
–100
5
10
15
20
25
30
–80
–100
–140
08919-122
0
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 21. AD9650-65 Single-Tone FFT with fIN = 9.7 MHz
Figure 24. AD9650-65 Single-Tone FFT with fIN = 141 MHz
0
0
65MSPS
30.3MHz @ –1dBFS
SNR = 81.5dB (82.5dBFS)
SFDR = 93.5dBc
–20
–40
–60
–80
–100
–60
–80
–100
10
15
20
25
30
5
10
15
20
25
30
FREQUENCY (MHz)
0
65MSPS
70.1MHz @ –1dBFS
SNR = 80.4dB (81.4dBFS)
SFDR = 86dBc
–20
0
Figure 25. AD9650-65 Single-Tone FFT with fIN = 30.3 MHz at −6 dBFS with
Dither Disabled
Figure 22. AD9650-65 Single-Tone FFT with fIN = 30.3 MHz
0
–140
08919-126
5
08919-123
0
FREQUENCY (MHz)
65MSPS
30.3MHz @ –6dBFS
SNR = 76.9dB (82.9dBFS)
SFDR = 100dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–40
–60
–80
–100
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 23. AD9650-65 Single-Tone FFT with fIN = 70.1 MHz
–140
0
5
10
15
20
FREQUENCY (MHz)
25
30
08919-127
–120
08919-124
–140
–40
–120
–120
–140
65MSPS
30.3MHz @ –6dBFS
SNR = 77.3dB (83.3dBFS)
SFDR = 96.2dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–60
–120
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–40
08919-125
–120
–140
65MSPS
141MHz @ –1dBFS
SNR = 78.5dB (79.5dBFS)
SFDR = 79.2dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
65MSPS
9.7MHz @ –1dBFS
SNR = 82.1dB (83.1dBFS)
SFDR = 98.7dBc
Figure 26. AD9650-65 Single-Tone FFT with fIN = 30.3 MHz @ −6 dBFS with
Dither Enabled
Rev. 0 | Page 18 of 44
AD9650
120
105
SFDR (dBFS)
100
100
SNR (dBFS), SFDR (dBc)
SNR (dBFS)
60
SFDR (dBc)
SNR (dB)
40
95
SFDR
90
85
SNR
80
20
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
75
45
08919-128
0
–100
50
55
60
65
70
75
80
08919-230
SNR/SFDR
80
85
SAMPLE RATE (MSPS)
Figure 30. AD9650-65 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 30 MHz
Figure 27. AD9650-65 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN =30.3 MHz
1400000
120
SFDR (dBFS) DITHER ON
115
1200000
1000000
105
NUMBER OF HITS
SNR/SFDR (dBFS)
110
100
95
SFDR (dBFS) DITHER OFF
90
SNR (dBFS) DITHER OFF
85
800000
600000
400000
SNR (dBFS) DITHER ON
80
200000
SFDR
50
80
40
SNR (–40°C)
SFDR (–40°C)
SNR (+25°C)
SFDR (+25°C)
SNR (+85°C)
SFDR (+85°C)
70
0
50
100
30
SNR
20
N–7
08919-133
2
0
–2
–4
10
150
200
250
0
300
INPUT FREQUENCY (MHz)
Figure 29. AD9650-65 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
with 2.7 V p-p Full Scale
Rev. 0 | Page 19 of 44
–6
0
10000
20000
30000
40000
50000
OUTPUT CODE
Figure 32. AD9650-65 INL with fIN = 9.7 MHz
60000
08919-134
75
SFDR (dBc)
85
INL ERROR (LSB)
70
60
N–6
4
80
08919-130
SNR (dBFS)
DITHER DISABLED
DITHER ENABLED
90
90
65
6
100
95
N–5
OUTPUT CODE
Figure 31. AD9650-65 Grounded Input Histogram
Figure 28. AD9650-65 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 30.3 MHz with and Without Dither Enabled
100
N–4
INPUT AMPLITUDE (dBFS)
N–3
0
N–2
–10
N–1
–20
N
–30
N+1
–40
N+2
–50
N+3
–60
N+4
–70
N+5
–80
N+6
0
–90
08919-129
70
–100
N+7
75
AD9650
700
1.5
600
0.5
0
–0.5
–1.0
–1.5
–2.0
0
10000
20000
30000
40000
50000
OUTPUT CODE
60000
08919-135
DNL ERROR (LSB)
1.0
TOTAL POWER LVDS (mW)
500
400
TOTAL POWER CMOS (mW)
300
LVDS AND CMOS IAVDD (mA)
200
100
0
25
CMOS IDRVDD (mA)
LVDS IDRVDD (mA)
35
45
55
65
75
85
95
SAMPLE RATE (MSPS)
Figure 34. AD9650-65 Power and Current vs. Sample Rate
Figure 33. AD9650-65 DNL with fIN = 9.7 MHz
Rev. 0 | Page 20 of 44
105
08919-234
TOTAL POWER (mW)/CURRENT (mA)
2.0
AD9650
AD9650-80
0
–20
–40
–60
–80
–100
–120
–80
–100
5
10
15
20
25
30
35
40
–140
0
5
10
15
20
25
30
35
Figure 38. AD9650-80 Single-Tone FFT with fIN = 141 MHz
0
0
80MSPS
30.3MHz @ –1dBFS
SNR = 81.8dB (82.8dBFS)
SFDR = 94.5dBc
AMPLITUDE (dBFS)
–60
–80
–100
–120
–60
–80
–100
5
10
15
20
25
30
35
40
Figure 36. AD9650-80 Single-Tone FFT with fIN = 30.3 MHz
0
–140
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
Figure 39. AD9650-80 Single-Tone FFT with fIN = 30.3 MHz at −6 dBFS with
Dither Disabled
0
80MSPS
70.1MHz @ –1dBFS
SNR = 80dB (81dBFS)
SFDR = 86.4dBc
–20
0
08919-141
0
FREQUENCY (MHz)
80MSPS
30.3MHz @ –6dBFS
SNR = 77dB (83dBFS)
SFDR = 98.4dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–40
–60
–80
–100
5
10
15
20
25
30
35
FREQUENCY (MHz)
Figure 37. AD9650-80 Single-Tone FFT with fIN = 70.1 MHz
40
–140
08919-139
0
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
08919-142
–120
–120
–140
–40
–120
08919-138
–140
80MSPS
30.3MHz @ –6dBFS
SNR = 77.3dB (83.3dBFS)
SFDR = 94.3dBc
–20
–40
40
FREQUENCY (MHz)
Figure 35. AD9650-80 Single-Tone FFT with fIN = 9.7 MHz
–20
AMPLITUDE (dBFS)
–60
08919-140
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–40
–120
08919-137
–140
80MSPS
141MHz @ –1dBFS
SNR = 79.3dB (80.3dBFS)
SFDR = 79.2dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
80MSPS
9.7MHz @ –1dBFS
SNR = 82.2dB (83.2dBFS)
SFDR = 95.8dBc
Figure 40. AD9650-80 Single-Tone FFT with fIN = 30.3 MHz at −6 dBFS with
Dither Enabled
Rev. 0 | Page 21 of 44
AD9650
120
105
SFDR (dBFS)
100
100
SNR (dBFS), SFDR (dBc)
SNR (dBFS)
SNR/SFDR
80
60
SFDR (dBc)
SNR (dB)
40
95
SFDR
90
85
SNR
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
75
60
08919-143
0
–100
65
70
75
80
85
90
95
08919-146
80
20
100
SAMPLE RATE (MSPS)
Figure 44. AD9650-80 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 30 MHz
Figure 41. AD9650-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 30.3 MHz
1400000
120
SFDR (dBFS) DITHER ON
1200000
100
NUMBER OF HITS
1000000
SNR/SFDR (dBFS)
80
SFDR (dBFS) DITHER OFF
60
40
SNR (dBFS) DITHER OFF
800000
900000
600000
SNR (dBFS) DITHER ON
20
100
4
80
2
60
80
SNR (–40°C)
SFDR (–40°C)
SNR (+25°C)
SFDR (+25°C)
SNR (+85°C)
SFDR (+85°C)
75
70
40
SNR
0
50
100
150
200
250
N–7
08919-148
N–6
0
–2
–4
20
65
DITHER DISABLED
DITHER ENABLED
0
300
INPUT FREQUENCY (MHz)
Figure 43. AD9650-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
Rev. 0 | Page 22 of 44
–6
0
10000
20000
30000
40000
50000
OUTPUT CODE
Figure 46. AD9650-80 INL with fIN = 9.7 MHz
60000
08919-149
85
INL ERROR (LSB)
SFDR
6
08919-145
SNR (dBFS)
90
120
SFDR (dBc)
95
N–5
OUTPUT CODE
Figure 45. AD9650-80 Grounded Input Histogram
Figure 42. AD9650-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 30.3 MHz with and Without Dither Enabled
100
N–4
INPUT AMPLITUDE (dBFS)
N–3
0
N–2
–10
N
–20
N–1
–30
N+1
–40
N+2
–50
N+3
–60
N+4
–70
N+5
–80
N+6
0
–90
08919-144
0
–100
N+7
200000
AD9650
800
1.5
700
0.5
0
–0.5
–1.0
–1.5
–2.0
0
10000
20000
30000
40000
50000
OUTPUT CODE
60000
600
500
TOTAL POWER CMOS (mW)
400
LVDS AND CMOS IAVDD (mA)
300
200
LVDS IDRVDD (mA)
CMOS IDRVDD (mA)
100
0
25
08919-150
DNL ERROR (LSB)
1.0
TOTAL POWER
LVDS (mW)
35
45
55
65
75
85
95
105
115
SAMPLE RATE (MSPS)
Figure 48. AD9650-80 Power and Current vs. Sample Rate
Figure 47. AD9650-80 DNL with fIN = 9.7 MHz
Rev. 0 | Page 23 of 44
125
08919-248
TOTAL POWER (mW)/CURRENT (mA)
2.0
AD9650
AD9650-105
0
–20
–40
–60
–80
–100
10
20
30
40
50
0
0
10
20
30
40
50
Figure 52. AD9650-105 Single-Tone FFT with fIN = 141 MHz
0
105MSPS
30.3MHz @ –6dBFS
SNR = 77.3dB (83.3dBFS)
SFDR = 94dBc
–20
–40
AMPLITUDE (dBFS)
–60
–80
–100
–60
–80
–100
–120
10
20
30
40
50
FREQUENCY (MHz)
Figure 50. AD9650-105 Single-Tone FFT with fIN = 30.3 MHz
0
–140
08919-153
0
10
20
30
40
50
FREQUENCY (MHz)
Figure 53. AD9650-105 Single-Tone FFT with fIN = 30.3 MHz @ −6 dBFS
with Dither Disabled
0
105MSPS
70.1MHz @ –1dBFS
SNR = 79.2dB (80.2dBFS)
SFDR = 92.2dBc
–20
0
08919-156
–120
–40
105MSPS
30.3MHz @ –6dBFS
SNR = 75.7dB (81.7dBFS)
SFDR = 96.2dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–40
–60
–80
–100
–120
10
20
30
40
50
FREQUENCY (MHz)
Figure 51. AD9650-105 Single-Tone FFT with fIN = 70.1 MHz
–140
08919-154
0
0
10
20
30
FREQUENCY (MHz)
40
50
08919-157
AMPLITUDE (dBFS)
–100
FREQUENCY (MHz)
105MSPS
30.3MHz @ –1dBFS
SNR = 81.2dB (82.2dBFS)
SFDR = 90.3dBc
–20
AMPLITUDE (dBFS)
–80
–140
08919-152
0
Figure 49. AD9650-105 Single-Tone FFT with fIN = 9.7 MHz
–140
–60
–120
FREQUENCY (MHz)
–140
–40
08919-155
–120
–140
105MSPS
141MHz @ –1dBFS
SNR = 79dB (80dBFS)
SFDR = 81.1dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
105MSPS
9.7MHz @ –1dBFS
SNR = 81.7dB (82.7dBFS)
SFDR = 90.7dBc
Figure 54. AD9650-105 Single-Tone FFT with fIN = 30.3 MHz @ −6 dBFS
with Dither Enabled
Rev. 0 | Page 24 of 44
AD9650
105
120
SFDR (dBFS)
100
100
SNR (dBFS), SFDR (dBc)
SNR (dBFS)
60
SFDR (dBc)
SNR (dB)
40
95
SFDR
90
85
80
20
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
75
85
08919-158
0
–100
SNR
95
100
105
110
115
120
125
SAMPLE RATE (MSPS)
Figure 58. AD9650-105 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 30 MHz
Figure 55. AD9650-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 30.3 MHz
0
120
SFDR (dBFS) DITHER ON
115
90
08919-258
SNR/SFDR
80
105MSPS
30.8MHz @ –7dBFS
25.4MHz @ –7dBFS
SFDR = 86.6dBc (93.6dBFS)
–20
AMPLITUDE (dBFS)
110
SNR/SFDR (dBFS)
105
100
SFDR (dBFS) DITHER OFF
95
90
85
80
SNR (dBFS) DITHER OFF
SNR (dBFS) DITHER ON
–40
–60
–80
–100
–120
–140
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
–40
SNR (–40°C)
SFDR (–40°C)
SNR (+25°C)
SFDR (+25°C)
SNR (+85°C)
SFDR (+85°C)
75
70
0
50
100
SFDR/IMD3
40
SFDR (dBc)
50
30
SNR
IMD3 (dBc)
–60
–80
–100
SFDR (dBFS)
20
–120
10
150
200
250
IMD3 (dBFS)
0
300
–140
–90
08919-160
SNR (dBFS)
60
80
65
SFDR (dBc)
70
85
50
40
–20
80
90
30
0
90
SFDR
20
Figure 59. AD9650-105 Two-Tone FFT with fIN1 = 25.4 MHz and fIN2 = 30.8 MHz
100
95
10
FREQUENCY (MHz)
Figure 56. AD9650-105 Single Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 30.3 MHz with and Without Dither Enabled
100
0
INPUT FREQUENCY (MHz)
Figure 57. AD9650-105 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
08919-163
–90
08919-159
70
–100
08919-162
75
Figure 60. AD9650-105 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 25.4 MHz, fIN2 = 30.8 MHz, fS = 105 MSPS
Rev. 0 | Page 25 of 44
AD9650
0
–20
1000000
–40
NUMBER OF HITS
–60
–80
800000
600000
400000
–100
N–8
08919-168
N–7
N–6
N–5
N–4
N–3
N–2
N
N–1
N+1
FREQUENCY (MHz)
0
N+2
50
40
N+3
30
N+4
20
N+5
10
N+6
0
08919-164
–140
N+7
200000
–120
N+8
AMPLITUDE (dBFS)
1200000
105MSPS
124.8MHz @ –7dBFS
128.3MHz @ –7dBFS
SFDR = 83.8dBc
OUTPUT CODE
Figure 64. AD9650-105 Grounded Input Histogram
Figure 61. AD9650-105 Two-Tone FFT with fIN1 = 124.8 MHz and fIN2 = 128.3 MHz
0
6
–20
DITHER DISABLED
DITHER ENABLED
4
SFDR (dBc)
INL ERROR (LSB)
SFDR/IMD3
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
2
0
–2
–4
–120
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBFS)
–6
08919-165
0
30000
40000
50000
60000
Figure 65. AD9650-105 INL with fIN = 9.7 MHz
900
2.0
TOTAL POWER LVDS (mW)
800
1.5
TOTAL POWER CMOS (mW)
700
1.0
DNL ERROR (LSB)
600
500
400
300
LVDS AND CMOS IAVDD (mA)
CMOS IDRVDD (mA)
LVDS IDRVDD (mA)
100
45
65
85
105
125
0.5
0
–0.5
–1.0
200
–1.5
145
SAMPLE RATE (MSPS)
08919-263
TOTAL POWER (mW)/CURRENT (mA)
20000
OUTPUT CODE
Figure 62. AD9650-105 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 128.3 MHz, fIN2 = 124.8 MHz, fs = 105 MSPS
0
25
10000
–2.0
0
10000
20000
30000
40000
50000
OUTPUT CODE
Figure 66. AD9650-105 DNL with fIN = 9.7 MHz
Figure 63. AD9650-105 Power and Current vs. Sample Rate
Rev. 0 | Page 26 of 44
60000
08919-170
–140
–90
08919-169
IMD3 (dBFS)
AD9650
100
TYPICAL VCM
SNR (dBFS)
90
SFDR (dBc)
70
60
50
40
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
COMMON-MODE VOLTAGE (V)
1.20
08919-171
SNR/SFDR
80
Figure 67. SNR/SFDR vs. Input Common Mode (VCM)
with fIN = 30.3 MHz
Rev. 0 | Page 27 of 44
AD9650
EQUIVALENT CIRCUITS
AVDD
VIN±x
350Ω
08919-012
08919-007
SENSE
Figure 68. Equivalent Analog Input Circuit
Figure 73. Equivalent SENSE Circuit
AVDD
DRVDD
0.9V
CLK–
350Ω
CSB
08919-008
CLK+
26kΩ
10kΩ
08919-013
10kΩ
Figure 69. Equivalent Clock Input Circuit
Figure 74. Equivalent CSB Input Circuit
AVDD
DRVDD
VREF
PAD
08919-009
08919-014
6kΩ
Figure 75. Equivalent VREF Circuit
Figure 70. Digital Output
DRVDD
26kΩ
350Ω
SDIO/DCS
PDWN
350Ω
Figure 71. Equivalent SDIO/DCS Circuit
Figure 76. Equivalent PDWN Input Circuit
DRVDD
SCLK/DFS
OR OEB
08919-015
08919-010
26kΩ
350Ω
08919-011
26kΩ
Figure 72. Equivalent SCLK/DFS or OEB Input Circuit
Rev. 0 | Page 28 of 44
AD9650
THEORY OF OPERATION
The AD9650 dual-core analog-to-digital converter (ADC) is
used for digitizing high frequency, wide dynamic range signals with
input frequencies of up to 300 MHz. The user can sample any fS/2
frequency segment from dc to 300 MHz using appropriate lowpass or band-pass filtering at the ADC inputs with little loss in
ADC performance. The ADCs can also be operated with
independent analog inputs.
In quadrature applications, the AD9650 can be used as a baseband
or direct down-conversion receiver, in which one ADC is used
for I input data, and the other is used for Q input data.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9650 are accomplished
using a 3-wire, SPI-compatible serial interface.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the inputs
to provide dynamic charging currents. This passive network
creates a low-pass filter at the ADC input; therefore, the precise
values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to the AN-742 Application Note, Frequency
Domain Response of Switched-Capacitor ADCs; the AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject (visit www.analog.com).
BIAS
ADC ARCHITECTURE
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing digital output noise to
be separated from the analog core. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9650 is a differential switchedcapacitor circuit that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see Figure 77). When the input is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within ½ of a clock cycle.
S
S
CFB
CS
VIN+x
CPAR1
CPAR2
H
S
S
CS
VIN–x
CPAR1
CPAR2
S
S
CFB
BIAS
08919-034
The AD9650 architecture consists of a dual front-end sampleand-hold circuit, followed by a pipelined, switched-capacitor
ADC. The quantized outputs from each stage are combined into
a final 16-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Figure 77. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+x and VIN−x should be matched, and the inputs should
be differentially balanced.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9650 are not internally dc biased.
In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is
recommended for optimum performance, but the device
functions over a wider range with reasonable performance
(see Figure 67). An on-chip, common-mode voltage reference
is included in the design and is available from the VCM pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCM pin voltage
(typically 0.5 × AVDD). The VCM pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section.
Rev. 0 | Page 29 of 44
AD9650
Common-Mode Voltage Servo
In applications where there may be a voltage loss between the VCM
output of the AD9650 and the analog inputs, the common-mode
voltage servo can be enabled. When the inputs are ac-coupled and
a resistance of >100 Ω is placed between the VCM output and the
analog inputs, a significant voltage drop can occur and the
common-mode voltage servo should be enabled. Setting Bit 0 in
Register 0x0F to a logic high enables the VCM servo mode. In
this mode, the AD9650 monitors the common-mode input level
at the analog inputs and adjusts the VCM output level to keep the
common-mode input voltage at an optimal level. If both channels
are operational, Channel A is monitored. However, if Channel A
is in power-down or standby mode, the Channel B input is
monitored.
Dither
The AD9650 has an optional dither mode that can be selected
for one or both channels. Dithering is the act of injecting a known
but random amount of white noise, commonly referred to as
dither, into the input of the ADC. Dithering has the effect of
improving the local linearity at various points along the ADC
transfer function. Dithering can significantly improve the SFDR
when quantizing small-signal inputs, typically when the input
level is below −6 dBFS.
As shown in Figure 78, the dither that is added to the input of
the ADC through the dither DAC is precisely subtracted out
digitally to minimize SNR degradation. When dithering is
enabled, the dither DAC is driven by a pseudorandom number
generator (PN gen). In the AD9650, the dither DAC is precisely
calibrated to result in only a very small degradation in SNR and
SINAD.
typically at very low levels and do not limit SFDR when the
ADC is quantizing large-signal inputs, dithering converts these
tones to noise and produces a whiter noise floor.
Small-Signal FFT
For small-signal inputs, the front-end sampling circuit typically
contributes very little distortion, and, therefore, the SFDR is likely
to be limited by tones caused by DNL errors due to random component mismatches. Therefore, for small-signal inputs (typically,
those below −6 dBFS), dithering can significantly improve
SFDR by converting these DNL tones to white noise.
Static Linearity
Dithering also removes sharp local discontinuities in the INL
transfer function of the ADC and reduces the overall peak-topeak INL.
In receiver applications, utilizing dither helps to reduce DNL errors
that cause small-signal gain errors. Often this issue is overcome
by setting the input noise 5 dB to 10 dB above the converter
noise. By using dither within the converter to correct the DNL
errors, the input noise requirement can be reduced.
Differential Input Configurations
Optimum performance is achieved while driving the AD9650
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9650 (see Figure 79), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
15pF
AD9650
200Ω
ADC CORE
DOUT
76.8Ω
VIN
33Ω
90Ω
15Ω
5pF
33Ω
15Ω
120Ω
Figure 78. Dither Block Diagram
Large-Signal FFT
In most cases, dithering does not improve SFDR for large-signal
inputs close to full scale, for example, with a −1 dBFS input. For
large-signal inputs, the SFDR is typically limited by front-end
sampling distortion, which dithering cannot improve. However,
even for such large-signal inputs, dithering may be useful for
certain applications because it makes the noise floor whiter.
As is common in pipeline ADCs, the AD9650 contains small
DNL errors caused by random component mismatches that
produce spurs or tones that make the noise floor somewhat
randomly colored part-to-part. Although these tones are
VIN+x
VCM
15pF
200Ω
08919-035
DITHER ENABLE
08919-058
PN GEN
0.1µF
AVDD
AD9650
ADA4938-2
DITHER
DAC
VIN–x
Figure 79. Differential Input Configuration Using the ADA4938-2
For baseband applications in which SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 80. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
C2
R2
VIN+x
R1
2V p-p
49.9Ω
AD9650
C1
R1
0.1µF
R2
VIN–x
VCM
C2
Figure 80. Differential Transformer-Coupled Configuration
Rev. 0 | Page 30 of 44
08919-036
VIN
AD9650
achieved by using a ferrite bead in series with a resistor and
removing the capacitors. However, these values are dependent
on the input signal and should be used only as a starting guide.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
Table 10. Example RC Network
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9650. For applications in
which SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 81). In this
configuration, the input is ac-coupled, and the CML is provided
to each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
Frequency
Range
(MHz)
0 to 100
100 to 200
100 to 300
1
R1 Series
(Ω Each)
33
10
101
C1 Differential
(pF)
5
5
Remove
R2 Series
(Ω Each)
15
10
66
In this configuration, R1 is a ferrite bead with a value of 10 Ω at 100 MHz.
An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352
differential driver. An example is shown in Figure 82. See the
AD8352 data sheet for more information.
In the double balun and transformer configurations, the value of
the input capacitors and resistors is dependent on the input frequency and source impedance and may need to be reduced or
removed. Table 10 displays recommended values to set the RC
network. At higher input frequencies, good performance can be
C2
0.1µF
0.1µF
2V p-p
R1
R2
VIN+x
33Ω
S
S
P
0.1µF
33Ω
0.1µF
AD9650
C1
R1
R2
VIN–x
VCM
08919-038
PA
C2
Figure 81. Differential Double Balun Input Configuration
VCC
ANALOG INPUT
0Ω
16
1
8, 13
11
0.1µF
2
CD
RD
RG
3
ANALOG INPUT
0.1µF
0Ω
R
VIN+x
200Ω
C
AD8352
10
4
5
0.1µF
0.1µF
200Ω
R
14
0.1µF
0.1µF
Figure 82. Differential Input Configuration Using the AD8352
Rev. 0 | Page 31 of 44
AD9650
VIN–x
VCM
08919-039
0.1µF
C2 Shunt
(pF Each)
15
10
Remove
AD9650
0
REFERENCE VOLTAGE ERROR (%)
The AD9650 can be configured for a stable 1.35 V internal
reference or a user-applied external reference. The input range
of the ADC always equals twice the voltage at the reference pin
(VREF) for either an internal or an external reference. Table 11
shows a summary of the internal and external reference
connections.
Internal Reference Connection
A stable and accurate 1.35 V reference is built into the AD9650,
allowing a 2.7 V p-p full-scale input. To configure the AD9650
for an internal reference, the SENSE pin must be tied low. In
addition, to achieve optimal noise performance, it is recommended
that the VREF pin be decoupled by 1.0 μF and 0.1 μF capacitors
close to the pin. Figure 83 shows the configuration for the internal
reference connection.
VIN–A/VIN–B
ADC
CORE
SELECT
LOGIC
SENSE
VSELECT
–2.0
–2.5
–3.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
LOAD CURRENT (mA)
Figure 84. Reference Voltage Error vs. Load Current
External Reference Operation
If the internal reference of the AD9650 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 84 shows
how the internal reference voltage is affected by loading.
–1
–2
–3
–4
–5
–6
–50
–30
–10
10
30
50
70
90
TEMPERATURE (°C)
Figure 85. Typical VREF Drift
Table 11. Reference Configuration Summary
Selected Mode
Internal Reference
External Reference
SENSE Voltage (V)
AGND to 0.2
AVDD
Resulting VREF (V)
1.35
N/A
Rev. 0 | Page 32 of 44
Resulting Differential Span (V p-p)
2.7
2 × external reference
08919-189
Figure 83. Internal Reference Configuration
REFERENCE VOLTAGE ERROR (mV)
0
08919-040
AD9650
–1.5
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 75). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.35 V.
VREF
0.1µF
–1.0
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 85 shows the typical drift characteristics of the
internal reference in 1.35 V mode.
VIN+A/VIN+B
1.0µF
–0.5
08919-188
VOLTAGE REFERENCE
AD9650
Clock Input Considerations
For optimum performance, the AD9650 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 86) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 89. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock
drivers offer excellent jitter performance.
0.1µF
CLOCK
INPUT
AVDD
0.1µF
CLK+
AD951x
CLK–
50kΩ
240Ω
50kΩ
240Ω
Figure 89. Differential PECL Sample Clock (Up to 625 MHz)
9pF
Clock Input Options
The AD9650 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 87 and Figure 88 show two preferred methods for clocking
the AD9650 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun’s
secondary windings limit the clock excursions into the AD9650
to approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9650 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
XFMR
0.1µF
ADC
CLOCK
INPUT
08919-045
SCHOTTKY
DIODES:
HSMS2822
ADC
AD9650
0.1µF
CLK+
0.1µF
1nF
Figure 88. Balun-Coupled Differential Clock (Up to 625 MHz)
08919-046
CLK–
SCHOTTKY
DIODES:
HSMS2822
LVDS DRIVER
0.1µF
ADC
AD9650
CLK–
50kΩ
50kΩ
Figure 90. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor (see Figure 91).
VCC
CLOCK
INPUT
0.1µF
1kΩ
AD951x
OPTIONAL
0.1µF
100Ω
CMOS DRIVER
50Ω1
CLK+
ADC
1kΩ
AD9650
CLK–
0.1µF
Input Clock Divider
Figure 87. Transformer-Coupled Differential Clock (Up to 200 MHz)
50Ω
0.1µF
Figure 91. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
CLK+
CLK–
1nF
CLK+
100Ω
150Ω RESISTOR IS OPTIONAL.
0.1µF
0.1µF
0.1µF
AD951x
AD9650
100Ω
50Ω
0.1µF
CLOCK
INPUT
08919-048
08919-044
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 90. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518 clock drivers offer excellent jitter performance.
Figure 86. Equivalent Clock Input Circuit
CLOCK
INPUT
ADC
AD9650
CLK–
9pF
CLOCK
INPUT
100Ω
0.1µF
08919-049
CLK+
PECL DRIVER
08919-047
CLOCK
INPUT
0.9V
0.1µF
The AD9650 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios of 1, 2, 4, or 8, the duty cycle stabilizer (DCS) is
optional. For other divide ratios, divide-by-3, -5, -6, and -7, the
duty cycle stabilizer must be enabled for proper part operation.
The AD9650 clock divider can be synchronized using the external
SYNC input. Bit 0 to Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Rev. 0 | Page 33 of 44
AD9650
82
Clock Duty Cycle
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit. The
duty cycle control loop does not function for clock rates of less
than 20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the clock
rate can change dynamically. A wait time of 1.5 μs to 5 μs is
required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal. During the
time period that the loop is not locked, the DCS loop is bypassed,
and internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications, enabling
the DCS circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. For inputs near full scale, the degradation in
SNR from the low frequency SNR (SNRLF) at a given input
frequency (fINPUT) due to jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ]
In the equation, the rms aperture jitter represents the clock input
jitter specification.
Improvements in SNR can be achieved for IF undersampling
applications by minimizing the effects of aperture jitter. This
can be accomplished by applying a high frequency clock input
and using the integrated clock divider to achieve the desired
sample rate of the ADC core. Inherently, the jitter performance
of the AD9650 improves as the frequency of the clock increases.
This is a result of the slew rate of the clock affecting the noise
performance of the ADC, where fast transition edges result in
the best performance. Figure 92 shows the improvement in SNR
for the different clock divide ratios for the 1 V p-p and 2 V p-p
sinusoidal clock inputs. Measurements in Figure 92 were taken
for the AD9650BCPZ-105 where the input frequency was
141 MHz. The same analysis can be performed for the various
speed grades of the AD9650 family of parts.
2V p-p CLK AMPLITUDE
78
76
1V p-p CLK AMPLITUDE
74
72
70
1
2
3
CLK DIVIDE RATIO
4
08919-293
The AD9650 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the
performance of the AD9650. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS
enabled.
80
SNR (dBFS)
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals and, as a result, may be sensitive to clock
duty cycle. The AD9650 requires a tight tolerance on the clock duty
cycle to maintain dynamic performance characteristics.
Figure 92. SNR vs. CLK Divide Ratio for fIN = 141 MHz and a
Sample Rate of 105 MSPS
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9650.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources.
Refer to the AN-501 Application Note and the AN-756 Application
Note (visit www.analog.com) for more information about jitter
performance as it relates to ADCs.
CHANNEL/CHIP SYNCHRONIZATION
The AD9650 has a SYNC input that offers the user flexible
synchronization options for synchronizing the clock divider.
The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The input clock
divider can be enabled to synchronize on a single occurrence of
the SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9650 varies with its sample rate.
In CMOS output mode, the digital power dissipation is determined
primarily by the strength of the digital drivers and the load on
each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (32 plus two DCO outputs
in the case of the AD9650).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is
Rev. 0 | Page 34 of 44
AD9650
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers
reduces digital power consumption.
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9650 is placed in power-down
mode. In this state, the ADC typically dissipates 3.3 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD9650 to its normal operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and must be recharged when returning to normal
operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required.
DIGITAL OUTPUTS
Voltage at Pin
AGND
AVDD
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled
(default)
Digital Output Enable Function (OEB)
The AD9650 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI. If the OEB pin is low, the output data drivers and
DCOs are enabled. If the OEB pin is high, the output data drivers
and DCOs are placed in a high impedance state. This OEB
function is not intended for rapid access to the data bus. Note
that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
When using the SPI, the data outputs and DCO of each channel
can be independently three-stated by using the output enable
bar bit (Bit 4) in Register 0x14.
The AD9650 output drivers can be configured to interface with
1.8 V CMOS logic families. The AD9650 can also be configured
for LVDS outputs (standard ANSI or reduced output swing mode)
using a DRVDD supply voltage of 1.8 V.
TIMING
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9650.
These transients can degrade converter dynamic performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The default output mode is CMOS, with each channel output
on a separate bus, as shown in Figure 2. The output can also be
configured for interleaved CMOS via the SPI port. In interleaved
CMOS mode, the data for both channels is output through the
Channel A output pins, and the Channel B output is placed into
high impedance mode. The timing diagram for interleaved
CMOS output mode is shown in Figure 3.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
The AD9650 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The lowest typical conversion rate of the AD9650 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can
degrade.
Data Clock Output (DCO)
The AD9650 provides two data clock output (DCO) signals
intended for capturing the data in an external register. In CMOS
output mode, the data outputs are valid on the rising edge of DCO,
unless the DCO clock polarity has been changed via the SPI. In
LVDS output mode, the DCO and data output switching edges
are closely aligned. Additional delay can be added to the DCO
output using SPI Register 0x17 to increase the data setup time.
In this case, the Channel A output data is valid on the rising
edge of DCO, and the Channel B output data is valid on the
falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a
graphical timing description of the output modes.
Table 13. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0V
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
Rev. 0 | Page 35 of 44
Twos Complement Mode
1000 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1111
ORx
1
0
0
0
1
AD9650
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9650 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9650.
Various output test options are also provided to place predictable
values on the outputs of the AD9650.
The outputs are not disconnected during this test; therefore, the
PN sequence can be observed as it runs. The PN sequence can
be continued from its last value or reset from the beginning,
based on the value programmed in Register 0x0E, Bit 2. The
BIST signature result varies based on the channel configuration.
BUILT-IN SELF-TEST (BIST)
The output test modes are shown in Table 17. When an output
test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see the
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
The BIST is a thorough test of the digital portion of the selected
AD9650 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value for Channel A or
Channel B is placed in Register 0x24 and Register 0x25. If one
channel is chosen, its BIST signature is written to the two registers.
If both channels are chosen, the results from Channel A are placed
in the BIST signature registers.
OUTPUT TEST MODES
Rev. 0 | Page 36 of 44
AD9650
SERIAL PORT INTERFACE (SPI)
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 93
and Table 5.
The AD9650 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
Other modes involving the CSB are available. When the CSB is
held low indefinitely, which permanently enables the device,
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI secondary pin functions.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent
to and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active-low control that enables or
disables the read and write cycles.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Table 14. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active-low control that gates the read
and write cycles.
tHIGH
tDS
tS
tDH
All data is composed of 8-bit words. Data can be sent in MSB-first
mode or in LSB-first mode. MSB first is the default on power-up
and can be changed via the SPI port configuration register. For
more information about this and other features, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
tCLK
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 93. Serial Port Interface Timing Diagram
Rev. 0 | Page 37 of 44
D4
D3
D2
D1
D0
DON’T CARE
08919-052
SCLK DON’T CARE
AD9650
HARDWARE INTERFACE
The pins described in Table 14 comprise the physical interface
between the user programming device and the serial port of the
AD9650. The SCLK pin and the CSB pin function as inputs
when using the SPI. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during
readback.
The SPI is flexible enough to be controlled by either FPGAs or
microcontrollers. One method for SPI configuration is
described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9650 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI is not being used.
When the pins are strapped to AVDD or ground during device
power-on, they are associated with a specific function. The
Digital Outputs section describes the strappable functions
supported on the AD9650.
When the device is in SPI mode, the PDWN and OEB pins
remain active. For SPI control of output enable and power-down,
the OEB and PDWN pins should be set to their default states.
Table 15. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
OEB
PDWN
AGND (default)
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or
standby
Normal operation
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail in
the AN-877 Application Note, Interfacing to High Speed ADCs via
SPI. The AD9650 part-specific features are described in detail
following Table 17, the external memory map register table.
Table 16. Features Accessible Using the SPI
Feature Name
Mode
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the
PDWN pin serve as standalone CMOS-compatible control pins.
When the device is powered up, it is assumed that the user
intends to use the pins as static control lines for the duty cycle
stabilizer, output data format, output enable, and power-down
feature control. In this mode, the CSB chip select bar should be
connected to AVDD, which disables the serial port interface.
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Rev. 0 | Page 38 of 44
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the sync
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode,
including LVDS
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
AD9650
MEMORY MAP
•
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
channel index and transfer registers (Address 0x05 and
Address 0xFF); the ADC functions registers, including setup,
control, and test (Address 0x08 to Address 0x30); and the digital
feature control register (Address 0x100).
The memory map register table (see Table 17) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For more information on this
function and others, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF. The
remaining register, Register 0x100, is documented in the Memory
Map Register Table section.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x17).
Default Values
After the AD9650 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 through Address 0x18 and Address 0x30 are
shadowed. Writes to these addresses do not affect part
operation until a transfer command is issued by writing 0x01 to
Address 0xFF, setting the transfer bit. This allows these registers
to be updated internally and simultaneously when the transfer
bit is set. The internal update takes place when the transfer bit is
set, and the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated for
each channel. These registers and bits are designated in Table 17
as local. These local registers and bits can be accessed by setting
the appropriate Channel A or Channel B bits in Register 0x05.
If both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are set
during an SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in Table 17 affect the entire
part or the channel features for which independent settings are not
allowed between channels. The settings in Register 0x05 do not
affect the global registers and bits.
Logic Levels
An explanation of logic level terminology follows:
Rev. 0 | Page 39 of 44
AD9650
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Address Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0
0x00
SPI port
configuration
(global)
0x01
0x02
Chip ID
(global)
Chip grade
(global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
8-bit Chip ID[7:0]
(AD9650 = 0x32, default)
Speed grade ID
Open
Open
001 = 105 MSPS
010 = 80 MSPS
011 = 65 MSPS
100 = 25 MSPS
Open
Default
Value
(Hex)
Default
Notes/
Comments
0x18
The nibbles
are mirrored
so that LSBfirst mode or
MSB-first mode
registers
correctly,
regardless of
shift mode.
Read only.
0x32
Open
Open
Speed grade
ID used to
differentiate
devices; read
only.
Channel Index and Transfer Registers
0x05
Channel
Open
index
Open
Open
Open
Open
Open
Data
Channel
B
(default)
Data
Channel
A
(default)
0x03
0xFF
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Functions
0x08
Power
modes (local)
1
Open
External
powerdown pin
function
(local)
0 = pdwn
1 = stndby
Open
Open
Open
0x09
Global clock
(global)
Open
Open
Open
Open
Open
0x0B
Clock divide
(global)
Open
Open
Open
Open
Open
Transfer
Rev. 0 | Page 40 of 44
Internal powerdown mode (local)
00 = normal
operation
01 = full powerdown
10 = standby
11 = normal
operation
Open
Open
Duty
cycle
stabilizer
(default)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x80
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers only.
Synchronously
transfers data
from the
master shift
register to the
slave.
Determines
various generic
modes of chip
operation.
0x01
0x00
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active.
AD9650
Address
(Hex)
0x0D
Register
Name
Test mode
(local)
Bit 7
(MSB)
Open
Bit 6
Open
0x0E
BIST enable
(global)
ADC input
(global)
Open
Open
Open
Open
0x0F
0x10
0x14
Offset adjust
(local)
Output
mode
0x16
Clock phase
control
(global)
0x17
DCO output
delay (global)
BIST signature
LSB (local)
0x25
BIST signature
MSB (local)
0x30
Dither
enable (local)
Digital Feature Control
0x100
SYNC control
(global)
Bit 5
Reset PN
long gen
Bit 2
Bit 1
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
Open
Open
Open
Reset BIST Open
BIST
sequence
enable
Open
Open
Open
Open
Open
Commonmode
servo
enable
Offset adjust in LSBs from +127 to −128
(twos complement format)
CMOS
Output
Open
Output
Output format
output
enable
(must be
invert
00 = offset binary
written
(local)
interleave bar
01 = twos
(local)
low)
enable
complement
(global)
01 = gray code
11 = offset binary
(local)
Drive
strength
0 = ANSI
LVDS;
1=
reduced
swing
LVDS
(global)
Invert
DCO
clock
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Open
Open
Open
Open
0x24
Bit 4
Reset
PN short
gen
Bit 0
(LSB)
Open
Bit 3
Open
Open
Default
Value
(Hex)
0x00
Default
Notes/
Comments
When this
register is set,
the test data
is placed on
the output
pins in place of
normal data.
0x04
0x00
0x00
0x00
Configures the
outputs and
the format of
the data.
0x00
Allows
selection of
clock delays
into the input
clock divider.
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
BIST signature[7:0]
0x00
Read only.
BIST signature[15:8]
0x00
Read only.
0x00
Open
Open
Open
Dither
enable
Open
Open
Open
Open
0x00
Open
Open
Open
Open
Open
Clock
divider
next
SYNC
only
Clock
divider
SYNC
enable
Master
SYNC
enable
0x00
Rev. 0 | Page 41 of 44
AD9650
MEMORY MAP REGISTER DESCRIPTIONS
Bit 1—Clock Divider SYNC Enable
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Bit 1 gates the SYNC pulse to the clock divider. The SYNC
signal is enabled when Bit 1 is high and Bit 0 is high. This is
continuous SYNC mode.
SYNC Control (Register 0x100)
Bits[7:3]—Reserved
Bit 0—Master SYNC Enable
Bit 2—Clock Divider Next SYNC Only
If the master SYNC enable bit (Address 0x100, Bit 0) and the clock
divider SYNC enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to synchronize to the first SYNC pulse it
receives and to ignore the rest. The clock divider SYNC enable bit
(Address 0x100, Bit 1) resets after it synchronizes.
Bit 0 must be high to enable any of the SYNC functions. If the
SYNC capability is not used, this bit should remain low to
conserve power.
Rev. 0 | Page 42 of 44
AD9650
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9650 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9650, it is recommended that
two separate 1.8 V supplies be used. Use one supply for the analog
outputs (AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9650. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
LVDS Operation
The AD9650 defaults to CMOS output mode on power-up.
If LVDS operation is desired, this mode must be programmed,
using the SPI configuration registers after power-up. When the
AD9650 powers up in CMOS mode with LVDS termination
resistors (100 Ω) on the outputs, the DRVDD current can be
higher than the typical value until the part is placed in LVDS
mode. This additional DRVDD current does not cause damage
to the AD9650, but it should be taken into account when considering the maximum DRVDD current for the part.
To avoid this additional DRVDD current, the AD9650 outputs
can be disabled at power-up by taking the OEB pin high. After
the part is placed in LVDS mode via the SPI port, the OEB pin
can be taken low to enable the outputs.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should mate to the
AD9650 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged to
prevent solder wicking through the vias, which can compromise
the connection.
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 80.
RBIAS
The AD9650 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with
a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9650 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
Rev. 0 | Page 43 of 44
AD9650
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
48
64 1
49
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
16
17
33
32
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
7.65
7.50 SQ
7.35
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
041509-A
8.75
BSC SQ
TOP VIEW
Figure 94. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9650BCPZ-25
AD9650BCPZRL7-25
AD9650BCPZ-65
AD9650BCPZRL7-65
AD9650BCPZ-80
AD9650BCPZRL7-80
AD9650BCPZ-105
AD9650BCPZRL7-105
AD9650-25EBZ
AD9650-65EBZ
AD9650-80EBZ
AD9650-105EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08919-0-7/10(0)
Rev. 0 | Page 44 of 44
Package Option
CP-64-6
CP-64-6
CP-64-6
CP-64-6
CP-64-6
CP-64-6
CP-64-6
CP-64-6