[ /Title (CD54H C74, CD74H C74, CD74H CT74) /Subject (Dual D FlipFlop with Set CD54HC74, CD74HC74, CD74HCT74 Data sheet acquired from Harris Semiconductor SCHS124 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger January 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD54HC74, CD74HC74 and CD74HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. • Asynchronous Set and Reset • Complementary Outputs This flip-flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input. • Buffered Inputs • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 74HCT logic family is functionally as well as pin compatible with the standard 74LS logic family. • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs TEMP. RANGE (oC) PACKAGE CD54HC74F -55 to 125 14 Ld CERDIP F14.3 CD74HC74E -55 to 125 14 Ld PDIP E14.3 CD74HCT74E -55 to 125 14 Ld PDIP E14.3 CD74HC74M -55 to 125 14 Ld SOIC M14.15 CD74HCT74M -55 to 125 14 Ld SOIC M14.15 PART NUMBER • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH PKG. NO. NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD54HC74, CD74HC74, CD74HCT74 (PDIP, SOIC, CERDIP) TOP VIEW 1R 1 14 VCC 1D 2 13 2R 1CP 3 12 2D 1S 4 11 2CP 1Q 5 10 2S 1Q 6 9 2Q GND 7 8 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 1476.1 CD54HC74, CD74HC74, CD74HCT74 Functional Diagram 1 RESET R 2 DATA 5 Q D F/F 1 3 6 Q CP CLOCK S 4 SET RESET 13 R 12 11 Q F/F 2 CP CLOCK S SET 9 D DATA 10 8 Q GND = PIN 7 VCC = PIN 14 TRUTH TABLE INPUTS OUTPUTS SET RESET CP D Q Q L H X X H L H L X X L H L L X X H (Note 3) H (Note 3) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 NOTE: H = High Level (Steady State) L = Low Level (Steady State) X = Don’t Care ↑ = Low-to-High Transition Q0 = the level of Q before the indicated input conditions were established. 3. This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level. 2 CD54HC74, CD74HC74, CD74HCT74 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . 120 CERDIP Package . . . . . . . . . . . . . . . . 130 55 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - - -0.02 2 1.9 - - 1.9 - 1.9 - V 4.5 4.4 - - 4.4 - 4.4 - V 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 4.5 - - 0.1 - 0.1 - 0.1 V 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 3 CD54HC74, CD74HC74, CD74HCT74 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 4 - 40 - 80 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL - 4.5 4.4 - - 4.4 - 4.4 - V -0.02 4.5 3.98 - - 3.84 - 3.7 - V -4 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 4 5.5 - ICC VCC or GND 0 5.5 - - 4 - 40 - 80 µA ∆ICC (Note 5) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 5. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS D 0.5 R 0.5 CP 0.7 S 0.75 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tSU - 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns HC TYPES Data to CP Setup Time (Figure 5) 4 CD54HC74, CD74HC74, CD74HCT74 Prerequisite For Switching Specifications PARAMETER Hold Time (Figure 5) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tH - 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns 2 30 - - 40 - 45 - ns 4.5 6 - - 8 - 9 - ns tREM Pulse Width R, S (Figure 1) tW CP Frequency 25oC TEST CONDITIONS Removal Time R, S, to CP (Figure 5) Pulse Width CP (Figure 1) (Continued) - - - tW - fMAX 6 5 - - 7 - 8 - ns 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 6 - - 5 - 4 - MHz 4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz HCT TYPES Data to CP Setup Time (Figure 6) tSU - 4.5 12 - - 15 - 18 - ns Hold Time (Figure 6) tH - 4.5 3 - - 3 - 3 - ns Removal Time R, S, to CP (Figure 6) tREM - 4.5 6 - - 8 - 9 - ns Pulse Width R, S (Figure 2) tW - 4.5 16 - - 20 - 24 - ns Pulse Width CP (Figure 2) tW - 4.5 18 - - 23 - 27 - ns fMAX - 4.5 25 - - 20 - 16 - MHz SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 175 - 220 - 265 ns CL = 50pF 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CP Frequency Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC HC TYPES Propagation Delay, CP to Q, Q (Figure 3) Propagation Delay, R, S to Q, Q (Figure 3) Transition Time (Figure 3) Input Capacitance tPLH, tPHL tTLH, tTHL CI CL = 50pF 2 - - 200 - 250 - 300 ns CL = 50pF 4.5 - - 40 - 50 - 60 ns CL = 15pF 5 - 17 - - - - - ns CL = 50pF 6 - - 34 - 43 - 51 ns CL = 50pF 2 - - 75 - 95 - 110 ns CL = 50pF 4.5 - - 15 - 19 - 22 ns CL = 50pF 6 - - 13 - 16 - 19 ns - - - 10 - 10 - 10 pF - 5 CD54HC74, CD74HC74, CD74HCT74 Switching Specifications Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS CP Frequency fMAX CL = 15pF 5 - 50 - - - - - MHz Power Dissipation Capacitance (Notes 6, 7) CPD - 5 - 25 - - - - - pF PARAMETER HCT TYPES Propagation Delay, CP to Q, Q (Figure 4) tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns Propagation Delay, R, S to Q, Q (Figure 4) tPHL, tPLH CL = 50pF 4.5 - - 40 - 50 - 60 ns Transition Time (Figure 4) tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns CI - - - - 10 - 10 - 10 pF CP Frequency fMAX CL = 15pF 5 - 50 - - - - - MHz Power Dissipation Capacitance (Notes 6, 7) CPD - 5 - 30 - - - - - pF Input Capacitance NOTES: 6. CPD is used to determine the dynamic power consumption, per flip-flop. 7. PD = CPD VCC2 fi + Σ (CL VCC2 fo) where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I tr = 6ns tf = 6ns tr = 6ns GND tTLH 3V 2.7V 1.3V 0.3V INPUT GND tTHL 90% 50% 10% INVERTING OUTPUT tWH FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH VCC tTHL GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tf = 6ns 90% 50% 10% 1.3V 1.3V tWL FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tPHL 1.3V 0.3V tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. INPUT 2.7V 0.3V GND tWL I fCL 3V CLOCK 50% 50% tfCL = 6ns fCL VCC 50% 10% tWL + tWH = trCL = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6 CD54HC74, CD74HC74, CD74HCT74 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 6. 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