EPC EPC120 Fully integrated light-barrier chips with 2-wire bus interface Datasheet

epc120
Fully integrated Light-Barrier Chips with 2-Wire Bus Interface
General Description
Features
The epc120 is a general purpose, fully integrated self-contained
CMOS circuit to be used in light-barrier applications. The chips
contain a controller which drives an LED, typically an IR-LED. The
LED is used in a pulsed mode to increase the signal-to-noise ratio
even when there is very strong sunlight biasing the photo diode.
It contains also a high sensitive photo diode amplifier and a signal
conditioning circuitry to cancel unwanted environmental light including
strong sunlight and pulsed light sources. The receiver is built around
a synchronous demodulator circuitry. Two output signals with a
different threshold level are implemented in order to trigger the light
barriers output or to indicate light reserve.
Fully integrated light barrier chip
Needs just a photo diode and an LED with an LED driver
Configurable
High speed 2-wire bus
Integrated clock generator
CSP10 package with very small footprint or
standard QFN16 package available
 Versions without 2-wire bus interface available (epc11x family)






Applications
 Light barriers ranging from millimeters to tens of meters
 Smoke detectors
 Liquid detectors
The chips also include a power supply circuitry to establish all
internally required voltages from the 2-wire bus.
They contain a 2-wire communication interface which is capable to
operate as many as 1023 devices on a 2-wire bus at a speed of up to
2MBit/s over the power supply. This feature allows to design of a
distributed light barrier system.
Functional Block Diagram
VDD
VLED
2-wire COM
Interface
LED
SCK
Parameter
Memory
VDD33
Voltage Regulator
VDD18
LED
Processor
SPI
Controller
Signal
Processor
PD
f
D1
GND
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
CS
SI
EN
SO
1
Datasheet epc12x - V2.1
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epc120
Absolute Maximum Ratings (Notes 1, 2)
Recommended Operating Conditions
Voltage to any pin except V DD
-0.3V to VDD+0.3 V
Min.
Max.
Units
Supply Voltage on 2-wire bus V DD
-0.3V to +8.0V
Operating Voltage on 2-wire bus V DD
4.5
5.5
V
Programming Voltage on 2-wire bus V DD
-0.3V to +8.0V
Programming Voltage on V DD
7.0
8.0
V
Input current at any pin except LED
-6mA to +6 mA
Power consumption with maximum load
125mW
Storage Temperature Range (T S)
-55°C to +155°C
Operating Temperature (T O)
-40°
+85
°C
Lead Temperature solder, 4 sec. (T L)
+260°C
Relative Humidity (non-condensing)
+5
+95
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions
indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specific ations and test conditions, see Electrical Characteristics.
Note 2: This device is a highly sensitive CMOS ac current amplifier with an ESD rating of JEDEC HBM class 0 (<250V). Handling and
assembly of this device should only be done at ESD protected workstations.
Electrical Characteristics
VDD = 4.5V … 5.5V, -40°C < T A < +85°C, unless otherwise specified
General Data
Symbol
Parameter
Conditions/Comments
Values
Min.
VPP
IDD_OP
Ripple on supply voltage,
peak to peak
2-wire interface V det
Input pulse I PD NST
Typ.
Units
Max.
50mV
48nA
150
mV
100mV
72nA
350
mV
200mV
108nA
600
mV
2
mA
50
200
mV
6.4
9.8
mA
Current consumption
in operation mode I PD = 0 mA
Vdet
Detection level for 2-wire interface
configurable
IMOD
Modulation current for 2-wire interface
fclk
Reference clock
dfclk
Temperature drift of the oscillator
VPUP
Power-up Threshold Voltage
The voltage at VDD33 when the device starts up
2.4
3
V
VIH
INPUT
Logical high (V N can be either VDD or VDD33)
0.7 *VN
VN
V
VIL
INPUT
Logical low (VN can be either VDD or VDD33)
GND
0.3 *VN
V
10
µA
ILEAKD
Internal oscillator
MHz
ppm/K
Input leakage current
VOH
Output high voltage
@ 4mA sink except pin SCK/LED
VOL
Output low voltage
@ 4mA source
Source current
@ PIN SCK / LED
ISCK/LED
1
640
VDD- 0.5
V
0.7
0.5
V
1.3
mA
VHist
Schmitt Trigger Hysteresis
0.1
RPU
Pull-Up Resistor
30
200
kΩ
IPDDC
DC Photo Diode Current
0.0
2
mA
generated by ambient light with no effect to the
sensitivity
V
CPD
Photodiode Capacitance
Photodiode Capacitance
40
pF
IN_Imin
Input related noise
@ IPDDC =0
15
nA RMS
IN_Imax
Input related noise
@ IPDDC =IPDDCMax
20
nA RMS
IPDN
Photo Current Sensitivity, normal
threshold
Parameter SENSN = 011 (60nA). T Pulse = 6µs
Photodiode pulse to generate a status “pulse detected”
45
60
75
nA
IPDH
Photo Current Sensitivity, upper
threshold
Parameter SENSH = 011 (96nA). T Pulse = 6µs
Photodiode pulse to generate a status “pulse detected”
1.4
1.6
1.8
IPDN
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Characteristics subject to change without notice
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Datasheet epc12x - V2.1
www.espros.ch
epc120
Symbol
Parameter
Conditions/Comments
Ipulse
Maximum Input Pulse Current
tPulse
LED Pulse Length
trelax
Relaxation time
If the input current pulse is above this level, the
recovery time tREC is undefined (refer to section 'Other
Parameters')
After a strong current pulse (I pulse = 100µA)
Values
Units
dependent on settings
µA
Programmable between
1 and 8
µs
dependent on settings
µs
Other Parameters
Sensitivity [nA]
(typical values, T amb = 25°C, VDD = 5.0V)
120
110
100
90
80
70
60
50
40
0
1
2
3
4
5
6
Pulse width [us]
Figure 1: Input Sensitivity vs. LED pulse width
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Characteristics subject to change without notice
3
Datasheet epc12x - V2.1
www.espros.ch
epc120
VDD18
VDD
PD
CS
2
3
4
1
2
3
SO
10-Pin Chip Scale Package (CSP)
Pin Name Type
PD
5
GND
1
16
VDD
GND
Top View
15
EN/
SI
7
LED/
SCK
5
4
CS
NC
Top View
14
VDD18
8
13
10
6
6
OUTN/
SO
12
7
EN/
SI
11
8
LED/S
CK
10
9
VDD33
9
VDD33
Connection Diagrams
16-Pin QFN Package
10-Pin
CSP
16-Pin
QFN
Description
1
9
VDD
Power supply
Positive power supply
2
7
GND
Power supply
Negative power supply pin.
3
6
PD
Analog Input
Photo diode input.
4
4
CS
Digital Input
SPI Interface: Chip Select. Active low, with pull up
6
1
SO
Digital Output
SPI interface serial out
7
15
SI
Digital Output
SPI interface serial input
8
14
LED
SCK
Digital In / Out
Light barrier:
SPI Interface:
9
12
VDD33
Power Supply
Decoupling
A power supply filter capacitor is connected to this pin.
10
10
VDD18
Analog Out
1.8V regulator output, used to connect a filter capacitor. Must not be used to supply
any other circuits.
5
2
NC
Not connected. Leave that pin floating.
n/a
3, 5, 8,
11, 13,
16
NC
Not connected. Connect this pin with VSS.
LED control
Shift Clock
05.12.2011
...
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© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
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Datasheet epc12x - V2.1
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epc120
1. Application Information
The epc120 chip set is a general purpose CMOS integrated circuit for light barrier applications. Up to 1023 devices may be connected to two
respectively four wires in parallel. Each device can be individually addressed by an epc100 chip which acts as the interface between a
microcontroller and the 2-wire bus. It manages the bus traffic between the microcontroller and the individual epc120 elements. Programmable
fuses i.e. for the address, sensitivity, LED light pulse width, etc. allow the device to be parametrized in the final system (OTP memory).
The bus controller activates the emitting side of the epc120 and reads the status of the levels at the photodiode input. The status of the
answers to the interface chip can be 'no light pulse received', 'low level light pulse received' and 'high level light pulse received'.
Each chip can be put into 'standby mode' or 'operating mode' to reduce power consumption. During 'standby mode', power consumption is
reduced and the photo diode is shorted. In the 'operation mode', the device is active and ready to receive a light pulse generated by an LED
activated by the LED pin. During a scan, the bus controller addresse s one device after the other and fetches the light barrier status.
This manual describes the various operation and programming modes in order to use epc120. For the interface chip epc100 please refer to
the epc10x “Reference Manual”.
2. Hardware Design Information
Figure 2 shows the epc120 as an example in a long range light barrier application as a single bus module in a bus-chain configuration with
minimal part count. The LED emits a light pulse when the chip is addressed by the bus controller. Light of the LED is reflected from a
reflecting object or a retro reflector back to the photo diode PD. If the received light is strong enough it triggers the internal thresholds
OUTN/H. The status of the receiver result can be read by the bus controller.
VDD Track for LEDs
VDD for 2-Wire Bus (Data & Power)
Bus Controller
1st Bus Module
R1
100R
R2
10k
VDD
epc120
VDD33
VDD18
C3
PD
C4
T2
BC807-40
CS
LED/SCK
SI
SO
T1
BC846
IR LED, i.e.
TSML1000
GND
100nF 4.7nF
PD
nth Bus
Module
R3
2R2
i.e.
epc300
C1
100μF
Low ESR
GND 2-Wire Bus (Data & Power)
GND Track for LEDs
Figure 2: Long range light barrier chain application with minimal part count
The output to drive the LED is a current source capable to drive typically 1mA. For a high performance light barrier, an LED peak current of
up to 2A is needed. To generate such a high LED current, an external amplifier is necessary. The circuitry in Figure 2 is a simple
implementation of such an amplifier. The complementary Darlington circuit with T1 and T2 and R2 and R3 does the job. In order to avoid
interference on the supply voltage, the supply is isolated (filtered) with R1 and C1. The high peak LED pulse current is delivered by the
capacitor C1, which itself is charged more or less constantly by R1. Make sure, that there is no coupling of the high LED current to the ground
and the supplies of the epc120 or to the cathode of the photo diode. This driver amplifier operates with a VDD LED in a range of 5 to 30 VDC.
Design Precautions
The sensitivity at pin PD is very high in order to achieve a long operation range of light barriers even without
lenses in front of the IR LED and/or the photo diode. Thus, the pin PD is very sensitive to EMI. Special care
should be taken to keep the PCB track at pin PD as short as possible (a few mm only!). This track should be
kept away from the IR LED signal tracks and from other sources which may induce unwanted signals. It is
strongly recommended to cover the chip, the photodiode and all passive components around the chip with a
metal shield. A recommended part is shown in Figure 3. The pins at the bottom are to solder the shield to
Figure 3: Recommended EMC
the PCB with electrical connection to GND. The hole in the front is the opening window for the photo diode.
shield
The back side of the PCB below the sensitive area (PD, epc120) shall be a polygon connected to GND to
shield the circuit from the back side as well.
Ambient Light
Photodiode DC current can be generated by ambient light, e.g. sun light. DC currents at pin PD do not generate a DC output signal. However,
if IPDDC is above the stated maximal value, the input is saturated which blocks the detection of AC current pulses.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
5
Datasheet epc12x - V2.1
www.espros.ch
epc120
3. System Concept
Out
active light beam
Bus
Interface
(epc100)
➊
Micro
Controller
SPIInterface
light cone
generated by the
LED
➊
2-Wire Bus
➊
Bus
Termination
50Ω, 100nF
➊
epc120 with PD and LED
➊
Figure 4: System overview
In a system with several reflective light barrier beams, each individual light barrier contains an emitter and a receiver. They are located at the
same place. As a receiver acts a photodiode and as an emitter a LED. Both can be controlled by only one single epc120. In contrast to the
epc11x-family, which are also light barrier chips, the epc120 can be used in a large distributed system. The devices are synchronized over the
2-wire bus line, organized by one epc100 and a microcontroller.
Figure 4 shows a typical distributed light barrier setup with five elements. Each element consist of an epc120, an emitter (LED), a receiver
(photodiode) and a few other components. Every element is connected to the 2-wire bus 1, which is controlled by a microcontroller through an
epc100. Because every epc120 element has a unique address, the microcontroller has individual access to all bus components.
Each of the epc120 elements sends light, typically infrared light, focused towards a reflector or an object. It reflects the light back to the
photodiode. If multiple sensors like this would be operated in close proximity, scattered light from all sensors are probably reflected to the
receivers. This would lead to false triggering. Thus, a sequential operation mode has to be implemented. Basically, a master controller
activates one sensor after the other and reads back the status of each individual light beam.
1 If the LED pulse current is rather high, i.e. 1 A, two separate bus wires for the LED supply current are needed. Please refer to Error:
Reference source not found for detailed information.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
6
Datasheet epc12x - V2.1
www.espros.ch
epc120
In more detail, such a sequential operation is typically like as follows:
1.
The first epc120 element is turned on (active mode).
2.
On a second command this element sends a short light pulse towards his reflector or object, forming the active light beam ➊.
3.
If there is no obstacle between epc120 and his reflector, the element receives this light pulse and stores it into a local memory.
4.
The bus controller reads out the content of the memory in the epc120 chip and stores the status (light beam interrupted or not
interrupted) into its data memory.
5.
Finally, epc120 is turned off (standby mode).
This sequence, which is also called 'scan', is repeated until all beams are checked and their status is stored in the beam status memory of the
bus controller.
The above mentioned sequence is repeated until power is switched off. Because of the fact, that an object can enter into a light beam right
after a beam has been checked with the above mentioned procedure, up to two full scan sequences are necessary to reliably detect an
object. Thus, the overall maximum response time of the system will be
t R=2∗n∗t beam t eval 
(1)
where
tR
= response time of the system
n
= number of elements or light beams
tbeam = time to evaluate one beam
teval = time to evaluate the beam status memory and generate the output signal
For further reference in optical design considerations please refer to the respective application notes available from epc.
Figure 5 shows the epc120 in a distributed light barrier system application. The epc100 acts as a bus controller.
+ ILED
VDD
VDD
epc120
epc120
epc120
VDD33
VDD33
VDD33
VDD33
µC
SI
SO
SCK
CS
PD
LED
PD
GND
GND
LED
PD
GND
LED
GND
RLED
RLED
RLED
50Ω
epc100
VDD µC
Element n
VDD
Bus Termination
VDD
Element 2
VDD
100nF
Element 1
GND
- ILED
Figure 5: epc120 in the light barrier application as receivers and the interface chip to the microcontroller
From the point of view of the microcontroller, the whole system looks like a single device with several addressable sensors: the microcontroller
activates one epc120 element and fetches the results after a predefined time.
In the circuit in Figure 5, the LED current is defined by a common current source in the I LED line. The resistor RLED limits the current through the
LED and is not needed in non-safety applications. If such a resistor is inserted, a failure mode can be detected, if more than one LED is active
due to a short circuit or a failure in the epc100. It is also possible to have a common voltage supply and to generate the LED current by a
resistor.
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Characteristics subject to change without notice
7
Datasheet epc12x - V2.1
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epc120
4. 2-Wire Bus
The 2-wire bus and the power supply utilize the same two wires. The data is transmitted by modulating the current on the power-line. The
modulated current, together with the resistor in the power supply, produce a voltage signal on the line. All devices receive this signal. The
system is designed to operate with a line impedance of 50Ω (±5%). An inductor in parallel of the resistor or a DC regulator with a lowpass
feedback shape the pulses and keep the the DC voltage drop over the resistor low. The required corner frequency of this L/R-filter is listed in
the table below.
The communication interface has been designed to be used for line lengths of up to 100m and with up to 1023 sensor devices. For line
lengths of up to 3m it is possible to operate the line without termination 2. Above this length the line has to be terminated by a resistor of 50 Ω
(±5%) which is equal to the line impedance and a capacitor of 100nF in series.
The data rate on the 2-wire bus is set by the parameter DRATE. It also defines T SCANmin (refer to Chapter Error: Reference source not found on
page Error: Reference source not found) and the required inductor according to Table 1. The maximum data rate allowed on the 2-wire bis is
depending on the bus length. The longer the bus wire, the lower the data rate. Table 1 shows the possible bus wire length according to the
data rate.
DRATE
k
Data Rate on the
2-Wire Bus
Minimal Data Rate
Required on SPI
Interface
Corner
Frequency L/R
Inductor
Bus Wire
Length3
00
8
250 kbit/s
300 kbit/s
0.5 MHz
16µH
12 … 100m
01
4
500 kbit/s
600 kbit/s
1 MHz
8µH
6 … 12m
10
2
1 Mbit/s
1.2 Mbit/s
2 MHz
4µH
3 … 6m
11
1
2 Mbit/s
2.4 Mbit/s
4 MHz
2µH
≤ 3m
Table 1: Data rate of the 2-wire communication
The default value of DRATE is 00. The parameter DRATE has to be identical for all devices on one physical 2-wire bus.
The SPI bus should be faster than the 2-wire bus, otherwise the communication does not work. Since the command length dependent on the
command type, the delay time to the next command has to be adjusted to the previous command. The time delay can be calculated with the
given data length in Table 7 on page 19.
The parameter CDET defines the optimal signal amplitude for the receiver. The maximum rate at pin VDDR (5.5V) should not be exceeded
and signals which are smaller than 70% of the recommended values are not detected.
Since the command length is dependent on the command type, the delay time to the next command has to be adjusted to the previous
command. The time delay can be calculated with the given data length in Table 7 on page 19. The data handling chain of the 2-wire
communication channel is shown in Figure 6.
Transmitter
Command
Receiver
Command
Data
Original
Message
Received
Message
Parity Bits
added
Error Correction
Manchester
Encoder
Manchester
Decoder +
Error Detection
Current
Sink
Line
Filter
Data
A/D
Converter
Figure 6: Data handling
2 Dependent on the electro-mechanical design and the bus location of the edge, the termination network can be necessary. It is in the
responsibility of the system designer that the data integrity on the bus is guaranteed. Data integrity can be tested by readout bus
transmission errors. It is strongly recommended to do that during type qualification during EMI qualification tests .
3 The effective length is dependent on the electro-mechanical design of the edge. The values in the table are indicative only.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
8
Datasheet epc12x - V2.1
www.espros.ch
epc120
Figure 7 shows the different messages with the parity bits. From the interface to the sensor/transmitter device the “normal command” is used
except for the register write command. In the other direction only the register readout has a different format. Notice the different start bits
which identify the direction of the transmission: 00 for the direction interface to sensor devices and 01 in the other direction. Between the
telegrams, an idle time of 2 clock periods are need to detect the start of the transmission.
Normal Command
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 C0 C1 C2 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9
Device Address
Write Command
A0 A1 A2
A8 A9 C0 C1 C2 P0 P1
Device Address
Results
D0 D1
A8 A9 P0 P1
Device Address
R0 R1 R2 R3 R4 D0 D1
Register
Register
D14 D15 P0 P1
Data
P8 P9
Parity Bits
P8 P9
Parity Bits
D14 D15 P0 P1
Data
Parity Bits
P8 P9 R0 R1 R2 R3 R4 D0 D1
Parity Bits
Command
D9 D10 A0 A1 A2
Data
Register Readout
Command
P 8 P9
Parity Bits
Figure 7: Message Structure
Bus Wire Considerations
The electromechanical design of a system using multiple epc10x devices on a twisted pair cable with an impedance of typically 100 Ohms has
an impact on the overall impedance of the system. Figure 8 shows the change of the cable impedance with smaller element pitch.
Impedance [Ohm]
120
100
80
60
40
20
0
1.0
1.8
3.2
5.6 10.0 17.8 31.6 56.2 100.0
Pitch [cm]
Figure 8: Line impedance as a function of the element pitch
on a 100 Ohm twisted pair cable
It is highly recommended to terminate the bus line on both sides with an AC terminator network (shown in Figure 9) which matches the overall
impedance of the system according to Figure 8. In order to avoid high DC currents in the termination resistor, a capacitor of 100nF should be
connected in series to the termination resistor.
100nF
RT
Figure 9: Bus termination network
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
9
Datasheet epc12x - V2.1
www.espros.ch
epc120
Another aspect is the distribution velocity of the electrical signals on the 2-wire bus. Since the bus wire itself as well as the individual elements
on the bus present a significant capacitance, the distribution velocity decreases with the number of elements and the pitch between the
elements.
1000
562
Delay [ns]
316
1
2
3
5
10
20
50
100
178
100
56
32
18
10
1
1.78 3.16 5.62
10 17.78 31.62 56.23 100
Pitch [cm]
Figure 10: Delay vs Pitch. Parameter: Line length [m]
It is important that the overall delay is less than 50% of the clock period of the transmission. E.g. if the system is operated with 2 MBit/s data
rate, the max. accepted delay must not be more than 125ns. Figure 10 shows, that a system operated at the full speed of 2 Mbit/s, a cable
length of up to 5m are possible with an element pitch down to 1cm.
Example:
If we have a system that contains 100 elements in a pitch of 10cm, the total bus length is 10m. According to Figure 10, the delay time of a
proper terminated bus is a little bit more than 100ns. Thus, such a system can be operated with the full speed of 2MBit/s.
Bus Signal Waveform
Figure 11 pictures the Manchester encoding and the signal on the bus. The signal on the bus can be monitored with an oscilloscope and
should look like in the drawing.
CDET
Message
VS
Manchester
Signal on Bus
TDataRate
Figure 11: Manchester encoded signal on the bus
CDET is the threshold set in the 2-wire communication receiver of the chip to detect the communication signal on the bus. This parameter,
described in Table 6 and Table 10, can be adjusted to mach the specific system requirements. Thus, the voltage swing V S of the
communication signal on the bus shall match this setting. A good principle is that the voltage swing V S measured on the bus should be min.
25% and max. 150% above the CDET value.
Example:
If CDET is set to 200mV, the voltage swing V S should be in a range of 250 to 500 mV. Ideal for this setting is a swing voltage V S of 400mV.
Attention:
Make sure that the voltage swing V S is in the given tolerance range at every physical location of the bus. Due to reflections in the cable, losses
of the wires (capacitive, inductive, and resistive), and the high bandwidth of the communication signals, significant differences can occur.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
10
Datasheet epc12x - V2.1
www.espros.ch
epc120
Parameter Memory
The epc120 device contains a memory to store the application parameters. The following classes of data are stored on each device:
•
Unique chip ID and chip adjustments (factory set)
•
Physical device address in the application, representing the beam number
•
Application parameters
This data can be permanently stored in a read-only memory 4 and is mirrored in a volatile memory 5. At power up, the data (except the chip ID)
is copied from the ROM to the RAM. During operation, the data from the RAM is used. Both memories are organized in 16 registers at 16 bits
each. The data can be accessed on a 16-bit register base. The following table shows the memory organization:
Non-Volatile Memory Address
Range
(Register no.)
Volatile Memory Address
Range
(Register no.)
Description
0-3
16 – 19
Application parameters
4-6
20 – 22
Trim values, factory set
7
23
8 – 15
-
-
24 – 31
Device Address
Chip ID, factory set
For factory test purpose. Read only.
Table 2: Memory map overview
As shown in the table above, registers 0 – 3 and 7 are used for configuring the chip in the application. Before the devices can be used in a
given light curtain system, the required application parameters and the physical address of the chip in the system have to be stored into the
devices memories. The following table shows a parameter memory overview:
ROM RAM
0
16
1
2
17
18
3
4
19
20
5
21
6
7
8
9
10
11
12
13
14
15
22
23
24
25
26
27
28
29
30
31
15
VMODE
14
13
MODE
12
11
SOFF
10
TPER
TSET
CDET
9
DRATE
8
7
TSTMP
SENS IVCOFF SLOW
C2X
6
5
SENSH
4
3
TPULSE
2
1
POL
SENSN / VTHRLED
0
FUSEBIT
FUSEBIT
FUSEBIT
Application
parameters
Trimming
Address
Device Address
Chip ID
Chip ID
Figure 12: Detailed memory map
Parameters in white fields only shall be programmed. Never change the memory content of gray marked cells. Because only complete
registers can be programmed, the bits which are gray marked must be set to zero.
The RAM can only be written, if the corresponding ROM memory hasn’t been written before or if the volatile mode is active (VMODE, refer to
Table 3 on page 11). The last bit of each 16-bit ROM register serves as write inhibit bit. To write to the ROM, the microcontroller has to write to
the RAM first. From there, the microcontroller can first double check the data integrity. When a memory section is verified, the content can be
transferred from the RAM memory using the command PROG to the ROM (refer to chapter Command PROG).
The device is fully operational as well without programming the ROM but data will be lost at power down. Operating the chips in this mode is
helpful during the development of the product. However, in the final application, the parameters must be stored into the ROM memory.
4 The non-volatile memory is a one-time-programmable memory (OTP). Once the memory is programmed, the programmed values cannot
be overwritten anymore! This memory type is hereinafter called ROM.
5 Hereinafter called RAM.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
11
Datasheet epc12x - V2.1
www.espros.ch
epc120
5. Parameter Setting Registers 0/16
Parameter
Name
FUSEBIT
POL
TPULSE
Register No.
RAM
ROM
0
16
0
0
Bit No.
0
This bit will automatically be set when register 16 is programmed.
0
Values
0
Register 16 is not
programmed
1
Register 16 is programmed
16
1
Polarity of the LED pulse. Setting is depending on the LED driver circuitry.
1
Values
0
active low
1
active high
16
4..2
Pulse length of the light pulse. Setting is dependent on the LED type, the LED current, the
required response time of the system, the scan rate, the operating range, the lens, etc.
2
Values
Default
Setting
0
0
0
1μs
X
0
0
1
2μs
0
1
0
3μs
0
1
1
4μs
1
0
0
5μs
1
0
1
6μs
1
1
0
7μs
1
1
1
8μs
16
5
TSTMP
0
16
8..6
16
X
3
0
0
Default Setting
4
n/a
DRATE
Function
Recommended Setting
X (typical setting)
no function, must be set to “0”
Time stamp. The LED pulse is generates in the middle of the time stamp range.
8
7
6
Values
Default Setting
0
0
0
30μs
X
0
0
1
60μs
0
1
0
90μs
0
1
1
120μs
1
0
0
150μs
1
0
1
180μs
1
1
0
210μs
1
1
1
240μs
10..9
Recommended Setting
This parameter should be set to the same length as the
receive window length, given by the scanning time by
the microcontroller. I.e., if the time between the SCAN
commands issued by the micro processor is 60μs, this
parameter should be set to 60μs.
Data rate on the 2-wire bus
10
9
Values
0
0
250 kbit/s
0
1
500 kbit/s
1
0
1 Mbit/s
1
1
2 Mbit/s
Default Setting
X
Recommended Setting
if the physical 2-wire bus length is up to 100 meters
if the physical 2-wire bus length is less than 3 meters
...continued on next page...
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
12
Datasheet epc12x - V2.1
www.espros.ch
epc120
Parameter
Name
SOFF
MODE
VMODE
Register No.
RAM
ROM
0
16
0
0
16
Bit No.
Function
11
Status of voltage regulator for internal VDD
11
Values
Default Setting
0
On
X
1
Off
when used a receiver
when used as interface chip with 3.3V micro controller
14..12
Mode for epc120 usage
14
13
12
Value
1
1
0
6
16
Recommended Setting
15
Volatile mode
15
Values
Default Setting
0
On
X
1
Off
Recommended Setting
This setting allows to overwrite the RAM contents, which is useful during
debugging. Once the system is fully developed, this parameter should be set to
“1”. This setting could also be useful, if the system parameters should be
changed “on the fly” in dynamic systems. it is recommended to program the
address and burn it into the ROM first. All other parameters can then be
downloaded upon power-up.
Set to “1” in the final product to avoid accidentally overwriting of the contents of
the RAM registers
Table 3: epc120 Registers 0 and 16
6. Parameter Setting Registers 1/17
Parameter
Name
FUSEBIT
Register No.
ROM
RAM
1
17
Bit No.
Function
0
This bit will automatically be set when register 17 is programmed.
0
Values
0
Register 17 is not programmed
1
Register 17 is programmed
n/a
1
17
12..1
no function, must be set to “0”
TPER
1
17
15..13
must be set to “010”
15
14
13
0
1
0
Table 4: epc120 Registers 1 and 17
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
13
Datasheet epc12x - V2.1
www.espros.ch
epc120
7. Parameter Setting Registers 2/18
Parameter
Name
FUSEBIT
SENSN
SENSH
Register No.
ROM
RAM
2
18
2
2
Bit No.
Function
0
This bit will automatically be set when register 18 is programmed.
0
Values
0
Register 18 is not programmed
1
Register 18 is programmed
18
3..1
Lower threshold setting of the receiver input (sensitivity). A lower value increases the sens itivity. A too sensitive setting leads to false readings because of shot noise of the receiver
photo diode and the internal amplifier (typ. input noise level is 7nA RMS without photo di ode). Also induced EMI can lead to false readings if the sensitivity is set too low. The EMI
sensitivity is heavily depending on the system architecture and the electromechanical
design. The better the shielding of the chip and the photo diode and the better the PCB
layout, the better the EMI immunity.
The tolerance of the threshold is approx. ±25%.
3
2
1
Values
Default Setting
0
0
0
24nA
X
0
0
1
36nA
0
1
0
48nA
0
1
1
60nA
1
0
0
72nA
1
0
1
84nA
1
1
0
96nA
1
1
1
108nA
18
6..4
Recommended Setting
X
Upper threshold setting of the receiver input (light reserve level). The tolerance of the
threshold is approx. ±25%.
6
5
4
Values
Default Setting
0
0
0
60nA
X
0
0
1
72nA
0
1
0
84nA
0
1
1
96nA
1
0
0
108nA
1
0
1
120nA
1
1
0
132nA
1
1
1
144nA
Recommended Setting
Set this value 50% above
the value set at SENSN,
i.e., if SENSN is set to
48nA, set SENSH to 72nA
SLOW
2
18
7
no function, must be set to “1”
IVCOFF
2
18
8
no function, must be set to “0”
SENSLC
2
18
9
must be set to “1”
n/a
2
18
12..10
no function, must be set to “0”
TSET
2
18
15..13
Settling time delay from inactive to active mode.
15
14
13
Values
Default Setting
0
0
0
0
X
0
0
1
1
Comments
If TSCAN >=60μs
If TSCAN <60μs
Table 5: epc120 Registers 2 and 18
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
14
Datasheet epc12x - V2.1
www.espros.ch
epc120
Parameter
Name
Register No.
FUSEBIT
RAM
ROM
3
19
Bit No.
0
This bit will automatically be set when register 18 is programmed.
0
Values
0
Register 18 is not programmed
1
Register 18 is programmed
n/a
3
19
8..1
C2X
3
19
9
9
CDET
3
TPER
3
Function
no function, must be set to “0”
Current amplitude on the 2-wire bus
Values
Default Setting
Recommended Setting
0
8mA
X
X
1
16mA
19
11..10
Detection level for the comparator on the 2-wire bus. The level represents the optimum sig nal amplitude on the bus.
11
10
Values
Default Setting
0
0
50mV
X
0
1
n/a
1
0
100mV
1
1
200mV
17
15..13
Recommended
Setting
X
must be set to “010”
15
14
13
0
1
0
Table 6: epc120 Registers 3 and 19
All other registers are factory set and must not be used or altered.
8. Sample Parameter Setting
Register #
If we are going to use a system with a maximum cable length of 3 meters, and the maximum speed on the 2-wire bus, it is recommended to
set the registers as follows:
ROM RAM
0
16
1
17
2
18
3
19
4
20
5
21
6
22
7
23
8
24
9
25
10 26
11 27
12 28
13 29
14 30
15 31
15
1
0
0
0
14
1
1
0
0
13
1
0
1
0
12
0
0
0
0
11
0
0
0
1
10
1
0
0
0
Bit #
8
7
0
0
0
0
0
1
0
0
don't use
don't use
don't use
9
1
0
1
0
6
0
0
0
0
5
0
0
0
0
4
1
0
1
0
Address
3
0
0
0
0
2
0
0
1
0
1
1
0
1
0
0
X
X
X
X
don't use
Chip ID
Figure 13: Sample parameter setting for high speed operation
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
15
Datasheet epc12x - V2.1
www.espros.ch
epc120
9. Timing
Overview
To operate the individual elements at the 2-wire bus, some steps per element are necessary. The following drawing shows the concept:
Rx & Tx
wakeup the epc120 element
(from standby to operation)
open the receive window and
send a light pulse out through
the LED pin after PDELAY
close the receive window and
put the device to standby
read the result of the last light
reception
Figure 14: Basic sequence to operate one light beam. Note that the process in the
receiver and in the transmitter are running concurrently.
The individual epc120 elements at the 2-wire bus are normally in a sleep mode in order to keep the overall power consumption as low as
possible. Thus, an epc120 element has to be activated before it can be used. This wakeup procedure needs a certain time until all internal
operating levels have been stabilized. This time is called settling time which can be set with the parameter TSET. Then, the receive window
can be opened and the internal LED driver send a pulse out through the LED pin, which the chip can receive, if no obstacle is in the light
beam. After that, the receive window must be turned off which also puts the receiver to standby. Finally, the receive results which are stored in
the ecp120 element can be read.
In fact, there are several steps to operate one light beam only. This needs quite a long time if everything is done in a strictly sequential way. In
order to improve the performance of the whole system, certain steps can be done in parallel. The following chapters describe the timing
processes in more detail.
Timing
The microprocessor in the bus controller controls epc120 with SCAN commands. Every SCAN command includes an address which selects
the requested epc120 element.
PD PIN operation: A first SCAN command switches the selected epc120 element from standby into operation mode. The process from
standby to operation requires a certain time which is called settling time (see Figure 15). The settling time minimum is 60μs. The second
SCAN command opens the the reception window, there also the pulse at the LED PIN is sent, where a third SCAN command closes the
reception window and puts the epc120 element back to standby. The fourth SCAN command fetches the received results.
LED PIN operation: A first SCAN command switches the selected epc120 element from standby into operation mode. The process from
standby to operation requires a certain time which is called settling time (see Figure 15). The second SCAN command starts the light pulse
window. After the time PDELAY, one light pulse of the length TPULSE is generated. A third SCAN command puts the element back to standby.
If the TSTMP and the period of the SCAN commands of the microprocessor are equal the pulse will be emitted exactly in the middle of the
reception window.
The whole operation is optimized for shortest possible scan periods. Figure 15 shows the timing for a settling time of one scan period
(TSET=0) and the addresses given in the shortest possible sequence.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
16
Datasheet epc12x - V2.1
www.espros.ch
epc120
TDEL
SPI in
Out n
Out n+1
Out n+2
SCAN n+3
SCAN n+4
SCAN n+5
TSCAN
SPI out
2-Wire Bus
SCAN n
SCAN n
SCAN n+1
SCAN n+2
SCAN n+1
SCAN n+2
Out n
SCAN n+3
Out n+1
SCAN n+4
PD n
Settling
Receive Window
Output, Standby
PD n+1
TSET
Settling
Receive Window
Output, Standby
Settling
Receive Window
PD n+2
LED n
Settling
Output, Standby
Standby
TPDELAY
LED n+1
Out n+2
TPULSE
Settling
Standby
Settling
LED n+2
Standby
Figure 15: Timing of the scan process
where
n
= element number
TSCAN = interval between two scan commands which is given by the micro processor
The minimum delay time between the first SCAN command and the earliest possible access of the result can be calculated as a function of
the parameter TSET and the scan period T SCAN:
T DEL=TSET 3⋅T SCAN
The sensor device counts the number of SCAN commands on the bus to present its result at the right time. If the number of a SCAN
command is n, the result will arrive with the SCAN command n+TSET+3 .
The timing of the emitter commands have to be adjusted in order to emit the light pulse near the center of the reception window of the corres ponding receiver. E.g. if the reception window length is set to 30 μs, the light pulse shall be generated 15μs after the opening of the receive
window. The length of the reception window is defined by the time elapsed between the second and the third SCAN
command. The parameter
<name>
TSTMP
defines
the
time
window
to
measure
the
arrival
time
of
the
received
light
pulse.
This
result
is
returned
in
the
result TIMESTAMP. The
<Title>
timing position of the following light pulses can be optimized to the center of the receiving window. The resolution of TIMESTAMP is 4 bits.
Thus, the value is 0000 if the pulse is received at the beginning of the window, and 1111 if it arrived at the end. A light pulse received approx.
in the by
middle
the receive
would
represented
ascopied
0011,
0100
or 0101.
s confidential and protected
law and of
international
trades. window
It must not be
shown be
to any
third party nor be
in any
form without
our written permission .
The minimal scan period, which is the time between two consecutive SCAN commands, is given by the communication on the 2-wire bus: 62
bits for the command and the results have to be transmitted in this time. The minimal scan period is then
T SCANmin=31∗T CLK∗k
k is given by the parameter DRATE and varies between 1 and 8 (refer to Table 1, Table 3 and Table 7). TCLK is 1μs. Thus, the minimal scan
period is 31μs.
Special Cases
•
If the same device is addressed again at the end of its reception window, it continues waiting for pulses. This procedure allows to
synchronize the receiver with the transmitter on an optical basis, if there is no electrical synchronization.
•
If a device detects a command during a scan operation which is not the command SCAN, it is put into standby mode.
•
A SCAN command with address 0 can be used to fetch the results without starting a new scan command.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
17
Datasheet epc12x - V2.1
www.espros.ch
14.09.2010
Page 1
epc120
10. SPI Interface
The SPI interface allows the microcontroller to communicate with the sensors over the 2-wire bus system via the interface device.
While data are sent to the interface chip by the microcontroller, the result of the last (or more generally: a previous) command is sent from the
interface chip to the microcontroller according to the SPI protocol. The timing diagram is shown in Figure 16).
CS
tL
SCK
t1
tH
1/fSCK
tHold
tSU
SI
tD
SO
Figure 16: SPI bus timing
Timing Specification SPI Interface
Symbol
Parameter
Conditions/Comments
Values
Min.
Typ.
Units
Max.
fSCK
SCK Clock frequency
tH / tL
HIGH and LOW period of SCK
50
10
ns
tSU / tHold
Set-up and hold time SI
15
ns
t1
Edge time CSB - SCK
trf / trfSCK
Rise / fall time
SO, SCK
20
ns
tD
Data valid after SCK edge
SO
20
ns
50
MHz
ns
Command Overview
General Description
Communication is based on telegrams, which are sent and received over the 2-wire bus. Such telegrams are initiated by the respective
command to the SPI interface. The epc10x chips accept two types of commands:
1.
2.
Commands which communicate to the interface chips, also called “Direct Commands” ( Figure 17).
Commands which communicate to the chips at the 2-wire bus, also called “Broadcast Commands” ( Figure 18).
The first bit in the data stream from the microprocessor to the interface chip (SI pin) defines whether it is a command to the interface chip (a
“0”) or the the chips on the 2-wire bus (a ”1”).
CS
SCK
SI
C0
C1
Command
C2
R0
R1
R2
R3
R4
D0
D1
Register Address or Cmd Extension
Dn
Data
Figure 17: Communication to the interface device (Direct Command)
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
18
Datasheet epc12x - V2.1
www.espros.ch
epc120
CS
SCK
A0
SI
A1
A2
A3
A4
A8
A9
C0
Device Address
C1
C2
R0
R1
R2
R3
R4
D0
Register Address
or Cmd Extension
Command
D1
Dn
Data
Figure 18: Communication to the sensor devices (Broadcast Command)
Command List
Name
Command
Code
C0 .. C2
SCAN
000
Command
Extension Code
R0 .. R4
Function
Scan
No operation
Mode
Number of data bits
on 2-wire bus
D0..Dn
Returned
Data
Broadcast
62
Yes
NOP
000
Direct
0
Yes
READ
010
Register address
Read
both
97
Yes
WRITE
011
Register address
Write to volatile register
both
62
No
ADRA
101
PROG
110
Register address
Address allocation
Broadcast
62
No
Program
both
62
No
TEST
111
10000
Test mode
both
80
Yes
RESET
111
11001
Reset the device
both
62
No
Table 7: Command list
Remarks:
•
Additional SCK clock cycles have no effect.
•
The telegram length on the 2-wire bus is given in the number of data clock cycles. It allows to calculate the minimum int erval between
two commands.
•
If an SPI command is given while another command is being transmitted on the 2-wire bus, the new command is ignored.
•
The READ and WRITE commands in the direct access mode require 2 additional SCK cycles.
Designed
<Text>
26.02.2009
Approved
<Text>
<Date>
Scale
M 1:1
DIN A3
Command SCAN
1
Page
The command
SCAN enables the addressed device, times the ongoing operation or fetches the scan result. The operation of thePart
command
Part Name
No.
SCAN is described more in detail in Chapter Error: Reference source not found.
<Partname>
<x000 000>
File:
CS
SCK
SI
N
D0
D1
D2
D3
D4
D5
D20
E0
E3
Figure 19: Timing of the results of a SCAN command
The bit N indicates whether a new result has been received. D 0...D4 contains the address, D 11...D20 contains the returned data, E 0...E3 contains
an error code. D 5...D10 are empty.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
19
Datasheet epc12x - V2.1
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26.05.2011
Page 1
File:
epc120
Data Bits
N
D0 … D3
D4
D5
Function
Indicates, if new data is available
N
Values
0
no new data available
1
new data available
Timestamp
Status of receiver threshold “normal”
D4
Values
0
Receiver threshold set by SENSN not reached
1
Receiver threshold set by SENSN exceeded
Status of receiver threshold “high” (light reserve)
D4
Values
0
Receiver threshold set by SENSH not reached
1
Receiver threshold set by SENSH exceeded
D5 … D10
empty, not used
D11 … D20
Device address
E0 … E3
Error codes, refer to Chapter Error Codes
Table 8: Result of a SCAN command
Command NOP
The command NOP can be used to fetch the last received data without sending a new command. With this command it is possible to monitor
the 2-wire interface by a second interface device in a redundant system.
Command TEST
The command TEST issues an internal test pulse or a DC current at the PD input pin on a specific receiver. It simulates basically a received
light pulse or DC sunlight influence to check the proper functionality of the receiver(s) without using an emitter. This mode is initialized by the
command TEST and is left after a complete SCAN sequence.
Code
C0 … C 2
Extension
R0 … R 4
111
10000
Amplitude
D0 … D 4
1xxxxx
x1xxxx
xx1xxx
xxx1xx
xxxx1x
xxxxx1
25nA
50nA
100nA
100μA
500μA DC
2mA DC
Current Shape
Pulse
Pulse
Pulse
Pulse
DC
DC
Table 9: Self Test
The applied current is the sum of different current sources: In column “Pulse Amplitude” of Table 9 a “1” means, that the corresponding
current is added. Example: 110000 generates a pulse of 75nA without DC.
Command RESET
The command RESET resets the device and initiates a startup. All devices can be reset simultaneously by using address 0.
Command ADRA
ADRA is used during the configuration of a light curtain system to allocate a logical address to the physical position of the the emitter or
receiver element.
The command ADRA stores the device address to the volatile memory only (RAM). If the device address has to be stored permanently, the
command PROG has to be used to copy the previous stored device address from the RAM register into the ROM register. ADRA can only be
used if there was no previous PROG command to the address register.
The address 0 is reserved to address all devices together or none and must not be used as an individual address.
The command ADRA generates no result.
For details refer to Chapter Address Programming.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
20
Datasheet epc12x - V2.1
www.espros.ch
epc120
Command READ
The RAM and ROM can be read by the command READ. The command is extended by the register address.
CS
SCK
SI
N
D0
D1
D2
D3
D4
D5
D20
Figure 20: Timing Result Data
The bit N indicates whether a new result has been received (broadcast mode). D 0...D4 contains the address, D11...D20 contains the returned
data.
Data Bits
N
Function
Indicates, if new data is available
N
Values
0
no new data available
1
new data available
D0 … D4
5 bit register address
D5 … D20
16 bit returned data (one complete register)
<Timming SPI read command
Table1>10:
Result of a READ command
<LST>
10.09.2010
Page 1
File:
This document is confidential and protected by law and international trades. It must not be shown to any third party nor be copied in any form without our written permission .
Command WRITE
Data can be written into the RAM by using the command WRITE. The command is extended by the register address and the data. It is only
possible to write to registers if the corresponding register in the ROM has not been written yet. It is not possible to write directly to a ROM
register. If the data has to be stored into the ROM register, a subsequent command PROG has to be used.
Command PROG
The command PROG transfers the data from the RAM register to the corresponding ROM register. See chapter Address Programming for a
detailed description.
Returned Results
The results at pin SO depends on one of the previous commands and can be fetched by any command or just by toggling SCK while CS is
low (=NOP).
•
The data is represented with the LSB first.
•
After an SPI communication the data register is cleared.
•
By holding the CS line to 0 it is possible to trigger on a positive edge of SO.
•
If more clock toggles SCK are issued than data can be fetched, zeros are transmitted.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
21
Datasheet epc12x - V2.1
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epc120
11. Address Programming
General Description
The device address is initially set to “00000” and the devices are not parametrized. However, all devices hold a unique chip ID. However, due
to the 2-wire bus concept, the physical location of an individual device is not known to the microcontroller. In order to operate the light
curtain, the microcontroller needs to allocate a specific receiver to a specific emitter. Usually, the receiver at one end of the 2-wire bus gets
the address 1, the next receiver the address 2 and so on. The same must be done on the emitter side. Once all devices on the receiver and
on the emitter side got their address, the microcontroller can operate the light curtain. The address allocation, meaning the allocation of a
physical location to a logical address, is usually done in the factory of the light curtain manufacturer.
To do so, a specific address allocation procedure together with the parametrization of the devices must be executed first. The following
procedure is an example how to allocate a unique address and how to parametrize each device.
No.
Step
Description
1
Set the address of
the interface
device
Set the address of the interface device with a direct command to a fix number, which should not be 0. It is
recommended to use generally the address 1023 for the interface device.
2
Parametrize the
devices on the 2wire bus
The data rate DRATE of the 2-wire interface is initially set to 300 kbit/s. It shall be set to the correct value
by addressing all devices, which are initially at address 0, simultaneously.
During this step, all other parameters in register 16 can also be set.
3
Parametrize the
interface device
The data rate of the 2-wire interface is initially set to 300 kbit/s. It has to be set to the same value like the
other devices on the same 2-wire bus.
4
Set all other
registers
For the address allocation the following parameters should be set:
TPER = 2
SENSN = 7
SLOW=1
This can be done to all devices at the same time by writing the registers to device 0.
5
Address allocation
Since the devices have an open receive window, all of them are able to receive light pulses. This mode is
used to allocate the logical address to the physical location. The procedure is as follows:
• Issue the command ADRA using address n
• flash a light pulse to the photo diode which is connected to the chip at the physical position n (make sure
that all the other photo diodes cannot receive a light pulse). By receiving a light pulse, the address n is
stored into the RAM of the element at the physical position n. Thus, the device, which receives a light
pulse, memorizes the address n as its own address in the final system.
This procedure has to be repeated for every individual element on the 2-wire bus. It is recommended to
start with the address 1 for the element which is closest to the controller and increment the address by 1
with every individual element. In the case of a 20-beam light curtain, addresses from 1 to 20 on the receiv er and on the emitter side are accessible. However, the interface chip is usually located at address 1023.
6
Address check
It is recommended to check the correct address setting by addressing every device in the system using the
READ command. All devices addressed shall response to the READ command.
7
Address
programming
Once all addresses of all devices at the 2-wire bus are stored into the RAM (register 23), the address
should be transferred to the ROM (register 7) for each device separately by using the command PROG.
Please refer to chapter 11. Address Programming.
8
Set parameters
Parameters like TSTMP, MODE, VMODE, TPULSE etc. are stored into the RAM of all devices using the
command WRITE. If the global address “0” is used, all devices receive the parameters at the same time.
Since the internal voltage regulator of the interface device is not needed, the parameter SOFF has to be
set to “1” (refer to Table 3). All other devices at the 2-wire bus must have a “0” for SOFF.
9
Check
parameters
The parameters should be checked by reading them back from each device using the READ command.
10
Program
parameters
If all parameters are stored correctly, store the parameters into the non-volatile memory by using the
command PROG.
11
Test
programming and
addressing
To check the programming of addresses and parameters, turn off the power supply or reset all devices and
readout all addresses and parameters again.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
22
Datasheet epc12x - V2.1
www.espros.ch
epc120
Programming Procedure
Programming the device is a transfer of the data from the RAM to the corresponding ROM register. Each 16-bit register must be transferred
individually. Thus, register 16 is transferred to register 0, register 17 to register 1, register 18 to register 2, register 19 to register 3, and
register 23 to register 7. All other registers must not be used.
Figure 21 shows the timing of the programming sequence for one register:
50μs
400μs
7.5V
VDD
5V
CS
SCK
SI
1
1
0 R0 R1 R2 R3 R4
PROG
Register
Figure 21: Direct programming procedure
50μs
400μs
7.5V
VDD
5V
CS
SCK
SI
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
1
Device Address
1
0 R0 R1 R2 R3 R4
PROG
Register
Figure 22: Broadcast programming procedure
“PROG” is the PROG command sequence (110).
“Register” means the address of the target register (ROM), e.g. 0, 1, 2, 3, 7.
During programming, the voltage at pin VDD has to be increased to V prog (7.5V) and has to be kept stable buffered during the whole
programming cycle. The timing parameters given in Figure 21 and Figure 22 have to be obeyed.
Remarks:
•
It is possible to program more than one register during a VDD high cycle. Between two PROG commands a delay of 400 μs is needed.
•
Each register can be programmed once only (OTP).
•
After programming a register, bit no. 0 of this register becomes automatically a one to indicate that the register is programmed.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
23
Datasheet epc12x - V2.1
www.espros.ch
epc120
12. Considerations for Safety Applications
Since the epc120-family chips can be used in safety related products, like machine safety light products, certain data integrity mechanisms
have been integrated. The safety concept on chip and communication level are described in this chapter.
Data Integrity on the 2-Wire Power-Bus
Several mechanisms on different layers are implemented to guarantee a low residual error rate on the 2-wire power-bus.
Physical layer
•
Modulation and medium: Current modulation on a twisted pair line is highly immune to interference.
•
Start bit detection: The start pulse must have the correct orientation. Otherwise, the pulse is discarded.
•
Pulse alternation: Since Manchester coding is used, the pulses need to alternate. An error is detected, if this is not the case.
•
Pulse timing: The timing of the information pulses is fixed. A missing bit (too long pause) is detected as an error.
•
End bit detection: Since current modulation is used and the current is switched off when the message is completed, the last pulse has a
specified orientation.
•
Sequence length: The message length is well known. A too short or too long message is detected as an error.
Data link layer
•
Error control coding: If no errors have been detected on the physical layer, the received pulse sequence is processed by an error
control algorithm. Depending on the application, either 2 errors can be corrected, or 4 errors can be detected. A higher number of errors
can be detected with a reliability of 1000:1.
•
Strict master-slave system: A sensor may only respond, if a request from the microcontroller was correctly received.
•
Explicit addressing: Each message (master > slave and slave > master) contains the address of the sensor element. Even if the wrong
sensor replies to the microcontroller call, the error will be detected.
Residual Error Rate
Although no explicit calculations have been done yet, the residual error rate of the 2-wire power-bus is at least as good as in the ASi. The ASi
has an residual error probability of a system with Hamming distance 5 (HD5) and belongs to the DIN 19244 data integrity class I2 for an error
probability p=1e-2, and to class I3 for p=1e-3.
Error Cases
Each sensor device has its unique address. The microprocessor addresses each device individually and fetches the result some scan periods
later. The result includes also the address of the answering device.
Error Cases
Consequences
2 sensor answer on the same
address
Collision during the transmission of the result. → Error detection in the interface
device → Error state.
Error during the scan command
No device answers → no data (all zero).
Error during result transmission
Error detection in the interface device → Error state.
Error Codes
Different error states are monitored:
Device
Error
Action
Error Code
E0 … E3
1
Sensor
Non-correctable error in the received telegram
Device doesn't response
-
2
Sensor
Command to fetch the result too early
Normal answer
-
4
Interface
No answer from the sensor device
Result data zero
-
5
Interface
Non-correctable error in the received telegram
Error reported
1xxx *)
6
Interface
Return telegram not complete
Error handling procedure
0100
Table 11: Error states
*) The last three error bits contain the number of detected errors.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
24
Datasheet epc12x - V2.1
www.espros.ch
Layout Information (all measures in mm,
)
CSP-10 Package
Designed
Approved
Scale
Page
0.15
1.9 +0.0/-0.1
Part Name
<Name>
26.02.2009
<Name>
<Data>
M 1:1
DIN A4
1
Part No.
<Partname>
<x000 000>
This document is confidential and protected by law and international trades. It must not be shown to any third party nor be copied in any form without our written permission
.
epc120
File: Unbenannt
0.1524
Bottom View ∅ 0.12
0.5
0.5
Pin 1
Solder balls Sn97.5Ag2.5
0.11 ±0.01
0.5
0.3
0.15
2.0
0.5
1.4 +0.0/-0.1
0.5
∅ 0.3
0.5
0.5
2.5
no solder mask inside this area
Figure 23: CSP10: Mechanical dimensions
Figure 24: CSP10: Layout recommendation
QFN-16 Package
<Title>
1.9
Top view
2.9 - 3.1
1.9
Bottom View
19.01.2012
<name>
Page 1
:
0.5
0.1 - 0.2
0.02
0.9
2.9 - 3.1
0.25
document is confidential and protected by law and international trades. It must not be shown to any third party nor be copied in any form without our written permission.
0.25
0.3
Figure 25: QFN-16: Mechanical dimensions
LST
Mechanical dimension QFN16 Package
15.08.2010
Page 1
File:
This document is confidential and protected by law and international trades. It must not be shown to any third party nor be copied in any form without our written permission.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
25
Datasheet epc12x - V2.1
www.espros.ch
epc120
Reflow Solder Profile
CSP6 Tape
QFN16 Tape
8
Pinhas
1 to follow the recommendations of IPC/JEDEC
Pin 1J-STD-020C (min. revision C) for
For infrared or conventional soldering the solder profile
Pb-free assembly for both types of packages. The peak soldering t emperature (TL) should not exceed +260°C for a maximum of 4 sec.
12
Packaging Information (all measures in mm)
Tape & Reel Information
The devices are mounted on embossed tape for2 automatic placement systems. The tape is wound on 178 mm (7 inch) or 330 mm (13 inch)
reels and individually packaged for shipment. General tape-and-reel specification data are available in a separate data sheet and indicate the
tape sizes for various package types. Further tape-and-reel specifications can be found in the 8Electronic Industries Association (EIA) standard
481-1, 481-2, 481-3.
CSP6 Tape
QFN16 Tape
Pin 1
12
8
Pin 1
4
8
Figure 26: CSP10 and QFN16 Tape Dimensions
ESPROS Photonics AG does not guarantee that there are no empty cavities. Thus, the pick-and-place machine should check the presence of
a chip during picking.
Ordering Information
Type
Package
RoHS compliance
Packaging
Method
epc120-CSP10
CSP10
Yes
Reel
epc120-QFN16
QFN16
Yes
Reel
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
26
Datasheet epc12x - V2.1
www.espros.ch
epc120
IMPORTANT NOTICE
ESPROS Photonics AG and its subsidiaries (epc) reserve the right to make corrections, modifications, enhancements, improvements, and
other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the
latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject
to epc’s terms and conditions of sale supplied at the time of order acknowledgment.
epc warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with epc’s standard war ranty. Testing and other quality control techniques are used to the extent epc deems necessary to support this warranty. Except where man dated by government requirements, testing of all parameters of each product is not necessarily performed.
epc assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applic ations using epc components. To minimize the risks associated with customer products and applications, customers should provide adequate
design and operating safeguards.
epc does not warrant or represent that any license, either express or implied, is granted under any epc patent right, copyright, mask work
right, or other epc intellectual property right relating to any combination, machine, or process in which epc products or services are used.
Information published by epc regarding third-party products or services does not constitute a license from epc to use such products or
services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other
intellectual property of the third party, or a license from epc under the patents or other intellectual property of epc.
Resale of epc products or services with statements different from or beyond the parameters stated by epc for that product or service voids all
express and any implied warranties for the associated epc product or service. epc is not responsible or liable for any such statements.
epc products are not authorized for use in safety-critical applications (such as life support) where a failure of the epc product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically
governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,
and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their
products and any use of epc products in such safety-critical applications, notwithstanding any applications-related information or support that
may be provided by epc. Further, Buyers must fully indemnify epc and its representatives against any damages arising out of the use of epc
products in such safety-critical applications.
epc products are neither designed nor intended for use in military/aerospace applications or environments unless the epc products are specifically designated by epc as military-grade or "enhanced plastic." Only products designated by epc as military-grade meet military specific ations. Buyers acknowledge and agree that any such use of epc products which epc has not designated as military-grade is solely at the
Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
epc products are neither designed nor intended for use in automotive applications or environments unless the specific epc products are
designated by epc as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, epc will not be responsible for any failure to meet such requirements.
© 2011 ESPROS Photonics Corporation
Characteristics subject to change without notice
27
Datasheet epc12x - V2.1
www.espros.ch