NSC DS08MB200 Dual 800 mbps 2:1/1:2 lvds mux/buffer Datasheet

DS08MB200
Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer
General Description
Features
The DS08MB200 is a dual-port 1 to 2 repeater/buffer and 2
to 1 multiplexer. High-speed data paths and flow-through
pinout minimize internal device jitter and simplify board layout. The differential inputs and outputs interface to LVDS or
Bus LVDS signals such as those on National's 10-, 16-, and
18- bit Bus LVDS SerDes, or to CML or LVPECL signals.
The 3.3V supply, CMOS process, and robust I/O ensure high
performance at low power over the entire industrial -40 to
+85°C temperature range.
■ Up to 800 Mbps data rate per channel
■ LVDS/BLVDS/CML/LVPECL compatible inputs, LVDS
■
■
■
■
■
■
■
compatible outputs
Low output skew and jitter
On-chip 100Ω input termination
15 kV ESD protection on LVDS Inputs/Outputs
Hot plug Protection
Single 3.3V supply
Industrial -40 to +85°C temperature range
48-pin LLP Package
Typical Application
20157420
Block Diagram
20157401
FIGURE 1. DS08MB200 Block Diagram
© 2007 National Semiconductor Corporation
201574
www.national.com
DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer
November 21, 2007
DS08MB200
Pin Descriptions
Pin
Name
LLP Pin
Number
I/O, Type
Description
SWITCH SIDE DIFFERENTIAL INPUTS
SIA_0+
SIA_0−
30
29
I, LVDS
Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML,
or LVPECL compatible.
SIA_1+
SIA_1−
19
20
I, LVDS
Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML,
or LVPECL compatible.
SIB_0+
SIB_0−
28
27
I, LVDS
Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML,
or LVPECL compatible.
SIB_1+
SIB_1−
21
22
I, LVDS
Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML,
or LVPECL compatible.
LINE SIDE DIFFERENTIAL INPUTS
LI_0+
LI_0−
40
39
I, LVDS
Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
LI_1+
LI_1−
9
10
I, LVDS
Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LVPECL compatible.
SWITCH SIDE DIFFERENTIAL OUTPUTS
SOA_0+
SOA_0−
34
33
O, LVDS
Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes
1, 3).
SOA_1+
SOA_1−
15
16
O, LVDS
Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes
1, 3).
SOB_0+
SOB_0−
32
31
O, LVDS
Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes
1, 3).
SOB_1+
SOB_1−
17
18
O, LVDS
Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes
1, 3).
LINE SIDE DIFFERENTIAL OUTPUTS
LO_0+
LO_0−
42
41
O, LVDS
Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes 1,
3).
LO_1+
LO_1−
7
8
O, LVDS
Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes 1,
3).
DIGITAL CONTROL INTERFACE
MUX_S0
MUX_S1
38
11
I, LVTTL
Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed
through to the Line-side.
ENA_0
ENA_1
ENB_0
ENB_1
36
13
35
14
I, LVTTL
Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and
B-side has a separate enable pin.
ENL_0
ENL_1
45
4
I, LVTTL
Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a
separate enable pin.
VDD
6, 12, 37,
43, 48
I, Power
VDD = 3.3V ±0.3V.
GND
2, 3, 46, 47
(Note 2)
I, Power
Ground reference for LVDS and CMOS circuitry.
For the LLP package, the DAP is used as the primary GND connection to the device. The DAP
is the exposed metal contact at the bottom of the LLP-48 package. It should be connected to the
ground plane with at least 4 vias for optimal AC and thermal performance.
N/C
1, 5, 23,
24, 25, 26,
44
POWER
No Connect
Note 1: For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet.
Note 2: Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package.
Note 3: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS08MB200 device have been optimized
for point-to-point backplane and cable applications.
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2
DS08MB200
Connection Diagrams
20157402
20157403
Top View
DAP = GND
Directional Signal Paths Top View
(Refer to pin names for signal polarity)
TRI-STATE and Powerdown Modes
Output Characteristics
The DS08MB200 has output enable control on each of the six
onboard LVDS output drivers. This control allows each output
individually to be placed in a low power TRI-STATE mode
while the device remains active, and is useful to reduce power
consumption on unused channels. In TRI-STATE mode,
some outputs may remain active while some are in TRISTATE.
When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a Powerdown mode that consumes only 0.5mA (typical) of supply
current. In this mode, the entire device is essentially powered
off, including all receiver inputs, output drivers and internal
bandgap reference generators. When returning to active
mode from Powerdown mode, there is a delay until valid data
is presented at the outputs because of the ramp to power up
the internal bandgap reference generators.
Any single output enable that remains active will hold the device in active mode even if the other five outputs are in TRISTATE.
When in Powerdown mode, any output enable that becomes
active will wake up the device back into active mode, even if
the other five outputs are in TRI-STATE.
The output characteristics of the DS08MB200 have been optimized for point-to-point backplane and cable applications,
and are not intended for multipoint or multidrop signaling.
Multiplexer Truth Table
Data Inputs
(Note 4)
Control Inputs
Output
SIA_0
SIB_0
MUX_S0
ENL_0
LO_0
X
valid
0
1
SIB_0
valid
X
1
1
SIA_0
X
X
X
0 (Note 5)
Z
X = Don't Care
Z = High Impedance (TRI-STATE)
Repeater/Buffer Truth Table
Data
Input
Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to VDD thru a pull up resistor and the negative
LVDS input pin is tied to GND by a pull down resistor. The pull
up and pull down resistors should be in the 5kΩ to 15kΩ range
to minimize loading and waveform distortion to the driver.
Please refer to application note AN-1194, “Failsafe Biasing of
LVDS Interfaces” for more information.
Control Inputs
LI_0
ENA_0
ENB_0
(Note 4)
Outputs
SOA_0
SOB_0
X
0
0
valid
0
1
Z (Note 5) Z (Note 5)
Z
LI_0
valid
1
0
LI_0
Z
valid
1
1
LI_0
LI_0
X = Don't Care
Z = High Impedance (TRI-STATE)
Note 4: Same functionality for channel 1
Note 5: When all enable inputs from both channels are Low, the device
enters a powerdown mode. Refer to the applications section titled TRISTATE and Powerdown modes.
3
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DS08MB200
Absolute Maximum Ratings (Note 6)
Supply Voltage (VDD)
CMOS Input Voltage
LVDS Receiver Input Voltage (Note
7)
LVDS Driver Output Voltage
LVDS Output Short Circuit Current
Junction Temperature
Storage Temperature
Lead Temperature (Solder, 4sec)
Max Pkg Power Capacity @ 25°C
Thermal Resistance (θJA)
Package Derating above +25°C
ESD Last Passing Voltage
HBM, 1.5kΩ, 100pF
LVDS pins to GND only
EIAJ, 0Ω, 200pF
CDM
−0.3V to +4.0V
-0.3V to (VDD+0.3V)
250V
1000V
Recommended Operating
Conditions
-0.3V to (VDD+0.3V)
-0.3V to (VDD+0.3V)
+40 mA
+150°C
−65°C to +150°C
260°C
5.2W
24°C/W
Supply Voltage (VCC)
Input Voltage (VI) (Note 7)
Output Voltage (VO)
Operating Temperature (TA)
Industrial
3.0V to 3.6V
0V to VCC
0V to VCC
−40°C to +85°C
Note 6: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not
recommend operation of products outside of recommended operation
conditions.
41.7mW/°C
8kV
15kV
Note 7: VID max < 2.4V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(Note 8)
Max
Units
LVTTL DC SPECIFICATIONS (MUX_Sn, ENA_n, ENB_n, ENL_n)
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = VDD = VDDMAX
−10
+10
µA
IIL
Low Level Input Current
VIN = VSS, VDD = VDDMAX
−10
+10
µA
CIN1
Input Capacitance
Any Digital Input Pin to VSS
3.5
pF
COUT1
Output Capacitance
Any Digital Output Pin to VSS
5.5
pF
VCL
Input Clamp Voltage
ICL = −18 mA
−0.8
V
−1.5
LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)
VTH
Differential Input High Threshold
(Note 9)
VCM = 0.8V or 1.2V or 3.55V,
VDD = 3.6V
VTL
Differential Input Low Threshold
(Note 9)
VCM = 0.8V or 1.2V or 3.55V,
VDD = 3.6V
VID
Differential Input Voltage
VCM = 0.8V to 3.55V, VDD = 3.6V
100
2400
mV
VCMR
Common Mode Voltage Range
VID = 150 mV, VDD = 3.6V
0.05
3.55
V
CIN2
Input Capacitance
IN+ or IN− to VSS
IIN
Input Current
VIN = 3.6V, VDD = VDDMAX
−15
+15
µA
VIN = 0V, VDD = VDDMAX
−15
+15
µA
500
mV
35
mV
1.475
V
35
mV
-40
mA
0
−100
100
0
mV
mV
3.5
pF
LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)
VOD
Differential Output Voltage,
(Note 9)
ΔVOD
Change in VOD between
Complementary States
-35
VOS
Offset Voltage (Note 10)
1.05
ΔVOS
Change in VOS between
Complementary States
-35
IOS
Output Short Circuit Current
OUT+ or OUT− Short to GND
−21
COUT2
Output Capacitance
OUT+ or OUT− to GND when TRISTATE
5.5
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RL is the internal 100Ω between OUT+
and OUT−
4
250
360
1.22
pF
Parameter
Conditions
Min
Typ
(Note 8)
Max
Units
225
275
mA
0.6
4.0
mA
170
250
ps
170
250
ps
1.0
2.5
ns
1.0
2.5
ns
SUPPLY CURRENT (Static)
ICC
ICCZ
Supply Current
All inputs and outputs enabled and
active, terminated with differential load of
100Ω between OUT+ and OUT-.
Supply Current - Powerdown Mode ENA_0 = ENB_0 = ENL_0= ENA_1 =
ENB_1 = ENL_1 = L
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High Transition
Time
tHLT
Differential High to Low Transition
Time
tPLHD
Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200
Delay
Mb/s, measure at 50% VOD between
Differential High to Low Propagation input to output.
Delay
tPHLD
Use an alternating 1 and 0 pattern at 200
Mb/s, measure between 20% and 80% of
VOD. (Note 15)
tSKD1
Pulse Skew
|tPLHD–tPHLD| (Note 15)
25
75
ps
tSKCC
Output Channel to Channel Skew
Difference in propagation delay (tPLHD or
tPHLD) among all output channels. (Note
15)
50
115
ps
RJ - Alternating 1 and 0 at 400 MHz (Note
12)
1.3
1.5
psrms
DJ - K28.5 Pattern, 800 Mbps (Note 13)
15
34
psp-p
Pattern, 800 Mbps (Note
16
34
psp-p
tJIT
Jitter
(Note 11)
TJ - PRBS
14)
27-1
tON
LVDS Output Enable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from TRI-STATE to active.
0.5
1.5
µs
tON2
LVDS Output Enable time from
powerdown mode
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from Powerdown to active
10
20
µs
tOFF
LVDS Output Disable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to TRI-STATE
or powerdown.
12
ns
Note 8: Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
Note 9: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
Note 10: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at
400 MHz, tr = tf = 50ps (20% to 80%).
Note 13: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been subtracted. The input
voltage = VID = 500mV, K28.5 pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 14: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input
voltage = VID = 500mV, 27-1 PRBS pattern at 800 Mbps, tr = tf = 50ps (20% to 80%).
Note 15: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
5
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DS08MB200
Symbol
DS08MB200
Typical Performance Characteristics
Power Supply Current vs. Bit Data Rate
Total Jitter vs. Temperature
20157410
20157412
Total Jitter measured at 0V differential while running a PRBS 27-1 pattern with
Dynamic power supply current was measured with all channels active and togone channel active, all other channels are disabled. VDD = 3.3V, VID = 0.5V,
gling at the bit data rate. Data pattern has no effect on the power consumption.
VCM = 1.2V, 800 Mbps data rate. Stimulus and fixture jitter has been subtracted.
VDD = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2V.
Total Jitter vs. Bit Data Rate
20157411
Total Jitter measured at 0V differential while running a PRBS 27-1 pattern with
one channel active, all other channels are disabled. VDD = 3.3V, TA = +25°C,
VID = 0.5V. Stimulus and fixture jitter has been subtracted.
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6
Interfacing LVDS to LVPECL
An LVPECL driver consists of a differential pair with coupled
emitters connected to GND via a current source. This drives
a pair of emitter-followers that require a 50 ohm to VCC-2.0
load. A modern LVPECL driver will typically include the termination scheme within the device for the emitter follower. If
the driver does not include the load, then an external scheme
must be used. The 1.3 V supply is usually not readily available
on a PCB, therefore, a load scheme without a unique power
supply requirement may be used.
An LVDS driver consists of a current source (nominal 3.5mA)
which drives a CMOS differential pair. It needs a differential
resistive load in the range of 70 to 130 ohms to generate
LVDS levels. In a system, the load should be selected to
match transmission line characteristic differential impedance
so that the line is properly terminated. The termination resistor
should be placed as close to the receiver inputs as possible.
When interfacing an LVDS driver with a non-LVDS receiver,
one only needs to bias the LVDS signal so that it is within the
common mode range of the receiver. This may be done by
using separate biasing voltage which demands another power supply. Some receivers have required biasing voltage
available on-chip (VT, VTT or VBB).
20157461
FIGURE 2. DC Coupled LVPECL to LVDS Interface
Figure 2 is a separated π termination scheme for a 3.3 V
LVPECL driver. R1 and R2 provides proper DC load for the
driver emitter followers, and may be included as part of the
driver device (Note 16). The DS08MB200 includes a 100 ohm
input termination for the transmission line. The common mode
voltage will be at the normal LVPECL levels – around 2 V.
This scheme works well with LVDS receivers that have railto-rail common mode voltage, VCM, range. Most National
Semiconductor LVDS receivers have wide VCM range. The
exceptions are noted in devices’ respective datasheets.
Those LVDS devices that do have a wide VCM range do not
vary in performance significantly when receiving a signal with
a common mode other than standard LVDS VCM of 1.2 V.
20157463
FIGURE 4. DC Coupled LVDS to LVPECL Interface
Figure 4 illustrates interface between an LVDS driver and a
LVPECL with a VT pin available. R1 and R2, if not present in
the receiver (Note 16), provide proper resistive load for the
driver and termination for the transmission line, and VT sets
desired bias for the receiver.
20157464
FIGURE 5. AC Coupled LVDS to LVPECL Interface
20157462
FIGURE 3. AC Coupled LVPECL to LVDS Interface
Figure 5 illustrates AC coupled interface between an LVDS
driver and LVPECL receiver without a VT pin available. The
resistors R1, R2, R3, and R4, if not present in the receiver
(Note 16), provide a load for the driver, terminate the transmission line, and bias the signal for the receiver.
An AC coupled interface is preferred when transmitter and
receiver ground references differ more than 1 V. This is a
likely scenario when transmitter and receiver devices are on
separate PCBs. Figure 3 illustrates an AC coupled interface
between a LVPECL driver and LVDS receiver. R1 and R2, if
not present in the driver device (Note 16), provide DC load for
the emitter followers and may range between 140-220 ohms
for most LVPECL devices for this particular configuration. The
DS08MB200 includes an internal 100 ohm resistor to terminate the transmission line for minimal reflections. The signal
after ac coupling capacitors will swing around a level set by
internal biasing resistors (i.e. fail-safe) which is either VDD/2
or 0 V depending on the actual failsafe implementation. If internal biasing is not implemented, the signal common mode
voltage will slowly wander to GND level.
Note 16: The bias networks shown above for LVPECL drivers and receivers
may or may not be present within the driver device. The LVPECL driver and
receiver specification must be reviewed closely to ensure compatibility
between the driver and receiver terminations and common mode operating
ranges.
7
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DS08MB200
Interfacing LVPECL to LVDS
DS08MB200
Physical Dimensions inches (millimeters) unless otherwise noted
48-Pin LLP
NS Package Number SQA48a
Ordering Code DS08MB200TSQ (250 piece Tape and Reel)
DS08MB200TSQX (2500 piece Tape and Reel)
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8
DS08MB200
Notes
9
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DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer
Notes
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