FEATURES Superb Clamping Characteristics 3 mV Clamp Error 1.5 ns Overdrive Recovery Minimized Nonlinear Clamping Region 240 MHz Clamp Input Bandwidth 3.9 V Clamp Input Range Wide Bandwidth AD8036 AD8037 Small Signal 240 MHz 270 MHz Large Signal (4 V p-p) 195 MHz 190 MHz Good DC Characteristics 2 mV Offset 10 V/C Drift Ultralow Distortion, Low Noise –72 dBc typ @ 20 MHz 4.5 nV/√Hz Input Voltage Noise High Speed Slew Rate 1500 V/s Settling 10 ns to 0.1%, 16 ns to 0.01% 3 V to 5 V Supply Operation APPLICATIONS ADC Buffer IF/RF Signal Processing High Quality Imaging Broadcast Video Systems Video Amplifier Full Wave Rectifier PRODUCT DESCRIPTION The AD8036 and AD8037 are wide bandwidth, low distortion clamping amplifiers. The AD8036 is unity gain stable. The AD8037 is stable at a gain of two or greater. These devices allow the designer to specify a high (VCH) and low (VCL) output clamp voltage. The output signal will clamp at these specified levels. Utilizing a unique patent pending CLAMPIN™ input clamp architecture, the AD8036 and AD8037 offer a 10× improvement in clamp performance compared to traditional output clamping devices. In particular, clamp error is typically 3 mV or less and distortion in the clamp region is minimized. This product can be used as a classical op amp or a clamp amplifier where a high and low output voltage are specified. The AD8036 and AD8037, which utilize a voltage feedback architecture, meet the requirements of many applications which previously depended on current feedback amplifiers. The AD8036 and AD8037 exhibit an exceptionally fast and accurate pulse response (16 ns to 0.01%), extremely wide small-signal and FUNCTIONAL BLOCK DIAGRAM 8-Lead Plastic DIP (N), Cerdip (Q), and SO Packages NC 1 –INPUT AD8036/ AD8037 8 VH 2 7 +VS +INPUT 3 6 OUTPUT –VS 4 5 VL (Top View) NC = NO CONNECT large-signal bandwidths and ultralow distortion. The AD8036 achieves –66 dBc at 20 MHz, and 240 MHz small-signal and 195 MHz large-signal bandwidths. The AD8036 and AD8037’s recover from 2× clamp overdrive within 1.5 ns. These characteristics position the AD8036/AD8037 ideally for driving as well as buffering flash and high resolution ADCs. In addition to traditional output clamp amplifier applications, the input clamp architecture supports the clamp levels as additional inputs to the amplifier. As such, in addition to static dc clamp levels, signals with speeds up to 240 MHz can be applied to the clamp pins. The clamp values can also be set to any value within the output voltage range provided that VH is greater that VL. Due to these clamp characteristics, the AD8036 and AD8037 can be used in nontraditional applications such as a full-wave rectifier, a pulse generator, or an amplitude modulator. These novel applications are only examples of some of the diverse applications which can be designed with input clamps. The AD8036 is offered in chips, industrial (–40°C to +85°C) and military (–55°C to +125°C) package temperature ranges and the AD8037 in industrial. Industrial versions are available in plastic DIP and SOIC; MIL versions are packaged in cerdip. 4 AD8036 VH = 3V 3 OUTPUT VOLTAGE – Volts a Low Distortion, Wide Bandwidth Voltage Feedback Clamp Amps AD8036/AD8037 VH = 2V 2 VH = 1V 1 0 VL = –1V –1 –2 VL = –2V VL = –3V –3 CLAMPIN is a trademark of Analog Devices, Inc. –4 –4 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. –3 –2 –1 0 1 INPUT VOLTAGE – Volts 2 3 4 Figure 1. Clamp DC Accuracy vs. Input Voltage One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD8036_8037* Last content update 08/19/2013 02:20 am DOCUMENTATION PARAMETRIC SELECTION TABLES AN-649: Using the Analog Devices Active Filter Design Tool AN-581: Biasing and Decoupling Op Amps in Single Supply Applications AN-402: Replacing Output Clamping Op Amps with Input Clamping Amps AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage High Speed Systems MT-060: Choosing Between Voltage Feedback and Current Feedback Op Amps MT-059: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-to-Voltage Converters MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps MT-056: High Speed Voltage Feedback Op Amps MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR MT-052: Op Amp Noise Figure: Don’t Be Mislead MT-050: Op Amp Total Output Noise Calculations for Second-Order System MT-049: Op Amp Total Output Noise Calculations for Single-Pole System MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and Equivalent Noise Bandwidth MT-033: Voltage Feedback Op Amp Gain and Bandwidth MT-032: Ideal Voltage Feedback (VFB) Op Amp A Stress-Free Method for Choosing High-Speed Op Amps UG-460: Evaluation Board for Single, High Speed Operational Amplifiers (8-Lead SOIC) FOR THE AD8036 Find Similar Products By Operating Parameters High Speed Amplifiers Selection Table AD8036: Military Data Sheet ADI Warns Against Misuse of COTS Integrated Circuits Space Qualified Parts List Choosing High-Speed Signal Processing Components for Ultrasound Systems FOR THE AD8037 EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for the AD8036 View the Evaluation Boards and Kits page for the AD8037 Symbols and Footprints for the AD8036 Symbols and Footprints for the AD8037 DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: Americas: Europe: China: India: Russia: 1-800-262-5643 00800-266-822-82 4006-100-006 1800-419-0108 8-800-555-45-90 Choosing High-Speed Signal Processing Components for Ultrasound Systems Quality and Reliability Lead(Pb)-Free Data DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE SAMPLE & BUY dBm/dBu/dBv Calculator Analog Filter Wizard 2.0 Power Dissipation vs Die Temp ADIsimOpAmp™ OpAmp Stability AD8036AN SPICE Macro-Model Rev B, SMR/ADI AD8036 AD8037 View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. AD8036/AD8037–SPECIFICATIONS (V = 5 V; R = 100 ; A = +1 (AD8036); A = +2 (AD8037), V , V open, unless S LOAD ELECTRICAL CHARACTERISTICS otherwise noted) Parameter DYNAMIC PERFORMANCE Bandwidth (–3 dB) Small Signal Large Signal1 Bandwidth for 0.1 dB Flatness Slew Rate, Average +/– Rise/Fall Time Settling Time To 0.1% To 0.01% HARMONIC/NOISE PERFORMANCE 2nd Harmonic Distortion 3rd Harmonic Distortion 3rd Order Intercept Noise Figure Input Voltage Noise Input Current Noise Average Equivalent Integrated Input Noise Voltage Differential Gain Error (3.58 MHz) Differential Phase Error (3.58 MHz) Phase Nonlinearity CLAMP PERFORMANCE Clamp Voltage Range 2 Clamp Accuracy Clamp Nonlinearity Range 3 Clamp Input Bias Current (V H or VL) Clamp Input Bandwidth (–3 dB) Clamp Overshoot Overdrive Recovery DC PERFORMANCE 4, RL = 150 Ω Input Offset Voltage5 V V AD8036A Min Typ Max Conditions AD8037A Min Typ Max Unit MHz MHz 240 195 200 160 130 1200 1.4 2.6 130 1100 1500 1.2 2.2 VOUT = 2 V Step VOUT = 2 V Step 10 16 2 V p-p; 20 MHz, RL = 100 Ω RL = 500 Ω 2 V p-p; 20 MHz, RL = 100 Ω RL = 500 Ω 25 MHz RS = 50 Ω 1 MHz to 200 MHz 1 MHz to 200 MHz –59 –66 –68 –72 46 18 6.7 2.2 0.1 MHz to 200 MHz RL = 150 Ω RL = 150 Ω DC to 100 MHz 95 0.05 0.02 1.1 VCH or VCL 2× Overdrive, VCH = +2 V, VCL = –2 V TMIN–TMAX 8036, VH, L = ± 1 V; 8037, VH, L = ± 0.5 V TMIN–TMAX VCH or VCL = 2 V p-p 2× Overdrive, VCH or VCL = 2 V p-p 2× Overdrive ± 3.3 ± 3.9 ±3 100 ± 40 150 240 1 1.5 2 ± 10 4 Offset Voltage Drift Input Bias Current TMIN –TMAX Input Offset Current 0.3 TMIN –TMAX VCM = ± 2 V VOUT = ± 2.5 V TMIN –TMAX 66 48 40 INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Voltage Range, R L = 150 Ω Output Current Output Resistance Short Circuit Current POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio L 150 VOUT ≤ 0.4 V p-p 8036, VOUT = 2.5 V p-p; 8037, V OUT = 3.5 V p-p 160 VOUT ≤ 0.4 V p-p 8036, RF = 140 Ω; 8037, RF = 274 Ω 900 VOUT = 4 V Step, 10–90% VOUT = 0.5 V Step, 10–90% VOUT = 4 V Step, 10–90% TMIN –TMAX Common-Mode Rejection Ratio Open-Loop Gain H TMIN –TMAX TMIN –TMAX 270 190 MHz V/µs ns ns 10 16 –52 –59 –61 –65 –52 –72 –70 –80 41 14 4.5 2.1 60 0.02 0.02 1.1 0.09 0.04 ± 10 ± 20 ± 60 ± 80 5 –45 –65 –63 –73 0.04 0.04 ± 3.3 ± 3.9 ±3 ± 10 ± 20 100 ± 50 ± 70 ± 90 180 270 1 5 1.3 7 11 2 ± 10 3 10 15 3 5 90 55 ns ns 0.1 70 54 46 7 10 9 15 3 5 90 60 dBc dBc dBc dBc dBm dB nV√Hz pA√Hz µV rms % Degree Degree V mV mV mV µA µA MHz % ns mV mV µV/°C µA µA µA µA dB dB dB 500 1.2 ± 2.5 500 1.2 ± 2.5 kΩ pF V ± 3.2 ± 3.9 70 0.3 240 ± 3.2 ± 3.9 70 0.3 240 V mA Ω mA ± 3.0 ± 5.0 20.5 50 60 ± 3.0 ± 5.0 ± 6.0 18.5 19.5 24 56 66 V mA mA dB ± 6.0 21.5 25 NOTES 1 See Max Ratings and Theory of Operation sections of data sheet. 2 See Max Ratings. 3 Nonlinearity is defined as the voltage delta between the set input clamp voltage (VH or VL) and the voltage at which VOUT starts deviating from VIN (see Figure 73). 4 Measured at AV = 50. 5 Measured with respect to the inverting input. Specifications subject to change without notice. –2– REV. B AD8036/AD8037 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Voltage Swing × Bandwidth Product . . . . . . . . . . . 350 V-MHz |VH–VIN| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 6.3 V |VL–VIN| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 6.3 V Internal Power Dissipation2 Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . 1.3 Watts Small Outline Package (SO) . . . . . . . . . . . . . . . . . . 0.9 Watts Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 1.2 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C Operating Temperature Range (A Grade) . . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C The maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8036 and AD8037 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic DIP: θJA = 90°C/W 8-Lead SOIC: θJA = 155°C/W 8-Lead Cerdip: θJA = 110°C/W. MAXIMUM POWER DISSIPATION – Watts 2.0 METALIZATION PHOTO Dimensions shown in inches and (mm). Connect Substrate to –V S. –IN VH 2 8 +VS 7 8-LEAD PLASTIC DIP PACKAGE TJ = +150C 1.5 1.0 8-LEAD SOIC PACKAGE 0.5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE – C 0.046 (1.17) 6 70 80 90 Figure 2. Plot of Maximum Power Dissipation vs. Temperature OUT ORDERING GUIDE 3 +IN 4 –VS 5 8036 VL Model AD8036 0.050 (1.27) –IN VH +VS 2 8 7 0.046 (1.17) 6 3 +IN 4 –VS 5 VL 0.050 (1.27) OUT Temperature Range Package Option AD8036AN AD8036AR AD8036AR-REEL AD8036AR-REEL7 AD8036ACHIPS AD8036-EB 5962-9559701MPA –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Plastic DIP SOIC 13" Tape and Reel 7" Tape and Reel Die Evaluation Board –55°C to +125°C Cerdip N-8 SO-8 SO-8 SO-8 AD8037AN AD8037AR AD8037AR-REEL AD8037AR-REEL7 AD8037ACHIPS AD8037-EB –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C N-8 SO-8 SO-8 SO-8 Plastic DIP SOIC 13" Tape and Reel 7" Tape and Reel Die Evaluation Board Q-8 8037 AD8037 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8036/AD8037 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B Package Description –3– WARNING! ESD SENSITIVE DEVICE AD8036/AD8037 AD8036–Typical Characteristics RF RF 10F +VS PULSE GENERATOR 10F +VH PULSE GENERATOR 0.1F T R /T F = 350ps +VS 0.1F 0.1F T R /T F = 350ps 130 AD8036 VIN VOUT 0.1F 49.9 AD8036 130 VIN RL = 100 49.9 10F VL TPC 1. Noninverting Configuration, G = +1 RL = 100 10F 0.1F –VS VOUT 0.1F –VS TPC 4. Noninverting Clamp Configuration, G = +1 TPC 5. Clamped Large Signal Transient Response (2× Overdrive); VO = 2 V p-p, G = +1, RF = 140 Ω, VH = +1 V, VL = –1 V TPC 2. Large Signal Transient Response; VO = 4 V p-p, G = +1, RF = 140 Ω TPC 6. Clamped Small Signal Transient Response (2 × Overdrive); VO = 400 mV p-p, G = +1, RF = 140 Ω, VH = +0.2 V, VL = –0.2 V TPC 3. Small Signal Transient Response; VO = 400 mV p-p, G = +1, RF = 140 Ω –4– REV. B AD8036/AD8037 AD8037–Typical Characteristics RF RF PULSE GENERATOR 10F +VS T R /T F = 350ps PULSE GENERATOR T R /T F = 350ps 0.1F AD8037 VIN VOUT 0.1F 49.9 0.1F 0.1F AD8037 100 VIN RL = 100 VOUT 0.1F 49.9 10F RL = 100 10F 0.1F VL –VS –VS TPC 10. Noninverting Clamp Configuration, G = +2 TPC 7. Noninverting Configuration, G = +2 TPC 11. Clamped Large Signal Transient Response (2 × Overdrive); VO = 2 V p-p, G = +2, RF = RIN = 274 Ω, VH = +0.5 V, VL = –0.5 V TPC 8. Large Signal Transient Response; VO = 4 V p-p, G = +2, RF = RIN = 274 Ω TPC 12. Clamped Small Signal Transient Response (2 × Overdrive); VO = 400 mV p-p, G = +2, RF = RIN = 274 Ω, VH = +0.1 V, VL = –0.1 V TPC 9. Small Signal Transient Response; VO = 400 mV p-p, G = +2, RF = RIN = 274 Ω REV. B +VS RIN RIN 100 10F +VH –5– AD8036/AD8037 AD8036–Typical Characteristics 2 400 140 GAIN – dB –2 VO = 300mV p-p VS = 5V RL = 100 –3dB BANDWIDTH – MHz 0 –1 RF 200 1 102 49.9 –3 –4 –5 VS = 5V RL = 100 GAIN = +1 350 130 AD8036 RL 49.9 N PACKAGE 300 R PACKAGE 250 –6 200 –7 –8 1M 10M 100M FREQUENCY – Hz 20 1G TPC 13. AD8036 Small Signal Frequency Response, G = +1 0 VO = 300mV p-p VS = 5V RL = 100 –1 140 130 –0.4 –2 –5 –6 –0.7 –7 10M 100M FREQUENCY – Hz TPC 14. AD8036 0.1 dB Flatness, N Package (for R Package Add 20 Ω to RF) 100 2 80 80 1 70 60 20 40 0 GAIN –1 GAIN – dB 50 –2 –20 20 –40 10 –60 0 –80 –6 –100 –7 100k 1M 10M FREQUENCY – Hz 100M VS = 5V VO = 300mV p-p RL = 100 140 –3 30 –10 1G 0 PHASE MARGIN – Degrees 40 10M 100M FREQUENCY – Hz TPC 17. AD8036 Large Signal Frequency Response, G = +1 90 PHASE 50 RF = 50 TO 250 BY 50 –8 1M 1G 60 VS = 5V VO = 2.5V p-p RL = 100 –4 –0.6 –0.8 1M 250 –3 –0.5 OPEN -LOOP GAIN – dB 240 0 OUTPUT – dB GAIN – dB 1 150 –0.1 –20 10k 220 2 158 0.1 –0.3 60 80 100 120 140 160 180 200 VALUE OF FEEDBACK RESISTOR (RF) – TPC 16. AD8036 Small Signal –3 dB Bandwidth vs. RF 0.2 –0.2 40 –4 –120 1G –8 100k TPC 15. AD8036 Open-Loop Gain and Phase Margin vs. Frequency, RL = 100 Ω (VO) AD8036 –5 1V 100 VH VL (VIN) 1M 10M FREQUENCY – Hz 100M 1G TPC 18. AD8036 Clamp Input Bandwidth, VH, VL –6– REV. B AD8036/AD8037 0.06 DIFF GAIN – % –50 VO = 2V p-p VS = 5V RL = 500 G = +1 –70 2ND HARMONIC –90 3RD HARMONIC –110 –130 10k 0.04 0.02 0.00 –0.02 –0.04 –0.06 DIFF PHASE – Degrees HARMONIC DISTORTION – dBc –30 100k 1M FREQUENCY – Hz 10M 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.04 0.02 0.00 –0.02 –0.04 100M TPC 19. AD8036 Harmonic Distortion vs. Frequency, RL = 500 Ω 1st TPC 22. AD8036 Differential Gain and Phase Error, G = +1, RL = 150 Ω, F = 3.58 MHz –50 0.05 VO = 2V p-p VS = 5V RL = 100 G = +1 0.04 0.03 0.02 2ND HARMONIC –70 ERROR – % HARMONIC DISTORTION – dBc –30 –90 0.01 0 –0.01 3RD HARMONIC –0.02 –110 –0.03 –0.04 –130 10k –0.05 100k 1M FREQUENCY – Hz 10M 100M 0 TPC 20. AD8036 Harmonic Distortion vs. Frequency, RL = 100 Ω 5 10 15 20 25 30 SETTLING TIME – ns 35 40 45 TPC 23. AD8036 Short-Term Settling Time to 0.01%, 2 V Step, G = +1, RL = 100 Ω 60 0.4 0.3 0.2 0.1 ERROR – % INTERCEPT – +dBm 50 40 0 –0.1 –0.2 –0.3 30 –0.4 –0.5 20 10 –0.6 20 40 FREQUENCY – MHz 60 80 100 0 TPC 21. AD8036 Third Order Intercept vs. Frequency REV. B 2 4 6 8 10 12 14 SETTLING TIME - s 16 18 TPC 24. AD8036 Long-Term Settling Time, 2 V Step, G = +1, RL = 100 Ω –7– AD8036/AD8037 AD8037–Typical Characteristics 8 475 7 374 VS = 5V RL = 100 GAIN = +2 350 GAIN – dB 5 VO = 300mV p-p VS = 5V RL = 100 4 –3dB BANDWIDTH – MHz 6 274 174 3 2 1 RIN 100 RF AD8037 RL 300 49.9 250 R PACKAGE N PACKAGE 200 0 –1 150 –2 1M 10M 100M FREQUENCY – Hz 1G 100 TPC 25. AD8037 Small Signal Frequency Response, G = +2 274 VO = 3.00mV p-p VS = 5V RL = 100 6 5 249 224 4 GAIN – dB GAIN – dB 550 RF = 475 7 –0.3 –0.4 1 0 –0.7 –1 RF = 75 TO 475 BY 100 –2 1M 1G TPC 26. AD8037 0.1 dB Flatness, N Package (for R Package Add 20 Ω to RF) RF = 75 2 –0.6 10M 100M FREQUENCY – Hz VO = 3.5 V p-p VS = 5V RL = 100 3 –0.5 –0.8 1M 10M 100M FREQUENCY – Hz 1G TPC 29. AD8037 Large Signal Frequency Response, G = +2 8 65 60 55 50 7 100 PHASE 6 50 35 0 30 25 20 –50 GAIN 15 10 –100 5 0 –150 –5 –10 –200 100k 1M 10M FREQUENCY – Hz 100M 5 GAIN – dB 45 40 PHASE MARGIN – Degrees OPEN -LOOP GAIN – dB 500 8 0 –15 10k 250 300 350 400 450 VALUE OF RF,RIN – 301 0.1 –0.2 200 TPC 28. AD8037 Small Signal –3 dB Bandwidth vs. RF, RIN 0.2 –0.1 150 4 VS = 5V VO = 300mV p-p RL = 100 274 3 2 274 0 1V –2 100k 100 VH VL (VIN) –1 –250 1G (VO) AD8037 1 1M 10M FREQUENCY – Hz 100M 1G TPC 30. AD8037 Clamp Input Bandwidth, VH, VL TPC 27. AD8037 Open-Loop Gain and Phase Margin vs. Frequency, RL = 100 Ω –8– REV. B AD8036/AD8037 0.03 DIFF GAIN – % –50 VO = 2V p-p VS = 5V RL = 500 G = +2 –70 0.02 0.01 0.00 –0.01 –0.02 –0.03 2ND HARMONIC 1st DIFF PHASE – Degrees HARMONIC DISTORTION – dBc –30 –90 3RD HARMONIC –110 –130 10k 100k 1M FREQUENCY – Hz 5th 6th 7th 8th 9th 10th 11th 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.01 0.00 –0.01 –0.02 –0.03 TPC 34. AD8037 Differential Gain and Phase Error G = +2, RL = 150 Ω, F = 3.58 MHz –30 –0.05 –0.04 VO = 2V p-p VS = 5V RL = 100 G = +2 –0.03 2ND HARMONIC –0.02 ERROR – % HARMONIC DISTORTION – dBc 4th 0.02 1st TPC 31. AD8037 Harmonic Distortion vs. Frequency, RL = 500 Ω –50 3rd 0.03 100M 10M 2nd –70 –90 3RD HARMONIC –0.01 0 –0.01 –0.02 –0.03 –110 –0.04 –0.05 –130 10k 100k 1M FREQUENCY – Hz 0 100M 10M 5 10 15 20 25 30 SETTLING TIME – ns 35 40 45 TPC 35. AD8037 Short-Term Settling Time to 0.01%, 2 V Step, G = +2, RL = 100 Ω TPC 32. AD8037 Harmonic Distortion vs. Frequency, RL = 100 Ω 60 0.4 0.3 0.2 0.1 ERROR – % INTERCEPT – +dBm 50 40 0 –0.1 –0.2 –0.3 30 –0.4 –0.5 –0.6 20 10 20 40 FREQUENCY – MHz 60 80 0 100 4 6 8 10 12 14 SETTLING TIME – s 16 18 TPC 36. AD8037 Long-Term Settling Time 2 V Step, RL = 100 Ω TPC 33. AD8037 Third Order Intercept vs. Frequency REV. B 2 –9– AD8036/AD8037–Typical Characteristics 17 28 15 INPUT NOISE VOLTAGE – nV/ Hz INPUT NOISE VOLTAGE – nV/ Hz 32 VS = 5V 24 20 16 12 VS = 5V 13 11 9 7 8 5 4 10 100 1k FREQUENCY – Hz 10k 3 10 100k TPC 37. AD8036 Noise vs. Frequency –PSRR 65 60 55 50 45 +PSRR 40 35 30 25 20 15 10 5 0 10k 100k 1M 10M FREQUENCY – Hz 100M 1G 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10k TPC 38. AD8036 PSRR vs. Frequency 10k 100k –PSRR +PSRR 100k 1M 10M FREQUENCY – Hz 100M 1G TPC 41. AD8037 PSRR vs. Frequency 100 100 VS = 5V VCM = 1V RL = 100 90 VS = 5V VCM = 1V RL = 100 90 80 CMRR – dB 80 CMRR – dB 1k FREQUENCY – Hz TPC 40. AD8037 Noise vs. Frequency PSRR – dB PSRR – dB 80 75 70 100 70 60 70 60 50 50 40 40 30 30 20 100k 1M 10M FREQUENCY – Hz 100M 20 100k 1G TPC 39. AD8036 CMRR vs. Frequency 1M 10M FREQUENCY – Hz 100M 1G TPC 42. AD8037 CMRR vs. Frequency –10– REV. B AD8036/AD8037 1400 1k 1300 VS = 5V G = +1 1200 OPEN -LOOP GAIN – V/ V 100 ROUT – 10 1 1100 AD8037 1000 +AOL 900 –AOL 800 700 600 0.1 500 +AOL AD8036 –AOL 0.01 0.1M 1.0M 10M FREQUENCY – Hz 100M 400 –60 300M –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE – C TPC 43. AD8036 Output Resistance vs. Frequency TPC 46. Open-Loop Gain vs. Temperature 1k 74 –PSRR 72 VS = 5V G = +2 100 AD8037 70 +PSRR PSRR – dB ROUT – 10 1 68 AD8037 66 64 –PSRR AD8036 +PSRR 0.1 62 AD8036 0.01 0.1M 1.0M 10M FREQUENCY – Hz 100M 60 –60 300M TPC 44. AD8037 Output Resistance vs. Frequency 120 140 VCM = 2V RL=150 +VOUT 95 4.0 94 –VOUT 3.9 CMRR – dB OUTPUT SWING – Volts 0 20 40 60 80 100 JUNCTION TEMPERATURE – C 96 4.1 3.8 3.7 3.6 3.5 –VOUT –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – C 93 92 91 90 +VOUT 120 RL= 50 89 140 88 15 TPC 45. AD8036/AD8037 Output Swing vs. Temperature REV. B –20 TPC 47. PSRR vs. Temperature 4.2 3.4 –60 –40 25 35 45 55 65 75 JUNCTION TEMPERATURE – C 85 95 TPC 48. AD8036/AD8037 CMRR vs. Temperature –11– AD8036/AD8037–Typical Characteristics 270 24 SHORT CIRCUIT CURRENT – mA 23 SUPPLY CURRENT – mA AD8036, VS = 6V 22 AD8037, VS = 6V 21 AD8036, VS = 5V 20 AD8037, VS = 5V 19 18 260 AD8036 250 AD8037 AD8037 SINK 240 AD8036 230 SOURCE 220 210 17 –60 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – C 120 200 –60 140 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – C 120 140 TPC 52. Short Circuit Current vs. Temperature TPC 49. Supply Current vs. Temperature –2.50 4.5 VS = 6V –IB 4.0 INPUT BIAS CURRENT – A INPUT OFFSET VOLTAGE – mV –2.25 –2.00 VS = 6V AD8037 –1.75 –1.50 VS = 5V VS = 5V –1.25 AD8036 –1.00 +IB 3.5 –IB 3.0 +IB 2.5 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – C 120 1.5 –60 140 TPC 50. Input Offset Voltage vs. Temperature 44 0 20 40 60 80 100 JUNCTION TEMPERATURE – C 120 140 3 WAFER LOTS COUNT = 853 40 36 32 FREQ. DIST 32 24 COUNT 28 COUNT –20 48 3 WAFER LOTS COUNT = 632 36 FREQ. DIST 20 16 28 24 20 16 12 12 8 8 4 4 0 –6 –40 TPC 53. Input Bias Current vs. Temperature 44 40 AD8037 2.0 –0.75 –0.50 –60 AD8036 –5 –4 –3 –2 –1 0 1 INPUT OFFSET VOLTAGE – mV 2 3 0 –4.5 4 TPC 51. AD8036 Input Offset Voltage Distribution –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 INPUT OFFSET VOLTAGE – mV 0 0.5 TPC 54. AD8037 Input Offset Voltage Distribution –12– REV. B Clamp Characteristics–AD8036/AD8037 20 –80 VCL = –3V 10 VCL = –2V VCL = –1V –75 AD8036, ACL = +1 AD8037, ACL = +2 HARMONIC DISTORTION – dBc INPUT ERROR VOLTAGE – mV 15 5 0 AD8036 –5 AD8037 –10 VCH = +1V –15 VCH = +2V VCH = +3V AD8037 3RD HARMONIC –65 –60 AD8037 2ND HARMONIC –55 –2 –1 0 1 OUTPUT VOLTAGE – Volts 2 AD8036 2ND HARMONIC –45 AD8036 AD8037 –40 VH VL G –30 0.6 3 TPC 55. Input Error Voltage vs. Clamped Output Voltage +1V –1V +1V +0.5V –0.5V +2V 0.65 0.7 0.75 0.8 0.85 0.9 0.95 ABSOLUTE VALUE OF OUTPUT VOLTAGE – Volts 1.0 TPC 58. Harmonic Distortion as Output Approaches Clamp Voltage; VO = 2 V p-p, RL = 100 , f = 20 MHz 20 80 CLAMP INPUT BIAS CURRENT – A VH = + 1V VL = – 1V 15 10 5 0 –5 –10 –15 60 POSITIVE IBH, IBL DENOTES CURRENT FLOW INTO CLAMP INPUTS VH, VL 40 20 IBL 0 IBH –20 –40 –60 –20 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 INPUT VOLTAGE AV – Volts 0.6 0.8 –80 –5 1.0 TPC 56. AD8036/AD8037 Nonlinearity Near Clamp Voltage –4 –3 –2 –1 0 1 2 3 INPUT CLAMP VOLTAGE (VH ,VL) – Volts 4 5 TPC 59. AD8036/AD8037 Clamp Input Bias Current vs. Input Clamp Voltage +2V +2V +1V +1V 0V 0V REF REF TPC 60. AD8037 Clamp Overdrive (2 ×) Recovery TPC 57. AD8036 Clamp Overdrive (2 ×) Recovery REV. B AD8036 3RD HARMONIC –50 –35 –20 –3 NONLINEARITY – mV –70 –13– 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 ERROR – % ERROR – % AD8036/AD8037–Clamp Characteristics 0 –0.1 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 0 10 20 30 40 50 60 SETTLING TIME – ns 70 80 90 0 TPC 61. AD8036 Clamp Settling (0.1%), VH = +1 V, VL = –1 V, 2 × Overdrive 10 20 30 40 50 60 SETTLING TIME – ns 70 80 90 TPC 64. AD8037 Clamp Settling (0.1%), VH = +0.5 V, VL = –0.5 V, 2 × Overdrive 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 ERROR – % ERROR – % 0 –0.1 –0.2 –0.5 0.1 0 –0.1 0.1 0 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 5 10 15 20 25 SETTLING TIME – ns 30 35 0 40 TPC 62. AD8036 Clamp Recovery Settling Time (High), from +2 × Overdrive to 0 V 5 10 15 20 25 SETTLING TIME – ns 30 35 40 TPC 65. AD8037 Clamp Recovery Settling Time (High), from +2 × Overdrive to 0 V 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 ERROR – % ERROR – % 0.1 0.1 0 –0.1 0.1 0 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 5 10 15 20 25 SETTLING TIME – ns 30 35 40 0 TPC 63. AD8036 Clamp Recovery Settling Time (Low), from –2 × Overdrive to 0 V 5 10 15 20 25 SETTLING TIME – ns 30 35 40 TPC 66. AD8037 Clamp Recovery Settling Time (Low), from –2 × Overdrive to 0 V –14– REV. B AD8036/AD8037 This estimation loses accuracy for gains of +2/–1 or lower due to the amplifier’s damping factor. For these “low gain” cases, the bandwidth will actually extend beyond the calculated value (see Closed-Loop BW plots, TPCs 13 and 25). THEORY OF OPERATION General The AD8036 and AD8037 are wide bandwidth, voltage feedback clamp amplifiers. Since their open-loop frequency response follows the conventional 6 dB/octave roll-off, their gain bandwidth product is basically constant. Increasing their closed-loop gain results in a corresponding decrease in small signal bandwidth. This can be observed by noting the bandwidth specification, between the AD8036 (gain of 1) and AD8037 (gain of 2). The AD8036/ AD8037 typically maintain 65 degrees of phase margin. This high margin minimizes the effects of signal and noise peaking. Pulse Response While the AD8036 and AD8037 can be used in either an inverting or noninverting configuration, the clamp function will only work in the noninverting mode. As such, this section shows connections only in the noninverting configuration. Applications that require an inverting configuration will be discussed in the Applications section. In applications that do not require clamping, Pins 5 and 8 (respectively VL and VH) may be left floating. See Input Clamp Amp Operation and Applications sections otherwise. Feedback Resistor Choice The value of the feedback resistor is critical for optimum performance on the AD8036 (gain +1) and less critical as the gain increases. Therefore, this section is specifically targeted at the AD8036. Unlike a traditional voltage feedback amplifier, where the slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the AD8036 and AD8037 provide “on demand” current that increases proportionally to the input “step” signal amplitude. This results in slew rates (1200 V/µs) comparable to wideband current feedback designs. This, combined with relatively low input noise current (2.1 pA/√Hz), gives the AD8036 and AD8037 the best attributes of both voltage and current feedback amplifiers. Large Signal Performance The outstanding large signal operation of the AD8036 and AD8037 is due to a unique, proprietary design architecture. In order to maintain this level of performance, the maximum 350 V-MHz product must be observed, (e.g., @ 100 MHz, VO ≤ 3.5 V p-p). Power Supply and Input Clamp Bypassing At minimum stable gain (+1), the AD8036 provides optimum dynamic performance with RF = 140 Ω. This resistor acts only as a parasitic suppressor against damped RF oscillations that can occur due to lead (input, feedback) inductance and parasitic capacitance. This value of RF provides the best combination of wide bandwidth, low parasitic peaking, and fast settling time. Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier’s response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 µF) will be required to provide the best settling time and lowest distortion. A parallel combination of at least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended. Some brands of electrolytic capacitors will require a small series damping resistor ≈4.7 Ω for optimum results. In fact, for the same reasons, a 100–130 Ω resistor should be placed in series with the positive input for other AD8036 noninverting configurations. The correct connection is shown in Figure 3. When the AD8036 and AD8037 are used in clamping mode, and a dc voltage is connected to clamp inputs VH and VL, a 0.1 µF bypassing capacitor is required between each input pin and ground in order to maintain stability. Driving Capacitive Loads +VS 10F R G = 1+ F RG VH 0.1F 100 - 130 VIN AD8036/ AD8037 RTERM VOUT 0.1F 10F VL RF The AD8036 and AD8037 were designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, the best frequency response is obtained by the addition of a small series resistance as shown in Figure 4. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL. For capacitive loads of 6 pF or less, no RSERIES is necessary. –VS RF RG RIN Figure 3. Noninverting Operation RIN For general voltage gain applications, the amplifier bandwidth can be closely estimated as: f 3 dB ≅ REV. B ωO R 2π 1+ F RG AD8036/ AD8037 RSERIES RL 1k Figure 4. Driving Capacitive Loads –15– CL AD8036/AD8037 Operation of the AD8036 for negative input voltages and negative clamp levels on VL is similar, with comparator CL controlling S1. Since the comparators see the voltage on the +VIN pin as their common reference level, then the voltage VH and VL are defined as “High” or “Low” with respect to +VIN. For example, if VIN is set to zero volts, VH is open, and VL is +1 V, comparator CL will switch S1 to “C,” so the AD8036 will buffer the voltage on VL and ignore +VIN. 40 R SERIES – 30 The performance of the AD8036 and AD8037 closely matches the ideal just described. The comparator’s threshold extends from 60 mV inside the clamp window defined by the voltages on VL and VH to 60 mV beyond the window’s edge. Switch S1 is implemented with current steering, so that A1’s +input makes a continuous transition from say, VIN to VH as the input voltage traverses the comparator’s input threshold from 0.9 V to 1.0 V for VH = 1.0 V. 20 10 0 5 10 15 20 25 CL– pF Figure 5. Recommended RSERIES vs. Capacitive Load The practical effect of these nonidealities is to soften the transition from amplification to clamping modes, without compromising the absolute clamp limit set by the CLAMPIN circuit. Figure 7 is a graph of VOUT vs. VIN for the AD8036 and a typical output clamp amplifier. Both amplifiers are set for G = +1 and VH = 1 V. INPUT CLAMPING AMPLIFIER OPERATION The key to the AD8036 and AD8037’s fast, accurate clamp and amplifier performance is their unique patent pending CLAMPIN input clamp architecture. This new design reduces clamp errors by more than 10× over previous output clamp based circuits, as well as substantially increasing the bandwidth, precision and versatility of the clamp inputs. Figure 6 is an idealized block diagram of the AD8036 connected as a unity gain voltage follower. The primary signal path comprises A1 (a 1200 V/µs, 240 MHz high voltage gain, differential to single-ended amplifier) and A2 (a G = +1 high current gain output buffer). The AD8037 differs from the AD8036 only in that A1 is optimized for closed-loop gains of two or greater. The CLAMPIN section is comprised of comparators CH and CL, which drive switch S1 through a decoder. The unity-gain buffers in series with +VIN, VH, and VL inputs isolate the input pins from the comparators and S1 without reducing bandwidth or precision. The worst case error between VOUT (ideally clamped) and VOUT (actual) is typically 18 mV times the amplifier closed-loop gain. This occurs when VIN equals VH (or VL). As VIN goes above and/or below this limit, VOUT will settle to within 5 mV of the ideal value. In contrast, the output clamp amplifier’s transfer curve typically will show some compression starting at an input of 0.8 V, and can have an output voltage as far as 200 mV over the clamp limit. In addition, since the output clamp in effect causes the amplifier to operate open loop in clamp mode, the amplifier’s output impedance will increase, potentially causing additional errors. The AD8036’s and AD8037’s CLAMPIN input clamp architecture works only for noninverting or follower applications and, since it operates on the input, the clamp voltage levels VH and VL, and input error limits will be multiplied by the amplifier’s The two comparators have about the same bandwidth as A1 (240 MHz), so they can keep up with signals within the useful bandwidth of the AD8036. To illustrate the operation of the CLAMPIN circuit, consider the case where VH is referenced to 1 V, VL is open, and the AD8036 is set for a gain of +1, by connecting its output back to its inverting input through the recommended 140 Ω feedback resistor. Note that the main signal path always operates closed loop, since the CLAMPIN circuit only affects A1’s noninverting input. RF 140 –VIN +VIN A1 A +1 A2 +1 VOUT S1 If a 0 V to 2 V voltage ramp is applied to the AD8036’s +VIN for the connection just described, VOUT should track +VIN perfectly up to 1 V, then should limit at exactly 1 V as +VIN continues to 2 V. VH +1 VL +1 B C S1 CH VIN > VH A B C 0 1 0 VL ≤ VIN ≤ VH 1 0 0 In practice, the AD8036 comes close to this ideal behavior. As the +VIN input voltage ramps from zero to 1 V, the output of the high limit comparator CH starts in the off state, as does the output of CL. When +VIN just exceeds VIN (ideally, by say 1 µV, practically by about 18 mV), CH changes state, switching S1 from “A” to “B” reference level. Since the + input of A1 is now connected to VH, further increases in +VIN have no effect on the AD8036’s output voltage. In short, the AD8036 is now operating as a unity-gain buffer for the VH input, as any variation in VH, for VH > 1 V, will be faithfully reproduced at VOUT. –16– VIN < VL 0 0 1 CL Figure 6. AD8036/AD8037 Clamp Amp System REV. B AD8036/AD8037 closed-loop gain at the output. For instance, to set an output limit of ± 1 V for an AD8037 operating at a gain of 3.0, VH and VL would need to be set to +0.333 V and –0.333 V, respectively. The only restriction on using the AD8036’s and AD8037’s +VIN, VL, VH pins as inputs is that the maximum voltage difference between +VIN and VH or VL should not exceed 6.3 V, and all three voltages be within the supply voltage range. For example, if VL is set at –3 V, then VIN should not exceed +3.3 V. Clamping with Gain Figure 9 shows an AD8037 configured for a noninverting gain of two. The AD8037 is used in this circuit since it is compensated for gains of two or greater and provides greater bandwidth. In this case, the high clamping level at the output will occur at VH 0.1F +5V 0.1F 1.6 10F 130 VIN VH AD8036 OUTPUT VOLTAGE – VOUT 1.4 VOUT VL 0.1F 1.2 10F 0.1F CLAMP ERROR – 25mV AD8036 –5V CLAMP ERROR – >200mV OUTPUT CLAMP RF 140 VL 1.0 AD8036 0.6 0.6 Figure 8. Unity Gain Noninverting Clamp OUTPUT CLAMP AMP 0.8 0.8 1.0 1.2 1.4 1.6 INPUT VOLTAGE – +VIN 1.8 2 × VH and the low clamping level at the output will be 2 × VL. The equations governing the output clamp levels in circuits configured for noninverting gain are: 2.0 VCH = G × VH VCL = G × VL Figure 7. Output Clamp Error vs. Input Clamp Error where: AD8036/AD8037 APPLICATIONS The AD8036 and AD8037 use a unique input clamping circuit to perform the clamping function. As a result, they provide the clamping function better than traditional output clamping devices and provide additional flexibility to perform other unique applications. VCH is the high output clamping level VCL is the low output clamping level G is the gain of the amplifier configuration VH is the high input clamping level (Pin 8) VL is the low input clamping level (Pin 5) *Amplifier offset is assumed to be zero. VH There are, however, some restrictions on circuit configurations; and some calculations need to be performed in order to figure the clamping level, as a result of clamping being performed at the input stage. 0.1F +5V 0.1F 10F 100 VIN The major restriction on the clamping feature of the AD8036/ AD8037 is that clamping occurs only when using the amplifiers in the noninverting mode. To clamp in an inverting circuit, an additional inverting gain stage is required. Another restriction is that VH be greater than VL, and that each be within the output voltage range of the amplifier (± 3.9 V). VH can go below ground and VL can go above ground as long as VH is kept higher than VL. VH 49.9 AD8037 VOUT VL 0.1F 10F 0.1F –5V RG 274 VL RF 274 Unity Gain Clamping The simplest circuit for calculating the clamp levels is a unity gain follower as shown in Figure 8. In this case, the AD8036 should be used since it is compensated for noninverting unity gain. Figure 9. Gain of Two Noninverting Clamp This circuit will clamp at an upper voltage set by VH (the voltage applied to Pin 8) and a lower voltage set by VL (the voltage applied to Pin 5). REV. B –17– AD8036/AD8037 +5V 806 +5V 0.1F 100 +5V 0.1F –0.5V to +0.5V 10µF 0.1F AD780 2.5V 49.9 –2V to 0V AD8037 0.1F 100 R1 499 49.9 VIN = –2V TO 0V CLAMPING RANGE –2.1V to +0.1V VL 0.1F 806 1N5712 AD9002 VH R3 750 10F 100 VIN 10F SUBSTRATE DIODE –5V 0.1F 0.1F R2 301 –5V –5.2V Figure 10. Gain of Two, Noninverting with Offset AD8037 Driving an AD9002—8-Bit, 125 MSPS A/D Converter it goes no more than 100 mV outside of this range in either direction. Thus, the high clamping level should be set at +0.1 V and the low clamping level should be set at –2.1 V as seen at the input of the AD9002 (output of AD8037). Clamping with an Offset Some op amp circuits are required to operate with an offset voltage. These are generally configured in the inverting mode where the offset voltage can be summed in as one of the inputs. Since AD8036/AD8037 clamping does not function in the inverting mode, it is not possible to clamp with this configuration. Because the clamping is done at the input stage of the AD8037, the clamping level as seen at the output is affected by not only the gain of the circuit as previously described, but also by the offset. Thus, in order to obtain the desired clamp levels, VH must be biased at +0.55 V while VL must be biased at –0.55 V. Figure 10 shows a noninverting configuration of an AD8037 that provides clamping and also has an offset. The circuit shows the AD8037 as a driver for an AD9002, an 8-bit, 125 MSPS A/D converter and illustrates some of the considerations for using an AD8037 with offset and clamping. The clamping levels as seen at the output can be calculated by the following: The analog input range of the AD9002 is from ground to –2 V. The input should not go more than 0.5 V outside this range in order to prevent disruptions to the internal workings of the A/D and to avoid drawing excess current. These requirements make the AD8037 a prime candidate for signal conditioning. VCH = VOFF + G × VH VCL = VOFF + G × VL Where VOFF is the offset voltage that appears at the output. The resistors used to generate the voltages for VH and VL should be kept to a minimum in order to reduce errors due to clamp bias current. This current is dependent on VH and VL (see TPC 59) and will create a voltage drop across whatever resistance is in series with each clamp input. This extra error voltage is multiplied by the closed-loop gain of the amplifier and can be substantial, especially in high closed-loop gain configurations. A 0.1 µF bypass capacitor should be placed between input clamp pins VH and VL and ground to ensure stable operation. When an offset is added to a noninverting op amp circuit, it is fed in through a resistor to the inverting input. The result is that the op amp must now operate at a closed-loop gain greater than unity. For this circuit a gain of two was chosen which allows the use of the AD8037. The feedback resistor, R2, is set at 301 Ω for optimum performance of the AD8037 at a gain of two. There is an interaction between the offset and the gain, so some calculations must be performed to arrive at the proper values for R1 and R3. For a gain of two the parallel combination of resistors R1 and R3 must be equal to the feedback resistor R2. Thus The 1N5712 Schottky diode is used for protection from forward biasing the substrate diode in the AD9002 during power-up transients. R1 × R3/R1 + R3 = R2 = 301 Ω Programmable Pulse Generator The reference used to provide the offset is the AD780 whose output is 2.5 V. This must be divided down to provide the 1 V offset desired. Thus The AD8036/AD8037’s clamp output can be set accurately and has a well controlled flat level. This along with wide bandwidth and high slew rate make them very well suited for programmable level pulse generators. 2.5 V × R1/(R1 + R3) = 1 V When the two equations are solved simultaneously we get R1 = 499 Ω and R3 = 750 Ω (using closest 1% resistor values in all cases). This positive 1 V offset at the input translates to a –1 V offset at the output. The usable input signal swing of the AD9002 is 2 V p-p. This is centered about the –1 V offset making the usable signal range from 0 V to –2 V. It is desirable to clamp the input signal so that Figure 11 is a schematic for a pulse generator that can directly accept TTL generated timing signals for its input and generate pulses at the output up to 24 V p-p with 2500 V/µs slew rate. The output levels can be programmed to anywhere in the range –12 V to +12 V. –18– REV. B AD8036/AD8037 VH 0.1F +5V +15V 0.1F 200 10F 100 TTLIN VH 1.3k 0.1F 100 AD8037 VL 10F VL 10 PULSE OUT AD811 –15V 0.1F VH 10 10F 0.1F 0.1F –5V VL –15V 274 10F 604 150 274 Figure 11. Programmable Pulse Generator The circuit uses an AD8037 operating at a gain of two with an AD811 to boost the output to the ± 12 V range. The AD811 was chosen for its ability to operate with ± 15 V supplies and its high slew rate. The circuit is configured as an inverting amplifier with a gain of one. The input drives the inverting amplifier and also directly drives VL, the lower level clamping input. The high level clamping input, VH, is left floating and plays no role in this circuit. R1 and R2 act as a level shifter to make the TTL signal levels be approximately symmetrical above and below ground. This ensures that both the high and low logic levels will be clamped by the AD8037. For well controlled signal levels in the output pulse, the high and low output levels should result from the clamping action of the AD8037 and not be controlled by either the high or low logic levels passing through a linear amplifier. For good rise and fall times at the output pulse, a logic family with high speed edges should be used. When the input is negative, the amplifier acts as a regular unitygain inverting amplifier and outputs a positive signal at the same amplitude as the input with opposite polarity. VL is driven negative by the input, so it performs no clamping action, because the positive output signal is always higher than the negative level driving VL. The high logic levels are clamped at two times the voltage at VH, while the low logic levels are clamped at two times the voltage at VL. The output of the AD8037 is amplified by the AD811 operating at a gain of 5. The overall gain of 10 will cause the high output level to be 10 times the voltage at VH, and the low output level to be 10 times the voltage at VL. High Speed, Full-Wave Rectifier The clamping inputs are additional inputs to the input stage of the op amp. As such they have an input bandwidth comparable to the amplifier inputs and lend themselves to some unique functions when they are driven dynamically. When the input is positive, the output result is the sum of two separate effects. First, the inverting amplifier multiplies the input by –1 because of its unity-gain inverting configuration. This effectively produces an offset as explained above, but with a dynamic level that is equal to –1 times the input. Second, although the positive input is grounded (through 100 Ω), the output is clamped at two times the voltage applied to VL (a positive, dynamic voltage in this case). The factor of two is because the noise gain of the amplifier is two. The sum of these two actions results in an output that is equal to unity times the input signal for positive input signals, see Figure 13. For a input/output scope photo with an input signal of 20 MHz and amplitude ± 1 V, see Figure 14. Figure 12 is a schematic for a full-wave rectifier, sometimes called an absolute value generator. It works well up to 20 MHz and can operate at significantly higher frequencies with some degradation in performance. The distortion performance is significantly better than diode based full-wave rectifiers, especially at high frequencies. INPUT LOWER CLAMPING LEVEL WITH NO NEG INPUT +5V 0.1F FULL WAVE RECTIFIED OUTPUT 10F 100 VH AD8037 VOUT = VIN VL 0.1F RG 274 RF 274 LOWER CLAMPING LEVEL –1 INPUT 10F OUTPUT –5V VIN Figure 13. Figure 12. Full-Wave Rectifier REV. B –19– AD8036/AD8037 The modulation signal is applied to both the input of a unity gain inverting amplifier and to VL, the lower clamping input. VH is biased at 0.5 V dc. To understand the circuit operation, it is helpful to first consider a simpler circuit. If both VL and VH were dc biased at –0.5 V and the carrier and modulation inputs driven as above, the output would be a 2 V p-p square wave at the carrier frequency riding on a waveform at the modulating frequency. The inverting input (modulation signal) is creating a varying offset to the 2 V p-p square wave at the output. Both the high and low levels clamp at twice the input levels on the clamps because the noise gain of the circuit is two. Figure 14. Full-Wave Rectifier Scope Thus for either positive or negative input signals, the output is unity times the absolute value of the input signal. The circuit can be easily configured to produce the negative absolute value of the input by applying the input to VH instead of VL. The circuit can get to within about 40 mV of ground during the time when the input crosses zero. This voltage is fixed over a wide frequency range and is a result of the switching between the conventional op amp input and the clamp input. But because there are no diodes to rapidly switch from forward to reverse bias, the performance far exceeds that of diode based full wave rectifiers. The 40 mV offset mentioned can be removed by adding an offset to the circuit. A 27.4 kΩ input resistor to the inverting input will have a gain of 0.01, while changing the gain of the circuit by only 1%. A plus or minus 4 V dc level (depending on the polarity of the rectifier) into this resistor will compensate for the offset. Full wave rectifiers are useful in many applications including AM signal detection, high frequency ac voltmeters and various arithmetic operations. Amplitude Modulator In addition to being able to be configured as an amplitude demodulator (AM detector), the AD8037 can also be configured as an amplitude modulator as shown in Figure 15. When VL is driven by the modulation signal instead of being held at a dc level, a more complicated situation results. The resulting waveform is composed of an upper envelope and a lower envelope with the carrier square wave in between. The upper and lower envelope waveforms are 180° out of phase as in a typical AM waveform. The upper envelope is produced by the upper clamp level being offset by the waveform applied to the inverting input. This offset is the opposite polarity of the input waveform because of the inverting configuration. The lower envelope is produced by the sum of two effects. First, it is offset by the waveform applied to the inverting input as in the case of the simplified circuit above. The polarity of this offset is in the same direction as the upper envelope. Second, the output is driven in the opposite direction of the offset at twice the offset voltage by the modulation signal being applied to VL. This results from the noise gain being equal to two, and since there is no inversion in this connection, it is opposite polarity from the offset. The result at the output for the lower envelope is the sum of these two effects, which produces the lower envelope of an amplitude modulated waveform. See Figure 16. VH +5V 0.1F 10F 100 CARRIER IN VH AD8037 AM OUT VL 0.1F RG 274 RF 274 10F Figure 16. AM Waveform –5V MODULATION IN Figure 15. Amplitude Modulator The positive input of the AD8037 is driven with a square wave of sufficient amplitude to produce clamping action at both the high and low levels. This is the higher frequency carrier signal. The depth of modulation can be modified in this circuit by changing the amplitude of the modulation signal. This changes the amplitude of the upper and lower envelope waveforms. The modulation depth can also be changed by changing the dc bias applied to VH. In this case the amplitudes of the upper and lower envelope waveforms stay constant, but the spacing between them changes. This alters the ratio of the envelope amplitude to the amplitude of the overall waveform. –20– REV. B AD8036/AD8037 Layout Considerations VH The specified high speed performance of the AD8036 and AD8037 requires careful attention to board layout and component selection. Proper RF design techniques and low pass parasitic component selection are mandatory. +VS 1k RF –VS 0.1F The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply and input clamp bypassing (see Figure 17). One end should be connected to the ground plane and the other within 1/8 inch of each power and clamp pin. An additional large (0.47 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel, though not necessarily so close, to supply current for fast, large signal changes at the output. +VS RG RO AD8036/ AD8037 RS VOUT IN RT –VS +VS 0.1F 1k VL –VS NONINVERTING CONFIGURATION The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about 1 inch). These should be designed with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end. Evaluation Board +VS OPTIONAL C1 0.01F C3 0.1F C5 10F C2 0.01F C4 0.1F C6 10F –VS SUPPLY BYPASSING Figure 17. Noninverting Configurations for Evaluation Boards An evaluation board for both the AD8036 and AD8037 is available that has been carefully laid out and tested to demonstrate that the specified high speed performance of the device can be realized. For ordering information, please refer to the Ordering Guide. The layout of the evaluation board can be used as shown or serve as a guide for a board layout. Table I. REV. B Component +1 +2 RF RG RO (Nominal) RS RT (Nominal) Small Signal BW (MHz) 140 Ω 274 Ω 274 Ω 49.9 Ω 100 Ω 49.9 Ω 90 49.9 Ω 130 Ω 49.9 Ω 240 AD8036A Gain +10 2 kΩ 221 Ω 49.9 Ω 100 Ω 49.9 Ω 10 –21– +100 +2 AD8037A Gain +10 +100 2 kΩ 20.5 Ω 49.9 Ω 100 Ω 49.9 Ω 1.3 274 Ω 274 Ω 49.9 Ω 100 Ω 49.9 Ω 275 2 kΩ 221 Ω 49.9 Ω 100 Ω 49.9 Ω 21 2 kΩ 20.5 Ω 49.9 Ω 100 Ω 49.9 Ω 3 AD8036/AD8037 Figure 18. Evaluation Board Silkscreen (Top) Figure 20. Board Layout (Solder Side) Figure 19. Evaluation Board Silkscreen (Bottom) Figure 21. Board Layout (Component Side) –22– REV. B AD8036/AD8037 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N Package) 8 5 0.280 (7.11) 0.240 (6.10) 1 4 0.325 (8.25) 0.300 (7.62) PIN 1 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) C01057–0–12/00 (rev. B) 0.430 (10.92) 0.348 (8.84) 0.015 (0.381) 0.008 (0.204) 0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE 8-Lead Plastic SOIC (SO Package) 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) 8 5 1 4 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0196 (0.50) 45 0.0099 (0.25) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 8 0.0500 (1.27) 0.0098 (0.25) 0 0.0160 (0.41) 0.0075 (0.19) 0.0192 (0.49) 0.0138 (0.35) 8-Lead Cerdip (Q Package) 0.005 (0.13) MIN 8 0.055 (1.4) MAX 5 0.310 (7.87) 0.220 (5.59) PIN 1 1 4 0.200.(5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.023 (0.58) 0.070 (1.78) PLANE 0.014 (0.36) 0.030 (0.76) REV. B –23– 0.320 (8.13) 0.290 (7.37) 15° 0° 0.015 (0.38) 0.008 (0.20) PRINTED IN U.S.A. 0.100 (2.54) BSC 0.405 (10.29) MAX