Cypress CY3672 Three-pll general purpose flash programmable clock generator Datasheet

1CY2295
CY22392
Three-PLL General Purpose
FLASH Programmable Clock Generator
Features
• Three integrated phase-locked loops
• Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit
Post Divide)
• Improved Linear Crystal Load capacitors
• Flash programmability
• Field programmable
• Low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Configurable Crystal drive strength
• Frequency Select via 3 external LVTTL Inputs
• 3.3V operation
• 16-pin TSSOP packages
• Non-Volatile programming enables easy customization, ultra-fast turnaround, performance tweaking,
design timing margin testing, inventory control, lower
part count, and more secure product supply. In
addition, any part in the family can also be programmed
multiple times which reduces programming errors and
provides an easy upgrade path for existing designs.
• In-house programming of samples and prototype
quantities is available using the CY3672 FTG Development Kit. Production quantities are available through
Cypress Semiconductor’s value added Distribution
partners or by using third party programmers from BP
Microsystems, HiLo Systems, and others.
• Performance suitable for high-end multimedia, communications, industrial, A/D Converters, and consumer
applications.
• Supports numerous low-power application schemes
and reduces EMI by allowing unused outputs to be
turned off.
• CyClocksRT™ Support
Benefits
• Generates up to 3 unique frequencies on 6 outputs up
to 200 MHz from an external source. Functional
upgrade for current CY2292 family.
• Adjust Crystal Drive Strength for compatibility with
virtually all crystals.
• 3-Bit External Frequency Select Options for PLL1,
CLKA, and CLKB.
• Allows for 0 ppm Frequency Generation and Frequency
Conversion under the most demanding applications.
• Industry-standard supply voltage.
• Improves frequency accuracy over temperature, age,
process, and initial offset.
• Easy to use software support for design entry.
• Industry-standard packaging saves on board space.
Logic Block Diagram
XTALIN
XTALOUT
XBUF
OSC.
CONFIGURATION
FLASH
PLL1
11 BIT P
8 BIT Q
SHUTDOWN/OE
PLL2
S0
11 BIT P
8 BIT Q
S1
S2/SUSPEND
4x4
Crosspoint
Switch
PLL3
11 BIT P
8 BIT Q
Cypress Semiconductor Corporation
Document #: 38-07013 Rev. *D
•
3901 North First Street
•
San Jose
Divider
/2,3, or 4
CLKE
Divider
7 BIT
CLKD
Divider
7 BIT
CLKC
Divider
7 BIT
CLKB
Divider
7 BIT
CLKA
•
CA 95134 • 408-943-2600
Revised June 22, 2004
CY22392
Pin Configuration
CY22392
16-pin TSSOP
CLKC
1
16
VDD
2
15
S2/SUSPEND
SHUTDOWN/OE
AGND
3
14
AVDD
XTALIN
4
13
S1
XTALOUT
XBUF
5
12
6
11
S0
GND
CLKD
7
10
CLKA
CLKE
8
9
CLKB
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY22392FC
6
8 MHz–30 MHz (external crystal) Up to 200 MHz
1 MHz–166 MHz (reference clock)
Commercial Temperature
CY22392FI
6
8 MHz–30 MHz (external crystal) Up to 166 MHz
1 MHz–150 MHz (reference clock)
Industrial Temperature
Pin Description
Name
Pin Number
Description
CLKC
1
Configurable clock output C
VDD
2
Power supply
AGND
3
Analog Ground
XTALIN
4
Reference crystal input or external reference clock input
XTALOUT
5
Reference crystal feedback
XBUF
6
Buffered reference clock output
CLKD
7
Configurable clock output D
CLKE
8
Configurable clock output E
CLKB
9
Configurable clock output B
CLKA
10
Configurable clock output A
GND
11
Ground
S0
12
General Purpose Input for Frequency Control; bit 0
S1
13
General Purpose Input for Frequency Control; bit 1
AVDD
14
Analog Power Supply
S2/
SUSPEND
15
General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control
input.
SHUTDOWN/OE
16
Places outputs in three-state condition and shuts down chip when LOW. Optionally,
only places outputs in tristate condition and does not shut down chip when LOW
Document #: 38-07013 Rev. *D
Page 2 of 8
CY22392
Operation
The CY22392 is an upgrade to the existing CY2292. The new
device has a wider frequency range, greater flexibility,
improved performance, and incorporates many features that
reduce PLL sensitivity to external system issues.
The device has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The output of PLL1 is also sent to a
/2, /3, or /4 synchronous post-divider that is output through
CLKE. The frequency of PLL1 can be changed by external
CMOS inputs, S0, S1, S2. See the following section on
General-Purpose Inputs for more details.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
General-Purpose Inputs
S0, S1, and S2 are general-purpose inputs that can be
programmed to allow for eight different frequency settings.
Options that may be switched with these general purpose
inputs are as follows; the frequency of PLL1, the output divider
of CLKB, and the output divider of CLKA.
CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, then XTALOUT must be left floating.
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed via a programmable crosspoint
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. In
addition, many outputs have a unique capability for even
greater flexibility. The following is a description of each output.
CLKA’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
S2 controls which of the two programmable registers is loaded
into CLKA’s 7-bit post divider. See the section
“General-Purpose Inputs” for more information.
CLKB’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
and S2 controls which of the two programmable registers is
loaded into CLKA’s 7-bit post divider. See the section
“General-Purpose” Inputs for more information.
CLKC’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD’s output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.
For example: the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
XBUF is simply the buffered reference.
Crystal Input
The SHUTDOWN/OE input three-states the outputs when
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, the reference oscillator, and
all other active components. The resulting current on the VDD
pins will be less than 5 µA (typical). After leaving shutdown
mode, the PLLs will have to relock.
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
Document #: 38-07013 Rev. *D
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.
Power Saving Features
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.
Page 3 of 8
CY22392
Junction Temperature Limitations
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment,
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKA–CLKD). This prevents the output edges
from aligning, allowing superior jitter performance.
Power Supply Sequencing
For parts with multiple VDD pins, there are no power supply
sequencing requirements. The part will not be fully operational
until all VDD pins have been brought up to the voltages
specified in the “Operating Conditions” table.
All grounds should be connected to the same ground plane.
CyClocksRT™ Software
It is possible to program the CY22392 such that the maximum
Junction Temperature rating is exceeded. The package θJA is
115 C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage ...............................................–0.5V to +7.0V
DC Input Voltage ............................–0.5V to + (AVDD + 0.5V)
Storage Temperature ................................. –65°C to +125°C
CyClocksRT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocksRT also has a power estimation feature that allows
you to see the power consumption of your specific configuration. You can download a copy of CyClocksRT for free on
Cypress’s web site at www.cypress.com.
Junction Temperature...................................................125°C
Data Retention @ Tj = 125°C.................................>10 years
Maximum Programming Cycles .......................................100
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................................
2000V
Latch up (per JEDEC 17) .................................... > ±200 mA
Operating Conditions[1]
Parameter
Description
VDD/AVDD
Supply Voltage
TA
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
Min.
Typ.
Max.
Unit
3.135
3.3
3.465
V
0
–
+70
°C
–40
–
+85
°C
CLOAD_OUT
Max. Load Capacitance
–
–
15
pF
fREF
External Reference Crystal
8
–
30
MHz
External Reference Clock[2], Commercial
1
–
166
MHz
1
–
150
MHz
0.05
–
500
ms
[2]
External Reference Clock , Industrial
tPU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
Notes:
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
Document #: 38-07013 Rev. *D
Page 4 of 8
CY22392
Electrical Characteristics
Parameter
IOH
IOL
Description
Output High Current
Output Low Current
Conditions
[3]
[3]
[3]
CXTAL_MIN
Crystal Load Capacitance
CXTAL_MAX
Crystal Load Capacitance[3]
[3]
Min.
Typ.
Max.
Unit
VOH = VDD – 0.5, VDD = 3.3 V
12
24
–
mA
VOL = 0.5V, VDD = 3.3 V
12
24
–
mA
Capload at minimum setting
–
6
–
pF
Capload at maximum setting
–
30
–
pF
–
7
–
pF
–
–
AVDD
CLOAD_IN
Input Pin Capacitance
Except crystal pins
VIH
HIGH-Level Input Voltage
CMOS levels,% of AVDD
70%
VIL
LOW-Level Input Voltage
CMOS levels,% of AVDD
–
–
30%
AVDD
IIH
Input HIGH Current
VIN = AVDD – 0.3 V
–
<1
10
µA
IIL
Input LOW Current
VIN = +0.3 V
–
<1
10
µA
IOZ
Output Leakage Current
Three-state outputs
–
10
µA
IDD
Total Power Supply Current
3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz
–
100
–
mA
3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz
–
50
–
mA
–
5
20
µA
IDDS
Total Power Supply Current in Shutdown active
Shutdown Mode
Switching Characteristics
Parameter
1/t1
t2
Name
Output Frequency[3, 4]
Output Duty
Cycle[3, 5]
Min.
Typ.
Max.
Unit
Clock output limit, Commercial
Description
–
–
200
MHz
Clock output limit, Industrial
–
–
166
MHz
Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2, measured at VDD/2
45%
50%
55%
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1, measured at VDD/2
40%
50%
60%
t3
Rising Edge Slew Rate[3] Output clock rise time, 20% to 80% of VDD
0.75
1.4
–
V/ns
t4
Falling Edge Slew
Rate[3]
Output clock fall time, 20% to 80% of VDD
0.75
1.4
–
V/ns
t5
Output three-state
Timing[3]
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
–
150
300
ns
t6
Clock Jitter[3, 6]
Peak-to-peak period jitter, CLK outputs measured
at VDD/2
–
400
–
ps
t7
Lock Time[3]
PLL Lock Time from Power-up
–
1.0
3
ms
Notes:
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07013 Rev. *D
Page 5 of 8
CY22392
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t1
t2
OUTPUT
t3
t4
Output Three-State Timing
OE
t5
t5
ALL
THREE-STATE
OUTPUTS
CLK Output Jitter
t6
CLK
OUTPUT
Frequency Change
SELECT
OLD SELECT
Fold
NEW SELECT STABLE
t7
Fnew
OUTPUT
Test Circuit
AVDD
0.1 µF
OUTPUTS
CLK out
CLOAD
VDD
0.1 µF
GND
Document #: 38-07013 Rev. *D
Page 6 of 8
CY22392
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY22392FC
Z16
16-TSSOP
Commercial (TA = 0°C to 70°C)
3.3V
CY22392FI
Z16
16-TSSOP
Industrial (TA = –40°C to 85°C)
3.3V
Z16
16-TSSOP
Commercial (TA = 0°C to 70°C)
3.3V
Z16
16-TSSOP
Industrial (TA = –40°C to 85°C)
3.3V
Z16
16-TSSOP
Commercial (TA = 0°C to 70°C)
3.3V
Z16
16-TSSOP
Industrial (TA = –40°C to 85°C)
3.3V
CY22392ZXC-xxx
Z16
16-TSSOP
Commercial (TA = 0°C to 70°C)
3.3V
CY22392ZXI-xxx[7]
Z16
16-TSSOP
Industrial (TA = –40°C to 85°C)
3.3V
CY22392ZC-xxx
CY22392ZI-xxx
[7]
[7]
CY3672
FTG Development Kit
Lead Free
CY22392FXC
CY22392FXI
[7]
Note:
7. The CY22392ZC-xxx and CY22392ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
100 Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Package Diagram
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05 gms
PART #
4.30[0.169]
4.50[0.177]
Z16.173
STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
CyClocksRT is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-07013 Rev. *D
Page 7 of 8
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges
CY22392
Document History Page
Document Title: CY22392 Three PLL General Purpose Flash Programmable Clock Generator
Document Number: 38-07013
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
106738
07/03/01
TLG
New Data Sheet
*A
108515
08/23/01
JWK
Updates based on characterization results. Removed “Preliminary” heading.
Added paragraph on Junction Temperature limitations and part configurations. Removed soldering temperature rating. Split crystal load into two typical
specs representing digital settings range. Changed t5 max to 300 ns.
Changed t7 typical to 1.0 ms.
*B
110052
12/09/01
CKN
Preliminary to Final.
*C
121864
12/14/02
RBI
Power up requirements added to Operating Conditions Information
*D
237811
See ECN
RGL
Added Lead Free Devices
Document #: 38-07013 Rev. *D
Page 8 of 8