AD AD8052ARM-REEL7 Low cost, high speed rail-to-rail amplifier Datasheet

a
FEATURES
Low Cost Single (AD8051), Dual (AD8052) and Quad
(AD8054)
Voltage Feedback Architecture
Fully Specified at +3 V, +5 V and ⴞ5 V Supplies
Single Supply Operation
Output Swings to Within 25 mV of Either Rail
Input Voltage Range: –0.2 V to +4 V; VS = +5 V
High Speed and Fast Settling on +5 V:
110 MHz –3 dB Bandwidth (G = +1) (AD8051/AD8052)
150 MHz –3 dB Bandwidth (G = +1) (AD8054)
145 V/␮s Slew Rate
50 ns Settling Time to 0.1%
Small Packaging
AD8051 Available in SOT-23-5
AD8052 Available in ␮SOIC-8
AD8054 Available in TSSOP-14
Good Video Specifications (G = +2)
Gain Flatness of 0.1 dB to 20 MHz; RL = 150 ⍀
0.03% Differential Gain Error; RL = 1K
0.03ⴗ Differential Phase Error; R L = 1K
Low Distortion
–80 dBc Total Harmonic @ 1 MHz, RL = 100 ⍀
Outstanding Load Drive Capability
Drives 45 mA, 0.5 V from Supply Rails (AD8051/AD8052)
Drives 50 pF Capacitive Load (G = +1) (AD8051/AD8052)
Low Power of 2.75 mA/Amplifier (AD8054)
Low Power of 4.4 mA/Amplifier (AD8051/AD8052)
APPLICATIONS
Coax Cable Driver
Active Filters
Video Switchers
A/D Driver
Professional Cameras
CCD Imaging Systems
CD/DVD ROM
Low Cost, High Speed
Rail-to-Rail Amplifiers
AD8051/AD8052/AD8054
CONNECTION DIAGRAMS
(Top Views)
SO-8
8
NC
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
R-8, ␮SOIC (RM)
AD8052
OUT1 1
–
+
–IN1 2
+IN1 3
–
+
–VS 4
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
5 +VS
+ –
+IN 3
4 –IN
R-14, TSSOP-14 (RU-14)
8
+VS
OUT A
1
14
OUT D
7
OUT
2IN A
2
13
2IN D
6
–IN2
+IN A
3
12
+IN D
5 +IN2
V+
4
+IN B
AD8054
11
V2
5
10
+IN C
2IN B
6
9
2IN C
OUT B
7
8
OUT C
The AD8051/AD8052/AD8054 offer low power supply current and can operate on a single +3 V power supply. These
features are ideally suited for portable and battery powered
applications where size and power are critical.
The wide bandwidth and fast slew rate on a single +5 V supply
make these amplifiers useful in many general purpose, high speed
applications where dual power supplies of up to ±6 V and single
supplies from +3 V to +12 V are needed.
All of this low cost performance is offered in an 8-lead SOIC,
along with a tiny SOT-23-5 package (AD8051), a µSOIC
package (AD8052) and a TSSOP-14 (AD8054).
5.0
4.5
(THD # 0.5%) – Volts
4.0
3.5
VS = +5V
G = –1
RF = 2kV
RL = 2kV
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1
REV. B
–VS 2
AD8051
portable equipment. Low distortion and fast settling make them
ideal for active filter applications.
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
Despite their low cost, the AD8051/AD8052/AD8054 provide
excellent overall performance and versatility. The output voltage swing extends to within 25 mV of each rail, providing the
maximum output dynamic range with excellent overdrive recovery. This makes the AD8051/AD8052/AD8054 useful for video
electronics such as cameras, video switchers or any high speed
VOUT 1
NC = NO CONNECT
PRODUCT DESCRIPTION
The AD8051 (single), AD8052 (dual) and AD8054 (quad) are
low cost, voltage feedback, high speed amplifiers designed to
operate on +3 V, +5 V or ± 5 V supplies. They have true single
supply capability with an input voltage range extending 200␣ mV
below the negative rail and within 1␣ V of the positive rail.
AD8051
NC 1
SOT-23-5 (RT)
1
FREQUENCY – MHz
10
50
Figure 1. Low Distortion Rail-to-Rail Output Swing
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
(@ TA = +25ⴗC, VS = +5 V, RL = 2 k⍀ to +2.5 V,
AD8051/AD8052/AD8054–SPECIFICATIONS unless otherwise noted)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
Conditions
Min
AD8051A/AD8052A
Typ
70
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to +2.5 V,
RF = 806 Ω for AD8051A/AD8052A
RF = 200 Ω for AD8054A
100
G = –1, VO = 2 V Step
G = +1, VO = 2 V p-p
G = –1, VO = 2 V Step
145
35
50
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to +2.5 V
RL = 1 kΩ to +2.5 V
G = +2, RL = 150 Ω to +2.5 V
RL = 1 kΩ to +2.5 V
f = 5 MHz, G = +2
–67
16
850
0.09
0.03
0.19
0.03
–60
DC PERFORMANCE
Input Offset Voltage
110
50
1.7
10
1.4
TMIN –T MAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
RL = 2 kΩ to +2.5 V
TMIN –T MAX
RL = 150 Ω to +2.5 V
TMIN –T MAX
86
76
0.1
98
96
82
78
72
RL = 10␣ kΩ to +2.5 V
RL = 2␣ kΩ to +2.5 V
RL = 150 Ω to +2.5 V
VOUT = 0.5 V to +4.5 V
TMIN –T MAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
0.015 to 4.985
0.1 to 4.9 0.025 to 4.975
0.3 to 4.625 0.2 to 4.8
45
45
80
130
50
Max
10
25
MHz
MHz
12
170
45
40
MHz
MHz
V/µs
MHz
ns
–68
16
850
0.07
0.02
0.26
0.05
–60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
1.7
15
2
2.5
3.25
0.75
82
74
70
70
–40
4.4
80
0.2
98
96
82
78
12
30
4.5
4.5
1.2
300
1.5
–0.2 to 4
86
3
68
+85 –40
2.75
80
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
kΩ
pF
V
dB
0.03 to 4.975
0.125 to 4.875 0.05 to 4.95
0.55 to 4.4
0.25 to 4.65
30
30
45
85
12
5
Units
150
60
V
V
V
mA
mA
mA
mA
pF
pF
40
3
OPERATING TEMPERATURE RANGE
140
290
1.4
–0.2 to 4
88
VCM = 0 V to +3.5 V
∆VS = ± 1 V
80
AD8054A
Typ
20
TMIN –T MAX
Offset Drift
Input Bias Current
Max Min
12
V
3.275 mA
dB
+85
°C
NOTES
1
Refer to Figure 15.
Specifications subject to change without notice.
–2–
REV. B
SPECIFICATIONS
AD8051/AD8052/AD8054
(@ TA = +25ⴗC, VS = +3 V, RL = 2 k⍀ to +1.5 V, unless otherwise noted)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
Conditions
Min
70
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V,
RF = 402 Ω for AD8051A/AD8052A
RF = 200 Ω for AD8054A
G = –1, VO = 2 V Step
90
G = +1, VO = 1 V p-p
G = –1, VO = 2 V Step
AD8051A/AD8052A
Typ
Max Min
110
50
AD8054A
Typ
80
Max
Units
135
65
MHz
MHz
10
150
85
55
MHz
MHz
V/µs
MHz
ns
–47
16
600
–48
16
600
dB
nV/√Hz
fA/√Hz
17
135
65
55
110
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1
fC = 5 MHz, VO = 2 V p-p,
G = –1, RL = 100 Ω to +1.5 V
Input Voltage Noise
f = 10 kHz
Input Current Noise
f = 10 kHz
Differential Gain Error (NTSC)
G = +2, VCM = +1 V
RL = 150 Ω to +1.5 V,
RL = 1 kΩ to +1.5 V
Differential Phase Error (NTSC)
G = +2, VCM = +1 V
RL = 150 Ω to +1.5 V
RL = 1 k Ω to +1.5 V
Crosstalk
f = 5 MHz, G = +2
0.11
0.09
0.13
0.09
%
%
0.24
0.10
–60
0.3
0.1
–60
Degrees
Degrees
dB
DC PERFORMANCE
Input Offset Voltage
1.6
TMIN –T MAX
Offset Drift
Input Bias Current
10
1.3
TMIN –T MAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
RL = 2 kΩ
TMIN –T MAX
RL = 150 Ω
TMIN –T MAX
80
74
72
RL = 10␣ kΩ to +1.5 V
RL = 2␣ kΩ to +1.5 V
RL = 150 Ω to +1.5 V
VOUT = 0.5 V to +2.5 V
TMIN –T MAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
0.01 to 2.99
0.075 to 2.9 0.02 to 2.98
0.2 to 2.75 0.125 to 2.875
45
45
60
90
45
15
2
80
72
70
0.1 to 2.9
0.35 to 2.55
0.2
96
94
80
76
12
30
4.5
4.5
1.2
68
–40
NOTES
1
Refer to Figure 15.
Specifications subject to change without notice.
–3–
4.2
80
12
4.8
kΩ
pF
V
dB
0.025 to 2.98
0.35 to 2.965
0.15 to 2.75
25
25
30
50
V
V
V
mA
mA
mA
mA
pF
pF
3
68
+85 –40
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
300
1.5
–0.2 to 2
86
35
3
∆VS = +0.5 V
1.6
2.6
3.25
0.8
290
1.4
–0.2 to 2
88
VCM = 0 V to 1.5 V
OPERATING TEMPERATURE RANGE
REV. B
0.15
96
94
82
76
10
25
2.625
80
12
V
3.125 mA
dB
+85
°C
(@ TA = +25ⴗC, VS = ⴞ5 V, RL = 2 k⍀ to Ground,
AD8051/AD8052/AD8054–SPECIFICATIONS unless otherwise noted)
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
Conditions
Min
AD8051A/AD8052A
Typ
G = +1, VO = 0.2 V p-p
70
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω,
RF = 1.1 kΩ for AD8051A/AD8052A
RF = 200 Ω for AD8054A
G = –1, V O = 2 V Step
105
G = +1, VO = 2 V p-p
G = –1, V O = 2 V Step
20
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω
RL = 1 kΩ
G = +2, RL = 150 Ω
RL = 1 kΩ
f = 5 MHz, G = +2
–71
16
900
0.02
0.02
0.11
0.02
–60
DC PERFORMANCE
Input Offset Voltage
110
50
1.8
10
1.4
TMIN –TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
RL = 2 kΩ
TMIN –TMAX
RL = 150 Ω
TMIN –TMAX
88
78
0.1
96
96
82
80
72
RL = 10␣ kΩ
RL = 2␣ kΩ
RL = 150 Ω
VOUT = –4.5 V to +4.5 V
TMIN –TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
–4.98 to +4.98
–4.85 to +4.85 –4.97 to +4.97
–4.45 to +4.3 –4.6 to +4.6
45
45
100
160
50
11
27
AD8054A
Typ
160
65
MHz
MHz
15
190
50
40
MHz
MHz
V/µs
MHz
ns
–72
16
900
0.06
0.02
0.15
0.03
–60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
1.8
15
2
2.6
3.5
0.75
84
76
70
Max Units
0.2
96
96
82
80
13
32
4.5
4.5
1.2
300
1.5
–5.2 to 4
86
68
–40
4.8
80
–4.97 to +4.97
–4.8 to +4.8 –4.9 to +4.9
–4.0 to +3.8 –4.5 to +4.5
30
30
60
100
12
5.5
3
68
+85
–40
2.875
80
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
kΩ
pF
V
dB
V
V
V
mA
mA
mA
mA
pF
pF
40
3
OPERATING TEMPERATURE RANGE
150
290
1.4
–5.2 to 4
88
VCM = –5 V to +3.5 V
∆VS = ± 1 V
85
170
40
50
TMIN –TMAX
Offset Drift
Input Bias Current
Max Min
12
3.4
V
mA
dB
+85
°C
Specifications subject to change without notice.
–4–
REV. B
AD8051/AD8052/AD8054
ABSOLUTE MAXIMUM RATINGS 1
plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die by
the package. Exceeding a junction temperature of +175°C for an
extended period can result in device failure.
Supply␣ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6␣ V
Internal␣ Power␣ Dissipation2
Small␣ Outline␣ Package (R) . . . Observe Power Derating Curves
SOT-23-5 Package . . . . . . . . Observe Power Derating Curves
µSOIC Package . . . . . . . . . . Observe Power Derating Curves
TSSOP-14 Package . . . . . . . Observe Power Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential␣ Input␣ Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 2.5␣ V
Output Short Circuit Duration
␣ ␣ . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering␣ 10␣ sec) . . . . . . . . +300°C
While the AD8051/AD8052/AD8054 are internally short circuit
protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
MAXIMUM POWER DISSIPATION – Watts
2.0
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead SOIC: θJA = 155°C/W
5-Lead SOT-23-5: θJA = 240°C/W
8-Lead µSOIC: θJA = 200°C/W
14-Lead SOIC: θJA = 120°C/W
14-Lead TSSOP: θJA = 180°C/W
14-LEAD SOIC
1.5
8-LEAD SOIC
PACKAGE
14-LEAD TSSOP-14
1.0
0.5
TJ = +1508C
mSOIC
SOT-23-5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – 8C
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8051/
AD8052/AD8054 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8051/AD8052/AD8054
ORDERING GUIDE
Model
Temperature
Range
Package
Descriptions
Package
Options*
Brand
Code
AD8051AR
AD8051AR-REEL
AD8051AR-REEL7
AD8051ART-REEL
AD8051ART-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
13" Tape and Reel
7" Tape and Reel
13" Tape and Reel
7" Tape and Reel
SO-8
SO-8
SO-8
RT-5
RT-5
H2A
H2A
AD8052AR
AD8052AR-REEL
AD8052AR-REEL7
AD8052ARM
AD8052ARM-REEL
AD8052ARM-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
13" Tape and Reel
7" Tape and Reel
8-Lead µSOIC
13" Tape and Reel
7" Tape and Reel
SO-8
SO-8
SO-8
RM-8
RM-8
RM-8
H4A
H4A
H4A
AD8054AR
AD8054AR-REEL
AD8054AR-REEL7
AD8054ARU
AD8054ARU-REEL
AD8054ARU-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
14-Lead SOIC
13" Tape and Reel
7" Tape and Reel
14-Lead µSOIC
13" Tape and Reel
7" Tape and Reel
R-14
R-14
R-14
RU-14
RU-14
RU-14
*R = Small Outline; RM = Micro Small Outline; RT = Surface Mount; RU = TSSOP .
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8051/AD8052/AD8054 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE
AD8051/AD8052/AD8054
3
5
2
0
G = +5
RF = 2kV
–1
–2
3
NORMALIZED GAIN – dB
NORMALIZED GAIN – dB
1
G = +1
RF = 0
G = +10
RF = 2kV
–3
–4
–5
–6
–7
0.1
VS = +5V
GAIN AS SHOWN
RF AS SHOWN
RL = 2kV
VO = 0.2V p-p
1
1
10
FREQUENCY – MHz
100
–1
–2
–4
1M
10M
FREQUENCY – Hz
500M
100M
6
VS = +3V
5
VS = +5V
1
4
0
3
GAIN – dB
VS = 65V
–1
–4
G = +5
RF = 2kV
Figure 6. AD8054 Normalized Gain vs. Frequency;
VS = +5 V
2
–3
G = +10
RF = 2kV
–3
–7
100k
500
G = +1
RF = 0
G = +2
RF = 2kV
0
–6
3
GAIN – dB
2
–5
Figure 3. AD8051/AD8052 Normalized Gain vs.
Frequency; VS = +5 V
–2
VS = +5V
GAIN AS SHOWN
RF AS SHOWN
RL = 5kV
VO = 0.2V p-p
4
G = +2
RF = 2kV
VS AS SHOWN
G = +1
RL = 2kV
VO = 0.2V p-p
+3V
G = +1
RL = 2kV
CL = 5pF
VO = 0.2V p-p
+5V
65V
2
1
0
65V
–1
–5
–2
–6
–3
+3V
–7
0.1
1
10
FREQUENCY – MHz
100
–4
100k
500
3
10M
FREQUENCY – Hz
100M
500M
4
2
+858C
+258C
3
–408C
1
2
0
+858C
+258C
–1
–408C
1
GAIN – dB
GAIN – dB
1M
Figure 7. AD8054 Gain vs. Frequency vs. Supply
Figure 4. AD8051/AD8052 Gain vs. Frequency
vs. Supply
–2
–3
0
VS = +5V
RL = 2kV TO 2.5V
CL = 5pF
G = +1
VO = 0.2V p-p
–1
–2
VS = +5V
G = +1
–5 RL = 2kV
VO = 0.2V p-p
–6 TEMPERATURE AS SHOWN
–4
–7
0.1
+5V
–3
–4
–5
1
10
FREQUENCY – MHz
100
500
1
Figure 5. AD8051/AD8052 Gain vs. Frequency vs.
Temperature
10
FREQUENCY – MHz
100
500
Figure 8. AD8054 Gain vs. Frequency vs. Temperature
–6–
REV. B
6.3
6.3
6.2
6.2
6.1
6.1
GAIN FLATNESS – dB
6.0
5.9
5.8
5.7
5.6
5.5
VS = +5V
G = +2
RL = 150V
RF = 806V
VO = 0.2V p-p
6.0
5.9
5.8
5.6
5.5
5.4
5.4
5.3
5.3
0.1
1
10
FREQUENCY – MHz
100
Figure 9. AD8051/AD8052 0.1 dB Gain Flatness vs.
Frequency; G = +2
6
5
5
GAIN – dB
GAIN – dB
7
6
4
VS = 65V
VO = 4V p-p
3
VS AS SHOWN
G = +2
RL = 2kV
RF = 2kV
VO AS SHOWN
–1
0.1
1
0
100
500
1
10
FREQUENCY – MHz
100
500
Figure 13. AD8054 Large Signal Frequency Response;
G = +2
80
VS = +5V
RL = 2kV
70
VS = +5V
RL = 2kV
CL = 5pF
70
60
OPEN-LOOP GAIN – dB
60
50
40
GAIN
0
30
20
PHASE
508 PHASE
MARGIN
–45
10
–90
0
–135
–10
–180
0.1
1
10
FREQUENCY – MHz
100
PHASE – Degrees
OPEN-LOOP GAIN – dB
VS AS SHOWN
G = +2
RL = 2kV
RF = 2kV
VO AS SHOWN
–1
0.1
80
50
40
GAIN
30
180
20
135
PHASE
10
458 PHASE
MARGIN
0
–20
30k
500
90
45
–10
Figure 11. AD8051/AD8052 Open-Loop Gain and
Phase vs. Frequency
REV. B
3
1
10
FREQUENCY – MHz
VS = 65V
VO = 4V p-p
4
2
Figure 10. AD8051/AD8052 Large Signal Frequency
Response; G = +2
–20
0.01
100
VS = +5V
VO = 2V p-p
8
7
0
10
FREQUENCY – MHz
9
VS = +5V
VO = 2V p-p
8
1
1
Figure 12. AD8054 0.1 dB Gain Flatness vs. Frequency;
G = +2
9
2
VS = +5V
RF = 200V
RL = 150V
G = +2
VO = 0.2V p-p
5.7
0
100k
1M
10M
FREQUENCY – Hz
100M
500M
Figure 14. AD8054 Open-Loop Gain and Phase
Margin vs. Frequency
–7–
PHASE MARGIN – Degrees
GAIN FLATNESS – dB
AD8051/AD8052/AD8054
AD8051/AD8052/AD8054
1000
VS = +3V, G = 21
RF = 2kV, RL = 100V
VO = 2V p-p
230
VS = +5V
VS = +5V, G = +2
RF = 2kV, RL = 100V
VS = +5V, G = +1
RL = 100V
240
250
VOLTAGE NOISE – nA Hz
TOTAL HARMONIC DISTORTION – dBc
220
260
270
VS = +5V, G = +1
RL = 2kV
280
VS = +5V, G = +2
RF = 2kV, RL = 2kV
290
100
10
2100
2110
1
2
3
4
5
6 7
FUNDAMENTAL FREQUENCY – MHz
1
10
8 9 10
1M
10M
Figure 18. Input Voltage Noise vs. Frequency
Figure 15. Total Harmonic Distortion
230
100
VS = +5V
240
10MHz
250
260
CURRENT NOISE – pA Hz
WORST HARMONIC – dBc
1k
10k
100k
FREQUENCY – Hz
100
270
280
5MHz
290
2100
VS = +5V
RL = 2kV
G = +2
1MHz
2110
2120
10
1
2130
2140
0
0.5
1.0
1.5
2.0 2.5
3.0 3.5
OUTPUT VOLTAGE – V p-p
4.0
4.5
0.1
10
5.0
RL = 1kV
VS = +5, G = +2
RF = 2kV, RL AS SHOWN
0
10
20
30
40
0.10
0.05
0.00
50
60
70
80
90
100
RL = 1kV
20.05
20.10
20.15
20.20
20.25
1M
10M
0.10
RL = 150V
NTSC SUBSCRIBER (3.58MHz)
DIFFERENTIAL
GAIN – %
0.10
0.08
0.06
0.04
0.02
0.00
20.02
20.04
20.06
1k
10k
100k
FREQUENCY – Hz
Figure 19. Input Current Noise vs. Frequency
DIFFERENTIAL
PHASE – Degrees
DIFFERENTIAL
PHASE ERROR – Degrees
DIFFERENTIAL
GAIN ERROR – %
Figure 16. Worst Harmonic vs. Output Voltage
100
RL = 150V
VS = +5, G = +2
RF = 2kV, RL AS SHOWN
NTSC SUBSCRIBER (3.58MHz)
0.00
–0.05 VS = +5, G = +2
RF = 2kV, RL AS SHOWN
–0.10
1st 2nd 3rd 4th 5th
0.3
10
20
30
40
50
60
70
80
MODULATING RAMP LEVEL – IRE
90
100
Figure 17. AD8051/AD8052 Differential Gain and Phase
Errors
RL = 150V
6th 7th
8th
9th 10th 11th
0.2
RL = 1kV
0.1
0.0
–0.1
–0.2
–0.3
0
RL = 1kV
0.05
VS = +5, G = +2
RF = 2kV,
RL AS SHOWN
1st 2nd
RL = 150V
3rd 4th 5th 6th 7th 8th 9th 10th 11th
MODULATING RAMP LEVEL – IRE
Figure 20. AD8054 Differential Gain and Phase Errors
–8–
REV. B
AD8051/AD8052/AD8054
–10
–20
–20
–30
–40
–40
CROSSTALK – dB
CROSSTALK – dB
–30
–10
VS = +5V
RF = 2kV
RL = 2kV
VO = 2V p-p
–50
–60
–70
RL = 100V
–50
–60
–70
RL = 1kV
–80
–80
–90
–90
–100
–100
0.1
1
10
FREQUENCY – MHz
100
–110
0.1
500
10
0
–30
–10
–40
–20
PSRR – dB
CMRR – dB
VS = +5V
–20
–50
–60
–80
–60
–90
–70
0.1
1
10
FREQUENCY – MHz
100
–80
0.01
500
+PSRR
0.1
1
10
FREQUENCY – MHz
100
500
70
100
VS = 15V
G = 11
60
SETTING TIME TO 0.1% 2 ns
OUTPUT RESISTANCE – V
–PSRR
Figure 25. PSRR vs. Frequency
Figure 22. CMRR vs. Frequency
10
3.1
1
0.31
0.1
AD8051/AD8052
50
AD8054
40
30
20
VS = 15V
G = 21
RL = 2kV
10
0.031
1
10
FREQUENCY – MHz
100
0
0.5
500
Figure 23. Closed Loop Output Resistance vs. Frequency
REV. B
500
VS = +5V
–40
–70
0.01
0.1
100
–30
–50
31
10
FREQUENCY – MHz
20
0
–100
0.03
1
Figure 24. AD8054 Crosstalk (Output-to-Output) vs.
Frequency
Figure 21. AD8052 Crosstalk (Output-to-Output) vs.
Frequency
–10
VS = 65V
RF = 1kV
RL = AS SHOWN
VO = 2V p-p
1
1.5
INPUT STEPS – Volts p-p
Figure 26. Settling Time vs. Input Step
–9–
2
AD8051/AD8052/AD8054
1.00
VS = +5V
VOH = +858C
0.90
0.80
OUTPUT SATURATION VOLTAGE – Volts
OUTPUT SATURATION VOLTAGE – Volts
1.00
VOH = +258C
0.70
VOH = –408C
VOL = +858C
0.60
0.50
0.40
0.30
VOL = +258C
0.20
VOL = –408C
0.10
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT – mA
Figure 27. AD8051/AD8052 Output Saturation Voltage vs.
Load Current
+5V –VOH (+1258C)
0.750
+5V –VOH (+258C)
0.625
+5V –VOH (–558C)
0.500
0.375
0.250
VOL (+1258C)
0.125
VOL (–558C)
0.00
0
0
0
VS = +5V
0.875
3
6
9
VOL (+258C)
12
15
18
21
LOAD CURRENT – mA
24
27
30
Figure 29. AD8054 Output Saturation Voltage vs. Load
Current
100
OPEN-LOOP GAIN – dB
RL = 2kV
90
RL = 150V
80
70
VS = +5V
60
0
0.5
1
1.5
2
2.5
3
3.5
OUTPUT VOLTAGE – Volts
4
4.5
5
Figure 28. Open-Loop Gain vs. Output Voltage
–10–
REV. B
AD8051/AD8052/AD8054
VOLTS
5
1.50V
2.5
Figure 33. Output Swing; G = –1, RL = +2 kΩ
Figure 30. 100 mV Step Response, G = +1
2.55
VOLTS
2.60
2.50
2.50
2.45
2.40
20ns
Figure 34. AD8054 100 mV Step Response; VS = +5 V,
G = +1
Figure 31. AD8051/AD8052 200 mV Step Response;
VS = +5 V, G = +1
4
3
VOLTS
3.5
2
1
2.5
21
1.5
22
23
24
Figure 35. Large Signal Step Response; VS = ± 5 V, G = +1
Figure 32. Large Signal Step Response; VS = +5 V, G = +2
REV. B
–11–
AD8051/AD8052/AD8054
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 36, the AD8051/AD8052/
AD8054 recovers within 60␣ ns from negative overdrive and
within 45␣ ns from positive overdrive.
2.60
2.55
2.50
2.45
2.40
Figure 38. AD8051/AD8052 200 mV Step Response:
CL = 50 pF
10000
VS = +5V
# 30%
OVERSHOOT
CAPACITIVE LOAD 2 PF
Figure 36.␣ Overdrive Recovery
Driving Capacitive Loads
Consider the AD8051/AD8052 in a closed-loop gain of +1 with
+VS = 5 V and a load of 2 kΩ in parallel with 50 pF. Figures 37
and 38 show its frequency and time domain responses, respectively, to a small-signal excitation. The capacitive load drive of
the AD8051/AD8052/AD8054 can be increased by adding a
low valued resistor in series with the load. Figures 39 and 40
show the effect of a series resistor on capacitive drive for varying
voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less peaking. Adding a series resistor with lower closed-loop gains accomplishes the same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and the load capacitance.
RS = 3V
1000
RS = 0V
100
RG
RS
VIN
100mV STEP
50V
10
1
RF
1
2
3
VOUT
CL
4
A C L – V/V
6
5
Figure 39. AD8051/AD8052 Capacitive Load Drive vs.
Closed-Loop Gain
8
1000
6
VS = +5V
# 30%
OVERSHOOT
4
CAPACITIVE LOAD – pF
GAIN – dB
2
0
22
24
VS = +5V
G = +1
RL = 2kV
CL = 50pF
VO = 200mV p-p
26
28
210
0.1
1
RS = 10V
RS = 0V
100
RG
RF
VIN
100mV STEP
50V
10
FREQUENCY – MHz
100
500
Figure 37. AD8051/AD8052 Closed-Loop Frequency
Response: CL = 50 pF
RS
VOUT
CL
10
1
2
3
4
A C L – V/V
5
6
Figure 40. AD8054 Capacitive Load Drive vs. Closed-Loop
Gain
Circuit Description
The AD8051/AD8052/AD8054 is fabricated on Analog Devices’
proprietary eXtra-Fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 2 GHz–4 GHz region. The process is
dielectrically isolated to eliminate the parasitic and latch-up
–12–
REV. B
AD8051/AD8052/AD8054
problems caused by junction isolation. These features allow the
construction of high frequency, low distortion amplifiers with low
supply currents. This design uses a differential output input stage
to maximize bandwidth and headroom (see Figure 1). The smaller
signal swings required on the first stage outputs (nodes S1P, S1N)
reduce the effect of nonlinear currents due to junction capacitances
and improve the distortion performance. With this design harmonic distortion of –80 dBc @ 1 MHz into 100 Ω with VOUT =
2 V p-p (Gain = +1) on a single 5 V supply is achieved.
The inputs of the device can handle voltages from –0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values will not cause phase reversal; however, the input
ESD devices will begin to conduct if the input voltages exceed
the rails by greater than 0.5 V. During this overdrive condition,
the output stays at the rail.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common-emitter output stage.
High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not
shown). This circuit topology allows the AD8051/AD8052 to drive
45 mA of output current and the AD8054 to drive 30 mA of output current with the outputs within 0.5␣ V of the supply rails.
to a minimum. Parasitic capacitance of less than 1 pF at the
inverting input can significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end.
Active Filters
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
Figure 42 shows an example of a 2␣ MHz biquad bandwidth
filter that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
noise bandwidth of the analog signal before A/D conversion.
Please note that the unused amplifiers’ inputs should be tied to
ground.
R6
1kV
C1
50pF
R2
2kV
VIN
R1
3kV
R26
I10
Q4
R39
Q25
1
R3
2kV
I2
6
7
Q51
Q31
Q7
Q1
VINN
SIP
Q2
R5
R21
AD8054
VOUT
AD8054
Figure 42. 2␣ MHz Biquad Bandpass Filter Using AD8054
VEE
The frequency response of the circuit is shown in Figure 43.
C3
VOUT
Q27
C9
SIN
Q3
9
10
I5
R23 R27
Q21
C7
Q39
Q23
Q22
R5
2kV
12
8
AD8054
Q36
Q5
VEE
Q13
I3
14
C2
50pF
5
I9
Q50
Q40
R15 R2
VINP
2
3
VCC
13
R4
2kV
0
Q8
Q11
Q24
R3
I7
Q47
I11
I8
210
VCC
GAIN – dB
VEE
Figure 41. AD8051/AD8052 Simplified Schematic
APPLICATIONS
Layout Considerations
230
The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and component selection. Proper RF design techniques and low-parasitic
component selection are necessary.
240
10k
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the
area near the input pins to reduce the parasitic capacitance.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within 3 mm of each power pin. An additional large (4.7␣ µF to
10 µF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the parasitic capacitance at this node
REV. B
220
100k
1M
FREQUENCY – Hz
10M
100M
Figure 43. Frequency Response of 2␣ MHz Bandpass
Biquad Filter
A/D and D/A Applications
Figure 44 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit 20 MSPS dual A/D converter. This
converter is designed to convert I and Q signals in communication systems. In this application, only the I channel is being
driven. The I channel is enabled by applying a logic HIGH to
SELECT, Pin 27.
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and
–13–
AD8051/AD8052/AD8054
0.33mF
+5V
10pF
1kV
CLK
SLEEP
22V
1VDD
SELECT
INA-I
22V
INB-I
0.1mF
10mF
0.01mF
22V
10mF
0.1mF
AD8051
50V
AD9201
10pF
0.1mF
1kV
0.1mF
10mF
10mF
0.1mF
DATA OUT
REFT-I
D9
0.1mF
REFB-I
D8
AVSS
D7
REFSENSE
D6
VREF
D5
D4
25V
15V
10mF
AVDD
0.1mF
1kV
0.1mF
10mF
0.1mF
D3
REFB-Q
D2
REFT-Q
D1
0.1mF
D0
22V
15V
DVDD
INB-Q
10pF
0.1mF
DVSS
22V
10mF
INA-Q
10pF
THREE–STATE
Figure 44. AD8051 Driving an AD9201, a 10-Bit 20 MSPS A/D Converter
applied to the noninverting input of the AD8051. The amplifier
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the A/D.
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 8) which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low pass filter that
also helps to reduce distortion.
The output of the op amp is ac coupled into INA-I (Pin 2) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 kΩ resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I will swing both
10.0
5.0
0.0
25.0
210.0
215.0
220.0
225.0
230.0
235.0
240.0
245.0
250.0
255.0
260.0
265.0
270.0
275.0
280.0
285.0
290.0
295.0
2100.0
2105.0
2110.0
2115.0
2120.0
0.0E10
PART#
FUND
With the sampling clock running at 20 MSPS, the A/D output
was analyzed with a digital analyzer. Two input frequencies
were used, 1 MHz and 9.5 MHz, which is just short of the
Nyquist frequency. These signals were well filtered to minimize
any harmonics.
Figure 45 shows the FFT response of the A/D for the case of
1 MHz analog input. The SFDR is 71.66 dB and the A/D is
producing 8.8 ENOB (effective number of bits). When the
analog frequency was raised to 9.5 MHz, the SFDR was reduced to 60.18 dB and the A/D operated with 8.46 ENOBs as
shown in Figure 46. The inclusion of the AD8051 in the circuit
had no worsening of the distortion performance of the AD9201.
10.0
5.0
0.0
25.0
210.0
215.0
0
FFTSIZE 8192
2ND
3RD
7TH
4TH
5TH
2.0E16
1.0E16
positive and negative with respect to the bias voltage applied to
INB-I.
4.0E16
3.0E16
8TH
6TH
6.0E16
5.0E16
9TH
8.0E16
7.0E16
FCLK
20.0E16
FUND
998.5E13
VIN
20.51dB
THD
268.13
SNR
54.97
SINAD
54.76
ENOB
8.80
SFDR
271.66
2ND
274.53
3RD
276.06
4TH
276.35
5TH
279.05
6TH
280.36
7TH
275.08
8TH
288.12
9TH
277.87
220.0
225.0
230.0
235.0
240.0
245.0
250.0
255.0
260.0
265.0
2ND
270.0
275.0
280.0
285.0
3RD
7TH
4TH
6TH
8TH
290.0
295.0
2100.0
2105.0
2110.0
2115.0
2120.0
0.0E10
10.0E16
9.0E16
Figure 45. FFT Plot for AD8051 Driving the AD9201 at
1 MHz
PART#
FUND
2.0E16
1.0E16
4.0E16
3.0E16
6.0E16
5.0E16
8.0E16
7.0E16
0
FFTSIZE 8192
FCLK
20.0E16
FUND
9.5E16
VIN
20.44dB
THD
257.08
SNR
54.65
SINAD
52.69
ENOB
8.46
SFDR
260.18
2ND
260.18
3RD
260.23
4TH
282.01
5TH
278.83
6TH
281.28
7TH
277.28
8TH
284.54
9TH
292.78
10.0E16
9.0E16
Figure 46. FFT Plot for AD8051 Driving the AD9201 at
9.5 MHz
–14–
REV. B
AD8051/AD8052/AD8054
goes high with a duty cycle that is a small fraction of a percent.
The opposite condition defines the other extreme.
Sync Stripper
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, like A/D conversion,
it is not desirable to have the sync pulses on the video signal.
These pulses will reduce the dynamic range of the video signal
and do not provide any useful information for such a function.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame, but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal will have negative-going
excursions is compliance with the composite video specifications. The combination of horizontal and vertical blanking intervals limit such a signal to being at the highest (white) level for a
maximum of about 75% of the time.
A sync stripper will remove the synchronizing pulses from a
video signal while passing all the useful video information. Figure 47 shows a practical single supply circuit that uses only a
single AD8051. It is capable of directly driving a reverse terminated video line.
VBLANK
As a result of the duty cycles between the two extremes presented above, a 1 V p-p composite video signal that is multiplied
by a gain of two requires about 3.2 V p-p of dynamic voltage
swing at the output for an op amp to pass a composite video
signal of arbitrary varying duty cycle without distortion.
VIDEO WITHOUT SYNC
VIDEO WITH SYNC
GROUND
+0.4V
GROUND
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level in order to lower the amount of dynamic
signal swing required. However, these circuits can have artifacts
like sync tip compression unless they are driven by a source with
a very low output impedance. The AD8051/AD8052/AD8054
have adequate signal swing when running on a single +5 V
supply to handle an ac coupled composite video signal.
+3V OR +5V
0.1mF
+
10mF
VIN
TO A/D
AD8051
100V
R2
1kV
The input to the circuit in Figure 48 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac coupling. The noninverting input of the op amp is biased to half of
the supply voltage.
R1
1kV
+0.8V
(OR 2 3 VBLANK)
Figure 47. Sync Stripper
The feedback circuit provides unity gain for the dc biasing of the
input, and provides a gain of two for any signals that are in the
video bandwidth. The output is ac coupled and terminated to
drive the line.
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set equal to
two via the two 1 kΩ resistors in the feedback circuit. A bias
voltage must be applied to R1 in order that the input signal has
the sync pulses stripped at the proper level.
The capacitor values were selected for providing minimum “tilt”
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broadcast quality. However, if a lower consumer grade of video,
sometimes referred to as “consumer video” is all that is desired,
the values and the cost of the capacitors can be reduced by as
much as a factor of five with minimum visible degradation in the
picture.
The blanking level of the input video pulse is the desired place
to remove the sync information. This level is multiplied by two
by the amplifier. This level must be at ground at the output in
order for the sync stripping action to take place. Since the gain
of the amplifier from the input of R1 to the output is –1, a voltage equal to 2 × VBLANK must be applied to make the blanking
level come out at ground.
+5V
4.99kV
Single Supply Composite Video Line Driver
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual supply amplifiers to pass
them. However, by ac level shifting a single supply amplifier can
be used to pass these signals. The following complications may
arise from such techniques.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak to peak amplitude after they are ac coupled. As a worst
case, the dynamic signal swing will approach twice the peakto-peak value. The two conditions that define the maximum
dynamic wing requirements are a signal that is mostly low, but
REV. B
4.99kV
COMPOSITE
47mF
VIDEO
+
IN
RT
10mF
75V
+
10mF
0.1mF
+
10mF
1000mF
+
AD8051
RBT
75V
RL
75V
RF
1kV
VOUT
0.1mF
RG
1kV
220mF
Figure 48. Single Supply Composite Video Line Driver
–15–
AD8051/AD8052/AD8054
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead SOIC
(R-14)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
PIN 1
0.3444 (8.75)
0.3367 (8.55)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
SEATING
PLANE
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8°
0°
8
1
7
0.0098 (0.25)
0.0040 (0.10)
0.0500
(1.27)
BSC
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0098 (0.25)
0.0075 (0.19)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
0.201 (5.10)
0.193 (4.90)
14
5
0.199 (5.05)
0.187 (4.75)
1
0.0192 (0.49)
0.0138 (0.35)
0.0196 (0.50)
x 45°
0.0099 (0.25)
14-Lead TSSOP
(RU-14)
0.122 (3.10)
0.114 (2.90)
8
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0098 (0.25)
0.0075 (0.19)
14
8-Lead ␮SOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
C3139b–0–9/99
8-Lead SOIC
(SO-8)
8
0.177 (4.50)
0.169 (4.30)
4
0.256 (6.50)
0.246 (6.25)
1
PIN 1
7
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
PIN 1
0.006 (0.15)
0.002 (0.05)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
SEATING
PLANE
0.011 (0.28)
0.003 (0.08)
33°
27°
0.028 (0.71)
0.016 (0.41)
SEATING
PLANE
0.0433
(1.10)
MAX
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
5-Lead Plastic Surface Mount
(RT-5)
0.0709 (1.800)
0.0590 (1.500)
5
4
1
2
3
PRINTED IN U.S.A.
0.1220 (3.100)
0.1063 (2.700)
0.1181 (3.000)
0.0984 (2.500)
PIN 1
0.0374 (0.950) REF
0.0748 (1.900)
REF
0.0512 (1.300)
0.0354 (0.900)
0.0590 (0.150)
0.0000 (0.000)
0.0079 (0.200)
0.0035 (0.090)
0.0571 (1.450)
0.0354 (0.900)
0.0197 (0.500)
0.0118 (0.300)
SEATING
PLANE
10°
0°
0.0236 (0.600)
0.0039 (0.100)
–16–
REV. B