March 2004 AS7C1024B ® 5V 128K X 8 CMOS SRAM Features - • Industrial and commercial temperatures • Organization: 131,072 words x 8 bits • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: ACTIVE 300 mil SOJ 400 mil SOJ 8 × 20mm TSOP 1 8 x 13.4mm sTSOP 1 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA - 605 mW / max @ 10 ns • Low power consumption: STANDBY - 55 mW / max CMOS Pin arrangement 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) Logic block diagram NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND VCC GND 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32-pin (8 x 20mm) TSOP I 32-pin (8 x 13.4mm) sTSOP1 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 I/O0 Control circuit A9 A10 A11 A12 A13 A14 A15 A16 Column decoder I/O7 WE OE CE1 CE2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1024B 512 x 256 x 8 Array (1,048,576) Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Row decoder Input buffer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1024B • 6T 0.18u CMOS technology • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum Operating Current 110 100 90 80 mA Maximum CMOS standby Current 10 10 10 10 mA 3/26/04, v 1.2 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C1024B ® Functional description The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1024B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/ O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Symbol Min Max Unit Voltage on VCC relative to GND Parameter Vt1 –0.50 +7.0 V Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 °C Ambient temperature with VCC applied Tbias –55 +125 °C DC current into outputs (low) IOUT – 20 mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 CE2 WE OE Data Mode H X X X High Z Standby (ISB, ISB1) X L X X High Z Standby (ISB, ISB1) L H H H High Z Output disable (ICC) L H H L DOUT Read (ICC) L H L X DIN Write (ICC) Key: X = don’t care, L = low, H = high 3/26/04, v 1.2 Alliance Semiconductor P. 2 of 9 AS7C1024B ® Recommended operating conditions Parameter Supply Voltage Min Nominal Max Unit VCC 4.5 5.0 5.5 V VIH 2.2 - VCC + 0.5 V VIL –0.5 – 0.8 V commercial TA 0 – 70 °C industrial TA –40 – 85 °C Input Voltage Ambient operating temperature Symbol VIL min = -1.0V for pulse width less than 5ns VIH max = VCC+2.0V for pulse width less than 5ns. DC operating characteristics (over the operating range)1 -10 Parameter -12 -15 -20 Unit Sym Test conditions Min Max Min Max Min Max Min Max Input leakage current |ILI| VCC = Max, VIN = GND to VCC - 1 – 1 – 1 – 1 µA Output leakage current |ILO| VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC - 1 – 1 – 1 – 1 µA Operating power supply current ICC VCC = Max, CE1 ≤ VIL, CE2 ≥ VIH, f = fMax, IOUT = 0 mA - 110 – 100 – 90 – 80 mA ISB VCC = Max, CE1 ≥ VIH and/or CE2 ≤ VIL, f = fMax - 50 – 45 – 45 – 40 - 10 – 10 – 10 – 10 Standby power supply current Output voltage VCC = Max, CE1 ≥ VCC–0.2V ISB1 and/or CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ VCC – 0.2V, f = 0 mA VOL IOL = 8 mA, VCC = Min - 0.4 – 0.4 – 0.4 – 0.4 VOH IOH = –4 mA, VCC = Min 2.4 - 2.4 – 2.4 – 2.4 – V Capacitance (f = 1 MHz, Ta = 25 °C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE1, CE2, WE, OE VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 3/26/04, v 1.2 Alliance Semiconductor P. 3 of 9 AS7C1024B ® Read cycle (over the operating range)3,9,12 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 - 12 – 15 – 20 – ns Address access time tAA - 10 – 12 – 15 – 20 ns 3 Chip enable (CE1) access time tACE1 - 10 – 12 – 15 – 20 ns 3, 12 Chip enable (CE2) access time tACE2 - 10 – 12 – 15 – 20 ns 3, 12 Output enable (OE) access time tOE - 5 – 6 – 7 – 8 ns Output hold from address change tOH CE1 Low to output in low Z tCLZ1 3 - 3 – 3 – 3 – ns 5 3 - 3 – 3 – 3 – ns 4, 5, 12 CE2 High to output in low Z tCLZ2 3 - 3 – 3 – 3 – ns 4, 5, 12 CE1 Low to output in high Z tCHZ1 - 4 – 5 – 6 – 7 ns 4, 5, 12 CE2 Low to output in high Z tCHZ2 - 4 – 5 – 6 – 7 ns 4, 5, 12 OE Low to output in low Z tOLZ 0 - 0 – 0 – 0 – ns 4, 5 OE High to output in high Z tOHZ – 4 – 5 – 6 – 7 ns 4, 5 Power up time tPU 0 - 0 – 0 – 0 – ns 4, 5, 12 Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5, 12 Key to switching waveforms Rising input Falling input Undefined / don’t care Read waveform 1 (address controlled)3,6,7,9,12 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12 tRC1 CE1 CE2 tOE OE DOUT Current supply 3/26/04, v 1.2 tOHZ tCHZ1, tCHZ2 tOLZ tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% Alliance Semiconductor ICC ISB P. 4 of 9 AS7C1024B ® Write cycle (over the operating range)11, 12 -10 Parameter Symbol -12 Min Max Min -15 Max -20 Min Max Min Max Unit Notes Write cycle time tWC 10 - 12 – 15 – 20 – ns Chip enable (CE1) to write end tCW1 8 - 9 – 10 – 12 – ns 12 Chip enable (CE2) to write end tCW2 8 - 9 – 10 – 12 – ns 12 Address setup to write end tAW 8 - 9 – 10 – 12 – ns Address setup time tAS 0 0 – 0 – 0 – ns Write pulse width tWP 7 8 – 9 – 12 – ns Write recovery time tWR 0 - 0 – 0 – 0 – ns Address hold from end of write tAH 0 - 0 – 0 – 0 – ns Data valid to write end tDW 5 6 – 8 – 10 – ns Data hold time tDH 0 0 – 0 – 0 – ns 4, 5 12 Write enable to output in high Z tWZ - 5 – 6 – 7 – 8 ns 4, 5 Output active from write end tOW 1 - 1 – 1 – 2 – ns 4, 5 Write waveform 1 (WE controlled)10,11,12 tWC tWR tAH tAW Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT 3/26/04, v 1.2 Alliance Semiconductor P. 5 of 9 AS7C1024B ® Write waveform 2 (CE1 and CE2 controlled)10,11,12 tAW tWC tAH tWR Address tAS tCW1, tCW2 CE1 CE2 tWP WE tWZ tDW DIN tDH Data valid DOUT AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.5V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. +5V Thevenin equivalent: 168Ω 480Ω +3.5V GND 90% 10% 90% 2 ns 10% Figure A: Input pulse DOUT 255Ω C13 DOUT +1.728V GND Figure B: 5V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE1 and OE are low and CE2 is high for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 3/26/04, v 1.2 Alliance Semiconductor P. 6 of 9 AS7C1024B ® Package dimensions D 32-pin SOJ 300 mil e E1E2 B Pin 1 c A A1 A2 b Seating Plane E Min Max Min Max A 0.128 0.145 0.132 0.146 A1 0.025 - 0.025 - A2 0.095 0.105 0.105 0.115 B 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 D 0.820 0.830 0.820 0.830 E 0.255 0.275 0.354 0.378 E1 0.295 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445 e b 0.050 BSC 0.050 BSC 32-pin TSOP 8×20 mm e Min α c D Hd A2 L pin 1 E 3/26/04, v 1.2 32-pin SOJ 400 mil pin 16 A A1 pin 32 pin 17 Alliance Semiconductor Max A – 1.20 A1 0.05 0.15 A2 0.95 1.05 b 0.17 0.27 c 0.10 0.21 D 18.30 18.50 e 0.50 nominal E 7.90 8.10 Hd 19.80 20.20 L 0.50 0.70 α 0° 5° P. 7 of 9 AS7C1024B ® Ordering codes Package \ Access time Plastic SOJ, 300 mil Plastic SOJ, 400 mil TSOP1 8×20 mm sTSOP1 8 x 13.4mm Temp commercial 10 ns 12 ns 15 ns 20 ns AS7C1024B-10TJC AS7C1024B-12TJC AS7C1024B-15TJC AS7C1024B-20TJC – AS7C1024B-12TJI AS7C1024B-15TJI AS7C1024B-20TJI AS7C1024B-10JC AS7C1024B-12JC AS7C1024B-15JC AS7C1024B-20JC – AS7C1024B-12JI AS7C1024B-15JI AS7C1024B-20JI AS7C1024B-10TC AS7C1024B-12TC AS7C1024B-15TC AS7C1024B-20TC – AS7C1024B-12TI AS7C1024B-15TI AS7C1024B-20TI industrial commercial industrial commercial industrial commercial AS7C1024B-10STC industrial – AS7C1024B-12STC AS7C1024B-15STC AS7C1024B-20STC AS7C1024B-12STI AS7C1024B-15STI AS7C1024B-20STI Note: Add suffix ‘N’ to the above part number for LEAD FREE PARTS (Ex: AS7C1024B-10TCN) Part numbering system AS7C 1024B –XX X X X SRAM prefix Device number Access time Package:T = TSOP1 8×20 mm ST = sTSOP1 8 x 13.4 mm J = SOJ 400 mil TJ = SOJ 300 mil Temperature range C = Commercial, 0° C to 70° C I = Industrial, -40° C to 85° C N = LEAD FREE PART 3/26/04, v 1.2 Alliance Semiconductor P. 8 of 9 AS7C1024B ® ® Alliance Semiconductor Corporation Copyright © Alliance Semiconductor 2575, Augustine Drive, All Rights Reserved Santa Clara, CA 95054 Part Number: AS7C1024B Tel: 408 - 855 - 4900 Document Version: v 1.2 Fax: 408 - 855 - 4999 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. 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