ASAHI KASEI [AK4626A] AK4626A High Performance Multi-channel Audio CODEC GENERAL DESCRIPTION The AK4626A is a single chip CODEC that includes two channels of ADC and six channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the newly developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4626A has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as the AK4112B. The AK4626A is available in a small 44pin LQFP package which will reduce system space. *AC-3 is a trademark of Dolby Laboratories. FEATURES 2ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Single-Ended Input - S/(N+D): 92dB - Dynamic Range, S/N: 102dB - Digital HPF for offset cancellation - I/F format: MSB justified, I2S or TDM - Overflow flag 6ch 24bit DAC - 128x Oversampling - Sampling Rate up to 192kHz - 24bit 8 times Digital Filter - Single-Ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM - Individual channel digital volume with 128 levels and 0.5dB step - Soft mute - De-emphasis for 32kHz, 44.1kHz and 48kHz - Zero Detect Function High Jitter Tolerance TTL Level Digital I/F 3-wire Serial and I2C Bus µP I/F for mode setting Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz 128fs, 192fs or 256fs for fs=64kHz to 96kHz 128fs for fs=120kHz to 192kHz Power Supply: 4.5 to 5.5V Power Supply for output buffer: 2.7 to 5.5V Small 44pin LQFP AK4626 Pin Compatible MS0397-E-00 2005/06 -1- ASAHI KASEI [AK4626A] Block Diagram LIN ADC HPF RIN ADC HPF Audio I/F RX1 RX2 RX3 RX4 XTI LOUT1 ROUT1 LPF LPF DAC DAC DATT DATT MCLK LRCK BICK MCLK XTO MCKO DIR LRCK BICK LRCK AK4112B DAUX LOUT2 LPF DAC BICK SDTO DATT Format Converter ROUT2 LPF DAC DATT SDOUT LOUT3 LPF DAC SDOS DATT SDTO ROUT3 LPF DAC DATT SDTI1 SDTI2 SDTI3 SDIN1 SDIN2 SDIN3 LRCK BICK AC3 SDIN SDOUT1 SDOUT2 SDOUT3 AK4626A Block Diagram (DIR and AC-3 DSP are external parts) MS0397-E-00 2005/06 -2- ASAHI KASEI [AK4626A] Ordering Guide -40 ∼ +85°C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4626A AK4626AVQ AKD4626 DZF1 AVSS AVDD VREFH VCOM 38 37 36 35 34 P/S DIF0/CSN 41 MCLK DIF1/SCL/CCLK 42 40 LOOP0/SDA/CDTI 39 TDM0 44 43 Pin Layout SDOS 1 33 DZF2/OVF I2C 2 32 RIN SMUTE 3 31 LIN 30 NC 29 TST5 28 ROUT1 27 LOUT1 26 ROUT2 BICK 4 LRCK 5 SDTI1 6 SDTI2 7 SDTI3 8 AK4626AVQ Top View 15 16 17 18 19 20 21 22 DVSS PDN TST2 CAD1 CAD0 TST3 TST4 LOUT3 14 23 DVDD 11 TVDD ROUT3 DFS0 13 LOUT2 24 12 25 10 DZFE 9 TST1 SDTO DAUX MS0397-E-00 2005/06 -3- ASAHI KASEI [AK4626A] Compatibility with AK4527B 1. Functions Functions DAC Sampling frequency TDM128 (96kHz) Digital Attenuator Soft Mute Analog Input (ADC) AK4527B Up to 96kHz Not available 256 levels Soft mute function is independent of Digital attenuator. Differential input AK4626A Up to 192kHz Available 128 levels Soft mute function is not independent of Digital attenuator. Single-ended Input AK4527B DFS NC TEST NC ADIF CAD1 CAD0 LINLIN+ RINRIN+ LOOP1 AK4626A DFS0 TST1 TST2 CAD1 CAD0 TST3 TST4 TST5 NC LIN RIN AK4527B Not available Not available DFS Not available Not available Not available AK4626A TDM0 TDM1 DFS0 DFS1 ATS1, ATS0 DZFM3 2. Pin Configuration pin# 11 12 18 19 20 21 22 29 30 31 32 44 TDM0 3. Register Addr 00H 00H 01H 01H 09H 0AH MS0397-E-00 2005/06 -4- ASAHI KASEI [AK4626A] PIN/FUNCTION No. 1 Pin Name SDOS I/O I 2 I2C I 3 SMUTE I 4 5 6 7 8 9 10 11 BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS0 I I I I I O I I 12 TST1 I 13 DZFE I 14 15 16 17 TVDD DVDD DVSS PDN I 18 TST2 I 19 20 21 CAD1 CAD0 TST3 I I O 22 TST4 O Function SDTO Source Select Pin (Note 1) “L”: Internal ADC output, “H”: DAUX input SDOS pin should be set to “L” when TDM= “1”. Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus Soft Mute Pin (Note 1) When this pin goes to “H”, soft mute cycle is initialized. When returning to “L”, the output mute releases. Audio Serial Data Clock Pin Input Channel Clock Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin Audio Serial Data Output Pin AUX Audio Serial Data Input Pin Double Speed Sampling Mode Pin (Note 1) “L”: Normal Speed, “H”: Double Speed Test Pin This pin should be connected to DVSS. Zero Input Detect Enable Pin “L”: mode 7 (disable) at parallel mode, zero detect mode is selectable by DZFM3-0 bits at serial mode “H”: mode 0 (DZF1 is AND of all six channels) Output Buffer Power Supply Pin, 2.7V∼5.5V Digital Power Supply Pin, 4.5V∼5.5V Digital Ground Pin, 0V Power-Down & Reset Pin When “L”, the AK4626A is powered-down and the control registers are reset to default state. If the state of P/S or CAD1-0 changes, then the AK4626A must be reset by PDN. Test Pin This pin should be connected to DVSS. Chip Address 1 Pin Chip Address 0 Pin Test Pin This pin should be left floating. Test Pin This pin should be left floating. MS0397-E-00 2005/06 -5- ASAHI KASEI [AK4626A] No. 23 24 25 26 27 28 29 Pin Name LOUT3 ROUT3 LOUT2 ROUT2 LOUT1 ROUT1 TST5 30 NC - 31 32 33 LIN RIN DZF2 I I O OVF O 34 VCOM O 35 36 37 38 VREFH AVDD AVSS DZF1 I O 39 40 MCLK P/S I I 41 DIF0 CSN I I 42 DIF1 SCL/CCLK I I 43 LOOP0 I SDA/CDTI 44 TDM0 I/O O O O O O O I I/O I Function DAC3 Lch Analog Output Pin DAC3 Rch Analog Output Pin DAC2 Lch Analog Output Pin DAC2 Rch Analog Output Pin DAC1 Lch Analog Output Pin DAC1 Rch Analog Output Pin Test pin (Internal pull-down pin) This pin should be left floating or connected to AVSS. No Connect No internal bonding. Lch Analog Input Pin Rch Analog Input Pin Zero Input Detect 2 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to “H”. It always is in “L” when P/S is “H”. Analog Input Overflow Detect Pin (Note 3) This pin goes to “H” if the analog input of Lch or Rch overflows. Common Voltage Output Pin, AVDD/2 Large external capacitor around 2.2µF is used to reduce power-supply noise. Positive Voltage Reference Input Pin, AVDD Analog Power Supply Pin, 4.5V∼5.5V Analog Ground Pin, 0V Zero Input Detect 1 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to “H”. Output is selected by setting DZFE pin when P/S is “H”. Master Clock Input Pin Parallel/Serial Select Pin “L”: Serial control mode, “H”: Parallel control mode Audio Data Interface Format 0 Pin in parallel control mode Chip Select Pin in 3-wire serial control mode This pin should be connected to DVDD at I2C bus control mode Audio Data Interface Format 1 Pin in parallel control mode Control Data Clock Pin in serial control mode I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus) Loopback Mode 0 Pin in parallel control mode Enables digital loop-back from ADC to 3 DACs. Control Data Input Pin in serial control mode I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus) TDM I/F Format Mode Pin (Note 1) “L”: Normal mode, “H”: TDM mode Notes: 1. SDOS, SMUTE, DFS0, and TDM0 pins are ORed with register data if P/S = “L”. 2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”. 3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode. 4. All digital input pins except for pull-down should not be left floating. MS0397-E-00 2005/06 -6- ASAHI KASEI [AK4626A] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 5) Parameter Symbol min AVDD -0.3 Power Supplies Analog DVDD -0.3 Digital TVDD -0.3 Output buffer |AVSS-DVSS| (Note 6) ∆GND Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage (Expect LRCK, BICK pins) VIND1 -0.3 (LRCK, BICK pins) VIND2 -0.3 Ambient Temperature (power applied) Ta -40 Storage Temperature Tstg -65 max 6.0 6.0 6.0 0.3 ±10 AVDD+0.3 Units V V V V mA V DVDD+0.3 TVDD+0.3 85 150 V V °C °C Notes: 5. All voltages with respect to ground. 6. AVSS and DVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 5) Parameter Symbol min typ Power Supplies Analog AVDD 4.5 5.0 (Note 7) Digital DVDD 4.5 5.0 Output buffer TVDD 2.7 5.0 max 5.5 5.5 5.5 Units V V V Notes: 5. All voltages with respect to ground. 7. The power up sequence between AVDD, DVDD and TVDD is not critical. Do not turn off only the AK4626A under the condition that a surrounding device is powered on and the I2C bus is in use. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0397-E-00 2005/06 -7- ASAHI KASEI [AK4626A] ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=48kHz 84 92 dB fs=96kHz 86 dB DR (-60dBFS) fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 96 dB fs=96kHz, A-weighted 93 102 dB dB 102 94 S/N (Note 8) fs=48kHz, A-weighted dB 96 88 fs=96kHz dB 102 93 fs=96kHz, A-weighted Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 ppm/°C Input Voltage AIN=0.62xVREFH Input Resistance (Note 9) Power Supply Rejection (Note 10) DAC Analog Output Characteristics Resolution S/(N+D) fs=48kHz fs=96kHz fs=192kHz DR (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted S/N (Note 11) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Output Voltage AOUT=0.6xVREFH Load Resistance Power Supply Rejection Notes: 2.90 3.10 15 25 50 80 78 95 88 94 95 88 94 90 90 88 88 2.75 5 (Note 10) 3.30 kΩ dB 24 Bits dB dB dB dB dB dB dB dB dB dB dB dB dB dB 0.5 3.25 dB ppm/°C Vpp kΩ dB 106 100 106 100 106 106 100 106 100 106 110 0.2 20 3.0 50 Vpp 8. S/N measured by CCIR-ARM is 98dB(@fs=48kHz). 9. Input resistance is 16kΩ typically at fs=96kHz. 10. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 11. S/N measured by CCIR-ARM is 102dB(@fs=48kHz). MS0397-E-00 2005/06 -8- ASAHI KASEI [AK4626A] Parameter Power Supplies Power Supply Current (AVDD+DVDD+TVDD) Normal Operation (PDN = “H”) AVDD fs=48kHz,96kHz fs=192kHz DVDD+TVDD fs=48kHz fs=96kHz fs=192kHz Power-down mode (PDN = “L”) TST=”L” min (Note 12) (Note 13) typ max Units 45 34 18 24 27 80 67 51 27 36 40 200 mA mA mA mA mA µA Notes: 12. TVDD=0.1mA(typ). 13. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS. MS0397-E-00 2005/06 -9- ASAHI KASEI [AK4626A] FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): PB 0 Passband (Note 14) ±0.1dB -0.2dB -3.0dB Stopband SB 28 Passband Ripple PR Stopband Attenuation SA 68 Group Delay (Note 15) GD Group Delay Distortion ∆GD ADC Digital Filter (HPF): Frequency Response (Note 14) -3dB FR -0.1dB DAC Digital Filter: Passband (Note 14) -0.1dB PB 0 -6.0dB Stopband SB 26.2 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 15) GD DAC Digital Filter + Analog Filter: FR Frequency Response: 0 ∼ 20.0kHz FR 40.0kHz (Note 16) FR 80.0kHz (Note 16) typ max Units 20.0 23.0 18.9 - 16 0 kHz kHz kHz kHz dB dB 1/fs µs 1.0 6.5 Hz Hz ±0.04 21.8 - 19.2 kHz kHz kHz dB dB 1/fs ±0.2 ±0.3 ±1.0 dB dB dB 24.0 ±0.02 Notes: 14. The passband and stopband frequencies scale with fs. For example, 21.8kHz at –0.1dB is 0.454 x fs. 15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 16. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz. DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V) Parameter Symbol min High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL High-Level Output Voltage (SDTO, LRCK, BICK pin: Iout=-100µA) VOH TVDD-0.5 (DZF1, DZF2/OVF pins: Iout=-100µA) VOH AVDD-0.5 Low-Level Output Voltage (SDTO, DZF1, DZF2/OVF pins: Iout= 100µA) VOL (SDA, LRCK, BICK pin: Iout= 3mA) VOL Input Leakage Current (Note 17) Iin - typ - max 0.8 Units V V - - V V - 0.5 0.4 ±10 V V µA Note 17: TST2 pin has an internal pull-down device, nominally 100kohm. MS0397-E-00 2005/06 - 10 - ASAHI KASEI [AK4626A] SWITCHING CHARACTERISTICS (Ta=-40°C∼85°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF) Parameter Symbol min Master Clock Timing 8.192 fCLK 256fsn, 128fsd: 27 tCLKL Pulse Width Low 27 tCLKH Pulse Width High 12.288 fCLK 384fsn, 192fsd: 20 tCLKL Pulse Width Low 20 tCLKH Pulse Width High 16.384 fCLK 512fsn, 256fsd: 15 tCLKL Pulse Width Low 15 tCLKH Pulse Width High LRCK Timing Normal mode (TDM0= “0”, TDM1= “0”) 32 Normal Speed Mode fsn 64 Double Speed Mode fsd 120 Quad Speed Mode fsq 45 Duty Cycle Duty TDM256 mode (TDM0= “1”, TDM1= “0”) LRCK frequency fsn 32 “H” time tLRH 1/256fs “L” time tLRL 1/256fs TDM128 mode (TDM0= “1”, TDM1= “1”) fsd 64 LRCK frequency tLRH 1/128fs “H” time tLRL 1/128fs “L” time Audio Interface Timing Normal mode (TDM0= “0”, TDM1= “0”) tBCK BICK Period 81 tBCKL BICK Pulse Width Low 32 tBCKH Pulse Width High 32 tLRB LRCK Edge to BICK “↑” (Note 18) 20 tBLR BICK “↑” to LRCK Edge (Note 18) 20 tLRS LRCK to SDTO(MSB) tBSD BICK “↓” to SDTO tSDH SDTI1-3,DAUX Hold Time 20 tSDS SDTI1-3,DAUX Setup Time 20 TDM256 mode (TDM0= “1”, TDM1= “0”) BICK Period tBCK 81 BICK Pulse Width Low tBCKL 32 Pulse Width High tBCKH 32 LRCK Edge to BICK “↑” (Note 18) tLRB 20 BICK “↑” to LRCK Edge (Note 18) tBLR 20 BICK “↓” to SDTO tBSD SDTI1 Hold Time tSDH 10 SDTI1 Setup Time tSDS 10 TDM128 mode (TDM0= “1”, TDM1= “1”) 81 tBCK BICK Period 32 tBCKL BICK Pulse Width Low 32 tBCKH Pulse Width High 20 tLRB LRCK Edge to BICK “↑” (Note 18) 20 tBLR BICK “↑” to LRCK Edge (Note 18) tBSD BICK “↓” to SDTO 10 tSDH SDTI1-2 Hold Time 10 tSDS SDTI1-2 Setup Time Notes: 18. BICK rising edge must not occur at the same time as LRCK edge. MS0397-E-00 typ max Units 12.288 MHz ns ns MHz ns ns MHz ns ns 18.432 24.576 48 96 192 55 kHz kHz kHz % 48 kHz ns ns 96 kHz ns ns 40 40 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2005/06 - 11 - ASAHI KASEI [AK4626A] Parameter Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 19) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 20) PDN “↑” to SDTO valid (Note 21) Symbol min tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP 4.7 4.0 4.7 4.0 4.7 0 0.25 4.0 0 tPD tPDV 150 typ max Units ns ns ns ns ns ns ns ns 100 1.0 0.3 50 522 kHz µs µs µs µs µs µs µs µs µs µs ns ns 1/fs Notes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 20. The AK4626A can be reset by bringing PDN “L” to “H” upon power-up. 21. These cycles are the number of LRCK rising from PDN rising. 22. I2C is a registered trademark of Philips Semiconductors. MS0397-E-00 2005/06 - 12 - ASAHI KASEI [AK4626A] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fsn, 1/fsd VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing (TDM= “0”) 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRH tLRL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing (TDM= “1”) MS0397-E-00 2005/06 - 13 - ASAHI KASEI [AK4626A] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Audio Interface Timing (TDM= “0”) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Audio Interface Timing (TDM= “1”) MS0397-E-00 2005/06 - 14 - ASAHI KASEI [AK4626A] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing (3-wire Serial mode) tCSW VIH CSN VIL tCSH VIH CCLK VIL CDTI D3 D2 D1 VIH D0 VIL WRITE Data Input Timing (3-wire Serial mode) VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start I2C Bus mode Timing tPD VIH PDN VIL tPDV SDTO 50%TVDD Power-down & Reset Timing MS0397-E-00 2005/06 - 15 - ASAHI KASEI [AK4626A] OPERATION OVERVIEW System Clock The external clocks, which are required to operate the AK4626A, are MCLK, LRCK and BICK. MCLK should be synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2, 3, 4). In Auto Setting Mode (ACKS = “1”), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS. External clocks (MCLK, BICK) should always be present whenever the AK4626A is in normal operation mode (PDN = “H”). If these clocks are not provided, the AK4626A may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4626A should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4626A is in the power-down mode until MCLK and LRCK are input. DFS1 0 0 1 DFS0 0 1 0 Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 120kHz~192kHz Default Table 1. Sampling Speed (Manual Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920 11.2896 12.2880 MCLK (MHz) 384fs 12.2880 16.9344 18.4320 512fs 16.3840 22.5792 24.5760 BICK (MHz) 64fs 2.0480 2.8224 3.0720 Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) LRCK fs 88.2kHz 96.0kHz 128fs 11.2896 12.2880 MCLK (MHz) 192fs 16.9344 18.4320 256fs 22.5792 24.5760 BICK (MHz) 64fs 5.6448 6.1440 Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) (Note: At Double speed mode(DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.) LRCK fs 176.4kHz 192.0kHz 128fs 22.5792 24.5760 MCLK (MHz) 192fs - 256fs - BICK (MHz) 64fs 11.2896 12.2880 Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode) (Note: At Quad speed mode(DFS1= “1”, DFS0 = “0”) are not available for ADC.) MS0397-E-00 2005/06 - 16 - ASAHI KASEI [AK4626A] MCLK 512fs 256fs 128fs Sampling Speed Normal Double Quad Table 5. Sampling Speed (Auto Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 MCLK (MHz) 256fs 22.5792 24.5760 - 512fs 16.3840 22.5792 24.5760 - Sampling Speed Normal Double Quad Table 6. System Clock Example (Auto Setting Mode) De-emphasis Filter The AK4626A includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”). Mode 0 1 2 3 Sampling Speed Normal Speed Normal Speed Normal Speed Normal Speed DEM1 0 0 1 1 DEM0 0 1 0 1 DEM 44.1kHz OFF 48kHz 32kHz Default Table 7. De-emphasis control Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and scales with sampling rate (fs). MS0397-E-00 2005/06 - 17 - ASAHI KASEI [AK4626A] Audio Serial Interface Format When TDM= “L”, four modes can be selected by the DIF1-0 as shown in Table 8. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are latched on the rising edge of BICK. Figures 1∼4 shows the timing at SDOS = “L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”, the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6, 7, 10, 11 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs. Mode TDM 1 TDM0 DIF1 DIF0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 SDTO SDTI1-3, DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK I/O BICK I/O H/L I ≥ 48fs I H/L I ≥ 48fs I H/L I ≥ 48fs I L/H I ≥ 48fs I Default Table 8. Audio data formats (Normal mode) The audio serial interface format becomes the TDM mode if TDM0 pin is set to “H”. In the TDM256 mode, the serial data of all DAC (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins are ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by the DIF1-0 as shown in Table 9. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM mode. TDM128 Mode can be set by TDM1 as show in Table10. In Double Speed Mode, the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other two data (L3, R3) are input to the SDTI2. TDM0 pin and TDM0 register should be set to “H” if TDM256 Mode is selected. TDM0 pin and TDM0 register, TDM1 register should be set to “H” if Double Speed Mode is selected in TDM128 Mode. Mode TDM 1 TDM0 DIF1 DIF0 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 SDTO SDTI1 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK I/O BICK I/O ↑ I 256fs I ↑ I 256fs I ↑ I 256fs I ↓ I 256fs I Table 9. Audio data formats (TDM256 mode) Mode TDM 1 TDM0 DIF1 DIF0 8 1 1 0 0 9 1 1 0 1 10 1 1 1 0 11 1 1 1 1 SDTO 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S SDTI1, SDTI2 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK I/O BICK I/O ↑ I 128fs I ↑ I 128fs I ↑ I 128fs I ↓ I 128fs I Table 10. Audio data formats (TDM128 mode) MS0397-E-00 2005/06 - 18 - ASAHI KASEI [AK4626A] LRCK 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 12 11 10 0 19 18 8 Don’t Care 23 22 7 1 12 11 10 Don’t Care 0 0 19 18 SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Lch Data 23 8 7 1 0 Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 16 15 14 Don’t Care 0 23 22 23:MSB, 0:LSB 23 22 8 7 1 16 15 14 Don’t Care 0 0 23 22 Lch Data 23 8 7 1 0 Rch Data Figure 2. Mode 1 Timing LRCK 0 1 2 21 22 23 24 28 29 30 31 0 1 2 22 23 24 28 29 30 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 23 22 2 1 0 23 22 2 1 0 23:MSB, 0:LSB Don’t Care 23 22 2 1 0 23 22 2 1 0 Lch Data 23 Don’t Care 23 Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 22 23 24 25 29 30 31 0 1 2 3 22 23 24 25 29 30 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 23 22 2 1 0 23 22 2 1 0 23:MSB, 0:LSB Don’t Care 23 22 2 1 0 23 22 2 1 0 Lch Data Don’t Care Rch Data Figure 4. Mode 3 Timing MS0397-E-00 2005/06 - 19 - ASAHI KASEI [AK4626A] 256 BICK LRCK BICK(256fs) SDTO(o) 23 22 0 23 22 Lch 32 BICK SDTI1(i) 0 23 22 Rch 19 18 32 BICK 0 19 18 0 L1 R1 32 BICK 32 BICK 19 18 0 19 18 0 19 18 0 19 18 0 L2 R2 L3 R3 32 BICK 32 BICK 32 BICK 32 BICK 19 18 0 19 18 0 19 32 BICK 32 BICK Figure 5. Mode 4 Timing 256 BICK LRCK BICK(256fs) SDTO(o) 23 22 0 23 22 Lch 32 BICK SDTI1(i) 0 23 22 Rch 23 22 32 BICK 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 L3 R3 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 32 BICK 23 22 0 23 32 BICK Figure 6. Mode 5 Timing 256 BICK LRCK BICK(256fs) SDTO(o) 23 22 0 Lch SDTI1(i) 0 23 22 Rch 32 BICK 23 22 23 22 0 32 BICK 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L1 R1 L2 R2 L3 R3 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 32 BICK 23 22 0 23 22 32 BICK Figure 7. Mode 6 Timing 256 BICK LRCK BICK(256fs) SDTO(o) SDTI1(i) 23 0 23 0 Lch Rch 32 BICK 32 BICK 23 0 23 0 23 23 0 23 0 23 0 23 0 L1 R1 L2 R2 L3 R3 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 0 32 BICK 23 0 23 32 BICK Figure 8. Mode 7 Timing MS0397-E-00 2005/06 - 20 - ASAHI KASEI [AK4626A] 128 BICK LRCK BICK(128fs) SDTO(o) SDTI1(i) SDTI2(i) 23 22 0 0 23 22 Lch Rch 32 BICK 32 BICK 19 18 0 19 18 23 22 0 19 18 0 19 18 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 19 18 0 19 18 0 L3 R3 32 BICK 32 BICK 19 18 0 19 18 32 BICK 0 19 0 19 32 BICK Figure 9. Mode 8 Timing 128 BICK LRCK BICK(128fs) 23 22 SDTI1(i) SDTI2(i) 0 0 23 22 Lch Rch 32 BICK 32 BICK 23 22 0 23 22 23 22 0 23 22 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 L3 R3 32 BICK 32 BICK 23 22 0 23 22 32 BICK 0 19 0 19 32 BICK Figure 10. Mode 9 Timing 128 BICK LRCK BICK(128fs) SDTO(o) 23 22 0 SDTI1(i) SDTI2(i) 23 22 Rch 32 BICK 23 22 0 23 22 Lch 32 BICK 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 L3 R3 32 BICK 32 BICK 23 22 0 32 BICK 23 22 0 23 22 0 23 22 32 BICK Figure 11. Mode 10 Timing MS0397-E-00 2005/06 - 21 - ASAHI KASEI [AK4626A] 128 BICK LRCK BICK(128fs) SDTO(o) SDTI1(i) SDTI2(i) 23 22 0 0 23 22 Lch Rch 32 BICK 32 BICK 23 22 0 23 22 0 23 0 23 22 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 L3 R3 32 BICK 32 BICK 0 23 22 32 BICK 23 22 0 23 0 23 32 BICK Figure 12. Mode 11 Timing MS0397-E-00 2005/06 - 22 - ASAHI KASEI [AK4626A] Overflow Detection The AK4626A has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1” at serial control mode. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 16/fs = 333µs @fs=48kHz). OVF is “L” for 522/fs (=11.8ms @fs=48kHz) after PDN = “↑”, and then overflow detection is enabled. Zero Detection The AK4626A has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L” (Table 11). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2 channels. However DZF2 pin becomes OVF pin if OVFE bit is set to “1”. Zero detection mode is set to mode 0 if DZFE= “H” regardless of P/S pin. DZF1 is AND of all six channels and DZF2 is disabled (“L”) at mode 0. Table 12 shows the relation of P/S, DZFE, OVFE and DZF. When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK cycles, DZF1(DZF2) pin goes to “H”. DZF1(DZF2) pin immediately goes to “L” if input data of any channels in the group 1(group 2) is not zero after going DZF1(DZF2) “H”. Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DZFM 2 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 L1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 AOUT R1 L2 R2 L3 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1 DZF2 DZF2 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 disable (DZF1=DZF2 = “L”) R3 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 Default Not Available disable (DZF1=DZF2 = “L”) Table 11. Zero detect control P/S pin “H” (parallel mode) “L” (serial mode) DZFE pin “L” “H” “L” “H” OVFE bit disable disable “0” “1” “0” “1” DZF mode Mode 7 Mode 0 Selectable Selectable Mode 0 Mode 0 DZF1 pin “L” AND of 6ch Selectable Selectable AND of 6ch AND of 6ch DZF2/OVF pin “L” “L” Selectable OVF output “L” OVF output Table 12. DZF1-2 pins outputs MS0397-E-00 2005/06 - 23 - ASAHI KASEI [AK4626A] Digital Attenuator The AK4626A has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 13). ATT7-0 00H 01H 02H : 7DH 7EH 7FH FEH FFH Attenuation Level 0dB -0.5dB -1.0dB : -62.5dB -63dB MUTE (-∞) : MUTE (-∞) MUTE (-∞) Default Table 13. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 14). Transition between set values is the soft transition. Therefore, the switching noise does not occur in the transition. Mode 0 1 2 3 ATS1 0 0 1 1 ATS0 0 1 0 1 ATT speed 1792/fs 896/fs 256/fs 256/fs Default Table 14. Transition time between set values of ATT7-0 bits The transition between set values is soft transition of 1792 levels in mode 0. It takes 1792/fs (37.3ms@fs=48kHz) from 00H(0dB) to 7FH(MUTE) in mode 0. If PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs are 00H when RSTN = “0”. When RSTN return to “1”, the ATTs fade to their current value. MS0397-E-00 2005/06 - 24 - ASAHI KASEI [AK4626A] Soft mute operation Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 14) from the current ATT level. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATT Level (1) (1) (3) Attenuation -∞ GD (2) GD AOUT DZF1,2 (4) 8192/fs Notes: (1) ATT_DATA×ATT transition time (Table 14). For example, in Normal Speed Mode, this time is 1792LRCK cycles (1792/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to 7FH (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data at all the channels of the group are continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin immediately goes to “L” if the input data of either channel of the group are not zero after going DZF “H”. Figure 13. Soft mute and zero detection System Reset The AK4626A should be reset once by bringing PDN = “L” upon power-up. The AK4626A is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4626A is in the power-down mode until MCLK and LRCK are input. MS0397-E-00 2005/06 - 25 - ASAHI KASEI [AK4626A] Power-Down The ADC and DACs of AK4626A are placed in the power-down mode by bringing PDN “L” and both digital filters are reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 14 shows the sequences of the power-down and the power-up. The ADC and all DACs can be powered-down individually by PWADN and PWDAN bits. In this case, the internal register values are not initialized. When PWADN = “0”, SDTO goes to “L”. When PWDAN = “0”, the analog outputs go to VCOM voltage and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted externally if the click noise influences system application. PDN 522/fs ADC Internal State Normal Operation Power-down (1) Init Cycle Normal Operation 516/fs (2) DAC Internal State Normal Operation Power-down Init Cycle Normal Operation GD (3) GD ADC In (Analog) (4) ADC Out (Digital) “0”data DAC In (Digital) “0”data (5) (3) GD GD (6) DAC Out (Analog) (6) (7) Clock In Don’t care MCLK,LRCK,SCLK 10∼11/fs (10) (8) DZF1/DZF2 External Mute (9) Mute ON Notes: (1) The analog part of ADC is initialized after exiting the power-down state. (2) The analog part of DAC is initialized after exiting the power-down state. (3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (4) ADC output is “0” data at the power-down state. (5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click noise influences system application. (6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN. (7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4626A should be in the power down mode. (8) DZF pins are “L” in the power-down mode (PDN = “L”). (9) Please mute the analog output externally if the click noise (6) influences system application. (10) DZF= “L” for 10∼11/fs after PDN= “↑”. Figure 14. Power-down/up sequence example MS0397-E-00 2005/06 - 26 - ASAHI KASEI [AK4626A] Reset Function When RSTN = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go to VCOM voltage, DZF1-2 pins go to “H” and SDTO pin goes to “L”. Because some click noise occurs, the analog output should muted externally if the click noise influences system application. Figure 15 shows the power-up sequence. RSTN bit 4~5/fs (9) 1~2/fs (9) Internal RSTN bit 516/fs (1) ADC Internal State Normal Operation Digital Block Power-down DAC Internal State Normal Operation Digital Block Power-down Normal Operation Init Cycle Normal Operation GD (2) GD ADC In (Analog) (3) ADC Out (Digital) DAC In (Digital) (4) “0”data “0”data (2) GD DAC Out (Analog) GD (5) (6) (6) (7) Clock In MCLK,LRCK,SCLK Don’t care 4∼5/fs (8) DZF1/DZF2 Notes: (1) The analog part of ADC is initialized after exiting the reset state. (2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (3) ADC output is “0” data at the power-down state. (4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click noise influences system application. (5) The analog outputs go to VCOM voltage. (6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This noise is output even if “0” data is input. (7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, “1” should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed. (8) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”. (9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”. Figure 15. Reset sequence example MS0397-E-00 2005/06 - 27 - ASAHI KASEI [AK4626A] Serial Control Interface The AK4626A can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be initialized. When the state of P/S pin is changed, the AK4626A should be reset by PDN pin. * Writing to control register is invalid when PDN = “L”. * AK4626A does not support the read command. (1) 3-wire Serial Control Mode (I2C = “L”) Internal registers may be written to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1=CAD1, C0=CAD0) Read/Write (Fixed to “1”, Write only) Register Address Control Data Figure 16. 3-wire Serial Control I/F Timing MS0397-E-00 2005/06 - 28 - ASAHI KASEI [AK4626A] (2) I2C-bus Control Mode (I2C= “H”) AK4626A supports the standard-mode I2C-bus (max:100kHz). Then AK4626A does not support a fast-mode I2C-bus system (max:400kHz). The CSN pin should be connected to DVDD at the I2C-bus mode. Figure 17 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 21). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) (Figure 18). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4626A and R/W bit is “0”, the AK4626A generates the acknowledge and the write operation is executed. If R/W bit is “1”, the AK4626A generates the not acknowledge since the AK4626A can be only a slave-receiver. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 22). The second byte consists of the address for control registers of the AK4626A. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 20). Those data after the second byte contain control data. The format is MSB first, 8bits (Figure 20). The AK4626A generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 20). The AK4626A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4626A generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 23) except for the START and the STOP condition. S T A R T SDA S S T O P R/W Slave Address Sub Address(n) A C K Data(n+x) Data(n+1) Data(n) A C K A C K A C K A C K P A C K Figure 17. Data transfer sequence at the I2C-bus mode 0 0 1 0 0 CAD1 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins) Figure 18. The first byte * * * A4 A3 A2 A1 A0 D2 D1 D0 (*: Don’t care) Figure 19. The second byte D7 D6 D5 D4 D3 Figure 20. Byte structure after the second byte MS0397-E-00 2005/06 - 29 - ASAHI KASEI [AK4626A] SDA SCL S P start condition stop condition Figure 21. START and STOP conditions DATA OUTPUT BY MASTER not acknowledge DATA OUTPUT BY SLAVE(AK4529) acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 22. Acknowledge on the I2C-bus SDA SCL data line stable; data valid change of data allowed Figure 23. Bit transfer on the I2C-bus MS0397-E-00 2005/06 - 30 - ASAHI KASEI [AK4626A] Mapping of Program Registers Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH Register Name Control 1 Control 2 LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control De-emphasis ATT speed & Reset Control Zero detect D7 0 0 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0 D6 0 DFS1 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0 D5 TDM1 LOOP1 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 DEMA1 D4 TDM0 LOOP0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 DEMA0 D3 DIF1 SDOS ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 DEMB1 D2 DIF0 DFS0 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 DEMB0 D1 0 ACKS ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 DEMC1 D0 SMUTE 0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 DEMC0 0 0 ATS1 ATS0 0 0 0 RSTN OVFE DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN Note: For addresses from 0BH to 1FH, data is not written. When PDN goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset and DZF1-2 pins go to “H”, but registers are not initialized to their default values. SMUTE, DFS0, SDOS and TDM0 are ORed with pins. MS0397-E-00 2005/06 - 31 - ASAHI KASEI [AK4626A] Register Definitions Addr 00H Register Name Control 1 Default D7 0 0 D6 0 0 D5 TDM1 0 D4 TDM0 0 D3 DIF1 1 D2 DIF0 0 D1 0 0 D0 SMUTE 0 SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted Register bit of SMUTE is ORed with the SMUTE pin if P/S = “L”. DIF1-0: Audio Data Interface Modes (see Table 8, 9, 10) Initial: “10”, mode 2 TDM1-0: TDM Format Select (see Table 8, 9, 10) Mode 0 1 2 TDM1 TDM0 0 0 0 1 1 1 SDTI 1-3 1 1-2 Sampling Speed Normal, Double, Four Times Speed Normal Speed Normal, Double Speed Register bit of TDM0 is ORed with the TDM0 pin if P/S = “L”. TDM0 pin should be “L” if the register control is used. MS0397-E-00 2005/06 - 32 - ASAHI KASEI Addr 01H Register Name Control 2 Default [AK4626A] D7 0 0 D6 DFS1 0 D5 LOOP1 0 D4 LOOP0 0 D3 SDOS 0 D2 DFS0 0 D1 ACKS 0 D0 0 0 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode. DFS1-0: Sampling speed mode (see Table 1.) Register bit of DFS0 is ORed with DFS0 pin if P/S = “L”. The setting of DFS is ignored at ACKS bit “1”. SDOS: SDTO source select 0: ADC 1: DAUX Register bit of SDOS is ORed with SDOS pin if P/S = “L”. SDOS should be set to “0” at TDM bit “1”. In the case of PWADN=”0” and PWDAN=”0”, the setting of SDOS becomes invalid. And ADC is selected. The output of SDTO becomes “L” at PWADN=”0”. LOOP1-0: Loopback mode enable 00: Normal (No loop back) 01: LIN → LOUT1, LOUT2, LOUT3 RIN → ROUT1, ROUT2, ROUT3 The digital ADC output (DAUX input if SDOS = “1”) is connected to the digital DAC input. In this mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO at loopback mode becomes mode 2 at mode 0, and mode 3 at mode 1, respectively. 10: SDTI1(L) → SDTI2(L), SDTI3(L) SDTI1(R) → SDTI2(R), SDTI3(R) In this mode the input DAC data to SDTI2-3 is ignored. 11: N/A LOOP1-0 should be set to “00” at TDM bit “1”. In the case of PWADN=”0” and PWDAN=”0”, the setting of LOOP1-0 becomes invalid. And ADC is selected. And it becomes the normal operation (No loop back). MS0397-E-00 2005/06 - 33 - ASAHI KASEI Addr 02H 03H 04H 05H 06H 07H Register Name LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control Default [AK4626A] D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0 D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0 D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 0 D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 0 D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 0 D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 0 D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 0 D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 0 ATT7-0: Attenuation Level (see Table 13.) Addr 08H Register Name De-emphasis Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0 0 0 0 1 0 1 0 1 DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (see Table 7.) Initial: “01”, OFF DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (see Table 7.) Initial: “01”, OFF DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (see Table 7.) Initial: “01”, OFF MS0397-E-00 2005/06 - 34 - ASAHI KASEI Addr 09H [AK4626A] Register Name ATT speed & Reset Control Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 ATS1 ATS0 0 0 0 RSTN 0 0 0 0 0 0 0 1 RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation ATS1-0: Digital attenuator transition time setting (see Table 14.) Initial: “00”, mode 0 Addr 0AH Register Name Zero detect Default D7 D6 D5 D4 D3 D2 D1 D0 OVFE DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN 0 0 1 1 1 1 1 1 PWDAN: Power-down control of DAC1-3 0: Power-down 1: Normal operation PWADN: Power-down control of ADC 0: Power-down 1: Normal operation PWVRN: Power-down control of reference voltage 0: Power-down 1: Normal operation DZFM3-0: Zero detect mode select (see Table 11.) Initial: “0111”, disable OVFE: Overflow detection enable 0: Disable, pin#33 becomes DZF2 pin. 1: Enable, pin#33 becomes OVF pin. MS0397-E-00 2005/06 - 35 - ASAHI KASEI [AK4626A] SYSTEM DESIGN Figure 24 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: TVDD=5V, 3-wire serial control mode, CAD1-0 = “00” Analog 5V + uP 10u + 2.2u 0.1u RIN 32 3 SMUTE LIN 31 4 BICK NC 30 TST5 29 MUTE 7 SDTI2 LOUT1 27 MUTE 8 SDTI3 ROUT2 26 MUTE 9 SDTO LOUT2 25 MUTE 10 DAUX ROUT3 24 MUTE 11 DFS0 LOUT3 23 MUTE + 21 TST3 20 CAD0 19 CAD1 18 TST2 17 PDN 16 DVSS 15 DVDD 14 TVDD 13 DZFE AK4626A 22 TST4 ROUT1 28 6 SDTI1 12 TST1 (MPEG/ AC3) DZF2 33 2 I2C 5 LRCK Audio DSP VCOM 34 AVDD 36 AVSS 37 DZF1 38 P/S 40 MCLK 39 CSN 41 1 SDOS VREFH 35 (DIR) CCLK 42 Digital Audio Source CDTI 43 TDM0 44 0.1u 0.1u 10u 5 Power-down control Digital Ground Analog Ground Figure 24. Typical Connection Diagram MS0397-E-00 2005/06 - 36 - ASAHI KASEI [AK4626A] 3 SMUTE 4 BICK 5 LRCK AK4626A RIN 32 LIN 31 NC 30 TST5 29 21 TST3 20 CAD0 LOUT3 23 19 CAD1 ROUT3 24 11 DFS0 18 TST2 LOUT2 25 10 DAUX 17 PDN ROUT2 26 9 SDTO 15 DVDD LOUT1 27 8 SDTI3 14 TVDD 7 SDTI2 13 DZFE ROUT1 28 12 TST1 6 SDTI1 16 DVSS Controller VCOM 34 AVDD 36 VREFH 35 DZF1 38 AVSS 37 P/S 40 MCLK 39 DZF2/OVF 33 22 TST4 System DIF0/CSN 41 1 SDOS 2 I2C DIF1/SCL/CCLK 42 TDM0 44 Analog Ground LOOP0/SDA/CDTI 43 Digital Ground Figure 25. Ground Layout Note: AVSS and DVSS must be connected to the same analog ground plane. 1. Grounding and Power Supply Decoupling The AK4626A requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4626A must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4626A as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4626A. 3. Analog Inputs ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and nominally 0.62 x VREFH Vpp (typ)@fs=48kHz. The ADC output data format 2’s compliment. The DC offset is removed by the internal HPF. The AK4626A samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4626A includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. MS0397-E-00 2005/06 - 37 - ASAHI KASEI [AK4626A] 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. Peripheral I/F Example The AK4626A can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for output buffer (TVDD) of the AK4626A should be 3.3V when the peripheral devices operate at a nominal 3.3V supply. Figure 26 shows an example with the mixed system of 3.3V and 5V. 3.3V Analog 5V for input 3.3V Digital Audio signal PLL I/F DSP AK4112B 5V Analog 3.3V for output 5V Digital uP & Others Analog Digital Control signal AK4626A Figure 26. Power supply connection example MS0397-E-00 2005/06 - 38 - ASAHI KASEI [AK4626A] PACKAGE 44pin LQFP (Unit: mm) 1.70max 12.80±0.30 0∼0.2 10.00 23 33 0.80 12.80±0.30 22 10.00 34 12 44 1 11 0.37±0.10 0.17±0.05 0°∼10° 0.60±0.20 0.15 Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0397-E-00 2005/06 - 39 - ASAHI KASEI [AK4626A] MARKING AK4626AVQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4626AVQ 4) Asahi Kasei Logo Revision History Date (YY/MM/DD) 05/06/03 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0397-E-00 2005/06 - 40 -