TI1 ADC10D040 Adc10d040 dual 10-bit, 40 msps, 267 mw a/d converter Datasheet

ADC10D040
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SNAS149G – OCT 2001 – REVISED MARCH 2013
ADC10D040 Dual 10-Bit, 40 MSPS, 267 mW A/D Converter
Check for Samples: ADC10D040
FEATURES
DESCRIPTION
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•
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The ADC10D040 is a dual low power, high
performance CMOS analog-to-digital converter that
digitizes signals to 10 bits resolution at sampling
rates up to 45 MSPS while consuming a typical 267
mW from a single 3.3V supply. No missing codes is
specified over the full operating temperature range.
The unique two stage architecture achieves 9.4
Effective Bits over the entire Nyquist band at 40 MHz
sample rate. An output formatting choice of offset
binary or 2's complement coding and a choice of two
gain settings eases the interface to many systems.
Also allowing great flexibility of use is a selectable 10bit multiplexed or 20-bit parallel output mode. An
offset correction feature minimizes the offset error.
1
2
•
•
•
•
Internal Sample-and-Hold
Internal Reference Capability
Dual Gain Settings
Offset Correction
Selectable Offset Binary or 2's Complement
Output
Multiplexed or Parallel Output Bus
Single +3.0V to 3.6V Operation
Power Down and Standby Modes
3V TTL Logic Input/Output Compatible
APPLICATIONS
•
•
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Digital Video
CCD Imaging
Portable Instrumentation
Communications
Medical Imaging
Ultrasound
KEY SPECIFICATIONS
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•
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•
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•
Resolution: 10 Bits
Conversion Rate: 40 MSPS
ENOB: 9.4 Bits (typ)
DNL: 0.35 LSB (typ)
Conversion Latency Parallel Outputs: 2.5
Clock Cycles
– Multiplexed Outputs, I Data Bus: 2.5 Clock
Cycles
– Multiplexed Outputs, Q Data Bus: 3 Clock
Cycles
PSRR: 90 dB
Power Consumption—Normal Operation: 267
mW (typ)
– Power Down Mode: < 1 mW (typ)
– Fast Recovery Standby Mode: 30 mW (typ)
To ease interfacing to most low voltage systems, the
digital output power pins of the ADC10D040 can be
tied to a separate supply voltage of 1.5V to 3.6V,
making the outputs compatible with other low voltage
systems. When not converting, power consumption
can be reduced by pulling the PD (Power Down) pin
high, placing the converter into a low power state
where it typically consumes less than 1 mW and from
which recovery is less than 1 ms. Bringing the STBY
(Standby) pin high places the converter into a
standby mode where power consumption is about 30
mW and from which recovery is 800 ns.
The ADC10D040's speed, resolution and single
supply operation make it well suited for a variety of
applications,
including
high
speed
portable
applications.
Operating over the industrial (−40° ≤ TA ≤ +85°C)
temperature range, the ADC10D040 is available in a
48-pin TQFP. An evaluation board is available to
ease the design effort.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
ADC10D040
SNAS149G – OCT 2001 – REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Connection Diagram
Figure 1. TOP VIEW
Block Diagram
2
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PIN DESCRIPTIONS and EQUIVALENT CIRCUITS
Pin No.
Symbol
Equivalent Circuit
Description
48
47
I+
I−
Analog inputs to “I” ADC. With VREF = 1.4V, conversion range is
1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V with GAIN pin
high.
37
38
Q+
Q−
Analog inputs to “Q” ADC. With VREF = 1.4V, conversion range is
1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V with GAIN pin
high.
VREF
Analog Reference Voltage input. The voltage at this pin should be in
the range of 0.6V to 1.6V. With 1.4V at this pin and the GAIN pin
low, the full scale differential inputs are 1.4 VP-P. With 1.4V at this pin
and the GAIN pin high, the full scale differential inputs are 2.8 VP-P.
This pin should be bypassed with a minimum 1 µF capacitor.
45
VCMO
This is an analog output which can be used as a reference source
and/or to set the common mode voltage of the input. It should be
bypassed with a minimum of 1 µF low ESR capacitor in parallel with
a 0.1 µF capacitor. This pin has a nominal output voltage of 1.5V
and has a 1 mA output source capability.
43
VRP
Top of the reference ladder. Do not drive this pin. Bypass this pin
with a 10 µF low ESR capacitor and a 0.1 µF capacitor.
44
VRN
Bottom of the reference ladder. Do not drive this pin. Bypass this
pin with a 10 µF low ESR capacitor and a 0.1 µF capacitor.
1
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PIN DESCRIPTIONS and EQUIVALENT CIRCUITS (continued)
Pin No.
Equivalent Circuit
Description
CLK
Digital clock input for both converters. The analog inputs are
sampled on the falling edge of this clock input.
OS
Output Bus Select. With this pin at a logic high, both the “I” and the
“Q” data are present on their respective 10-bit output buses (Parallel
mode of operation). When this pin is at a logic low, the “I” and “Q”
data are multiplexed onto the “I” output bus and the “Q” output lines
all remain at a logic low (multiplexed mode).
31
OC
Offset Correct pin. A low-to-high transition on this pin initiates an
independent offset correction sequence for each converter, which
takes 34 clock cycles to complete. During this time 32 conversions
are taken and averaged. The result is subtracted from subsequent
conversions. Each input pair should have 0V differential value during
this entire 34 clock period.
32
OF
Output Format pin. When this pin is LOW the output format is Offset
Binary. When this pin is HIGH the output format is 2's complement.
This pin may be changed asynchronously, but this will result in
errors for one or two conversions.
STBY
Standby pin. The device operates normally with a logic low on this
and the PD (Power Down) pin. With this pin at a logic high and the
PD pin at a logic low, the device is in the standby mode where it
consumes just 30 mW of power. It takes just 800 ns to come out of
this mode after the STBY pin is brought low.
35
PD
Power Down pin that, when high, puts the converter into the Power
Down mode where it consumes just 1 mW of power. It takes less
than 1 ms to recover from this mode after the PD pin is brought low.
If both the STBY and PD pins are high simultaneously, the PD pin
dominates.
36
GAIN
This pin sets the internal signal gain at the inputs to the ADCs. With
this pin low the full scale differential input peak-to-peak signal is
equal to VREF. With this pin high the full scale differential input peakto-peak signal is equal to 2 x VREF.
I0–I9 and Q0–Q9
3V TTL/CMOS-compatible Digital Output pins that provide the
conversion results of the I and Q inputs. I0 and Q0 are the LSBs, I9
and Q9 are the MSBs. Valid data is present just after the rising edge
of the CLK input in the Parallel mode. In the multiplex mode, Ichannel data is valid on I0 through I9 when the I/Q output is high
and the Q-channel data is valid on I0 through I9 when the I/Q output
is low.
28
I/Q
Output data valid signal. In the multiplexed mode, this pin transitions
from low to high when the data bus transitions from Q-data to I-data,
and from high to low when the data bus transitions from I-data to Qdata. In the Parallel mode, this pin transitions from low to high as the
output data changes.
40, 41
VA
Positive analog supply pin. This pin should be connected to a quiet
voltage source of +3.0V to +3.6V. VA and VD should have a common
supply and be separately bypassed with 10 µF to 50 µF capacitors in
parallel with 0.1 µF capacitors.
4
VD
Digital supply pin. This pin should be connected to a quiet voltage
source of +3.0V to +3.6V. VA and VD should have a common supply
and be separately bypassed with 10 µF to 50 µF capacitors in
parallel with 0.1 µF capacitors.
6, 30
VDR
Digital output driver supply pins. These pins should be connected to
a voltage source of +1.5V to VD and be bypassed with 10 µF to 50
µF capacitors in parallel with 0.1 µF capacitors.
3, 39, 42,
46
AGND
The ground return for the analog supply. AGND and DGND should
be connected together close to the ADC10D040 package.
5
DGND
The ground return for the digital supply. AGND and DGND should be
connected together close to the ADC10D040 package.
7, 29
DR GND
33
2
34
8 thru 27
4
Symbol
The ground return of the digital output drivers.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Positive Supply Voltages
3.8V
−0.3V to (VA or VD +0.3V)
Voltage on Any Pin
Input Current at Any Pin (4)
Package Input Current
±25 mA
(4)
±50 mA
Package Dissipation at TA = 25°C
See
ESD Susceptibility (6)
Human Body Model
2500V
Machine Model
250V
Soldering Temperature, Infrared, 10 sec.
235°C
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
(5)
(6)
(5)
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 25 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax - TA )/θJA. In the 48-pin TQFP, θJA is 76°C/W, so PDMAX = 1,645 mW at 25°C and 855 mW at the maximum
operating ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 307
mW (267 mW quiescent power + 40 mW due to 1 LVTTL load on each digital output). The values for maximum power dissipation listed
above will be reached only when the ADC10D040 is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Operating Ratings (1) (2)
−40°C ≤ TA ≤ +85°C
Operating Temperature Range
VA, VD Supply Voltage
+3.0V to +3.6V
VDR Supply Voltage
VIN Differential Voltage Range
VCM Input Common Mode Range
+1.5V to VD
GAIN = Low
±VREF
GAIN = Low
VREF/4 to (VA–VREF/4)
GAIN = High
VREF/2 to (VA–VREF/2)
VREF Voltage Range
0.6V to 1.8V
−0.3V to (VA +0.3V)
Digital Input Pins Voltage Range
(1)
(2)
±VREF/2
GAIN = High
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
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Converter Electrical Characteristics
The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5 VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN
(a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
Symbol
Parameter
Limits (3)
Units
(Limits)
±0.65
±1.9
LSB (max)
±0.35
+1.2
−1.0
LSB (max)
LSB (min)
10
Bits
Typical (2)
Conditions
STATIC CONVERTER CHARACTERISTICS
INL
Integral Non-Linearity
DNL
Differential Non-Linearity
Resolution with No Missing Codes
VOFF
GE
Without Offset Correction
−3.3
+7
−12
LSB (max)
LSB (min)
With Offset Correction
+0.4
+1.5
−0.5
LSB (max)
LSB (min)
−4
+5
−12
%FS (max)
%FS (min)
9.1
Bits (min)
Offset Error
Gain Error
DYNAMIC CONVERTER CHARACTERISTICS
ENOB
SINAD
SNR
THD
HS2
HS3
SFDR
IMD
FPBW
(1)
(2)
(3)
6
fIN = 4.43 MHz, VIN = FSR −0.1 dB
9.5
fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C
9.5
fIN = 19.7 MHz, VIN = FSR −0.1 dB
9.4
fIN = 4.43 MHz, VIN = FSR −0.1 dB
59
fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C
59
fIN = 19.7 MHz, VIN = FSR −0.1 dB
58
dB
fIN = 4.43 MHz, VIN = FSR −0.1 dB
60
dB
fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C
60
fIN = 19.7 MHz, VIN = FSR −0.1 dB
59
dB
fIN = 4.43 MHz, VIN = FSR −0.1 dB
−70
dB
fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C
−69
fIN = 19.7 MHz, VIN = FSR −0.1 dB
−67
dB
fIN = 4.43 MHz, VIN = FSR −0.1 dB
−86
dB
fIN = 10.4 MHz, VIN = FSR −0.1 dB
−83
dB
fIN = 19.7 MHz, VIN = FSR −0.1 dB
−81
dB
fIN = 4.43 MHz, VIN = FSR −0.1 dB
−73
dB
fIN = 10.4 MHz, VIN = FSR −0.1 dB
−73
dB
fIN = 19.7 MHz, VIN = FSR −0.1 dB
−72
dB
fIN = 4.43 MHz, VIN = FSR −0.1 dB
72
dB
fIN = 10.4 MHz, VIN = FSR −0.1 dB
72
dB
fIN = 19.7 MHz, VIN = FSR −0.1 dB
70
dB
Intermodulation Distortion
fIN1 < 8.5 MHz, VIN = FSR −6.1 dB
fIN2 < 9.5 MHz, VIN = FSR −6.1 dB
71
dB
Overrange Output Code
(VIN+−VIN−) > 1.5V
Underrange Output Code
(VIN+−VIN−) < −1.5V
Effective Number of Bits
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
Second Harmonic
Third Harmonic
Spurious Free Dynamic Range
Full Power Bandwidth
Bits
Bits
dB
56.3
57.3
−61
dB (min)
dB (min)
dB (min)
1023
0
140
MHz
The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables.
Typical figures are at TJ = 25°C, and represent most likely parametric norms.
Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is specified only at VREF = 1.4V and a clock duty
cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are
performed and limits specified with clock low and high levels of 0.3V and VD−0.3V, respectively.
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5 VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN
(a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
Symbol
Parameter
Conditions
Typical (2)
Limits (3)
Units
(Limits)
INTER-CHANNEL CHARACTERISTICS
Crosstalk
1 MHz input to tested channel, 10.3 MHz input to
other channel
−72
dB
Channel - Channel Aperture Delay
Match
fIN = 8 MHz
8.5
ps
0.1
%FS
Gain Pin = AGND
1.4
VP-P
Gain Pin = VA
Channel - Channel Gain Matching
REFERENCE AND ANALOG CHARACTERISTICS
VIN
Analog Differential Input Range
CIN
Analog Input Capacitance (each
input)
RIN
2.8
VP-P
Clock High
6
pF
Clock Low
3
pF
Analog Differential Input Resistance
13.5
kΩ
VREF
Reference Voltage
1.4
IREF
Reference Input Current
<1
VCMO
Common Mode Voltage Output
TC
VCMO
Common Mode Voltage Temperature
Coefficient
1 mA load to ground (sourcing current)
1.5
0.6
V (min)
1.6
V (max)
µA
1.35
V (min)
1.6
V (max)
30
ppm/°C
DIGITAL INPUT CHARACTERISTICS
VIH
Logical “1” Input Voltage
VD = +3.0V
2.0
V (min)
VIL
Logical “0” Input Voltage
VD = +3.6V
0.5
V (max)
IIH
Logical “1” Input Current
VIH = VD
<1
µA
IIL
Logical “0” Input Current
VIL = DGND
>−1
µA
DIGITAL OUTPUT CHARACTERISTICS
VOH
Logical “1” Output Voltage
VDR = +2.5V, IOUT = −0.5 mA
VOL
Logical “0” Output Voltage
VDR = +2.5V, IOUT = 1.6 mA
+ISC
−ISC
Output Short Circuit Source Current
Output Short Circuit Sink Current
VOUT = 0V
VOUT = VDR
VDR
−0.2V
V (min)
0.4
V (max)
−4.7
mA
Multiplexed Mode
−9
mA
Parallel Mode
4.7
mA
9
mA
Parallel Mode
Multiplexed Mode
POWER SUPPLY CHARACTERISTICS
IA
ID
IDR
(4)
Analog Supply Current
Digital Supply Current
Digital Output Driver Supply
Current (4)
PD = LOW, STBY = LOW, d.c. input
70
PD = LOW, STBY = HIGH
10
PD = HIGH, STBY = LOW or HIGH
0.1
PD = LOW, STBY = LOW, d.c. input
9
80
mA (max)
mA
mA
10
mA (max)
PD = LOW, STBY = HIGH
0.1
mA
PD = HIGH, STBY = LOW or HIGH
0.1
mA
PD = STBY = LOW, dc input
1.9
2.5
mA (max)
IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output
pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR (CO x fO + C1 x f1
+ ... + C9 x f9) where VDR is the output driver power supply voltage, Cn is the total capacitance on the output pin, and fn is the average
frequency at which that pin is toggling.
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5 VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN
(a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
Symbol
PD
Typical (2)
Limits (3)
Units
(Limits)
PD = LOW, STBY = LOW, d.c. input
267
305
mW (max)
PD = LOW, STBY = LOW, 1 MHz Input
270
mW
PD = LOW, STBY = HIGH
30
mW
PD = HIGH, STBY = LOW or HIGH
0.6
mW
90
dB
52
dB
Parameter
Conditions
Power Consumption
PSRR1
Power Supply Rejection Ratio
Change in Full Scale with 3.0V to 3.6V Supply
Change
PSRR2
Power Supply Rejection Ratio
Rejection at output with 10.3 MHz, 250 mVP-P
Riding on VA and VD
AC Electrical Characteristics
OS = Low (Multiplexed Mode)
The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c.
coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
Symbol
Typical (2)
Limits (3)
Units
(Limits)
40
MHz (min)
45
55
% (min)
% (max)
I Data
2.5
Clock
Cycles
Q Data
3.0
Clock
Cycles
10
ns (min)
19
ns (max)
Parameter
Conditions
fCLK1
Maximum Clock Frequency
45
fCLK2
Minimum Clock Frequency
20
Duty Cycle
Pipeline Delay (Latency)
50
MHz
tr, tf
Output Rise and Fall Times
tOC
Offset Correction Pulse Width
tOD
Output Delay from CLK Edge to Data Valid
13
tDIQ
I/Q Output Delay
13
ns
tSKEW
I/Q to Data Skew
±200
ps
tAD
Sampling (Aperture) Delay
2.2
ns
tAJ
Aperture Jitter
<10
ps (rms)
tVALID
Data Valid Time
7.5
ns
50
ns
Overrange Recovery Time
5
Differential VIN step from
1.5V to 0V
ns
(1)
The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables.
(2)
(3)
Typical figures are at TJ = 25°C, and represent most likely parametric norms.
Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is specified only at VREF = 1.4V and a clock duty
cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are
performed and limits specified with clock low and high levels of 0.3V and VD−0.3V, respectively.
8
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AC Electrical Characteristics
OS = Low (Multiplexed Mode) (continued)
The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c.
coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
Symbol
Parameter
Typical (2)
Conditions
Limits (3)
Units
(Limits)
tWUPD
PD Low to 1/2 LSB Accurate Conversion (Wake-Up Time)
<1
ms
tWUSB
STBY Low to 1/2 LSB Accurate Conversion (Wake-Up Time)
800
ns
AC Electrical Characteristics
OS = High (Parallel Mode)
The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = +3.3V, VIN
(a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.
Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1)
Symbol
Parameter
Conditions
Typical (2)
Limits (3)
Units
(Limits)
40
MHz (min)
45
55
% (min)
% (max)
2.5
Clock Cycles
fCLK1
Maximum Clock Frequency
45
fCLK2
Minimum Clock Frequency
20
Duty Cycle
50
Pipeline Delay (Latency)
MHz
tr, tf
Output Rise and Fall Times
tOC
OC Pulse Width
tOD
Output Delay from CLK Edge to Data
Valid
16
tDIQ
I/Q Output Delay
13
tAD
Sampling (Aperture) Delay
2.2
ns
tAJ
Aperture Jitter
<10
ps (rms)
tVALID
Data Valid Time
16
ns
Overrange Recovery Time
9
Differential VIN step from 1.5V to 0V
ns
10
ns
22
ns (max)
ns
50
ns
tWUPD
PD Low to 1/2 LSB Accurate Conversion
(Wake-Up Time)
<1
ms
tWUSB
STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
800
ns
(1)
The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables.
(2)
(3)
Typical figures are at TJ = 25°C, and represent most likely parametric norms.
Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is specified only at VREF = 1.4V and a clock duty
cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are
performed and limits specified with clock low and high levels of 0.3V and VD−0.3V, respectively.
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Timing Diagrams
Figure 2. ADC10D040 Timing Diagram for Multiplexed Mode
Figure 3. ADC10D040 Timing Diagram for Parallel Mode
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Figure 4. AC Test Circuit
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after
the clock goes low.
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input
noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is high to the total time of one clock
period.
CROSSTALK is coupling of energy from one channel into the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 40 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76)/6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is the frequency at which the magnitude of the reconstructed output
fundamental drops 3 dB below its 1 MHz value.
GAIN ERROR is the difference between the ideal and actual differences between the input levels at which the
first and last code transitions occur. That is, how far this difference is from Full Scale.
INTEGRAL NON LINEARITY (INL) is a measure of the maximum deviation of each individual code from a line
drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above
the last code transition). The deviation of any given code from this straight line is measured from the center of
that code value. The end point test method is used. Measured at 40 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of spectral components that are not present in the
input as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as
the ratio of the power in the second and third order intermodulation products to the total power in one of the
original frequencies. IMD is usually expressed in dB.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value of weight of all bits. This value is
m * VREF/2n
(1)
where “m” is the reference scale factor and “n” is the ADC resolution, which is 10 in the case of the ADC10D040.
The value of “m” is determined by the logic level at the gain pin and has a value of 1 when the gain pin is at a
logic low and a value of 2 when the gain pin is at a logic high.
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
OFFSET ERROR is a measure of how far the mid-scale transition point is from the ideal zero voltage input.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the
output pins.
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OVERRANGE RECOVERY TIME is the time required after the differential input voltages goes from 1.5V to 0V
for the converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output driver stage. New data is available at every clock cycle, but the data output lags the
input by the Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) can be one of two specifications. PSRR1 (DC PSRR) is the ratio
of the change in full scale gain error that results from a power supply voltage change from 3.0V to 3.6V. PSRR2
(AC PSRR) is measured with a 10 MHz, 250 mVP-P signal riding upon the power supply and is the ratio of the
signal amplitude on the power supply pins to the amplitude of that frequency at the output. PSRR is expressed in
dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the fundamental signal at the
output to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the fundamental signal at the output to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
fundamental signal at the output and the peak spurious signal, where a spurious signal is any signal present in
the output spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
(2)
where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the
first 9 harmonic frequencies in the output spectrum.
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Typical Performance Characteristics
VA = VD = 3.3V, VDR = 2.5V, fCLK = 40 MHz, fIN = 10.4 MHz, unless otherwise specified
Typical INL
INL vs. VA
Figure 5.
Figure 6.
INL vs. VREF
INL vs. fCLK
Figure 7.
Figure 8.
INL vs. Clock Duty Cycle
INL vs. Temperature
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
VA = VD = 3.3V, VDR = 2.5V, fCLK = 40 MHz, fIN = 10.4 MHz, unless otherwise specified
14
Typical DNL
DNL vs. VA
Figure 11.
Figure 12.
DNL vs. VREF
DNL vs. fCLK
Figure 13.
Figure 14.
SNR, SINAD & SFDR vs. VA
DISTORTION vs. VA
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
VA = VD = 3.3V, VDR = 2.5V, fCLK = 40 MHz, fIN = 10.4 MHz, unless otherwise specified
DNL vs. Clock Duty Cycle
DNL vs. Temperature
Figure 17.
Figure 18.
SNR, SINAD & SFDR vs. VREF
DISTORTION vs. VREF
Figure 19.
Figure 20.
SNR, SINAD & SFDR vs. fCLK
DISTORTION vs. fCLK
Figure 21.
Figure 22.
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Typical Performance Characteristics (continued)
VA = VD = 3.3V, VDR = 2.5V, fCLK = 40 MHz, fIN = 10.4 MHz, unless otherwise specified
16
SNR, SINAD & SFDR vs. fIN
DISTORTION vs. fIN
Figure 23.
Figure 24.
SNR, SINAD & SFDR vs. Temperature
DISTORTION vs. Temperature
Figure 25.
Figure 26.
CROSSTALK vs. fIN
CROSSTALK vs. Temperature
Figure 27.
Figure 28.
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Typical Performance Characteristics (continued)
VA = VD = 3.3V, VDR = 2.5V, fCLK = 40 MHz, fIN = 10.4 MHz, unless otherwise specified
Total Power vs. TEMP
Spectral Response at fIN = 10.4 MHz
Figure 29.
Figure 30.
IMD Response fIN = 8.5 MHz, 9.5 MHz
Figure 31.
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FUNCTIONAL DESCRIPTION
Using a subranging architecture, the ADC10D040 achieves 9.4 effective bits over the entire Nyquist band at 40
MSPS while consuming just 267 mW. The use of an internal sample-and-hold amplifier (SHA) not only enables
this sustained dynamic performance, but also lowers the converter's input capacitance and reduces the number
of external components required.
Analog signals at the “I” and “Q” inputs that are within the voltage range set by VREF and the GAIN pin are
digitized to ten bits at up to 45 MSPS. VREF has a range of 0.6V to 1.6V, providing a differential peak-to-peak
input range of 0.6 VP-P to 1.6 VP-P with the GAIN pin at a logic low, or a differential input range of 1.2 VP-P to 3.2
VP-P with the GAIN pin at a logic high. Differential input voltages less than −VREF/2 with the GAIN pin low, or less
than −VREF with the GAIN pin high will cause the output word to indicate a negative full scale. Differential input
voltages greater than VREF/2 with the GAIN pin low, or greater than VREF with the GAIN pin high, will cause the
output word to indicate a positive full scale.
Both “I” and “Q” channels are sampled simultaneously on the falling edge of the clock input, while the timing of
the data output depends upon the mode of operation.
In the parallel mode, the “I” and “Q” output busses contain the conversion result for their respective inputs. The
“I” and “Q” channel data are present and valid at the data output pins tOD after the rising edge of the input clock.
In the multiplexed mode, “I” channel data is available at the digital outputs tOD after the rise of the clock edge,
while the “Q” channel data is available at the I0 through I9 digital outputs tOD after the fall of the clock. However,
a delayed I/Q output signal should be used to latch the output for best, most consistent results.
Data latency in the parallel mode is 2.5 clock cycles. In the multiplexed mode data latency is 2.5 clock cycles for
the “I” channel and 3.0 clock cycles for the “Q” channel. The ADC10D040 will convert as long as the clock signal
is present and the PD and STBY pins are low.
Throughout this discussion,VCM refers to the Common Mode input voltage of the ADC10D040 while VCMO refers
to its Common Mode output voltage.
Applications Information
THE ANALOG SIGNAL INPUTS
Each of the analog inputs of the ADC10D040 consists of a switch (transmission gate) followed by a switched
capacitor amplifier. The capacitance seen at each input pin changes with the clock level, appearing as about 2
pF when the clock is low, and about 5 pF when the clock is high. This switching action causes analog input
current spikes that work with the input source impedance to produce voltage spikes.
The LMH6702 and the CLC428 dual op-amp have been found to be a good amplifiers to drive the ADC10D040
because of their wide bandwidth and low distortion. They also have good Differential Gain and Differential Phase
performance.
Care should be taken to avoid driving the input beyond the supply rails, even momentarily, as during power-up.
The ADC10D040 is designed for differential input signals for best performance. With a 1.4V reference and the
GAIN pin at a logic low, differential input signals up to 1.4 VP-P are digitized. See Figure 32. For differential
signals, the input common mode is expected to be about 1.5V, but the inputs are not sensitive to the commonmode voltage and can be anywhere within the supply rails (ground to VA) with little or no performance
degradation, as long as the signal swing at the individual input pins is no more than 300 mV beyond the supply
rails.
Single-ended drive is not recommended as it can result in degraded dynamic performance and faulty operation. If
single-ended input drive is absolutely required, it is recommended that a sample rate above 30 MSPS be used. If
the desired sample rate is lower than this, operate the ADC10D040 at a multiple of the desired rate and decimate
the output (use every "nth" sample).
For single-ended drive, operate the ADC10D040 with the GAIN pin at a logic low, connect one pin of the input
pair to 1.5V (VCM) through a resistor of 1k to 10 k Ohms, bypassing this input pin to ground with a 1 µF capacitor.
Drive the other input pin of the input pair with 1.0 VP-P centered around 1.5V.
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Because of the larger signal swing at one input for single-ended operation, distortion performance will not be as
good as with a differential input signal. Alternatively, single-ended to differential conversion with a transformer
provides a quick, easy solution for those applications not requiring response to d.c. and low frequencies. See
Figure 33. The 36Ω resistors and 56 pF capacitor values are chosen to provide a cutoff frequency near the clock
frequency to compensate for the effects of input sampling. A lower time constant should be used for
undersampling applications.
The signal swing should not cause any pin to experience a swing more than 300 mV beyond the supply rails.
Figure 32. The ADC10D040 is designed for use with differential signals of 1.4 VP-P with a common mode
voltage of 1.5V.
REFERENCE INPUTS
The VRP and VRN pins should each be bypassed with a 5 µF (or larger) tantalum or electrolytic capacitor and a
0.1 µF ceramic capacitor. Use these pins only for bypassing. DO NOT connect anything else to these pins.
Figure 34 shows a simple reference biasing scheme with minimal components. While this circuit will suffice for
many applications, the value of the reference voltage will depend upon the supply voltage.
The circuit of Figure 35 is an improvement over the circuit of Figure 34 because the reference voltage is
independent of supply voltage. This reduces problems of reference voltage variability. The reference voltage at
the VREF pin should be bypassed to AGND with a 5 µF (or larger) tantalum or electrolytic capacitor and a 0.1 µF
ceramic capacitor.
The circuit of Figure 36 may be used if it is desired to obtain a precise reference voltage not available with a
fixed reference source. The 604Ω and 1.40k resistors can be replaced with a potentiometer, if desired.
Figure 33. Use of an input transformer for single-ended to differential conversion can simplify circuit
design for single-ended signals.
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Figure 34. Simple Reference Biasing
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Figure 35. Improved Low Component Count Reference Biasing
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Figure 36. Setting An Accurate Reference Voltage
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Figure 37. The VCMO output pin may be used as an internal reference source if its output is not loaded
excessively.
The VCMO output can be used as the ADC reference source as long as care is taken to prevent excessive loading
of this pin. However, the VCMO output was not designed to be a precision reference and has move variability than
does a precision reference. Refer to VCMO, Common Mode Voltage Output, in the Electrical Characteristics table.
Since the reference input of the ADC10D040 is buffered, there is virtually no loading on the VCMO output by the
VREF pin. While the ADC10D040 will work with a 1.5V reference voltage, it is fully specified for a 1.4V reference.
To use the VCMO for a reference voltage at 1.4V, the 1.5V VCMO output needs to be divided down. The divider
resistor values need to be carefully chosen to prevent excessive VCMO loading. See Figure 37. While the average
temperature coefficient of VCMO is 30 ppm/°C, that temperature coefficient can be broken down to a typical 70
ppm/°C between −40°C and +25°C and a typical −11 ppm/°C between +25°C and +85°C.
Reference Voltage
The reference voltage should be within the range specified in the Operating Ratings table (0.6V to 1.6V). A
reference voltage that is too low could result in a noise performance that is less than desired because the
quantization level falls below other noise sources. On the other hand, a reference voltage that is too high means
that an input signal that produces a full scale output uses such a large input range that the input stage is less
linear, resulting in a degradation of distortion performance. Also, for large reference voltages, the internal ladder
buffer runs out of head-room, leading to a reduction of gain in that buffer and causing gain error degradation.
The Reference bypass pins VRP and VRN are output compensated and should each be bypassed with a parallel
combination of a 5 µF (minimum) and 0.1 µF capacitors.
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VCMO Output
The VCMO output pin is intended to provide a common mode bias for the differential input pins of the
ADC10D040. It can also be used as a voltage reference source. Care should be taken, however, to avoid loading
this pin with more than 1 mA. A load greater than this could result in degraded long term and temperature
stability of this voltage. The VCMO pin is output compensated and should be bypassed with a 1 µF/0.1 µF
combination, minimum. See REFERENCE INPUTS for more information on using the VCMO output as a reference
source.
DIGITAL INPUT PINS
The seven digital input pins are used to control the function of the ADC10D040.
The ADC Clock (CLK) Input
The clock (CLK) input is common to both A/D converters. This pin is CMOS/LVTTL compatible with a threshold
of about VA/2. Although the ADC10D040 is tested and its performance is specified with a 40 MHz clock, it
typically will function well with low-jitter clock frequencies from 20 MHz to 45 MHz. The analog inputs I = (I+) –
(I−) and Q = (Q+) – (Q−) are simultaneously sampled on the falling edge of this input to ensure the best possible
aperture delay match between the two channels.
Low Sample Rate Considerations
While the ADC10D040 will typically function well with sample rates below 20 MSPS, it is important to note that it
is possible for some production lots not to perform well below 20 MSPS. To ensure adequate performance over
lot to lot and over temperature extremes, we recommend not operating the ADC10D040 at sample rates below
20 MSPS.
Clock Termination
The clock source should be series terminated to match the clock source impedance with the characteristic
impedance of the clock line, ZO. It may also be necessary to a.c. terminate the ADC clock pin with a series RC to
ground. This series network should be located near the ADC10D040 clock pin but on the far side of that pin as
seen from the clock source. The resistor value should equal the characteristic impedance, ZO, of the clock line
and the capacitor should have a value such that C × ZO ≥ 4 × tPD, where tPD is the time of propagation of the
clock signal from its source to the ADC clock pin. The typical propagation rate on a board of FR4 material is
about 150 ps/inch. The rise and fall times of the clock supplied to the ADC clock pin should be no more than 4
ns.
Output Bus Select (OS) Pin
The Output Bus Select (OS) pin determines whether the ADC10D040 is in the parallel or multiplexed mode of
operation. A logic high at this pin puts the device into the parallel mode of operation where “I” and “Q” data
appear at their respective output buses. A logic low at this pin puts the device into the multiplexed mode of
operation where the “I” and “Q” data are multiplexed onto the “I” output bus and the “Q” output lines all remain at
a logic low.
Offset Correct (OC) Pin
The Offset Correct (OC) pin is used to initiate an offset correction sequence. This procedure should be done
after power up and need not be performed again unless power to the ADC10D040 is interrupted. An independent
offset correction sequence for each converter is initiated when there is a low-to-high transition at the OC pin. This
sequence takes 34 clock cycles to complete, during which time 32 conversions are taken and averaged. The
result is subtracted from subsequent conversions. Because the offset correction is performed digitally at the
output of the ADC, the output range of the ADC is reduced by the offset amount.
Each input pair should have a 0V differential voltage value during this entire 34 clock period, but the “I” and “Q”
input common mode voltages do not have to be equal to each other. Because of the uncertainty as to exactly
when the correction sequence starts, it is best to allow 35 clock periods for this sequence.
Output Format (OF) Pin
The Output Format (OF) pin provides a choice of offset binary or 2's complement output formatting. With this pin
at a logic low, the output format is offset binary. With this pin at a logic high, the output format is 2's complement.
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Standby (STBY) Pin
The Standby (STBY) pin may be used to put the ADC10D040 into a low power mode where it consumes just 30
mW and can quickly be brought to full operation. The device operates normally with a logic low on this and the
PD pins.
While in the Standby mode the data outputs contain the results of the last conversion before going into this
Mode.
Power Down (PD) Pin
The Power Down (PD) pin puts the device into a low-power “sleep” state where it consumes less than 1 mW
when the PD pin is at a logic high. Power consumption is reduced more when the PD pin is high than when the
STBY pin is high, but recovery to full operation is much quicker from the standby state than it is from the power
down state. When the STBY and PD pins are both high, the ADC10D040 is in the power down mode.
While in the Power Down mode the data outputs contain the results of the last conversion before going into this
mode. The output pins are always in the active state. That is, the output pins do not have a high impedance
state.
GAIN Pin
The GAIN pin sets the internal signal gain of the “I” and “Q” inputs. With this pin at a logic low, the full scale
differential peak-to-peak input signal is equal to VREF. With the GAIN pin at a logic high, the full scale differential
peak-to-peak input signal is equal to 2 times VREF.
INPUT/OUTPUT RELATIONSHIP ALTERNATIVES
The GAIN pin of the ADC10D040 offers input range selection, while the OF pin offers a choice of offset binary or
2's complement output formatting.
The relationship between the GAIN, OF, analog inputs and the output code are as defined in Table 1. Keep in
mind that the input signals must not exceed the power supply rails.
Table 1. ADC10D040 Input/Output Relationships
GAIN
OF
I+ / Q+
I− / Q−
Output Code
0
0
VCM + 0.25*VREF
VCM − 0.25*VREF
11 1111 1111
0
0
VCM
VCM
10 0000 0000
0
0
VCM − 0.25*VREF
VCM + 0.25*VREF
00 0000 0000
0
1
VCM + 0.25*VREF
VCM − 0.25*VREF
01 1111 1111
0
1
VCM
VCM
00 0000 0000
0
1
VCM − 0.25*VREF
VCM + 0.25*VREF
10 0000 0000
1
0
VCM + 0.5*VREF
VCM − 0.5*VREF
11 1111 1111
1
0
VCM
VCM
10 0000 0000
1
0
VCM − 0.5*VREF
VCM + 0.5*VREF
00 0000 0000
1
1
VCM + 0.5*VREF
VCM − 0.5*VREF
01 1111 1111
1
1
VCM
VCM
00 0000 0000
1
1
VCM − 0.5*VREF
VCM + 0.5*VREF
10 0000 0000
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF to 50 µF tantalum or aluminum electrolytic capacitor should be placed within half an inch (1.2 centimeters)
of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed as close as possible to each of the
converter's power supply pins. Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source should be used for the analog and digital supplies of the ADC10D040, these
supply pins should be well isolated from each other to prevent any digital noise from being coupled to the analog
power pins. A choke is recommended between the VA and VD supply lines. VDR should have a separate supply
from VA and VD to avoid noise coupling into the input. Be sure to bypass VDR.
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The VDR pin is completely isolated from the other supply pins. Because of this isolation, a separate supply can be
used for these pins. This VDR supply can be significantly lower than the three volts used for the other supplies,
easing the interface to lower voltage digital systems. Using a lower voltage for this supply can also reduce the
power consumption and noise associated with the output drivers.
The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should
be the same supply used for the ADC10D040 analog supply.
As is the case with all high speed converters, the ADC10D040 should be assumed to have little high frequency
power supply rejection. A clean analog power source should be used.
No pin should ever have a voltage on it that is more than 300 mV in excess of the supply voltages or below
ground, not even on a transient basis. This can be a problem upon application of power to a circuit and upon turn
off of the power source. Be sure that the supplies to circuits driving the CLK, or any other digital or analog inputs
do not come up any faster than does the voltage at the ADC10D040 power pins.
LAYOUT AND GROUNDING
Proper routing of all signals and proper ground techniques are essential to ensure accurate conversion. Separate
analog and digital ground planes may be used if adequate care is taken with signal routing, but may result in
EMI/RFI. A single ground plane with proper component placement will yield good results while minimizing
EMI/RFI.
Analog and digital ground current paths should not coincide with each other as the common impedance will
cause digital noise to be added to analog signals. Accordingly, traces carrying digital signals should be kept as
far away from traces carrying analog signals as is possible. Power should be routed with traces rather than the
use of a power plane. The analog and digital power traces should be kept well away from each other. All power
to the ADC10D040, except VDR, should be considered analog. The DR GND pin should be considered a digital
ground and not be connected to the ground plane in close proximity with the other ground pins of the
ADC10D040.
Each bypass capacitor should be located as close to the appropriate converter pin as possible and connected to
the pin and the appropriate ground plane with short traces. The analog input should be isolated from noisy signal
traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor)
connected between the converter's input and ground should be connected to a very clean point in the ground
return.
The clock line should be properly terminated, as discussed in Clock Termination, and be as short as possible.
Figure 38 gives an example of a suitable layout and bypass capacitor placement. All analog circuitry (input
amplifiers, filters, reference components, etc.) and interconnections should be placed in an area reserved for
analog circuitry. All digital circuitry and I/O lines should be placed in an area reserved for digital circuitry.
Violating these rules can result in digital noise getting into the analog circuitry, which will degrade accuracy and
dynamic performance (THD, SNR, SINAD).
Figure 38. An Acceptable Layout Pattern
26
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ADC10D040
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SNAS149G – OCT 2001 – REVISED MARCH 2013
DYNAMIC PERFORMANCE
The ADC10D040 is a.c. tested and its dynamic performance is specified. To meet the published specifications,
the clock source driving the CLK input must be free of jitter. For best dynamic performance, isolating the ADC
clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 39.
Figure 39. Isolating the ADC Clock from Digital Circuitry
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, no input should
go more than 300 mV beyond the supply pins, Exceeding these limits on even a transient basis can cause faulty
or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit
overshoot and undershoot that goes a few hundred millivolts beyond the supply rails. A resistor of 50Ω to 100Ω
in series with the offending digital input, close to the source, will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the ADC10D040 (or any device) with a device that is
powered from supplies outside the range of the ADC10D040 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to
charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These
large charging current spikes can couple into the analog section, degrading dynamic performance. Adequate
bypassing and attention to board layout will reduce this problem. Buffering the digital data outputs (with a
74ACTQ841, for example) may be necessary if the data bus to be driven is heavily loaded. Dynamic
performance can also be improved by adding series resistors of 47Ω to 56Ω at each digital output, close to the
ADC output pins.
Using a clock source with excessive jitter. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR and SINAD performance. The use of simple gates with RC timing as a clock
source is generally inadequate.
Using the same voltage source for VD and external digital logic. As mentioned in POWER SUPPLY
CONSIDERATIONS, VD should use the same power source used by VA and other analog components, but
should be decoupled from VA.
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27
ADC10D040
SNAS149G – OCT 2001 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision F (March 2013) to Revision G
•
28
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADC10D040CIVS/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TQFP
PFB
48
250
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU SN
Level-3-260C-168 HR
(4/5)
-40 to 85
10D040
CIVS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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