Renesas EL7536 Monolithic 1a step-down regulator Datasheet

DATASHEET
NOT RECOMMENDED FOR NEW DESIGNS
POSSIBLE SUBSTITUTE PRODUCT
ISL97536
EL7536
FN7396
Rev 8.00
July 13, 2006
Monolithic 1A Step-Down Regulator
The EL7536 is a synchronous, integrated FET 1A step-down
regulator with internal compensation. It operates with an
input voltage range from 2.5V to 5.5V, which accommodates
supplies of 3.3V, 5V, or a Li-Ion battery source. The output
can be externally set from 0.8V to VIN with a resistive
divider.
Features
The EL7536 features PWM mode control. The operating
frequency is typically 1.4MHz. Additional features include a
100ms Power-On-Reset output, <1µA shut-down current,
short-circuit protection, and over-temperature protection.
• 100ms Power-On-Reset output (POR)
The EL7536 is available in the 10 Ld MSOP package,
making the entire converter occupy less than 0.15in2 of PCB
area with components on one side only. Both packages are
specified for operation over the full -40°C to +85°C
temperature range.
• <1µA shut-down current
Ordering Information
PART NUMBER
(BRAND)
PART
MARKING
• Components on one side of PCB
• Max height 1.1mm MSOP10
• Internally-compensated voltage mode controller
• Up to 94% efficiency
• Overcurrent and over-temperature protection
• Pb-free plus anneal available (RoHS compliant)
Applications
• PDA and pocket PC computers
TAPE &
REEL PACKAGE
PKG.
DWG. #
EL7536IY
BDAAA
-
10 Ld MSOP MDP0043
EL7536IY-T7
BDAAA
7”
10 Ld MSOP MDP0043
EL7536IY-T13
BDAAA
13”
10 Ld MSOP MDP0043
EL7536IYZ
(Note)
BFAAA
-
10 Ld MSOP
(Pb-free)
MDP0043
EL7536IYZ-T7
(Note)
BFAAA
7”
10 Ld MSOP
(Pb-free)
MDP0043
EL7536IYZ-T13 BFAAA
(Note)
13”
10 Ld MSOP
(Pb-free)
MDP0043
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Bar code readers
• Cellular phones
• Portable test equipment
• Li-Ion battery powered devices
• Small form factor (SFP) modules
Typical Application Diagram
EL7536
TOP VIEW
VS
(2.5V to 5.5V)
R3 100
C2
10µF
LX
EL7536
R5 100k
EL7536 (10 LD MSOP)
TOP VIEW
1 SGND
FB 10
2 PGND
VO 9
3 LX
R1*
124k
POR
R4 100k
R6
100k
1.8µH
C1
10µF
VDD
C3
0.1µF
VO
L1
VIN
EN
Pinout
FN7396 Rev 8.00
July 13, 2006
• Less than 0.15in2 (0.97cm2) footprint for the complete 1A
converter
FB
RSI
PGND
SGND
R2*
100k
VO
C4
470pF
(1.8V @ 1A)
* VO = 0.8V * (1 + R1 / R2)
POR 8
4 VIN
EN 7
5 VDD
RSI 6
Page 1 of 9
EL7536
Absolute Maximum Ratings (TA = 25°C)
VIN, VDD, POR to SGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
RSI, EN, VO, FB to SGND . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2A
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
790
800
810
mV
250
nA
2.5
5.5
V
DC CHARACTERISTICS
VFB
Feedback Input Voltage
IFB
Feedback Input Current
VIN, VDD
Input Voltage
VIN,OFF
Minimum Voltage for Shutdown
VIN falling
2
2.2
V
VIN,ON
Maximum Voltage for Startup
VIN rising
2.2
2.4
V
IDD
Supply Current
PWM, VIN = VDD = 5V
400
500
µA
EN = 0, VIN = VDD = 5V
0.1
1
µA
PMOS FET Resistance
VDD = 5V, wafer test only
70
100
m
RDS(ON)-NMOS NMOS FET Resistance
VDD = 5V, wafer test only
45
75
m
RDS(ON)-PMOS
ILMAX
Current Limit
TOT,OFF
Over-temperature Threshold
TOT,ON
1.5
A
T rising
145
°C
Over-temperature Hysteresis
T falling
130
°C
IEN, IRSI
EN, RSI Current
VEN, VRSI = 0V and 3.3V
VEN1, VRSI1
EN, RSI Rising Threshold
VDD = 3.3V
VEN2, VRSI2
EN, RSI Falling Threshold
VDD = 3.3V
VPOR
Minimum VFB for POR, WRT Targeted
VFB Value
VFB rising
POR Voltage Drop
ISINK = 5mA
VOLPOR
VFB falling
-1
1
V
2.4
V
0.8
V
95
86
%
%
35
70
mV
1.5
1.75
MHz
25
50
ns
AC CHARACTERISTICS
FPWM
PWM Switching Frequency
tRSI
Minimum RSI Pulse Width
tSS
Soft-start Time
tPOR
Power On Reset Delay Time
FN7396 Rev 8.00
July 13, 2006
1.4
Guaranteed by design
650
80
100
µs
120
ms
Page 2 of 9
EL7536
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
SGND
Negative supply for the controller stage
2
PGND
Negative supply for the power stage
3
LX
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
5
VDD
Power supply for the controller stage
6
RSI
Resets POR timer
7
EN
Enable
8
POR
9
VO
Output voltage sense
10
FB
Voltage feedback input; connected to an external resistor divider between VO and SGND for variable
output
Power on reset open drain output
Block Diagram
VDD
VO
+
-
10pF
124K
FB
5M
+
PWM
COMPENSATION
100K
CLOCK
1.4MHz
CURRENT
LIMIT
+
PWM
COMPARATOR
P-DRIVER
LX
CONTROL
LOGIC
RAMP
GENERATOR
1.8µ
1.8V
1A
EN
EN
SOFTSTART
10µF
2.5V3.5V
VIN
+
–
BANDGAP
REFERENCE
UNDERVOLTAGE
LOCKOUT
RSI
PGND
100K
TEMPERATURE
SENSE
SGND
FN7396 Rev 8.00
July 13, 2006
10µF
N-DRIVER
POR
PG
POR
Page 3 of 9
EL7536
Performance Curves and Waveforms
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise
noted.
100
VIN=5V
100
VO=3.3V
95
95
VO=2.5V
90
EFFICIENCY (%)
90
EFFICIENCY (%)
VIN=3.3V
85
VO=1.8V
80
VO=2.5V
VO=1.2V
75
70
85
VO=1V
80
VO=1.8V
VO=1.2V
75
70
65
65
60
60
0
200
400
600
800
1000
0
200
400
IO (mA)
FIGURE 1. EFFICIENCY
VIN=5V IO=0A
FS (MHz)
1.42
0.0%
1.4
VIN=3.3V IO=0A
1.38
1.36
-0.1%
VIN=3.3V
-0.2%
VIN=5V
-0.3%
-0.4%
1.34
-0.5%
1.32
-50
0
50
100
150
0
0.2
0.4
0.8
1
FIGURE 4. LOAD REGULATIONS
FIGURE 3. FS vs JUNCTION TEMPERATURE
0.1%
12
0.0%
VIN=5V IO=0A
10
VIN=3.3V IO=0A
8
-0.2%
-0.3%
IIN (mA)
VO CHANGES
0.6
IO (A)
TA (°C)
-0.1%
1000
0.1%
VIN=3.3V IO=1A
VIN=5V IO=1A
800
FIGURE 2. EFFICIENCY
VO CHANGES
1.44
600
IO (mA)
VIN=3.3V IO=1A
-0.4%
6
4
-0.5%
-0.6%
-0.7%
-50
2
VIN=5V IO=1A
0
50
100
150
TJ (°C)
FIGURE 5. LOAD/LINE REGULATIONS vs JUNCTION
TEMPERATURE
FN7396 Rev 8.00
July 13, 2006
0
2.5
3
3.5
4
4.5
5
VIN (V)
FIGURE 6. NO LOAD INPUT CURRENT
Page 4 of 9
EL7536
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise
noted.
VIN
(2V/d)
VIN
(1V/d)
VO
(2V/d)
IIN
(0.5A/d)
POR
(2V/d)
VO
(1V/d)
50ms/d
0.5ms/d
FIGURE 8. START-UP 2
FIGURE 7. START-UP 1
VIN
(2V/d)
VO
(2V/d)
0.75A
0.25A
IO
RSI
(2V/d)
VO
20mV/d
POR
(2V/d)
50ms/d
0.2ms/d
FIGURE 9. POR FUNCTION
FIGURE 10. TRANSIENT RESPONSE
VIN
100mV/d
0.5A/d
iL
VLX
2V/d
VO
10mV/d
1µs/d
FIGURE 11. STEADY-STATE
FN7396 Rev 8.00
July 13, 2006
Page 5 of 9
EL7536
Performance Curves and Waveforms
(Continued)
0.5
0.4

JA
0.3
M
SO
P
=2
06 10
°C
/W
0.2
0.1
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7396 Rev 8.00
July 13, 2006
ALLOWABLE POWER DISSIPATION (W)
0.6
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.00
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.90
0.80
0.70
0
P1
/W
°C
SO
M 115
=
A
J
ALLOWABLE POWER DISSIPATION (W)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise
noted.
0.60
0.50
0.40
0.30
0.20
0.10
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Page 6 of 9
EL7536
Applications Information
Product Description
The EL7536 is a synchronous, integrated FET 1A step-down
regulator which operates from an input of 2.5V to 6V. The
output voltage is user-adjustable with a pair of external
resistors.
The internally-compensated controller makes it possible to
use only two ceramic capacitors and one inductor to form a
complete, very small footprint 1A DC:DC converter.
Start-Up and Shut-Down
When the EN pin is tied to VIN, and VIN reaches
approximately 2.4V, the regulator begins to switch. The
output voltage is gradually increased to ensure proper softstart operation.
When the EN pin is connected to a logic low, the EL7536 is
in the shut-down mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 1µA.
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
PWM Operation
In the PWM mode, the P channel MOSFET and N channel
MOSFET always operate complementary. When the
PMOSFET is on and the NMOSFET off, the inductor current
increases linearly. The input energy is transferred to the
output and also stored in the inductor. When the P channel
MOSFET is off and the N channel MOSFET on, the inductor
current decreases linearly, and energy is transferred from
the inductor to the output. Hence, the average current
through the inductor is the output current. Since the inductor
and the output capacitor act as a low pass filter, the duty
cycle ratio is approximately equal to VO divided by VIN.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 22µF ceramic. The
inductor is nominally 1.8µH, but 1.5µA to 2.2µH can be used.
100% Duty Ratio Operation
EL7536 utilizes CMOS power FET's as the internal
synchronous power switches. The upper switch is a PMOS
and lower switch a NMOS. This not only saves a boot
capacitor, it also allows 100% turn-on of the upper PFET
switch, achieving VO close to VIN. The maximum achievable
VO is,
V O = V IN –  R L + R DSON1   I O
FN7396 Rev 8.00
July 13, 2006
Where RL is the DC resistance on the inductor and RDSON1
the PFET on-resistance, nominal 70m at room temperature
with tempco of 0.2m/°C.
As the input voltage drops gradually close or even below the
preset VO, the converter gets into 100% duty ratio. At this
condition, the upper PFET needs some minimum turn-off
time if it is turned off. This off-time is related to input/output
conditions. This makes the duty ratio appears randomly and
increases the output ripple somewhat until the 100% duty
ratio is reached. Larger output capacitor could reduce the
random-looking ripple. Users need to verify if this condition
has adverse effect on overall circuit if close to 100% duty
ratio is expected.
RSI/POR Function
When powering up, the open-collector Power-On-Reset
output holds low for about 100ms after VO reaches the
preset voltage. When the active-HI reset signal RSI is
issued, POR goes to low immediately and holds for the
same period of time after RSI comes back to LOW. The
output voltage is unaffected. (Please refer to the timing
diagram). When the function is not used, connect RSI to
ground and leave open the pull-up resister R4 at POR pin.
The POR output also serves as a 100ms delayed Power
Good signal when the pull-up resister R4 is installed. The
RSI pin needs to be directly (or indirectly through a resister
R6) connected to Ground for this to function properly.
VO
MIN
25ns
RSI
100ms
100ms
POR
FIGURE 14. RSI & POR TIMING DIAGRAM
Output Voltage Selection
Users can set the output voltage of the converter with a
resister divider, which can be chosen based on the following
formula:
R 2

V O = 0.8   1 + -------
R

1
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. We recommend 10µF to 22µF
multi-layer ceramic capacitors with X5R or X7R rating for
both the input and output capacitors, and 1.5µH to 2.2µH
inductance for the inductor.
Page 7 of 9
EL7536
At extreme conditions (VIN < 3V, IO > 0.7A, and junction
temperature higher than 75°C), input cap C1 is
recommended to be 22µF. Otherwise, if any of the above 3
conditions is not true, C1 can remain as low as 10µF.
The RMS current present at the input capacitor is decided by
the following formula:
V O   V IN - V O 
I INRMS = ------------------------------------------------  I O
V IN
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
 V IN - V O   V O
I IL = -------------------------------------------L  V IN  f S
• L is the inductance
• fS the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 1.5A surge current that can occur during a
current limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
1
f Z = ---------------------2R 2 C 4
Over a normal range of R2 (~10-100k), C4 will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R1
and R2, which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
Thermal Performance
The EL7536 is in a fused-lead MSOP10 package. Compared
with regular MSOP10 package, the fused-lead package
provides lower thermal resistance. The JA is 100°C/W on a
4-layer board and 125°C/W on 2-layer board. Maximizing the
copper area around the pins will further improve the thermal
performance.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
• Separate the Power Ground ( ) and Signal Ground (
connect them only at one point right at the pins
• Place the input capacitor as close to VIN and PGND pins
as possible
• Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
• If used, connect the trace from the FB pin to R1 and R2 as
close as possible
• Maximize the copper area around the PGND pin
• Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7536 Application Brief.
1
f P = --------------------------------------2  R 1 R 2 C 4
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
FN7396 Rev 8.00
July 13, 2006
);
Page 8 of 9
EL7536
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. C 6/99
0.08 M C A B
b
SYMBOL
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
L1
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
A
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
A1
L
0.25
3° ±3°
DETAIL X
© Copyright Intersil Americas LLC 2003-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7396 Rev 8.00
July 13, 2006
Page 9 of 9