16 Pin DIL 5 Tap 10K ECL Compatible Active Delay Lines TAP 1 nS ±5% 3.0 Typ† 3.0 Typ† 3.0 Typ 4 ± 1.0 5 ± 1.0 6 ± 1.0 8 ± 1.0 10 ± 1.0 15 ± 1.5 20 ± 2.0 30 ± 2.0 40 50 60 70 80 90 100 120 140 160 180 200 TAP 2 nS ±5% 4 ± 0.3 5 ± 0.5 6 ± 0.5 8 ± 0.5 10 ± 1.0 12 ± 1.0 16 ± 1.5 20 ± 2.0 30 ± 2.0 40 60 80 100 120 140 160 180 200 240 280 320 360 400 TAP 3 nS ±5% TAP 4 nS ±5% OUTPUT nS ±5% RISE TIME nS MAX PART NUMBER 5 ± 0.3 7 ± 0.5 9 ± 0.5 12 ± 1.0 15 ± 1.5 18 ± 1.5 24 ± 2.0 30 ± 2.0 45 60 90 120 150 180 210 240 270 300 360 420 480 520 600 6 ± 0.3 9 ± 0.5 12 ± 1.0 16 ± 1.5 20 ± 2.0 24 ± 2.0 32 ± 2.0 40 60 80 120 160 200 240 280 320 360 400 480 560 640 720 800 7 ± 0.3 11 ± 0.5 15 ± 1.5 20 ± 2.0 25 ± 2.0 30 ± 2.0 40 50 75 100 150 200 250 300 350 400 450 500 600 700 800 900 1000 4 4 4 4 4 4 5 5 8 10 15 20 25 30 35 40 45 50 50 50 50 50 50 EP9445-7 EP9445-11 EP9445-15 EP9445-20 EP9445-25 EP9445-30 EP9445-40 EP9445-50 EP9445-75 EP9445-100 EP9445-150 EP9445-200 EP9445-250 EP9445-300 EP9445-350 EP9445-400 EP9445-450 EP9445-500 EP9445-600 EP9445-700 EP9445-800 EP9445-900 EP9445-1000 Delay time measured at - 1.3V, no load Delay times referenced from input to leading edges †Inherent delay Rise time output measured from 20% to 80% Output terminated (externally) with 50Ω to - 2.0Vdc DC Electrical Characteristics Parameter *Test Conditions VOH VOHT VOLT VOH IIH IIL IEE High-Level Output Voltage High-Level Output Threshold Voltage Low-Level Output Threshold Voltage Low-Level Output Voltage High-Level Input Current Low-Level Input Current VEE Supply Current VIL = Min Schematic Min Max Unit -960 mV -980 mV 8 VEE 15 3 14 4 13 5 -1630 -1650 265 VIH = Max VIH = Max VIL = Min 0.5 50 mV mV µA µA mA 1, 16 * (VCC1 = VCC2 = GRD, VEE = -5.2V ± 0.01V, Output Loading with 50Ω to -2.0V ± 0.01V) Recommended Operating Conditions VEE VCC VIH VIHT VILT VIL PW* d* TA Supply Voltage (Negative) Circuit Ground (Pins 1 and 16) HIgh-Level Input Voltage High-Level Input Threshold Voltage Low-Level Input Threshold Voltage Low-Level Input Voltage Pulse Width of Total Delay Duty Cycle Operating Free-Air Temperature Package Dimensions Min Max 4.94 0 -980 5.46 0 -1105 -1475 -1630 300 -30 20 +80 Unit V V mV mV mV mV % % °C White Dot Pin#1 PCA EP9445-7 Date Code .800 Max. .020 .040 .275 Max. .010 x .018 *These two values are inter-dependent. .400 Max. .130 Typ. .100 .300 Input Pulse Test Conditions @ 25° C VIN PW TRI PRR VEE Pulse Input Voltage Pulse Width of Total Delay Pulse Rise Time (20% to 80%) Pulse Spacing Supply Voltage -1.0V (-0.75 to -1.75V) 3x Total Delay 2 nS 10x Total Td -5.2V QAF-CSO1 Rev. B 8/25/94 DSD9445 8/25/94 Unless Otherwise Noted Dimensions in Inches Tolerances: Fractional = ± 1/32 .XX = ± .030 .XXX = ± .010 ELECTRONICS INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 TEL: (818) 892-0761 FAX: (818) 894-5791