AD AD7801 2.7 v to 5.5 v, parallel input, voltage output 8-bit dac Datasheet

a
FEATURES
Single 8-Bit DAC
20-Pin SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer Rail-to-Rail Operation
Low Power Operation 1.75 mA max @ 3.3 V
Power-Down to 1 mA max @ 258C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
+2.7 V to +5.5 V, Parallel Input,
Voltage Output 8-Bit DAC
AD7801
FUNCTIONAL BLOCK DIAGRAM
D7
D0
WR
CS
INPUT
REGISTER
DAC
REGISTER
CONTROL
LOGIC
I DAC
I/V
MUX
POWER-ON
RESET
÷2
AD7801
PD
CLR
LDAC
REFIN
VDD
VOUT
AGND
DGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7801 is a single, 8-bit, voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision output
buffer allows the DAC output to swing rail to rail. The AD7801
has a parallel microprocessor and DSP compatible interface with
high speed registers and double buffered interface logic. Data is
loaded to the input register on the rising edge of CS or WR.
1. Low Power, Single Supply operation. This part operates
from a single +2.7 V to +5.5 V supply and consumes typically
5 mW at 3 V, making it ideal for battery powered applications.
Reference selection for the AD7801 can be either an internal
reference derived from the VDD or an external reference applied
at the REFIN pin. The output of the DAC can be cleared by
using the asynchronous CLR input.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consumption is less than 5 mW at 3.3 V, reducing to less than 3 µW in
power-down mode.
2. The on-chip output buffer amplifier allows the output of the
DAC to swing rail to rail with a settling time of typically 1.2 µs.
3. Internal or external reference capability.
4. High speed parallel interface.
5. Power-down capability. When powered down the DAC
consumes less than 1 µA at 25°C.
6. Packaged in 20-lead SOIC and TSSOP packages.
The AD7801 is available in a 20-lead SOIC and a 20-lead
TSSOP package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
(VDD = +2.7 V to +5.5 V, Internal Reference; CL = 100 pF, RL = 10 kV to VDD and GND.
All specifications TMIN to TMAX unless otherwise noted.)
AD7801–SPECIFICATIONS
Parameter
B Versions1
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy2
Differential Nonlinearity
Zero-Code Error @ +25°C
Full-Scale Error
Zero-Code Error Drift
Gain Error3
8
±1
±1
3
–0.75
100
±1
Bits
LSB max
LSB max
LSB typ
LSB typ
µV/°C typ
% FSR typ
Guaranteed Monotonic
All Zeros Loaded to DAC Register
All Ones Loaded to DAC Register
DAC REFERENCE INPUT
REFIN Input Range
REFIN Input Impedance
1 to VDD/2
10
V min/V max
MΩ typ
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
Power Supply Rejection Ratio4
0 to VDD
2
7.5
1
0.2
40
14
0.0003
V min/V max
µs max
V/µs typ
nV-s typ
nV-s typ
Ω typ
mA typ
%/% max
LOGIC INPUTS
Input Current
VINL, Input Low Voltage
VINL, Input Low Voltage
VINH, Input High Voltage
VINH, Input High Voltage
Pin Capacitance
± 10
0.8
0.6
2.4
2.1
7
µA max
V max
V max
V min
V min
pF max
2.7/5.5
V min/V max
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 3.3 V
@ 25°C
TMIN to TMAX
VDD = 5.5 V
@ 25°C
TMIN to TMAX
IDD (Power-Down)
@ 25°C
TMIN to TMAX
1.55
1.75
mA max
mA max
2.35
2.5
mA max
mA max
1
2
µA max
µA max
Typically 1.2 µs
1 LSB Change Around Major Carry
∆VDD = ± 10%
VDD = +5 V
VDD = +3 V
VDD = +5 V
VDD = +3 V
DAC Active and Excluding Load Current
VIH = VDD and VIL = GND
See Figure 6
VIH = VDD and VIL = GND
See Figure 18
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +105°C
2
Relative Accuracy is calculated using a reduced code range of 15 to 245.
3
Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4
Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
t1
t2
CS
t3
WR
t4
t5
D7-D0
t6
t7
LDAC
t8
CLR
Figure 1. Timing Diagram for Parallel Data Write
–2–
REV. 0
AD7801
TIMING CHARACTERISTICS1, 2
(VDD = +2.7 V to +5.5 V; GND = 0 V; Internal V DD/2 Reference. All specifications TMIN to TMAX
unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(B Version)
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
0
0
20
15
4.5
20
20
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
Data Setup Time
Data Hold Time
Write to LDAC Setup Time
LDAC Pulse Width
CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of
(VIL + VIH)/2. tr and tf should not exceed 1 µs on any digital input.
2
See Figure 1.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Reference Input Voltage to AGND . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 700 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Model
Temperature
Range
Package
Option*
AD7801BR
AD7801BRU
–40°C to +105°C
–40°C to +105°C
R-20
RU-20
*R = Small Outline; RU = Thin Shrink Small Outline.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7801 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
AD7801
PIN CONFIGURATION
20 DGND
(MSB) DB7 1
DB6 2
19 VOUT
DB5 3
18 NC
17 AGND
DB4 4
DB3 5
AD7801
16 REFIN
TOP VIEW 15 V
DD
(Not to Scale)
14 CLR
DB1 7
DB2 6
13 LDAC
(LSB) DB0 8
CS 9
12 PD
WR 10
11 DGND
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1–8
9
10
11
12
13
D7–D0
CS
WR
DGND
PD
LDAC
14
CLR
15
16
VDD
REFIN
17
18
19
20
AGND
NC
VOUT
DGND
Parallel Data Inputs. 8-bit data is loaded to the input register of the AD7801 under the control of CS and WR.
Chip Select. Active low logic input.
Write Input. WR is an active low logic input used in conjunction with CS to write data to the input register.
Digital Ground
Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.
Load DAC Logic Input. When this logic input is taken low the DAC output is updated with the contents of
its DAC register. If LDAC is permanently tied low the DAC is updated on the rising edge of WR.
Asynchronous Clear Input (Active Low). When this input is taken low the DAC register is loaded with all
zeroes and the DAC output is cleared to zero volts.
Power Supply Input. This part can be operated from +2.7 V to +5.5 V and should be decoupled to GND.
External Reference Input. This can be used as the reference for the DAC. The range on this reference input is
1 V to VDD/2. If REFIN is tied directly to VDD the internal VDD/2 reference is selected.
Analog Ground reference point and return point for all analog current on the part.
No Connect Pin.
Analog Output Voltage from the DAC. The output amplifier can swing rail to rail on its output.
Digital Ground reference point and return point for all digital current on the part.
–4–
REV. 0
Typical Performance Characteristics– AD7801
5
3.5
4.92
3.25
800
640
480
VOUT – Volts
VOUT – mV
560
VDD = 5V AND 3V
INTERNAL REFERENCE
TA = +25 C
DAC LOADED WITH 00HEX
400
320
240
4.84
3.0
4.76
2.75
4.68
4.6
4.52
4.36
80
4.28
4.2
8
2
4
6
SINK CURRENT – mA
Figure 2. Output Sink Current Capability with VDD = 3 V and VDD = 5 V
VDD = 5V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHEX
TA = +25°C
4.44
160
0
0
0
2.0
1.25
1.0
8
0.4
2
3
4
5
6
SOURCE CURRENT – mA
7
8
DAC ACTIVE
INTERNAL REFERENCE
TA = +25°C
3.0
3.0
LOGIC INPUTS = VIH OR VIL
INL ERROR
0.25
0.2
VDD = 5.5V
2.0
1.5
0.15
2.0
LOGIC INPUTS = VDD OR GND
VDD = 3.3V
1.0
DNL ERROR
IDD – mA
2.5
IDD – mA
ERROR – LSBs
1
4.0
0.35
0.3
0
Figure 4. Output Source Current
Capability with VDD = 3 V
INTERNAL REFERENCE
LOGIC INPUTS = VDD OR GND
DAC ACTIVE
3.5
VDD = 3V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHex
TA = +25°C
1.5
2
4
6
SOURCE CURRENT – mA
4.0
VDD = 5V
TA = +25 C
2.5
2.25
1.75
Figure 3. Output Source Current
Capability with VDD = 5 V
0.5
0.45
VOUT – Volts
720
1.0
0.1
0.5
0.05
0
–50
0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE – Volts
Figure 5. Relative Accuracy vs.
External Reference
–25
0
25
50
75
TEMPERATURE – C
100
0
2.5
125
Figure 6. Typical Supply Current
vs. Temperature
3.0
3.5
4.0
4.5
VDD – Volts
5.0
5.5
Figure 7. Typical Supply Current
vs. Supply Voltage
10
5
WR
ATTENUATION – dB
0
T
1←
–5
PD
2←
–10
2←
–15
VOUT
VOUT
–20
–25
VDD = 5V
EXTERNAL SINEWAVE REFERENCE
DAC REGISTER LOADED WITH FFHEX
TA = +25°C
–30
–35
–40
1
10
100
1k
FREQUENCY – Hz
Figure 8. Large Scale Signal
Frequency Response
REV. 0
3←
10k
←
VDD = 3V
INTERNAL VOLTAGE
REFERENCE
FULL SCALE CODE
CHANGE 00H-FFH
TA = +25°C
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200 ns/Div
Figure 9. Full-Scale Settling Time
–5–
1←
VOUT
AD7801 POWER-UP TIME
VDD = 5V
INTERNAL REFERENCE
DAC IN POWER-DOWN INITIALLY
CH1 = 2V/div, CH2 = 5V/Div,
TIME BASE = 2 µs/Div
Figure 10. Exiting Power-Down (Full
Power-Down)
AD7801–Typical Performance Characteristics
10
9
T
8
ZERO CODE ERROR – LSB
VDD
1
T
2
VOUT
7
6
5
5.00V CH2
VOUT
4
3
2
0
–50
5.00V M20.0ms CH1
VDD = 5V
INTERNAL VOLTAGE
REFERENCE
10 LSB STEP CHANGE
TA = +258C
VDD = 2.7 TO 5.5V
DAC LOADED WITH ALL ZEROES
INTERNAL REFERENCE
2←
1
CH1
WR
1←
–25
0
25
50
75
100
CH1 5.00V, CH2 50.0mV, M 250ns
125
TEMPERATURE – C
Figure 11. Power-On—Reset
Figure 12. Zero Code Error vs.
Temperature
0.5
VDD = 5V
INTERNAL REFERENCE
5kΩ 100pF LOAD
LIMITED CODE RANGE (15–245)
TA = +25°C
0.5
0.4
0.4
0.3
0.1
0
–0.1
–0.2
0.2
0.1
0.3
DNL ERROR – LSB
0.2
0.5
VDD = 5V
INTERNAL REFERENCE
0
–0.1
–0.2
0.2
0.1
0
–0.2
–0.3
–0.3
–0.4
–0.4
–0.4
–0.5
–0.5
–60 –40 –20
0
32
64 96 128 160 192 224 256
INPUT CODE (15 to 245)
Figure 14. Integral Linearity Plot
0 20 40 60 80 100 120 140
TEMPERATURE – C
Figure 15. Typical INL vs. Temperature
0 20 40 60 80 100 120 140
TEMPERATURE – C
Figure 16. Typical DNL vs. Temperature
VDD = 5V
LOGIC INPUTS = VDD OR GND
900
VDD = 5V
%
–0.5
–60 –40 –20
1000
1.0
0.8
INT REFERENCE ERROR –
VDD = 5V
INTERNAL REFERENCE
–0.1
–0.3
POWER DOWN CURRENT – nA
INL ERROR – LSB
0.3
INL ERROR – LSB
0.4
Figure 13. Small-Scale Settling Time
0.6
0.4
0.2
800
700
600
500
400
300
200
100
0
–60 –40 –20
0
–50
0 20 40 60 80 100 120 140
TEMPERATURE – C
Figure 17. Typical Internal Reference
Error vs. Temperature
–25
0
25
50
75
TEMPERATURE – C
100
150
Figure 18. Power-Down Current vs.
Temperature
–6–
REV. 0
AD7801
TERMINOLOGY
Integral Nonlinearity
AD7801
REFERENCE
AMPLIFIER
VDD
For the DAC, Relative Accuracy or End-Point nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A graphical representation of the transfer curve is
shown in Figure 14.
11.7kΩ
30kΩ
CURRENT
DAC
REFIN
I/V
VOUT
11.7kΩ
30kΩ
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity.
Zero-Code Error
Zero-Code Error is the measured output voltage from VOUT of
the DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero-code error is expressed in LSBs.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale value. It includes fullscale errors but not offset errors.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into
the analog output when the digital inputs change state with
the DAC selected and the LDAC used to update the DAC. It
is normally specified as the area of the glitch in nV-secs and
measured when the digital input code is changed by 1 LSB at
the major carry transition.
Digital Feedthrough
Digital Feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-secs and measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa.
Figure 19. DAC Architecture
The DAC output is internally buffered and has rail-to-rail
output characteristics. The output amplifier is capable of driving
a load of 100 pF and 10 kΩ to both VDD and ground. The
reference selection for the DAC can be either internally generated from VDD or externally applied through the REFIN pin. A
comparator on the REFIN pin detects whether the required
reference is the internally generated reference or the externally
applied voltage to the REFIN pin. If REFIN is connected to
VDD, the reference selected is the internally generated VDD/2
reference. When an externally applied voltage is more than one
volt below VDD, the comparator selection switches to the externally
applied voltage on the REFIN pin. The range on the external
reference input is from 1.0 V to VDD/2 V. The output voltage
from the DAC is given by:
 N 
V O = 2V REF × 

 256 
where VREF is the voltage applied to the external REFIN pin or
VDD/2 when the internal reference is selected. N is the decimal
equivalent of the code loaded to the DAC register and ranges
from 0 to 255.
VDD
VTH
PMOS
Power Supply Rejection Ratio (PSRR)
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power supply rejection
ratio is quoted in terms of % change in output per % change in
VDD for full-scale output of the DAC. VDD is varied ± 10%.
COMPARATOR
INT REF
REFIN
EXT REF
INT
REF
GENERAL DESCRIPTION
D/A Section
The AD7801 is an 8-bit voltage output digital-to-analog converter. The architecture consists of a reference amplifier and a
current source DAC followed by a current-to-voltage converter
capable of generating rail-to-rail voltages on the output of the
DAC. Figure 19 shows a block diagram of the basic DAC
architecture.
REV. 0
MUX
SELECTED REFERENCE
OUTPUT
Figure 20. Reference Selection Circuitry
–7–
AD7801
Reference
Automatic Update Mode
The AD7801 has the ability to use either an external reference
applied through the REFIN pin or an internal reference generated
from VDD. Figure 20 shows the reference input arrangement
where either the internal VDD/2 or the externally applied reference
can be selected.
In this mode of operation the LDAC signal is permanently tied
low. The state of the LDAC is sampled on the rising edge of
WR. LDAC being low allows the DAC register to be automatically updated on the rising edge of WR. The output update
occurs on the rising edge of WR. Figure 23 shows the timing
associated with the automatic update mode of operation and
also the status of the various registers during this frame.
The internal reference is selected by tying the REFIN pin to
VDD. If an external reference is to be used, this can be directly
applied to the REFIN pin and if this is 1 V below VDD, the
internal circuitry will select this externally applied reference as
the reference source for the DAC.
CS
WR
Digital Interface
The AD7801 contains a fast parallel interface allowing this
DAC to interface to industry standard microprocessors,
microcontrollers and DSP machines. There are two modes in
which this parallel interface can be configured to update the
DAC output. The synchronous update mode allows synchronous updating of the DAC output; the automatic update mode
allows the DAC to be updated individually following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. The PON STRB signal is internally generated
from the power-on reset circuitry and is low during the poweron reset phase of the power up procedure.
D7-D0
LDAC = 0
I/P REG (MLE)
DAC REG (SLE)
TRACK
HOLD
HOLD
TRACK
Figure 23. Timing and Register Arrangement for Automatic Update Mode
CLR
Synchronous Update Mode
In this mode of operation the LDAC signal is used to update the
DAC output to synchronize with other updates in the system.
The state of the LDAC is sampled on the rising edge of WR. If
LDAC is high, the automatic update mode is disabled and the
DAC latch is updated at any time after the write by taking
LDAC low. The output update occurs on the falling edge of
LDAC. LDAC must be taken back high again before the next
data transfer takes place. Figure 24 shows the timing associated
with the synchronous update mode of operation and also the
status of the various registers during this frame.
PON STRB
CLEAR
SET SLE
DAC CONTROL
LDAC
LOGIC
TRACK
VOUT
CLR
LDAC
HOLD
MLE
SLE
ENABLE
CS
WR
Figure 21. Logic Interface
The AD7801 has a double buffered interface, which allows for
synchronous updating of the DAC output. Figure 22 shows a
block diagram of the register arrangement within the AD7801.
CS
15
15
DRIVERS
15
DRIVERS
4
DAC
REGISTER
8
4 TO 15
DECODER
INPUT
REGISTER
DB7-DB0
15
DAC
REGISTER
4 TO 15
DECODER
WR
4
30
D7-D0
UPPER
NIBBLE
LDAC
I/P REG (MLE)
HOLD
TRACK
HOLD
30
DAC REG (SLE)
HOLD
TRACK
HOLD
LOWER
NIBBLE
VOUT
MLE
CS
WR
LDAC
CLR
SLE
Figure 24. Timing and Register Arrangement for Synchronous Update Mode
CONTROL LOGIC
Figure 22. Register Arrangement
–8–
REV. 0
AD7801
POWER-ON RESET
The AD7801 has a power-on reset circuit designed to allow
output stability during power up. This circuit holds the DAC in
a reset state until a write takes place to the DAC. In the reset
state all zeros are latched into the input register of the DAC and
the DAC register is in transparent mode thus the output of the
DAC is held at ground potential until a write takes place to the
DAC. The power-on reset circuitry generates a PON STRB
signal which is a gating signal used within the logic to identify
a power-on condition.
 N 
V OUT = 2 ×V REF 

 256 
where:
N
is the decimal equivalent of the binary input
code. N ranges from 0 to 255.
VREF is the voltage applied to the external REFIN pin
when the external reference is selected and is VDD/2
if the internal reference is used.
Table I. Output Voltage for Selected Input Codes
POWER-DOWN FEATURES
The AD7801 has a power-down feature implemented by
exercising the external PD pin. An active low signal puts the
complete DAC into power-down mode. When in power-down,
the current consumption of the device is reduced to less than
1 µA max at +25°C or 2 µA max over temperature, making the
device suitable for use in portable battery powered equipment.
The internal reference resistors, the reference bias servo loop,
the output amplifier and associated linear circuitry are all shut
down when the power-down is activated. The output terminal
sees a load of ≈ 23 kΩ to GND when in power-down mode as
shown in Figure 25. The contents of the data register are
unaffected when in power-down mode. The device typically
comes out of power-down in 13 µs (see Figure 10).
Digital
MSB . . . LSB
Analog Output
1111 1111
2×
255
×V REF V
256
1111 1110
2×
254
×V REF V
256
1000 0001
2×
129
×V REF V
256
1000 0000
VREF V
0111 1111
2×
127
×V REF V
256
0000 0001
2×
V REF
V
256
0000 0000
0V
11.7kΩ
VDD
IDAC
2VREF
11.7kΩ
DAC OUTPUT VOLTAGE
VREF
Figure 25. Output Stage During Power-Down
Analog Outputs
The AD7801 contains a voltage output DAC with 8-bit resolution
and rail-to-rail operation. The output buffer provides a gain of
two at the output. Figures 2, 3 and 4 show the source and sink
capabilities of the output amplifier. The slew rate of the output
amplifier is typically 7.5 V/µs and has a full-scale settling to
eight bits with a 100 pF capacitive load in typically 1.2 µs.
0
DAC INPUT CODE
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7801. Figure 26 shows
the DAC transfer function for binary coding. Any DAC output
voltage can be expressed as:
REV. 0
VREF
00 01
7F 80 81
FE FF
Figure 26. DAC Transfer Function
–9–
AD7801
Figure 27 shows a typical setup for the AD7801 when using its
internal reference. The internal reference is selected by tying the
REFIN pin to VDD. Internally in the reference section there is a
reference detect circuit that will select the internal VDD/2 based
on the voltage connected to the REFIN pin. If REFIN is within
a threshold voltage of a PMOS device (approximately 1 V) of
VDD the internal reference is selected. When the REFIN voltage
is more than 1 V below VDD, the externally applied voltage at
this pin is used as the reference for the DAC. The internal
reference on the AD7801 is VDD/2, the output current to
voltage converter within the AD7801 provides a gain of two.
Thus the output range of the DAC is from 0 V to VDD, based on
Table I.
MICROPROCESSOR INTERFACING
AD7801–ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7801 and the ADSP2101/ADSP-2103. The fast interface timing associated with the
AD7801 allows easy interface to the ADSP-2101/ADSP-2103.
LDAC is permanently tied low in this circuit so the DAC
output is updated on the rising edge of the WR signal.
Data is loaded to the AD7801 input register using the following
ADSP-21xx instruction.
DM(DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
DAC = Decoded DAC Address.
VDD = 3V TO 5V
DMA14
0.1mF
10mF
ADDRESS BUS
DMA0
AD7801*
VDD
REF IN
EN
ADDR
DECODE
ADSP-2101*/
ADSP-2103*
VOUT
AD7801
CLR
DMS
AGND DGND
VOUT
LDAC
WR
WR
PD
D7-D0
CS WR
CS
LDAC
DB7
VDD
DB0
DATA BUS
CONTROL
INPUTS
DMD15
DATA BUS
DMD0
Figure 27. Typical Configuration Selecting the Internal
Reference
Figure 28 shows a typical setup for the AD7801 when using an
external reference. The reference range for the AD7801 is from
1 V to VDD/2 V. Higher values of reference can be incorporated
but will saturate the output at both the top and bottom end of
the transfer function. There is a gain of two from input to output
on the AD7801. Suitable references for 5 V operation are the
AD780 and REF192. For 3 V operation a suitable external
reference would be the AD589 a 1.23 V bandgap reference.
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
Figure 29. AD7801–ADSP-2101/ADSP-2103 Interface
AD7801–TMS320C20 Interface
Figure 30 shows an interface between the AD7801 and the
TMS320C20. Data is loaded to the AD7801 using the following
instruction:
OUT DAC, D
DAC = Decoded DAC Address.
D = Data Memory Address.
VDD = 3V TO 5V
A15
0.1mF
10mF
ADDRESS BUS
A0
VIN
EXT REF VOUT
GND
VDD
REF IN
0.1mF
CLR
AD7801*
AGND DGND
IS
AD7801
VOUT
D7-D0
ADDR
DECODE
LDAC
STRB
CS
WR
WR
LDAC
VDD
R/W
DATA BUS
CS
TMS320C20
VOUT
PD
AD780/REF192 WITH VDD = 5V
OR
AD589 WITH VDD = 3V
EN
DB7
DB0
CONTROL
INPUTS
D15
DATA BUS
Figure 28. Typical Configuration Using An External
Reference
D0
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
Figure 30. AD7801–TMS320C20 Interface
–10–
REV. 0
AD7801
In the circuit shown the LDAC is hardwired low thus the DAC
output is updated on the rising edge of WR. Some applications
may require synchronous updating of the DAC in the AD7801.
In this case the LDAC signal can be driven from an external
timer or can be controlled by the microprocessor. One option
for synchronous updating is to decode the LDAC from the address bus so a write operation at this address will synchronously
update the DAC output. A simple OR gate with one input
driven from the decoded address and the second input from the
WR signal will implement this function.
AD7801–8051/8088 Interface
VDD = 3V TO 5V
0.1mF
R4
20kΩ
10mF
R3
10kΩ
VIN
EXT REF VOUT
REF IN
0.1mF
GND
CLR
AD820/
OP295
VDD AGND DGND
D7-D0
–5V
AD7801
R1
10kΩ
CS
WR
LDAC
R2
20kΩ
VDD
Figure 31 shows a serial interface between the AD7801 and the
8051/8088 processors.
±5V
VOUT
PD
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
+5V
DATA
BUS
CONTROL
INPUTS
Figure 32. Bipolar Operation Using the AD7801
A15
Decoding Multiple AD7801s in a System
ADDRESS BUS
A8
AD7801*
ADDR
DECODE
EN
PSEN OR DEN
WR
WR
LDAC
8051/8088*
ALE
CS
OCTAL
LATCH
DB7
DB0
AD7
DATA BUS
AD0
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
The CS pin on the AD7801 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to one
channel in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the Enable input on the
74HC139 should be brought to its inactive state while the
Coded Address inputs are changing state. Figure 33 shows a
diagram of a typical setup for decoding multiple AD7801
devices in a system. The built-in power-on reset circuit on the
AD7801 ensures that the outputs of all DACs in the system
power up with zero volts on their outputs.
Figure 31. AD7801–8051/8088 Interface
AD7801
DATA BUS
APPLICATIONS
Bipolar Operation Using the AD7801
WR
VOUT
WR
The AD7801 has been designed for unipolar operation but
bipolar operation is possible using the circuit in Figure 32. The
circuit shown is configured for an output voltage range of –5 V
to +5 V. Rail-to-rail operation at the amplifier output is achievable
by using an AD820 or OP295 as the output amplifier.
D0
D7
VDD
1G
VCC
1Y0
ENABLE
1A
1B
The output voltage for any input code can be calculated as
follows:
CODED
ADDRESS
1Y1
1Y2
WR
74HC139
)
LDAC
AD7801
CS
1Y3
  R4
 2V REF D
 R4 
−V REF   
V O =  R2 1+  / R1+ R2 × 

 256 
 R3 
  R3
(
CS
D0
D7
VOUT
LDAC
DGND
AD7801
CS
Where D is the decimal equivalent of the code loaded to the
DAC and VREF is the reference voltage input.
VOUT
WR
D0
D7
With VREF = 2.5 V, R1 = R3 = 10 kΩ and R2 = R4 = 20 kΩ and
VDD = 5 V.
10D
VO = 
 –5
 256 
LDAC
AD7801
CS
VOUT
WR
D0
D7
LDAC
Figure 33. Decoding Multiple AD7801s
REV. 0
–11–
AD7801
VDD = 5V
AD7801 as a Digitally Programmable Indicator
A digitally programmable upper limit detector using the DAC is
shown in Figure 34. The upper limit for the test is loaded to the
DAC, which in turn sets the limit for the CMP04. If a signal at
the VIN input is not below the programmed value, an LED will
indicate the Fail condition.
VSOURCE
0.1µF
10µF
LOAD
VIN
EXT REF VOUT
VDD
REF IN
+5V
VOUT
0.1µF
GND
2N3904/
BC107
AD820/
OP295
AD7801
+5V
10 F
0.1 F
VDD
VIN
1kΩ
FAIL
AD780/ REF192
WITH VDD = 5V
1kΩ
PASS
AGND DGND
4.7kΩ
REFIN
470Ω
AD7801
VOUT
D7
Figure 35. Programmable Current Source
PASS/
D0
Coarse and Fine Adjustment using two AD7801s
1/4
CMP-04
DVDD
DGND
1/6
74HC05
AGND
Figure 34. Digitally Programmable Indicator
Programmable Current Source
Figure 35 shows the AD7801 used as the control element of a
programmable current source. In this circuit the full-scale
current is set to 1 mA. The output voltage from the DAC is
applied across the current setting resistor of 4.7 kΩ in series with
the full-scale setting resistor of 470 Ω. Suitable transistors to
place in the feedback loop of the amplifier include the BC107
and the 2N3904, which enable the current source to operate
from a minimum VSOURCE of 6 V. The operating range is
determined by the operating characteristics of the transistor.
Suitable amplifiers include the AD820 and the OP295, both of
which have rail-to-rail operation on their outputs. The current
for any digital input code can be calculated as follows:
I=
The two DACs can be paired together to form a coarse and fine
adjustment function for a setpoint as shown in Figure 36. In this
circuit, the first DAC is used to provide the coarse adjustment
and the second DAC is used to provide the fine adjustment.
Varying the ratio of R1 and R2 will vary the relative effect of the
coarse and fine tune elements in the circuit. For the resistor
values shown, the second DAC has a resolution of 148 µV
giving a fine tune range of 38 mV (approximately 2 LSB) for
operation with a VDD of 5 V and a reference of 2.5 V. The
amplifier shown allows a rail-to-rail output voltage to be
achieved on the output. A typical application for the circuit
would be in a setpoint controller.
(2 V REF D )
(256 (5 kΩ))
VDD = 5V
R3
51.2kΩ
0.1µF
R4
390Ω
10µF
+5V
VIN
EXT REF VOUT
GND
REF IN
0.1µF
R1
390Ω
VDD
AD820/
OP295
VO
VOUT
AD7801
AGND DGND
AD780/ REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
REF IN
0.1µF
VDD
VOUT
AD7801
R2
51.2kΩ
AGND DGND
Figure 36. Coarse and Fine Adjustment
–12–
REV. 0
AD7801
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7801 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD7801 is in a system where multiple devices
require an AGND to DGND connection, the connection should
be made at one point only, a star ground point which should be
established as closely as possible to the AD7801. The AD7801
should have ample supply bypassing of 10 µF in parallel with
0.1 µF located as close to the package as possible, ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitors should have low Effective
Series Resistance (ESR) and Effective Series Inductance (ESI),
such as the common ceramic types, which provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
REV. 0
The power supply lines of the AD7801 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board and should never be run near
reference inputs. Avoid crossover of digital and analog signals.
Traces on opposite sides of the board should run at right angles
to each other. This reduces the effect of feedthrough through
the board. A microstrip technique is by far the best, but not
always possible with a double-sided board. In this technique, the
component side of the board is dedicated to the ground plane
while signal traces are placed on the solder side.
–13–
AD7801
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Wide Body SOIC
(R-20)
11
1
10
PIN 1
0.4193 (10.65)
0.3937 (10.00)
20
0.2992 (7.60)
0.2914 (7.40)
0.5118 (13.00)
0.4961 (12.60)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0500 0.0192 (0.49)
0°
(1.27) 0.0138 (0.35) SEATING 0.0125 (0.32)
PLANE
BSC
0.0091 (0.23)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
20-Lead TSSOP
(RU-20)
0.260 (6.60)
0.252 (6.40)
11
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
20
1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
10
PIN 1
0.0433
(1.10)
MAX
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
–14–
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
REV. 0
–15–
–16–
PRINTED IN U.S.A.
C2995–12–4/97