CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE (TOP VIEW) Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine Differential Clock Outputs Output Reference Voltage (VREF ) Allows Distribution From a Single-Ended Clock Input Packaged In a 28-Pin Plastic Chip Carrier description 5 VCC Y7 Y6 Y6 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN) to nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-Ω transmission lines. Y8 Y8 Y7 Y0 Y0 Y1 VCC Y1 Y2 Y2 VCC Y4 Y3 Y3 D NC VREF CLKIN VCC CLKIN NC GND D Differential Low-Voltage Pseudo-ECL NC – No internal connection The VREF output can be strapped to the CLKIN input for a single-ended CLKIN input. The CDCVF111 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS CLKIN CLKIN Yn Yn X X L H H L H L H L H L L VREF VREF L H H L L H L H L H H VREF VREF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 logic diagram (positive logic) 25 24 23 21 20 19 18 17 CLKIN CLKIN 28 16 2 14 13 12 11 10 9 7 6 5 VREF 3 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "80 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 mW Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 recommended operating conditions VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level TA Operating free-air temperature fclock Input frequency MIN MAX UNIT 3 3.6 V VCC = 3 V to 3.6 V VCC = 3.3 V VCC–1.165 2.135 VCC–0.88 2.42 V VCC = 3 V to 3.6 V VCC = 3.3 V VCC–1.81 1.49 VCC–1.475 1.825 V –40 85 °C 650 MHz V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VREF VOH TEST CONDITIONS MIN MAX UNIT VCC –1.38 1.92 VCC –1.26 2.04 V VCC = 3 V to 3.6 V, TA = 0°C to 85°C, f(max) = 650 MHz VCC –1.12 VCC – 0.83 VCC = 3 V to 3.6 V, TA = –40°C to 85°C, f(max) = 650 MHz VCC –1.15 VCC – 0.83 2.275 2.42 VCC = 3 V to 3.6 V VCC = 3.3 V IREF = 100 µA A VCC = 3.3 V VCC = 3 V to 3.6 V TA = 0°C to 85°C, f(max) = 650 MHz VOL II ICC (Internal) V VCC = 3 V to 3.6 V, TA = –40°C to 85°C, f(max) = 650 MHz VCC = 3.3 V VI = 2.4 V, IO = 0, VCC –1.86 VCC –1.49 VCC –1.86 VCC –1.52 1.49 1.68 VCC = 3 .6 V VCC = 3 .6 V 150 µA 100 mA switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (see Figure 1 and Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT tPLH tPHL CLKIN CLKIN CLKIN, Y Y Y, 450 600 ps tsk(o) Y, Y 50 ps tsk(pr) Y, Y 150 ps tr tf Y Y Y, 600 ps POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 200 3 CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 ESD information ESD MODELS LIMIT Human Body Model (HBM) 2.0 kV Machine Model (MM) 200 V Charge Device Model (CDM) 2.0 kV thermal information THERMAL AIR FLOW (CFM) PIN PLCC CDCVF111 28 28-PIN 0 150 250 500 UNIT RθJA High K 48 44 42 39 °C/W RθJA Low K 70 58 52 46 °C/W RθJC High K 22 °C/W RθJC Low K 28 °C/W PARAMETER MEASUREMENT INFORMATION VCC = 2 V Oscilloscope LVPECL Driver ZO = 50 Ω Yn 50 Ω Yn ZO = 50 Ω 50 Ω VEE = –1.3 V LOAD CIRCUIT (See Note B) Y, Y Outputs 80% 20% tr VOH 80% 20% VOL tf VOLTAGE WAVEFORMS RISE AND FALL TIMES CLKIN VCC – 0.9 V VCC – 1.7 V CLKIN tPLH tPHL VOH Y Outputs VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 45 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns. B. For additonal signal interface, see the Interfacing Between LVPECL, LVDS, and CML application note, Literature Number SCAA056. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 CLKIN CLKIN Y0 Y0 tPLH1 tPHL1 tPLH2 tPHL2 tPLH3 tPHL3 tPLH4 tPHL4 tPLH5 tPHL5 tPLH6 tPHL6 tPLH7 tPHL7 tPLH8 tPHL8 tPLH9 tPHL9 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 NOTES: A. Output skew, tsk(o), is calculated as the greater of: – The difference between the fastest and slowest tPLHn (n = 1, 2, . . . 9) – The difference between the fastest and slowest tPHLn (n = 1, 2, . . . 9) B. Process skew, tsk(pr), is calculated as the greater of: – The difference between the fastest and slowest tPLHn (n = 1, 2, . . . 9) – The difference between the fastest and slowest tPHLn (n = 1, 2, . . . 9) across multiple devices C. For additional information on skew and propagation delay parameters, see the Defining Skew, Propagation Delay, Phase-Offset (Phase Error) application note, literature number SCAA055. Figure 2. Waveforms for Calculation of tsk(o), tsk(pr) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 MECHANICAL DATA FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 19-May-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCVF111FN ACTIVE PLCC FN 28 37 TBD CU Level-1-220C-UNLIM CDCVF111FNR ACTIVE PLCC FN 28 750 TBD CU Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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