ETC DPL4519G Sound processor for digital and analog surround system Datasheet

PRELIMINARY DATA SHEET
MICRONAS
Edition Oct. 31, 2000
6251-512-1PD
DPL 4519G
Sound Processor for
Digital and Analog
Surround Systems
MICRONAS
DPL 4519G
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
4
5
6
1.
1.1.
1.2.
Introduction
Features of the DPL 4519G
Application Fields of the DPL 4519G
7
7
8
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8
8
8
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8
8
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10
11
11
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13
2.
2.1.
2.2.
2.3.
2.4.
2.5.
2.5.1.
2.6.
2.6.1.
2.6.1.1.
2.6.1.2.
2.6.1.3.
2.6.1.4.
2.6.2.
2.6.3.
2.6.3.1.
2.6.3.2.
2.6.3.3.
2.6.3.4.
2.6.4.
2.7.
2.7.1.
2.7.2.
2.8.
2.8.1.
2.8.2.
2.8.3.
2.8.4.
2.9.
2.10.
Functional Description
Architecture of the DPL 4519G Family
Preprocessing I2S Input Signals
Selection of Internal Processed Surround Signals
Source Selection and Output Channel Matrix
Audio Baseband Processing
Main and Aux Outputs
Surround Processing
Surround Processing Mode
Decoder Matrix
Surround Reproduction
Center Modes
Useful Combinations of Surround Processing Modes
Examples
Application Tips for using 3D-PANORAMA
Sweet Spot
Clipping
Loudspeaker Requirements
Cabinet Requirements
Input and Output Levels for Dolby Surround Pro Logic
SCART Signal Routing
SCART Out Select
Stand-by Mode
I2S Bus Interfaces
Synchronous I2S-Interface(s)
Asynchronous I2S-Interface
Multichannel I2S-Output
Asynchronous Multichannel I2S-Input
Digital Control I/O Pins
Clock PLL Oscillator and Crystal Specifications
14
14
14
14
15
15
16
16
16
16
16
16
3.
3.1.
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.1.5.
3.1.5.1.
3.1.5.2.
3.1.5.3.
3.1.5.4.
3.2.
Control Interface
I2C Bus Interface
Device and Subaddresses
Internal Hardware Error Handling
Description of CONTROL Register
Protocol Description
Proposals for General DPL 4519G I2C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start-Up Sequence: Power-Up and I2C Controlling
2
Micronas
PRELIMINARY DATA SHEET
DPL 4519G
Contents, continued
Page
Section
Title
16
16
19
19
21
21
33
34
34
34
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.4.
3.5.
3.5.1.
DPL 4519G Programming Interface
User Registers Overview
Description of User Registers
Write Registers on I2C Subaddress 10hex
Read Registers on I2C Subaddress 11hex
Write Registers on I2C Subaddress 12hex
Read Registers on I2C Subaddress 13hex
Programming Tips
Examples of Minimum Initialization Codes
Micronas Dolby Digital chipset (with MAS 3528E)
35
35
37
40
43
45
47
47
48
48
48
49
50
50
51
52
53
54
56
58
58
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.2.3.
4.6.3.
4.6.3.1.
4.6.3.2.
4.6.3.3.
4.6.3.4.
4.6.3.5.
4.6.3.6.
4.6.3.7.
4.6.3.8.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Pin Configurations
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions (TA = 0 to 70 °C)
General Recommended Operating Conditions
Analog Input and Output Recommendations
Crystal Recommendations
Characteristics
General Characteristics
Digital Inputs, Digital Outputs
Reset Input and Power-Up
I2C-Bus Characteristics
I2S-Bus Characteristics
Analog Baseband Inputs and Outputs, AGNDC
Power Supply Rejection
Analog Performance
61
61
62
5.
5.1.
5.2.
Appendix A: Application Information
Phase Relationship of Analog Outputs
Application Circuit
64
6.
Data Sheet History
License Notice:
“Dolby Pro Logic” and “Dolby Digital” are trademarks of Dolby Laboratories.
Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to
use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
Micronas
3
DPL 4519G
PRELIMINARY DATA SHEET
Sound Processor for Digital and Analog Surround
Systems
The hardware and software description in this document is valid for the DPL 4519G version A1 and following versions.
1. Introduction
The DPL 4519G processor is designed as part of the
Micronas chip set for digital and analog Surround Systems i. e. Dolby Digital, MPEG 2 Audio, or Dolby ProLogic. The combination of MAS 3528E, DPL 4519G,
and MSP 44x0G is a complete 5.1 channel Dolby Digital decoder and playback solution, while DPL 4519G
and MSP 44x0G alone, represent a complete Dolby
Surround Pro Logic system.
The DPL 4519G receives its incoming data via highly
flexible I2S interfaces. The three I2S input interfaces
can be configured as three asynchronous I2S inputs or
two synchronous and one asynchronous interface. In
the latter case, the asynchronous interface allows
reception of 2-8 channels with arbitrary sample rate
ranging from 8 to 48 kHz. The synchronization is performed by means of an adaptive high-quality sample
rate converter.
I2S
I2S
I2S3
I2S
(2..8-channel)
SCART1
The baseband processing including e.g. balance,
bass, treble, and loudness is performed at a fixed sample rate of 48 kHz.
Fig. 1–1 shows a simplified functional block diagram of
the DPL 4519G.
The DPL 4519G is pin-compatible to members of the
MSP 34xx family. This speeds up PCB development
for customers using MSPs.
The software interface of the DPL 4519G is also
largely the same as for members of the MSP family.
The ICs are produced in submicron CMOS technology
and are available in PQFP80, PLQFP64 and in
PSDIP64 packages.
ProLogic
processing
SCART2
SCART3
SCART4
DAC
Main
Subwoofer
Source Select
I2S2
Similar to the multichannel I2S input interface, the DPL
is provided with an 8-channel I2S output interface,
which can be connected to a MSP 44x0G. Therefore
all 8 channels can be routed to each output in both
ICs.
Main
Sound
Processing
Prescale
I2S1
In an application together with the Dolby Digital
decoder MAS 3528E, eight channels (left, right, surround left, surround right, center, subwoofer, Pro Logic
encoded left, Pro Logic encoded right) are fed in and
processed in the DPL 4519G.
AUX
Sound
Processing
DAC
AUX
I2S
(8-channel)
DAC
SCART
Output
Select
SCART1
SCART2
MONO
Fig. 1–1: Simplified block diagram of the DPL 4519G
4
Micronas
PRELIMINARY DATA SHEET
DPL 4519G
1.1. Features of the DPL 4519G
– 8-channel asynchonous I2S input interface (multichannel mode)
+ 2 synchronous I2S input channels (e.g. for MSP and ADR)
or
3 asynchronous two-channel I2S input interfaces
– Main and AUX channel with balance, bass, treble, loudness, volume
– 5-band graphic equalizer for Main channel
– Dolby Surround Pro Logic Adaptive Matrix
– Micronas Effect Matrix
– Micronas “3D-Panorama” virtualizer compliant to “Virtual Dolby Surround” technology
– Micronas Panorama sound mode (3D Surround sound via two loudspeakers)
– Noise Generator
– Spatial Effect for Surround
– 30-ms Surround delay
– Surround matrix control: Adaptive/Passive/Effect
– Center mode control: Normal/Phantom/Wide/Off
– Surround reproduction control: Rear speaker, Front speaker, Panorama, 3D-Panorama
– Two digital input/output pins controlled by I2C bus
Fig. 1–2 shows a typical Dolby Digital application using DPL 4519G, MSP 4450G, and MAS 3528E.
Micronas
5
DPL 4519G
PRELIMINARY DATA SHEET
1.2. Application Fields of the DPL 4519G
S/PDI1
Input
Buffer
MPEG
SID*
SII*
SIC*
AC-3
I2S-In: Slave
SPDO
L
R
2
Ls
Rs
SOD3
SOD2
SOD1
SOD
SOI
SOC
C/
Sub
Lt
Rt
Dolby Digital / Pro Logic Configurations
Example 1:
- internal L, C, R
- internal woofer for low freq. of L, (C), R
- ext. Surround speakers S L, SR
- ext. Subwoofer for SUB channel.
Noise
Gen.
SID
SII
SIC
Amp./
Osc.
18.432 MHz
S/PDIF Out
PCM-Format (Lt/Rt or L/R or Lo/Ro)
or Loop-through (e.g. DTS)
Multipl.
PCM
S/PDI2
Post Processing
Delay Lines
AC-3, MPEG L2, PCM or other Format
Deemphasis
S/PDIF In 1/2
PLL
Synth.
CLKO
Example 2:
- internal Left and Right used as C
- internal woofer for low freq. of C
- ext. L, R
- ext. Surround speakers S L, SR
- ext. Subwoofer for SUB channel.
MAS 3528E
Dolby Digital Decoder
MPEG-L2 Decoder
Configuration Examples
I2S_Inputs
1
2
I2S-Mode:Multichannel Mode auf D0
(6 - 8 Channels, fs=32, 44.1 or 48 kHz,
16,18,....32 Bit)
3
I2S_1_L
I2S_1_R
I2S_WS3
I2S_CL3
I2S_2_L
I2S_2_R
AUDIO_
CL_OUT
normal
2-8 Ch. Input
(LT, RT,L, R
SL, SR,C, SUB)
I2S_3_Lt
I2S_3_Rt
18.432
MHz
Dolby Digital /
Pro Logic
1
2
-------
Cint
SUBext
(Cint)
Lext
SUBext
Rext
-----
SL
SR
SL
SR
-----
Lt
Rt
Lt
Rt
---
L, R
C, SUB
SL, SR
Lt, Rt
L, R
C, SUB
SL, SR
Lt, Rt
L
Subw
R
Lint
Subwint
Rint
Cint
Subwint
Cint
L
R
Lt
Rt
Lt
Rt
L
R
Lt
Rt
Lt
Rt
L
R
Lt
Rt
Lt
Rt
L, R
L, R
L, R
Main
Bass
Treble
Balance
Volume
D/A
analog
Volume
Bass
Treble
Balance
Volume
D/A
analog
Volume
Aux
SCART1
L
6 Channel
Loop-through
or
Dolby
Pro Logic
Decoder
D/A
R
SL
I2S_Out_L/R
SR
C
SUB
I2S_WS
I2S_CL
Dolby
Digital
Upgrade
Module
Volume
DPL 4519G
Pro Logic Decoder
Dolby Digital: (L t, Rt, L, R, SL, SR, C, SUB)
Pro Logic: (L t, Rt, L, R, C, SubW)
Basic
TVSound
System
I2S_Inputs
1
18.432
MHz
SCART1_In
SCART4_In
3
I2S_1_L
I2S_1_R
I2S_WS
I2S_CL
I2S_2_L
I2S_2_R
2-8
Channel
Serial
Input
I2S_3_Lt
I2S_3_Rt
I2S_3_L
I2S_3_R
I2S_3_SL
I2S_3_SR
I2S_3_C
I2S_3_SUB
SoundProcess.
Balance
Volume
D/A
analog
Volume
Bass
Treble
Balance
Volume
D/A
analog
Volume
.
.
.
Main
Aux
SCART1
Volume
D/A
Volume
D/A
SCART2
Demod
SIF-IN
2
2
I2S_WS3
I2S_CL3
I2S_Out_L/R
A/D
MSP 4450G
Multistandard Sound Processor
Fig. 1–2: Typical DPL 4519G application
6
Micronas
I2S
Interface
Interface
I2 S
I2 S
Interface
synchronization
(11hex )
(4Dhex)
(36hex )
(49hex )
(4Ahex)
(4Bhex)
(4Chex)
Surround
Processing
SUB
SUB
SR
SL
R
C
SR
SL
R
L
C
(36hex)
I2S_3 Resorting Matrix
Noise
Generator
Prescale
I2S3
L
Rt
Lt
Prescale
I2S2
Prescale
(12hex)
(16hex)
10
9
8
7
6
5
Source Select
(48hex )
Surround
Channel
Matrix
(0Ahex)
SCART1
Channel
Matrix
(0Bhex)
I2S
Channel
Matrix
(09hex)
Aux
Channel
Matrix
(08hex)
Σ
(07hex )
Σ
(01hex)
D
A
(30hex)
Balanc
(2Chex)
Subwoofer Level
Adjust
Balance
Beeper
Volume
(31/32/33hex )
Bass/
Treble/
Loudness
(14hex)
(02/03/04hex )
(20..25hex )
Bass/
Treble/
Loudness/
Equalizer
Fig. 2–1: Signal flow block diagram of the DPL 4519G (input and output names correspond to pin names)
MONO_IN
SC4_IN_R
SC4_IN_L
SC3_IN_R
SC3_IN_L
SC2_IN_R
SC2_IN_L
SC1_IN_R
SC1_IN_L
I2S_DA_IN3
(async. 8-48 kHz)
I2S_CL3
I2S_WS3
I2S_DA_IN2
(sync. 48kHz)
I2S_CL
I2S_WS
I2S_DA_IN1
(sync. 48kHz)
I2S1
Internal/External Switch
Micronas
D
D
A
A
SCART1_L/R
I2S
Interface
(06hex)
Volume
(00hex)
Volume
SCART Output Select
Main
Channel
Matrix
SC2_OUT_R
SC2_OUT_L
SC1_OUT_R
SC1_OUT_L
I2S_DA_OUT
(sync. 48kHz)
DACA_R
DACA_L
DACM_SUB
DACM_R
DACM_L
PRELIMINARY DATA SHEET
DPL 4519G
2. Functional Description
2.1. Architecture of the DPL 4519G Family
Fig. 2–1 shows a simplified block diagram of the IC.
7
DPL 4519G
PRELIMINARY DATA SHEET
2.2. Preprocessing I2S Input Signals
2.6. Surround Processing
The I2S inputs can be adjusted in level by means of the
I2S prescale registers.
2.6.1. Surround Processing Mode
The I2S_3 interface is able to receive more than two
channels (see Section 2.6. on page 8). The incoming
signals can be resorted by a programmable matrix in
order to obtain a certain order, which means an unified
postprocessing afterwards.
Since the I2S_3 interface is asynchronous, incoming
sound signals with arbitrary sample rates in the range
of 8-48 kHz are interpolated to 48 kHz by means of an
adaptive high quality sample rate converter. Therefore
all subsequent processing is calculated on a fixed
sampling rate, which even can be synchronized to
I2S_WS e.g. to a MSP 4450 being locked to an incoming NICAM signal.
Surround sound processing is controlled by three functions:
The "Decoder Matrix" defines which method is used to
create a multichannel signal (L, C, R, S) out of a stereo
input.
The "Surround Reproduction" determines whether the
surround signal “S” is fed to surround speakers. If no
surround speaker is actually connected, it defines the
method that is used to create surround effects.
The “Center Mode” determines how the center signal
“C” is to be processed. It can be left unmodified, distributed to left and right, discarded or high pass filtered, whereby the low pass signals are distributed to
left and right.
2.3. Selection of Internal Processed
Surround Signals
Instead of having an multichannel input via the I2S_3
interface, a multichannel signal can be created by an
internal Dolby Pro Logic decoder. In that case channels 3..8 of the multichannel input are replaced by the
internally generated signals.
2.4. Source Selection and Output Channel Matrix
The Source Selector makes it possible to distribute all
source signals (I2S input signals) to the desired output
channels (Main, Aux, etc.). All input and output signals
can be processed simultaneously. Each source channel is identified by a unique source address.
For each output channel, the output channel matrix
can be set to sound A (left mono), sound B (right
mono), stereo, or mono (sound left and right).
2.5. Audio Baseband Processing
2.5.1. Main and Aux Outputs
The following baseband features are implemented in
the Main and Aux output channels: bass/treble, loudness, balance, and volume. A square wave beeper can
be added to these outputs. The Main channel additionally supports an equalizer function (this is not simultaneously available with bass/treble).
8
2.6.1.1. Decoder Matrix
The Decoder Matrix allows three settings:
– ADAPTIVE:
The Adaptive Matrix is used for Dolby Surround Pro
Logic. Even sound material not encoded in Dolby
Surround will produce good surround effects in this
mode. The use of the Adaptive Matrix requires a
license from Dolby Laboratories (See License
Notice on page 3).
– PASSIVE:
A simple fixed matrix is used for surround sound.
– EFFECT:
A fixed matrix that is used for mono sound and special effects. With Adaptive or Passive Matrix no surround signal is present in case of mono, moreover in
Adaptive mode even the left and right output channels carry no signal (or just low frequency signals in
case of Center Mode = NORMAL). If surround
sound is still required for mono signals, the Effect
Matrix can be used. This forces the surround channel to be active. The Effect Matrix can be used
together with 3D-PANORAMA. The result will be a
pseudo stereo effect or a broadened stereo image
respectively.
Micronas
PRELIMINARY DATA SHEET
2.6.1.2. Surround Reproduction
DPL 4519G
2.6.1.4. Useful Combinations of
Surround Processing Modes
Surround sound can be reproduced with four choices:
– REAR_SPEAKER:
If there are any surround speakers connected to the
system, this mode should be used. Useful loudspeaker combinations are (L, C, R, S) or (L, R, S).
– FRONT_SPEAKER:
If there is no surround speaker connected, this
mode can be used. Surround information is mixed to
left and right output but without creating the illusion
of a virtual speaker. It is similar to stereo but an
additional center speaker can be used. This mode
should be used with the Adaptive decoder Matrix
only. Useful loudspeaker combinations are (L, C, R)
(Note: the surround output channel is muted).
– PANORAMA:
The surround information is mixed to left and right in
order to create the illusion of a virtual surround
speaker. Useful loudspeaker combinations are (L,
C, R) or (L, R) (Note: the surround output channel is
muted).
– 3D-PANORAMA:
Like PANORAMA with improved effect. This algorithm has been approved by the Dolby Laboratories
for compliance with the "Virtual Dolby Surround"
technology. Useful loudspeaker combinations are
(L, C, R) or (L, R) (Note: the surround output channel is muted).
2.6.1.3. Center Modes
Four center modes are supported:
– NORMAL:
small center speaker connected, L and R speakers
have better bass capability. Center signal is high
pass filtered.
In principle, "Decoder Matrix", "Surround Reproduction", and "Center Modes" are independent settings (all
"Decoder Matrix" settings can be used with all "Surround Reproduction" and "Center Modes") but there
are some combinations that do not create "good"
sound. Useful combinations are
Surround Reproduction and Center Modes
– REAR_SPEAKER:
This mode is used if surround speakers are available. Useful center modes are NORMAL, WIDE,
PHANTOM, and OFF.
– FRONT_SPEAKER:
This mode can be used if no surround speaker but a
center speaker is connected. Useful center modes
are NORMAL and WIDE.
– PANORAMA or 3D-PANORAMA:
No surround speaker used. Two (L and R) or three
(L, R, and C) loudspeakers can be used. Useful
center modes are NORMAL, WIDE, PHANTOM,
and OFF.
Center Modes and Decoder Matrix
– PHANTOM:
Should only be used together with ADAPTIVE
Decoder Matrix.
– NORMAL and WIDE:
Can be used together with any Surround Decoder
Matrix.
– OFF:
This mode can be used together with the PASSIVE
and EFFECT Decoder Matrix (no center speaker
connected).
– WIDE:
L, R, and C speakers all have good bass capability.
– PHANTOM:
No center speaker used. Center signal is distributed
to L and R (Note: the center output channel C is
muted).
– OFF:
No center speaker used. Center signal C is discarded (Note: the center output channel C is
muted).
Micronas
9
DPL 4519G
PRELIMINARY DATA SHEET
2.6.2. Examples
Table 2–1 shows some examples of how these modes
can be used to configure the IC. The list is not
intended to be complete, more modes are possible.
Table 2–1: Examples of Surround Configurations
Configurations
Speaker
Configuration1)
Surround Processing Mode
Register (4Bhex)
Decoder Matrix
[15:8]
Surround
Reproduction
[7:4]
Center Mode
[3:0]
−
−
−
(L,C,R,S)
ADAPTIVE
REAR_
SPEAKER
NORMAL
WIDE
(L,R,S)
ADAPTIVE
REAR_
SPEAKER
PHANTOM
Dolby 3 Stereo
(L,C,R)
ADAPTIVE
FRONT_
SPEAKER
NORMAL
WIDE
Virtual Dolby Surround
(L,R)
ADAPTIVE
3D_PANORAMA
PHANTOM
(L,C,R)
ADAPTIVE
3D_PANORAMA
NORMAL
WIDE
4-Channel Surround
(L,C,R,S)
PASSIVE
REAR_
SPEAKER
NORMAL
WIDE
3-Channel Surround
(L,R,S)
PASSIVE
REAR_
SPEAKER
OFF
2-Channel Micronas 3D Surround Sound (MSS)
(L,R)
PASSIVE
3D_PANORAMA
OFF
3-Channel Micronas 3D Surround Sound (MSS)
(L,C,R)
PASSIVE
3D_PANORAMA
NORMAL
WIDE
4-Channel Surround for mono
(L,C,R,S)
EFFECT
REAR_
SPEAKER
NORMAL
WIDE
2-Channel Virtual Surround for mono
(L,R)
EFFECT
3D_PANORAMA
OFF
3-Channel Virtual Surround for mono
(L,C,R)
EFFECT
3D_PANORAMA
NORMAL
WIDE
Stereo
Stereo
(L,R)
Surround Modes as defined by Dolby Laboratories 2)
Dolby Surround Pro Logic
Surround Modes that use the Dolby Adaptive Matrix2)
3-Channel Virtual Surround
Passive Matrix Surround Sound
Special Effects Surround Sound
1)
2)
10
Speakers not in use are muted automatically.
The implementation in products requires a license from Dolby Laboratories Licensing Corporation (see note on page 3).
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
2.6.3. Application Tips for using 3D-PANORAMA
2.6.3.1. Sweet Spot
Good results are only obtained in a rather close area
along the middle axis between the two loudspeakers:
the sweet spot. Moving away from this position
degrades the effect.
Great care has to be taken with systems that use one
common subwoofer: A single loudspeaker cannot
reproduce virtual sound locations. The crossover frequency must be lower than 120 Hz.
2.6.3.4. Cabinet Requirements
During listening tests at Dolby Laboratories, no resonances in the cabinet should occur.
2.6.3.2. Clipping
For the test at Dolby Labs, it is very important to have
no clipping effects even with worst case signals. The
I2S-prescale register has to be set to values of max
10hex (16dec). This is sufficient in terms of clipping.
However, it was found, that by reducing the prescale to
a value lower than 16dec more convincing effects are
generated in case of very high dynamic signals. A
value of 10dec is a good compromise between overall
volume and additional headroom.
Test signals: sine sweep with 0 dBFS; L only, R only,
L&R equal phase, L&R anti phase.
Listening tests: Dolby Trailers (train trailer, city trailer,
canyon trailer...)
2.6.3.3. Loudspeaker Requirements
The loudspeakers used and their positioning inside the
TV set will greatly influence the performance of the virtualizer. The algorithm works with the direct sound
path. Reflected sound waves reduce the effect. So it’s
most important to have as much direct sound as possible, compared to indirect sound.
To obtain the approval for a TV set, Dolby Laboratories
require mounting the loudspeakers at the front of the
set. Loudspeakers radiating to the side of the TV set
will not produce convincing effects. Good directionality
of the loudspeakers towards the listener is optimal.
The virtualizer was specially developed for implementation in TV sets. Even for rather small stereo TV's, sufficient sound effects can be obtained. For small sets,
the loudspeaker placement should be to the side of the
CRT; for large screen sets (or 16:9 sets), mounting the
loudspeakers below the CRT is acceptable (large separation is preferred, low frequency speakers should be
outmost to avoid cancellation effects). Using external
loudspeakers with a large stereo base will not create
optimal effects.
The loudspeakers should be able to reproduce a wide
frequency range. The most important frequency range
starts from 160 Hz and ranges up to 5 kHz.
Micronas
Good material to check for resonances are the Dolby
Trailers or other dynamic sound tracks.
2.6.4. Input and Output Levels for
Dolby Surround Pro Logic
The nominal input level (input sensitivity) for the I2SInputs is −15 dBFS. The highest possible input level of
0 dBFS is accepted without internal overflow. The I2Sprescale value should be set to values of max 0 dB
(16dec).
With higher prescale values lower input sensitivities
can be accommodated. A higher input sensitivity is not
possible, because at least 15 dB headroom is required
for every input according to the Dolby specifications.
A full-scale left only input (0 dBFS) will produce a fullscale left only output (at 0 dB volume). The typical output level is 1.37 Vrms for DACM_L. The same holds
true for right only signals (1.37 Vrms for DACM_R). A
full-scale input level on both inputs (Lin=Rin=0 dBFS)
will give a center only output with maximum level. A
full-scale input level on both inputs (but Lin and Rin
with inverted phases) will give a surround-only signal
with maximum level.
For reproducing Dolby Pro Logic according to its specifications, the center and surround outputs must be
amplified by 3 dB with respect to the L and R output
signals. This can be done in two ways:
1. By implementing 3 dB more amplification for center
and surround loudspeaker outputs.
2. By always selecting volume for L and R 3 dB lower
than center and surround. Method 1 is preferable,
as method 2 lowers the achievable SNR for left and
right signals by 3 dB.
2.7. SCART Signal Routing
2.7.1. SCART Out Select
The SCART Output Select block includes full matrix
switching facilities. The switches are controlled by the
ACB user register (see page page 30).
11
DPL 4519G
PRELIMINARY DATA SHEET
2.7.2. Stand-by Mode
2.8.2. Asynchronous I2S-Interface
If the DPL 4519G is switched off by first pulling
STANDBYQ low and then (after >1 µs delay) switching
off DVSUP and AVSUP, but keeping AHVSUP (‘Standby’-mode), the SCART switches maintain their position and function. This allows the copying from
selected SCART-inputs to SCART-outputs in the TV
set’s stand-by mode.
The asynchronous I2S slave interface allows the
reception of digital audio signals with arbitrary sample
rates from 5 to 50 kHz. The synchronization is performed by means of an adaptive sample rate converter. No oversampling clock is required.
In case of power on or starting from stand-by (see
details on the power-up sequence in Fig. 4–19 on
page 52), all internal registers except the ACB register
(page 30) are reset to the default configuration (see
Table 3–5 on page 17). The reset position of the ACB
register becomes active after the first I2C transmission
into the Baseband Processing part (subaddress
12hex). By transmitting the ACB register first, the reset
state can be redefined.
2.8. I2S Bus Interfaces
The DPL 4519G has two kinds of interfaces: synchron
master/slave input/output interfaces running on 48 kHz
and an asynchron slave interface.
The interfaces accept a variety of formats with different
sample width, bit-orientation, and wordstrobe timing.
All I2S options are set by means of the MODUS or
I2S_CONFIG register.
2.8.1. Synchronous I2S-Interface(s)
The synchronous I2S bus interface consists of the
pins:
– I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 in
PQFP80 package):
I2S serial data input, 16, 18...32 bits per sample.
– I2S_DA_OUT:
I2S serial data output, 16, 18...32 bits per sample.
– I2S_CL:
I2S serial clock.
– I2S_WS:
I2S word strobe signal defines the left and right
sample.
If the DPL 4519G serves as the master on the I2S
interface, the clock and word strobe lines are driven by
the DPL 4519G. In this mode, only 16, 32 bits per
sample can be selected. In slave mode, these lines are
input to the DPL 4519G and the DPL 4519G clock is
synchronized to 384 times the I2S_WS rate (48 kHz).
An I2S timing diagram is shown in Fig. 4–21 on
page 55.
12
The following pins are used for the asynchronous I2S
bus interface (serve only as input):
– I2S_WS3
– I2S_CL3
– I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package).
The interface accepts I2S-input streams with MSB first
and with sample widths of 16,18...32 bits. With left/
right alignment and wordstrobe timing polarity, there
are additional parameters available for the adaption to
a variety of formats in the I2S CONFIGURATION register.
2.8.3. Multichannel I2S-Output
Bit[0:1] of the I2S CONFIGURATION register (see
page 20) switches the output to 8 channel multichannel output mode. The bit resolution per channel is 32
bit in master mode. While the first two channels can be
selected on the source select matrix, channels 3-8 are
always connected to the I2S_3 input channels 3-8.
Both, master and slave mode is possible, as long as as
the wordstrobe has only one positive edge per frame in
slave mode.
2.8.4. Asynchronous Multichannel I2S-Input
The DPL 4519G supports two kinds of asynchronous
multichannel input:
– the asynchronous I2S_3 interface can be switched
to multichannel mode (bit [8] of the I2S CONFIGURATION register is set to 1. The number of channels must be even and less or equal eight.
– All I2S input lines (I2S_DA_IN1, I2S_DA_IN2 and
I2S_DA_IN3 in PQFP80 package) can be switched
to asynchronous two channel mode (bit[2] set to 1 in
the I2S CONFIGURATION register). The common
clock is I2S_WS3 and I2S_CL3. No synchronous
I2S interfaces are available in this mode.
Micronas
PRELIMINARY DATA SHEET
DPL 4519G
2.9. Digital Control I/O Pins
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 30). This enables the controlling of external
hardware switches or other devices via I2C-bus.
The Modus Register can set the digital input/output
pins to high impedance (see page 19). So the pins can
be used as input. The current state can be read out of
the STATUS register (see page page 21).
2.10. Clock PLL Oscillator and
Crystal Specifications
The DPL 4519G derives all internal system clocks
from the 18.432 MHz oscillator. In I2S-slave mode of
the synchronous interface, the clock is phase-locked to
the corresponding source.
For proper performance, the DPL clock oscillator
requires a 18.432-MHz crystal. Note that for the
phase-locked modes (I2S-slave), crystals with tighter
tolerance are required. The asynchronous I2S3 slave
interface uses a different locking mechanism and does
not require tighter crystal tolerances.
Micronas
13
DPL 4519G
PRELIMINARY DATA SHEET
typical response time is about 0.3 ms. If the DPL cannot accept another complete byte of data until it has
performed some other function (for example, servicing
an internal interrupt), it will hold the clock line I2C_CL
LOW to force the transmitter into a wait state. The
positions within a transmission where this may happen
are indicated by “Wait” in Section 3.1.4. The maximum
wait period of the DPL during normal operation mode
is less than 1 ms.
3. Control Interface
3.1. I2C Bus Interface
3.1.1. Device and Subaddresses
The DPL 4519G is controlled via the I2C bus slave
interface.
The IC is selected by transmitting one of the
DPL 4519G device addresses. In order to allow up to
three DPL or MSP ICs to be connected to a single bus,
an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left
open, the DPL 4519G responds to different device
addresses. A device address pair is defined as a write
address and a read address (see Table 3–1).
3.1.2. Internal Hardware Error Handling
In case of any internal hardware error (e.g. interruption
of the power supply of the DPL), the DPL’s wait period
is extended to 1.8 ms. After this time period elapses,
the DPL releases data and clock lines.
Writing is done by sending the device write address,
followed by the subaddress byte, two address bytes,
and two data bytes. Reading is done by sending the
write device address, followed by the subaddress byte
and two address bytes. Without sending a stop condition, reading of the addressed data is completed by
sending the device read address and reading two
bytes of data. Refer to Section 3.1.4. for the I2C bus
protocol and to Section 3.4. “Programming Tips” on
page 34 for proposals of DPL 4519G I2C telegrams.
See Table 3–2 for a list of available subaddresses.
Indicating and solving the error status:
To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high.
Additionally, bit[14] of CONTROL is set to one. The
DPL can then be reset via the I2C bus by transmitting
the reset condition to CONTROL.
Indication of reset:
Besides the possibility of hardware reset, the DPL can
also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus.
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I2C bus is shown in
Fig. 4–21 on page 55.
Due to the internal architecture of the DPL 4519G, the
IC cannot react immediately to an I2C request. The
Table 3–1: I2C Bus Device Addresses
ADR_SEL
Low
(connected to DVSS)
High
(connected to DVSUP)
Left Open
Mode
Write
Read
Write
Read
Write
Read
DPL device address
80hex
81hex
84hex
85hex
88hex
89hex
Table 3–2: I2C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
0000 0000
00
Read/Write
Write: Software reset of DPL (see Table 3–3)
Read: Hardware error status of DPL
WR_DEM
0001 0000
10
Write
write address demodulator
RD_DEM
0001 0001
11
Write
read address demodulator
WR_DSP
0001 0010
12
Write
write address DSP
RD_DSP
0001 0011
13
Write
read address DSP
14
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
3.1.3. Description of CONTROL Register
Table 3–3: CONTROL as a Write Register
Name
Subaddress
Bit[15] (MSB)
Bits[14:0]
CONTROL
00 hex
1 : RESET
0 : normal
0
Table 3–4: CONTROL as a Read Register (only DPL 4519G-versions from A2 on)
Name
Subaddress
Bit[15] (MSB)
Bit[14]
Bits[13:0]
CONTROL
00 hex
Reset status after last reading of CONTROL:
0 : no reset occured
1 : reset occured
Internal hardware status:
0 : no error occured
1 : internal error occured
not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be
read once to be resetted.
3.1.4. Protocol Description
Write to DSP
S
Wait
write
device
address
ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P
high
low
high
low
Read from DSP
S
Wait
write
device
address
ACK sub-addr ACK addr-byte ACK addr-byte ACK S
high
low
read
device
address
Wait
ACK data-byte- ACK data-byte NAK P
high
low
Write to Control
S
Wait
write
device
address
ACK sub-addr ACK data-byte ACK data-byte ACK P
high
low
Read from Control
S
Wait
write
device
address
Note: S =
P=
ACK =
NAK =
Wait =
Micronas
ACK
00hex
ACK S
read
device
address
Wait
ACK data-byte- ACK data-byte NAK P
high
low
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
Acknowledge-Bit: LOW on I2C_DA from slave (= DPL, light gray) or master (= controller dark gray)
Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from DPL indicating internal error state
I2C-Clock line is held low, while the DPL is processing the I2C command.
This waiting time is max. 1 ms
15
DPL 4519G
PRELIMINARY DATA SHEET
1
0
I2C_DA
S
P
I2C_CL
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.5. Proposals for General DPL 4519G
I2C Telegrams
3.2. Start-Up Sequence:
Power-Up and I2C Controlling
3.1.5.1. Symbols
After POWER ON or RESET (see Fig. 4–21), the IC is
in an inactive state. All registers are in the reset position, the analog outputs are muted. The controller has
to initialize all registers for which a non-default setting
is necessary.
daw
dar
<
>
aa
dd
write device address (80hex, 84hex or 88hex)
read device address (81hex, 85hex or 89hex)
Start Condition
Stop Condition
Address Byte
Data Byte
3.3. DPL 4519G Programming Interface
3.3.1. User Registers Overview
3.1.5.2. Write Telegrams
<daw 00 d0 00>
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
write to CONTROL register
write data into demodulator
write data into DSP
The DPL 4519G is controlled by means of user registers. The complete list of all user registers is given in
the following tables. The registers are partitioned into
two sections:
1. Subaddress 10hex for writing, 11hex for reading and
3.1.5.3. Read Telegrams
2. Subaddress 12hex for writing, 13hex for reading.
read data from
CONTROL register
<daw 11 aa aa <dar dd dd> read data from demodulator
<daw 13 aa aa <dar dd dd> read data from DSP
Write and read registers are 16-bit wide, whereby the
MSB is denoted bit[15]. Transmissions via I2C bus
have to take place in 16-bit words (two byte transfers,
with the most significant byte transferred first). All write
registers, except MODUS and I2S CONFIGURATION,
are readable.
<daw 00 <dar dd dd>
3.1.5.4. Examples
<80 00 80 00>
<80 00 00 00>
<80 12 00 08 08 20>
<80 12 00 00 73 00>
RESET DPL statically
Clear RESET
Set Main channel
source to I2S3 - L/R
Set Main volume to 0 dB
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
accessed.
More examples of typical application protocols are
listed in Section 3.4. “Programming Tips” on page 34.
16
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–5: List of DPL 4519G Write Registers
Write Register
Address
(hex)
Bits
Description and Adjustable Range
Reset
See
Page
I2C Subaddress = 10hex ; Registers are not readable
MODUS
00 30
[15:0]
I2S options, D_CTR_I/O modes
00 00
19
I2S CONFIGURATION
00 40
[15:0]
Configuration of I2S format
00 00
20
24
2
2
I C Subaddress = 12hex ; Registers are all readable by using I C Subaddress = 13hex
Volume Main channel
Balance Main channel [L/R]
00 00
00 01
Balance mode Main
[15:8]
[+12 dB ... −114 dB, MUTE]
MUTE
[7:5]
[4:0]
1/8 dB Steps
must be set to 0
000bin
00000bin
[15:8]
[0...100 / 100% and 100 / 0...100%]
[−127...0 / 0 and 0 / −127...0 dB]
100%/100%
[7:0]
[Linear / logarithmic mode]
linear mode
25
Bass Main channel
00 02
[15:8]
[+20 dB ... −12 dB]
0 dB
26
Treble Main channel
00 03
[15:8]
[+15 dB ... −12 dB]
0 dB
27
Loudness Main channel
00 04
[15:8]
[0 dB ... +17 dB]
0 dB
28
[7:0]
[NORMAL, SUPER_BASS]
NORMAL
[15:8]
[+12 dB ... −114 dB, MUTE]
MUTE
[7:5]
[4:0]
1/8 dB Steps
must be set to 0
000bin
00000bin
[15:8]
[+12 dB ... −114 dB, MUTE]
Loudness filter characteristic
Volume Aux channel
Volume SCART1 output channel
Main source select
00 06
00 07
00 08
Main channel matrix
Aux source select
00 09
Aux channel matrix
SCART1 source select
00 0A
SCART1 channel matrix
I2S source select
I2S
00 0B
channel matrix
2
2
2
2
24
MUTE
29
[15:8]
[I S1, I S2, I S3 ch1&2, I S3 ch3&4,...]
undefined
23
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
23
[15:8]
[I2S1, I2S2, I2S3
undefined
23
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
23
[15:8]
[I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...]
undefined
23
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
23
[15:8]
[I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...]
undefined
23
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
23
ch1&2,
I2S3
ch3&4,...]
Prescale I2S3
00 11
[15:8]
[00hex ... 7Fhex]
10hex
21
Prescale I2S2
00 12
[15:8]
[00hex ... 7Fhex]
10hex
21
ACB: SCART Switches a. D_CTR_I/O
00 13
[15:0]
Bits [15:0]
00hex
30
Beeper
00 14
[15:0]
[00hex ... 7Fhex]/[00hex ... 7Fhex]
00/00hex
30
Prescale I2S1
00 16
[15:8]
[00hex ... 7Fhex]
10hex
21
Mode tone control
00 20
[15:8]
[BASS/TREBLE, EQUALIZER]
BASS/TREB
26
Equalizer Main ch. band 1
00 21
[15:8]
[+12 dB ... −12 dB]
0 dB
27
Equalizer Main ch. band 2
00 22
[15:8]
[+12 dB ... −12 dB]
0 dB
27
Equalizer Main ch. band 3
00 23
[15:8]
[+12 dB ... −12 dB]
0 dB
27
Equalizer Main ch. band 4
00 24
[15:8]
[+12 dB ... −12 dB]
0 dB
27
Equalizer Main ch. band 5
00 25
[15:8]
[+12 dB ... −12 dB]
0 dB
27
Subwoofer level adjust
00 2C
[15:8]
[0 dB ... −30 dB, mute]
0 dB
29
Micronas
17
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–5: List of DPL 4519G Write Registers, continued
Write Register
Address
(hex)
Bits
Description and Adjustable Range
Reset
See
Page
Balance Aux channel [L/R]
00 30
[15:8]
[0...100 / 100% and 100 / 0...100%]
[−127...0 / 0 and 0 / −127...0 dB]
100 %/100 %
25
[7:0]
[Linear mode / logarithmic mode]
linear mode
Balance mode Aux
Bass Aux channel
00 31
[15:8]
[+20 dB ... −12 dB]
0 dB
26
Treble Aux channel
00 32
[15:8]
[+15 dB ... −12 dB]
0 dB
27
Loudness Aux channel
00 33
[15:8]
[0 dB ... +17 dB]
0 dB
28
[7:0]
[NORMAL, SUPER_BASS]
NORMAL
Loudness filter characteristic
I2S3 Resorting
00 36
[15:8]
through, straight eight, l/r eight, l/r six, l/r four,
2ch through
00hex
22
Surround source select
00 48
[15:8]
[I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,...]
undefined
23
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO]
SOUNDA
23
Surround channel matrix
Spatial effect for surround processing
00 49
[15:8]
[0% - 100%]
00hex
31
Virtual surround effect strength
00 4A
[15:8]
[0% - 100%]
00hex
31
Decoder matrix
00 4B
[15:8]
[ADAPTIVE/PASSIVE/EFFECT]
00hex
32
Surround reproduction
[7:4]
[REAR_SPEAKER/FRONT_SPEAKER/PANORAMA/
3D_PANORAMA]
0hex
32
Center mode
[3:0]
[PHANTOM/NORMAL/WIDE/OFF]
0hex
32
Surround delay
00 4C
[15:0]
[5...31ms]
00hex
32
Noise Generator
00 4D
[15:0]
[NOISEL, NOISEC, NOISER, NOISES]
00hex
32
Table 3–6: List of DPL 4519G Read Registers
Read Register
Address
(hex)
Bits
Description and Adjustable Range
See
Page
[15:0]
Monitoring of settings e.g. D_CTR_I/O
21
[15:8]
[00hex ... FFhex]
33
[7:0]
[00hex ... FFhex]
33
[15:8]
[00hex ... FFhex]
33
[7:0]
[00hex ... FFhex]
33
I2C Subaddress = 11hex ; Registers are not writable
STATUS
02 00
I2C Subaddress = 13hex ; Registers are not writable
DPL hardware version code
00 1E
DPL major revision code
DPL product code
DPL ROM version code
18
00 1F
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
3.3.2. Description of User Registers
3.3.2.1. Write Registers on I2C Subaddress 10hex
Table 3–7: Write Registers on I2C Subaddress 10hex
Register
Address
Function
Name
MODUS Register
MODUS
MODUS
00 30hex
bit[15:8]
0
undefined, must be 0
bit[7]
0/1
active/tristate state of audio clock output pin
AUD_CL_OUT
0
1
word strobe alignment (synchronous I2S)
WS changes at data word boundary
WS changes one clock cycle in advance
bit[5]
0/1
master/slave mode of I2S interface
bit[4]
0/1
active/tristate state of I2S output pins
bit[6]
bit[3]
0
1
bit[2:0]
Micronas
0
state of digital output pins D_CTR_I/O_0 and _1
active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register)
tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
undefined, must be 0
19
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–7: Write Registers on I2C Subaddress 10hex, continued
Register
Address
Function
Name
I2S CONFIGURATION
00 40hex
I2S CONFIGURATION Register
I2S_CONFIG
I2S31)
bit[11]
I2S data alignment (must be 0 if bit[2] = 1)
0/1
left/right aligned
I2S3_ALIGN
bit[10]
wordstrobe polarity (must be 0 if bit[2] = 1)
1
0 = right, 1 = left
0
1 = right, 0 = left
I2S3_WS_POL
bit[9]
wordstrobe alignment (asynchronous I2S_3)
0
WS changes at data word boundary
1
WS changes one clock cycle in advance
I2S3_WS_MODE
bit[8]
Sample Mode
0/1
Two/Multi sample
I2S3_MSAMP
bit[7:4]
Word length of each data packet = (n−2)/2
bit[3]=0, bit[8]=1 (multi-sample input mode)
0111
16 bit
1000
18 bit
...
1111
32 bit
I2S3_MBIT
bit[3]=0, bit[8]=0 (two-sample input mode)
xxxx
16...32 bit, 18-bit valid
bit[3]=1, bit[8]=1 (multi-sample output mode)
1111
32 bit
bit[3]=1, bit[8]=0 (two-sample output mode)
0111
16 bit
1111
32 bit
bit[3]
I2S3 Mode
1
output (I2S3 CL/WS active)
0
input (I2S3 CL/WS tristate)
I2S3_MODE
I2S1/2/3 Timing
1
I2S3 timing for all I2S inputs (1/2/3)
0
default mode
I2S_TIMING
I2S1/2/3
bit[2]
I2S Out
bit[1:0]
1)
20
I2S_CL frequency and I2S_DA_OUT sample length
00
2 * 16 bit (1.536 MHz Clk)
01
2 * 32 bit (3.072 MHz Clk)
10
8 * 32 bit (12.288 MHz Clk)
I2S_CL3 frequency depends on bit[8] and bits[7:4] as follows:
[8] = 0, [7:4] = 0111
f = fs*(2*16)
[8] = 0, [7:4] = else
f = fs*(2*32)
[8] = 1
f = fs*(8*32)
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
3.3.2.2. Read Registers on I2C Subaddress 11hex
Table 3–8: Read Registers on I2C Subaddress 11hex
Register
Address
Function
Name
02 00hex
STATUS Register
STATUS
Contains the status of the D_CTR_I/O pins
bit[15:5]
undefined
bit[4]
0/1
low/high level of digital I/O pin D_CTR_I/O_1
bit[3]
0/1
low/high level of digital I/O pin D_CTR_I/O_0
bit[2:0]
undefined
3.3.2.3. Write Registers on I2C Subaddress 12hex
Table 3–9: Write Registers on I2C Subaddress 12hex
Register
Address
Function
Name
PREPROCESSING
00 16hex
00 12hex
00 11hex
PRE_I2S1
PRE_I2S2
PRE_I2S3
I2S1 Prescale
I2S2 Prescale
I2S3 Prescale
Defines the prescale value for digital I2S input signals
bit[15:8]
Micronas
00hex
10hex
7Fhex
off
0 dB gain (recommendation)
+18 dB gain (maximum gain)
21
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
I2S3 RESORTING MATRIX
00 36hex
I2S3 Resorting Matrix
(not mentioned bit combinations must not be used)
I2S3_Sort
Resorting of multichannel inputs
bit[15:8]
0000hex : 8 channel, “through”
1,2,3,4,5,6,7,8
Lt,Rt
Lt,Rt,Lvirtual,Rvirtual
→
→
→
0001hex : 8 channel, “straight eight”
1,2,3,4,5,6,7,8
→
→
L,R,SL,SR,C,LFE,Lt,Rt
1,2,3,4,5,6,7,8
Lt,Rt,--,--,--,--,--,-Lt,Rt,Lvirtual,Rvirtual,--,--,--,-7,8,1,2,3,4,5,6
Lt,Rt,L,R,SL,SR,C,LFE
0002hex : 8 channel, “left/right eight”, “MAS 3528E”
1,2,3,4,5,6,7,8
→ 4,8,1,5,2,6,3,7
→ Lt,Rt,L,R,SL,SR,C,LFE
L,SL,C,Lt,R,SR,LFE,Rt
0003hex : 6 channel, “left/right six”
1,2,3,4,5,6
L,SL,C,R,SR,LFE
→
→
-,-,1,4,2,5,3,6
--,--,L,R,SL,SR,C,LFE
0004hex : 4 channel, “left/right four”, ”External ProLogic”
1,2,3,4
→ -,-,1,3,4,4,2,L,C,R,S
→ --,--,L,R,SL,SR,C,-0010hex : 2 channel, “through”; “Internal ProLogic”
1,2
→ 1,2,+,+,+,+,+,+
→ Lt,Rt,LPL,RPL,SPL,SPL,CPL,SUBPL
Lt,Rt
“+”: channel will be replaced by internally generated signal
“XPL”: internally generated signal
22
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
SOURCE SELECT AND OUTPUT CHANNEL MATRIX
00 08hex
00 09hex
00 0Ahex
00 0Bhex
00 48hex
Source for:
Main Output
Aux Output
SCART1 DA Output
I2S Output
Surround Processing
bit[15:8]
5
I2S1 input
6
I2S2 input
7
I2S3 input channels 1&2 (e.g. Lt,Rt)1)
8
I2S3 input channels 3&4 (e.g. L,R)1) or
Pro Logic processed L, R
9
I2S3 input channels 5&6 (e.g. SL,SR)1) or
Pro Logic processed S, S (both channels same signal)
10
I2S3 input channels 7&8 (e.g. C,SUB)1) or
Pro Logic processed C, SUB
SRC_MAIN
SRC_AUX
SRC_SCART1
SRC_I2S
SRC_DPL
1)
exemplary channel assignment in a Micronas digital multichannel sound system with MAS 3528E and MSP 4450G.
00 08hex
00 09hex
00 0Ahex
00 0Bhex
00 48hex
Channel Matrix for:
Main Output
Aux Output
SCART1 DA Output
I2S Output
Surround Processing
bit[7:0]
00hex
10hex
20hex
30hex
MAT_MAIN
MAT_AUX
MAT_SCART1
MAT_I2S
MAT_DPL
Sound A Mono (or Left Mono)
Sound B Mono (or Right Mono)
Stereo (transparent mode)
Mono (L+R)/2
Usually the matrix modes should be set to “Stereo” (transparent).
Micronas
23
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
MAIN AND AUX PROCESSING
00 00hex
00 06hex
Volume Main
Volume Aux
bit[15:8]
volume table with 1 dB step size
+12 dB (maximum volume)
7Fhex
+11 dB
7Ehex
...
+1 dB
74hex
0 dB
73hex
−1 dB
72hex
...
−113 dB
02hex
−114 dB
01hex
Mute (reset condition)
00hex
Fast Mute
FFhex
bit[7:5]
higher resolution volume table
0
+0 dB
1
+0.125 dB increase in addition to the volume table
...
7
+0.875 dB increase in addition to the volume table
bit[4:0]
not used
must be set to 0
VOL_MAIN
VOL_AUX
With large scale input signals, positive volume settings may lead to signal clipping.
The DPL 4519G Main and Aux Volume function is divided into a digital and an
analog section. With Fast Mute, volume is reduced to mute position by digital
volume only. Analog volume is not changed. This reduces any audible DC plops.
To turn volume on again, the volume step that has been used before Fast Mute
was activated must be transmitted.
24
Micronas
PRELIMINARY DATA SHEET
DPL 4519G
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 01hex
00 30hex
Balance Main Channel
Balance Aux Channel
BAL_MAIN
BAL_AUX
bit[15:8]
Linear Mode
Left muted, Right 100%
7Fhex
Left 0.8%, Right 100%
7Ehex
...
Left 99.2%, Right 100%
01hex
Left 100%, Right 100%
00hex
Left 100%, Right 99.2%
FFhex
...
Left 100%, Right 0.8%
82hex
Left 100%, Right muted
81hex
bit[15:8]
Logarithmic Mode
Left −127 dB, Right 0 dB
7Fhex
Left −126 dB, Right 0 dB
7Ehex
...
Left −1 dB, Right 0 dB
01hex
Left 0 dB, Right 0 dB
00hex
Left 0 dB, Right −1 dB
FFhex
...
Left 0 dB, Right −127 dB
81hex
Left 0 dB, Right −128 dB
80hex
bit[3:0]
Balance Mode
linear
0hex
logarithmic
1hex
Positive balance settings reduce the left channel without affecting the right
channel; negative settings reduce the right channel leaving the left channel
unaffected.
Micronas
25
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 20hex
Tone Control Mode Main Channel
TONE_MODE
bit[15:8]
00hex
FFhex
bass and treble is active
equalizer is active
Defines whether Bass/Treble or Equalizer is activated for the Main channel.
Bass/Treble and Equalizer cannot work simultaneously. If Equalizer is used,
Bass and Treble coefficients must be set to zero and vice versa.
00 02hex
00 31hex
Bass Main Channel
Bass Aux Channel
bit[15:8]
normal range
+12 dB
60hex
+11 dB
58hex
...
+1 dB
08hex
0 dB
00hex
−1 dB
F8hex
...
−11 dB
A8hex
−12 dB
A0hex
bit[15:8]
extended range
+20 dB
7Fhex
+18 dB
78hex
+16 dB
70hex
+14 dB
68hex
BASS_MAIN
BASS_AUX
Higher resolution is possible: an LSB step in the normal range results in a gain
step of about 1/8 dB, in the extended range about 1/4 dB.
With positive bass settings, internal clipping may occur even with overall volume
less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result
in an overall positive gain.
26
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 03hex
00 32hex
Treble Main Channel
Treble Aux Channel
TREB_MAIN
TREB_AUX
bit[15:8]
78hex
70hex
...
08hex
00hex
F8hex
...
A8hex
A0hex
+15 dB
+14 dB
+1 dB
0 dB
−1 dB
−11 dB
−12 dB
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.
With positive treble settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not
recommended to set treble to a value that, in conjunction with volume, would
result in an overall positive gain.
00 21hex
00 22hex
00 23hex
00 24hex
00 25hex
Equalizer Main Channel Band 1 (below 120 Hz)
Equalizer Main Channel Band 2 (center: 500 Hz)
Equalizer Main Channel Band 3 (center: 1.5 kHz)
Equalizer Main Channel Band 4 (center: 5 kHz)
Equalizer Main Channel Band 5 (above: 10 kHz)
bit[15:8]
60hex
58hex
...
08hex
00hex
F8hex
...
A8hex
A0hex
EQUAL_BAND1
EQUAL_BAND2
EQUAL_BAND3
EQUAL_BAND4
EQUAL_BAND5
+12 dB
+11 dB
+1 dB
0 dB
−1 dB
−11 dB
−12 dB
Higher resolution is possible: an LSB step results in a gain step of about 1/8 dB.
With positive equalizer settings, internal clipping may occur even with overall
volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is
not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain.
Micronas
27
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 04hex
00 33hex
Loudness Main Channel
Loudness Aux Channel
LOUD_MAIN
LOUD_AUX
bit[15:8]
Loudness Gain
+17 dB
44hex
+16 dB
40hex
...
+1 dB
04hex
0 dB
00hex
bit[7:0]
Loudness Mode
normal (constant volume at 1 kHz)
00hex
Super Bass (constant volume at 2 kHz)
04hex
Higher resolution of Loudness Gain is possible: An LSB step results in a gain
step of about 1/4 dB.
Loudness increases the volume of low- and high-frequency signals, while keeping the amplitude of the 1-kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness
introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain.
The corner frequency for bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.
28
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 2Chex
Subwoofer Level Adjustment
SUBW_LEVEL
bit[15:8]
00hex
FFhex
...
E3hex
E2hex
...
80hex
0 dB
−1 dB
−29 dB
−30 dB
Mute
SCART OUTPUT CHANNEL
00 07hex
Micronas
Volume SCART1 Output Channel
bit[15:8]
volume table with 1 dB step size
+12 dB (maximum volume)
7Fhex
+11 dB
7Ehex
...
+1 dB
74hex
0 dB
73hex
−1 dB
72hex
...
−113 dB
02hex
−114 dB
01hex
Mute (reset condition)
00hex
bit[7:5]
higher resolution volume table
0
+0 dB
1
+0.125 dB increase in addition to the volume table
...
7
+0.875 dB increase in addition to the volume table
bit[4:0]
01hex
VOL_SCART1
this must be 01hex
29
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
SCART SWITCHES AND DIGITAL I/O PINS
00 13hex
ACB_REG
ACB Register
Defines the level of the digital output pins and the position of the SCART switches
bit[15]
0/1
low/high of digital output pin D_CTR_I/O_1
(MODUS[3]=0)
bit[14]
0/1
low/high of digital output pin D_CTR_I/O_0
(MODUS[3]=0)
bit[13:5]
SCART1 Output Select
xx00xx x0x SCART3 input to SCART1 output (RESET position)
xx01xx x0x SCART2 input to SCART1 output
xx10xx x0x MONO input to SCART1 output
xx11xx x0x SCART1 DA to SCART1 output
xx01xx x1x SCART1 input to SCART1 output
xx10xx x1x SCART4 input to SCART1 output
xx11xx x1x mute SCART1 output
bit[13:5]
SCART2 Output Select
00xxxx 0xx SCART1 DA to SCART2 output (RESET position)
01xxxx 0xx SCART1 input to SCART2 output
10xxxx 0xx MONO input to SCART2 output
01xxxx 1xx SCART2 input to SCART2 output
10xxxx 1xx SCART3 input to SCART2 output
11xxxx 1xx SCART4 input to SCART2 output
11xxxx 0xx mute SCART2 output
The RESET position becomes active at the time of the first write transmission
on the control bus to the audio processing part. By writing to the ACB register
first, the RESET state can be redefined.
BEEPER
00 14hex
30
Beeper Volume and Frequency
bit[15:8]
Beeper Volume
off
00hex
maximum volume
7Fhex
bit[7:0]
Beeper Frequency
16 Hz (lowest)
01hex
1 kHz
40hex
4 kHz
FFhex
BEEPER
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
SURROUND PROCESSING
00 49hex
Spatial Effects for Surround Processing
bit[15:8]
Spatial Effect Strength
Enlargement 100%
7Fhex
Enlargement 50%
3Fhex
...
Enlargement 1.5%
01hex
Effect off
00hex
bit[7:0]
00hex
SUR_SPAT
must be 0
Increases the perceived basewidth of the reproduced left and right front channels. Recommended value: 50% = 40hex.
00 4Ahex
Virtual Surround Effect Strength
bit[15:8]
bit[7:0]
SUR_3DEFF
Virtual Surround Effect Strength
Effect 100%
7Fhex
Effect 50%
3Fhex
...
01hex
00hex
Effect 1.5%
Effect off
00hex
must be 0
Strength of the surround effect in PANORAMA or 3D-PANORAMA mode. In
other Surround Reproduction Modes this value must be set to 0. Recommended
value: 66% = 54hex.
Micronas
31
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–9: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 4Bhex
Surround Processing Mode
SUR_MODE
bit[15:8]
Decoder Matrix
ADAPTIVE (for Dolby Surround Pro Logic and Virtual
00hex
Surround)
PASSIVE (for MSS, Micronas Surround Sound)
10hex
EFFECT (used for special effects and monophonic
20hex
signals)
DEC_MAT
bit[7:4]
Surround Reproduction
SUR_REPRO
bit[3:0]
0hex
REAR_SPEAKER: The surround signal is reproduced by
rear speakers.
3hex
FRONT_SPEAKER: The surround signal is redirected to
the front channels. There is no physical rear speaker connected.
5hex
PANORAMA: The surround signal is processed and redirected to the left and right front speakers in order to create
the illusion of a virtual rear speaker, although no physical
rear speaker is connected.
6hex
3D-PANORAMA: The surround signal is processed and
redirected to the left and right front speakers in order to
create the illusion of a virtual rear speaker, although no
physical rear speaker is connected.
Center Mode
0hex
1hex
2hex
3hex
00 4Chex
PHANTOM mode (no Center speaker connected)
NORMAL mode (small Center speaker)
WIDE mode (large Center speaker)
OFF mode (Center output of the Surround Decoder is
discarded. Useful only in special effect modes)
SUR_DELAY
Surround Delay
bit[15:8]
bit[7:0]
C_MODE
05hex
06hex
...
1Fhex
5 ms delay in surround path (lowest)
6 ms delay in surround path
00hex
must be 0
31 ms delay in surround path (highest))
For Dolby Surround Pro Logic designs, only 20 ms fixed or 15-30 ms variable
delay must be used. This register has no effect in 3D-PANORAMA and PANORAMA mode.
00 4Dhex
SUR_NOISE
Noise Generator
bit[15:8]
00hex
80hex
Noise generator off
Noise generator on
bit[7:0]
A0hex
B0hex
C0hex
D0hex
Noise on left channel
Noise on center channel
Noise on right channel
Noise on surround channel
Determines the active channel for the noise generator.
32
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
3.3.2.4. Read Registers on I2C Subaddress 13hex
Table 3–10: Read Registers on I2C Subaddress 13hex
Register
Address
Function
Name
DPL 4519G VERSION READOUT Registers
00 1Ehex
DPL Hardware Version Code
bit[15:8]
01hex
DPL_HARD
DPL 4519G-A1
A change in the hardware version code defines hardware optimizations that
may have influence on the chip’s behavior. The readout of this register is identical to the hardware version code in the chip’s imprint.
DPL_FAMILY
DPL Family Code
bit[7:4]
3hex
DPL 4519G-A1
DPL Major Revision Code
bit[3:0]
00 1Fhex
7hex
DPL 4519G-A1
DPL_PRODUCT
DPL Product Code
bit[15:8]
13hex
DPL_REVISION
DPL 4519G - A1
By means of the DPL-Product Code, the control processor is able to decide
which TV sound standards have to be considered.
DPL ROM Version Code
bit[7:0]
41hex
42hex
DPL_ROM
DPL 4519G - A1
DPL 4519G - A2
A change in the ROM version code defines internal software optimizations,
that may have influence on the chip’s behavior, e.g. new features may have
been included. While a software change is intended to create no compatibility
problems, customers that want to use the new functions can identify new
DPL 4519G versions according to this number.
Micronas
33
DPL 4519G
PRELIMINARY DATA SHEET
3.4. Programming Tips
3.5. Examples of Minimum Initialization Codes
This section describes the preferred method for initializing the DPL 4519G. The initialization is grouped into
four sections: analog signal path, input processing for
I2S, and output processing. See Fig. 2–1 on page 7 for
a complete signal flow.
Initialization of the DPL 4519G according to these listings reproduces sound of the selected standard on the
Main output. All numbers are hexadecimal. The examples have the following structure:
1. Perform an I2C controlled reset of the IC.
2. Write MODUS register
SCART Signal Path
1. Select the source for each analog SCART output
with the ACB register.
I2S Inputs
1. Select preferred prescale for I2S inputs
(set to 0 dB after RESET).
2. Select I2S3 Resorting matrix according to the channel order of your decoding device (e.g. for
MAS 3528E chose mode 02hex)
Output Channels
1. Select the source channel and matrix for each output.
3. Set Source Selection for Main channel
(with matrix set to STEREO).
4. Set Volume Main channel to 0 dB.
3.5.1. Micronas Dolby Digital chipset
(with MAS 3528E)
<84 00 80 00>
// Softreset
<84 00 00 00>
<84 10 00 30 00 20>
// MODUS-Register: I2S slave
<84 10 00 40 01 F2>
// I2S-config-Register
<84 12 00 36 00 02>
// I2S3 Resorting matrix, Mode 2
<84 12 00 0B 07 20>
// Source Sel. I2S_out = I2S3 - Lt/Rt
<84 12 00 08 08 20>
// Source Sel. Main_out = I2S3 - L/R
<84 12 00 00 73 00>
// Main Volume 0 dB
2. Set audio baseband features
3. Select volume for each output.
34
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4. Specifications
4.1. Outline Dimensions
23 x 0.8 = 18.4 ± 0.1
0.17 ± 0.04
41
40
80
25
1
14 ± 0.1
0.37 ± 0.04
17.2 ± 0.15
0.8
65
15 x 0.8 = 12.0 ± 0.1
64
0.8
1.3 ± 0.05
24
2.7 ± 0.1
23.2 ± 0.15
3 ±0.2
20 ± 0.1
0.1
SPGS705000-3(P80)/1E
Fig. 4–1:
80-Pin Plastic Quad Flat Pack
(PQFP80)
Weight approximately 1.61 g
Dimensions in mm
15 x 0.5 = 7.5 ± 0.1
0.145 ± 0.055
64
17
1
0.22 ± 0.05
16
1.4 ± 0.05
1.75
12 ± 0.2
15 x 0.5 = 7.5 ± 0.1
32
0.5
49
12 ± 0.2
1.75
0.5
33
10 ± 0.1
48
1.5 ± 0.1
0.1
10 ± 0.1
D0025/3E
Fig. 4–2:
64-Pin Plastic Low-Profile Quad Flat Pack
(PLQFP64)
Weight approximately 0.35 g
Dimensions in mm
Micronas
35
DPL 4519G
PRELIMINARY DATA SHEET
SPGS703000-1(P64)/1E
33
1
32
19.3 ±0.1
18 ±0.05
0.8 ±0.2
3.8 ±0.1
64
57.7 ±0.1
1.778
0.48 ±0.06
3.2 ±0.2
0.28 ±0.06
1 ±0.05
20.3 ±0.5
31 x 1.778 = 55.1 ±0.1
Fig. 4–3:
64-Pin Plastic Shrink Dual-Inline Package
(PSDIP64)
Weight approximately 9.0 g
Dimensions in mm
36
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4.2. Pin Connections and Short Descriptions
NC = not connected (leave vacant for future compatibility reasons)
TP = Test Pin (leave vacant - pin is used for production test only)
LV = leave vacant
X = obligatory; connect as described in application circuit diagram
AHVSS: connect to AHVSS
Pin No.
Pin Name
Type
Connection
Short Description
(if not used)
PQFP
80-pin
PLQFP
64-pin
PSDIP
64-pin
1
64
8
NC
2
1
9
I2C_CL
3
2
10
4
3
5
LV
Not connected
IN/OUT
X
I2C clock
I2C_DA
IN/OUT
X
I2C data
11
I2S_CL
IN/OUT
LV
I2S clock
4
12
I2S_WS
IN/OUT
LV
I2S word strobe
6
5
13
I2S_DA_OUT
OUT
LV
I2S data output
7
6
14
I2S_DA_IN1
IN
LV
I2S1 data input
8
7
15
TP
LV
Test pin
9
8
16
TP
LV
Test pin
10
9
17
TP
LV
Test pin
11
−
−
DVSUP
X
Digital power supply +5 V
12
−
−
DVSUP
X
Digital power supply +5 V
13
10
18
DVSUP
X
Digital power supply +5 V
14
−
−
DVSS
X
Digital ground
15
−
−
DVSS
X
Digital ground
16
11
19
DVSS
X
Digital ground
−
12
20
I2S_DA_IN2/3
IN
LV
I2S2/3-data input
17
−
−
I2S_DA_IN2
IN
LV
PQFP80: pin 22 separate I2S_DA_IN3
18
13
21
NC
LV
Not connected
19
14
22
I2S_CL3
IN
LV
I2S3 clock
20
15
23
I2S_WS3
IN
LV
I2S3 word strobe
21
16
24
RESETQ
IN
X
Power-on-reset
22
−
−
I2S_DA_IN3
IN
LV
I2S3-data input
23
−
−
NC
LV
Not connected
24
17
25
DACA_R
OUT
LV
Aux out, right
25
18
26
DACA_L
OUT
LV
Aux out, left
Micronas
37
DPL 4519G
Pin No.
PRELIMINARY DATA SHEET
Pin Name
Type
Connection
Short Description
(if not used)
PQFP
80-pin
PLQFP
64-pin
PSDIP
64-pin
26
19
27
VREF2
27
20
28
DACM_R
28
21
29
DACM_L
29
22
30
NC
30
23
31
DACM_SUB
31
24
32
32
−
33
X
Reference ground 2
OUT
LV
Loudspeaker out, right
OUT
LV
Loudspeaker out, left
LV
Not connected
LV
Subwoofer output
NC
LV
Not connected
−
NC
LV
Not connected
25
33
SC2_OUT_R
OUT
LV
SCART output 2, right
34
26
34
SC2_OUT_L
OUT
LV
SCART output 2, left
35
27
35
VREF1
X
Reference ground 1
36
28
36
SC1_OUT_R
OUT
LV
SCART output 1, right
37
29
37
SC1_OUT_L
OUT
LV
SCART output 1, left
38
30
38
CAPL_A
X
Volume capacitor AUX
39
31
39
AHVSUP
X
Analog power supply 8.0 V
40
32
40
CAPL_M
X
Volume capacitor MAIN
41
−
−
NC
LV
Not connected
42
−
−
NC
LV
Not connected
43
−
−
AHVSS
X
Analog ground
44
33
41
AHVSS
X
Analog ground
45
34
42
AGNDC
X
Analog reference voltage
46
−
−
NC
LV
Not connected
47
35
43
SC4_IN_L
IN
LV
SCART 4 input, left
48
36
44
SC4_IN_R
IN
LV
SCART 4 input, right
49
37
45
ASG
AHVSS
Analog Shield Ground
50
38
46
SC3_IN_L
IN
LV
SCART 3 input, left
51
39
47
SC3_IN_R
IN
LV
SCART 3 input, right
52
40
48
ASG
AHVSS
Analog Shield Ground
53
41
49
SC2_IN_L
IN
LV
SCART 2 input, left
54
42
50
SC2_IN_R
IN
LV
SCART 2 input, right
55
43
51
ASG
AHVSS
Analog Shield Ground
56
44
52
SC1_IN_L
LV
SCART 1 input, left
38
OUT
IN
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Type
Connection
Short Description
(if not used)
PQFP
80-pin
PLQFP
64-pin
PSDIP
64-pin
57
45
53
SC1_IN_R
58
46
54
59
−
60
IN
LV
SCART 1 input, right
NC
LV
Not connected
−
NC
LV
Not connected
47
55
MONO_IN
LV
Mono input
61
−
−
AVSS
X
Analog ground
62
48
56
AVSS
X
Analog ground
63
−
−
NC
LV
Not connected
64
−
−
NC
LV
Not connected
65
−
−
AVSUP
X
Analog power supply +5 V
66
49
57
AVSUP
X
Analog power supply +5 V
67
50
58
NC
LV
Not connected
68
51
59
NC
LV
Not connected
69
52
60
NC
LV
Not connected
70
53
61
TESTEN
IN
AVSS
Test pin
71
54
62
XTAL_IN
IN
X
Crystal oscillator
72
55
63
XTAL_OUT
OUT
X / LV
IN
Crystal oscillator (See also 4.3.
Pin descriptions)
73
56
64
TP
LV
Test pin
74
57
1
AUD_CL_OUT
LV
Audio clock output (18.432 MHz)
-
−
−
NC
LV
Not connected
75
58
2
NC
LV
Not connected
76
59
3
NC
LV
Not connected
77
60
4
D_CTR_I/O_1
IN/OUT
LV
D_CTR_I/O_1
78
61
5
D_CTR_I/O_0
IN/OUT
LV
D_CTR_I/O_0
79
62
6
ADR_SEL
IN
X
I2C Bus address select
80
63
7
STANDBYQ
IN
X
Stand-by (low-active)
Micronas
OUT
39
DPL 4519G
4.3. Pin Descriptions
Pin numbers refer to the 80-pin PQFP package
Pin 1, NC – Pin not connected.
Pin 2, I2C_CL – I2C Clock Input/Output (Fig. 4–8)
Via this pin, the I2C-bus clock signal has to be supplied. The signal can be pulled down by the DPL in
case of wait conditions.
Pin 3, I2C_DA – I2C Data Input/Output (Fig. 4–8)
Via this pin, the I2C-bus data is written to or read from
the DPL.
Pin 4, I2S_CL – I2S Clock Input/Output (Fig. 4–11)
Clock line for the I2S bus. In master mode, this line is
driven by the DPL; in slave mode, an external I2S clock
has to be supplied.
Pin 5, I2S_WS – I2S Word Strobe Input/Output
(Fig. 4–11)
Word strobe line for the I2S bus. In master mode, this
line is driven by the DPL; in slave mode, an external
I2S word strobe has to be supplied.
Pin 6, I2S_DA_OUT1 – I2S Data Output (Fig. 4–7)
Output of digital serial sound data of the DPL on the
I2S bus.
Pin 7, I2S_DA_IN1 – I2S Data Input 1 (Fig. 4–9)
First input of digital serial sound data to the DPL via
the I2S bus.
Pin 8, 9, 10, TP– Test pins
Pins 11, 12, 13, DVSUP* – Digital Supply Voltage
Power supply for the digital circuitry of the DPL. Must
be connected to a power supply.
Pins 14, 15, 16, DVSS* – Digital Ground
Ground connection for the digital circuitry of the DPL.
Pin 17, I2S_DA_IN2 – I2S Data Input 2 (Fig. 4–9)
Second input of digital serial sound data to the DPL via
the I2S bus. In all packages except PQFP-80-pin this
pin is also connected to the asynchronous I2S interface 3.
Pins 18, NC – Pin not connected.
Pins 19, I2S_CL3 – I2S Clock Input (Fig. 4–9)
Clock line for the I2S bus. Since only a slave mode is
available an external I2S clock has to be supplied.
Pins 20, I2S_WS3 – I2S Word Strobe Input (Fig. 4–9)
Word strobe line for the I2S bus. Since only a slave
mode is available an external I2S word strobe has to
be supplied.
40
PRELIMINARY DATA SHEET
Pin 21, RESETQ – Reset Input (Fig. 4–9)
In the steady state, high level is required. A low level
resets the DPL 4519G.
Pin 22, I2S_DA_IN3 – I2S Data Input 3 (Fig. 4–9)
Asynchronous input of digital serial sound data to the
DPL via the I2S bus.
Pins 23, NC – Pin not connected.
Pins 24, 25, DACA_R/L – Aux Outputs (Fig. 4–16)
Output of the aux signal. A 1 nF capacitor to AHVSS
must be connected to these pins. The DC offset on
these pins depends on the selected aux volume.
Pin 26, VREF2 – Reference Ground 2
Reference analog ground. This pin must be connected
separately to ground (AHVSS). VREF2 serves as a
clean ground and should be used as the reference for
analog connections to the Main and AUX outputs.
Pins 27, 28, DACM_R/L – Main Outputs
(Fig. 4–16)
Output of the Main signal. A 1 nF capacitor to AHVSS
must be connected to these pins. The DC offset on
these pins depends on the selected Main volume.
Pin 29 NC – Pin not connected.
Pin 30, DACM_SUB – Subwoofer Output (Fig. 4–16)
Output of the subwoofer signal. A 1-nF capacitor to
AHVSS must be connected to this pin. Due to the low
frequency content of the subwoofer output, the value
of the capacitor may be increased for better suppression of high-frequency noise. The DC offset on this pin
depends on the selected Main volume.
Pins 31, 32 NC – Pin not connected.
Pins 33, 34, SC2_OUT_R/L – SCART2 Outputs
(Fig. 4–18)
Output of the SCART2 signal. Connections to these
pins must use a 100-Ω series resistor and are intended
to be AC-coupled.
Pin 35, VREF1 – Reference Ground 1
Reference analog ground. This pin must be connected
separately to ground (AHVSS). VREF1 serves as a
clean ground and should be used as the reference for
analog connections to the SCART outputs.
Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs
(Fig. 4–18)
Output of the SCART1 signal. Connections to these
pins must use a 100-Ω series resistor and are intended
to be AC-coupled.
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Pin 38, CAPL_A – Volume Capacitor Aux (Fig. 4–13)
A 10-µF capacitor to AHVSUP must be connected to
this pin. It serves as a smoothing filter for volume
changes in order to suppress audible plops. The value
of the capacitor can be lowered to 1-µF if faster
response is required. The area encircled by the trace
lines should be minimized; keep traces as short as
possible. This input is sensitive for magnetic induction.
Pin 55, ASG* – Analog Shield Ground
Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
Pins 56, 57 SC1_IN_L/R – SCART1 Inputs (Fig. 4–15)
The analog input signal for SCART1 is fed to this pin.
Analog input connection must be AC-coupled.
Pin 58, NC – Pin not connected
Pin 39, AHVSUP* – Analog Power Supply High Voltage
Power is supplied via this pin for the analog circuitry of
the DPL. This pin must be connected to the +8 V supply. (+5 V-operation is possible with restrictions in performance)
Pin 40, CAPL_M – Volume Capacitor Loudspeakers
(Fig. 4–13)
A 10-µF capacitor to AHVSUP must be connected to
this pin. It serves as a smoothing filter for volume
changes in order to suppress audible plops. The value
of the capacitor can be lowered to 1 µF if faster
response is required. The area encircled by the trace
lines should be minimized; keep traces as short as
possible. This input is sensitive for magnetic induction.
Pin 59, NC – Pin not connected.
Pin 60 MONO_IN – Mono Input (Fig. 4–15)
The analog mono input signal is fed to this pin AC-coupled.
Pins 61, 62, AVSS* – Analog Power Supply Voltage
Ground connection for the analog IF input circuitry of
the DPL.
Pins 63, 64, NC – Pins not connected.
Pins 65, 66, AVSUP* – Analog Power Supply Voltage
Power is supplied via this pin for the analog IF input circuitry of the DPL. This pin must be connected to the
+5 V supply.
Pins 41, 42, NC – Pins not connected.
Pin 67, 68, 69, NC – Pin not connected.
Pins 43, 44, AHVSS* – Ground for Analog Power Supply High Voltage
Ground connection for the analog circuitry of the DPL.
Pin 45, AGNDC – Internal Analog Reference Voltage
This pin serves as the internal ground connection for
the analog circuitry. It must be connected to the VREF
pins with a 3.3-µF and a 100-nF capacitor in parallel.
This pins shows a DC level of typically 3.73 V.
Pin 46, NC – Pin not connected.
Pins 47, 48, SC4_IN_L/R – SCART4 Inputs
(Fig. 4–15)
The analog input signal for SCART4 is fed to this pin.
Analog input connection must be AC-coupled.
Pin 49, ASG* – Analog Shield Ground
Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
Pins 50, 51, SC3_IN_L/R – SCART3 Inputs
(Fig. 4–15)
The analog input signal for SCART3 is fed to this pin.
Analog input connection must be AC-coupled.
Pin 52, ASG* – Analog Shield Ground
Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
Pin 70, TESTEN – Test Enable Pin (Fig. 4–9)
This pin enables factory test modes. For normal operation, it must be connected to ground.
Pins 71, 72 XTAL_IN, XTAL_OUT – Crystal Input and
Output Pins (Fig. 4–12)
These pins are connected to an 18.432 MHz crystal
oscillator which is digitally tuned by integrated capacitances. An external clock can be fed into XTAL_IN
(leave XTAL_OUT vacant in this case). The audio
clock output signal AUD_CL_OUT is derived from the
oscillator. External capacitors at each crystal pin to
ground (AVSS) are required. It should be verified by
layout, that no supply current for the digital circuitry is
flowing through the ground connection point.
Pin 73, TP – This pin is needed for factory tests. For
normal operation, it must be left vacant.
Pin 74, AUD_CL_OUT – Audio Clock Output
(Fig. 4–12)
This is the 18.432 MHz main clock output.
Pins 75, 76, NC – Pins not connected.
Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/
Output Pins (Fig. 4–11)
General purpose input/output pins.
Pins 53, 54 SC2_IN_L/R – SCART2 Inputs (Fig. 4–15)
The analog input signal for SCART2 is fed to this pin.
Analog input connection must be AC-coupled.
Micronas
41
DPL 4519G
PRELIMINARY DATA SHEET
Pin 79, ADR_SEL – I2C Bus Address Select
(Fig. 4–10)
This pin selects the device address for the DPL. (see
Table 3–1).
Pin 80, STANDBYQ – Stand-by
In normal operation, this pin must be High. If the DPL
is switched to ‘Stand-by’-mode, the SCART switches
maintain
their
position
and
function.
(see
Section 2.7.2.)
* Application Note:
All ground pins should be connected to one low-resistive ground plane.
All supply pins should be connected separately with
short and low-resistive lines to the power supply.
Decoupling capacitors from DVSUP to DVSS, AVSUP
to AVSS, and AHVSUP to AHVSS are recommended
as closely as possible to these pins. Decoupling of
DVSUP and DVSS is most important. We recommend
using more than one capacitor. By choosing different
values, the frequency range of active decoupling can
be extended. In our application boards we use: 220 pF,
470 pF, 1.5 nF, and 10 µF. The capacitor with the lowest value should be placed nearest to the pins.
The ASG pins should be connected as closely as possible to the IC ground. They are intended for leading
with the SCART signals as shield lines and should not
be connected to ground at the SCART-connector
again.
42
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4.4. Pin Configurations
SC2_IN_L
SC2_IN_R
ASG
SC3_IN_R
ASG
SC3_IN_L
SC1_IN_L
ASG
SC1_IN_R
SC4_IN_R
NC
SC4_IN_L
NC
NC
MONO_IN
AGNDC
AVSS
AHVSS
AVSS
AHVSS
NC
NC
NC
NC
AVSUP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65
40
CAPL_M
AVSUP
66
39
AHVSUP
NC
67
38
CAPL_A
NC
68
37
SC1_OUT_L
NC
69
36
SC1_OUT_R
TESTEN
70
35
VREF1
XTAL_IN
71
34
SC2_OUT_L
XTAL_OUT
72
33
SC2_OUT_R
TP
73
32
NC
AUD_CL_OUT
74
31
NC
NC
75
30
DACM_SUB
NC
76
29
NC
D_CTR_I/O_1
77
28
DACM_L
D_CTR_I/O_0
78
27
DACM_R
ADR_SEL
79
26
VREF2
STANDBYQ
80
25
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DPL 4519G
1
2
3
4
5
6
7
8
9
DACA_L
DACA_R
NC
I2C_CL
NC
I2C_DA
I2S_DA_IN3
I2S_CL
RESETQ
I2S_WS
I2S_WS3
I2S_DA_OUT
I2S_CL3
I2S_DA_IN1
NC
NC
I2S_DA_IN2
NC
DVSS
NC
DVSS
DVSUP
DVSUP
DVSS
DVSUP
Fig. 4–4: 80-pin PQFP package
Micronas
43
DPL 4519G
PRELIMINARY DATA SHEET
SC2_IN_L
ASG
SC2_IN_R
SC3_IN_R
ASG
SC3_IN_L
SC1_IN_L
ASG
SC1_IN_R
SC4_IN_R
NC
SC4_IN_L
MONO_IN
AGNDC
AVSS
AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AVSUP
49
32
CAPL_M
NC
50
31
AHVSUP
NC
51
30
CAPL_A
NC
52
29
SC1_OUT_L
TESTEN
53
28
SC1_OUT_R
XTAL_IN
54
27
VREF1
XTAL_OUT
55
26
SC2_OUT_L
TP
56
25
SC2_OUT_R
AUD_CL_OUT
57
24
NC
NC
58
23
DACM_SUB
NC
59
22
NC
D_CTR_I/O_1
60
21
DACM_L
C_CTR_I/O_0
61
20
DACM_R
ADR_SEL
62
19
VREF2
STANDBYQ
63
18
DACA_L
NC
64
17
DACA_R
DPL 4519G
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
RESETQ
I2C_CL
I2S_WS3
I2C_DA
I2S_CL3
I2S_CL
NC
I2S_WS
I2S_DA_OUT
I2S_DA_IN2/3
DVSS
I2S_DA_IN1
TP
DVSUP
TP
TP
Fig. 4–5: 64-pin PLQFP package
44
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4.5. Pin Circuits
AUD_CL_OUT
1
64
TP
NC
2
63
XTAL_OUT
NC
3
62
XTAL_IN
D_CTR_I/O_1
4
61
TESTEN
D_CTR_I/O_0
5
60
NC
ADR_SEL
6
59
NC
STANDBYQ
7
58
NC
NC
8
57
AVSUP
I2C_CL
9
56
AVSS
I2C_DA
10
55
MONO_IN
I2S_CL
11
54
NC
12
53
SC1_IN_R
13
52
SC1_IN_L
I2S_DA_IN1
14
51
ASG
TP
15
50
SC2_IN_R
TP
16
49
SC2_IN_L
TP
17
48
ASG
DVSUP
18
47
SC3_IN_R
DVSS
19
46
SC3_IN_L
I2S_DA_IN2/3
20
45
ASG
NC
21
44
SC4_IN_R
I2S_CL3
22
43
SC4_IN_L
I2S_WS3
23
42
AGNDC
RESETQ
24
41
AHVSS
DACA_R
25
40
CAPL_M
DACA_L
26
39
AHVSUP
VREF2
27
38
CAPL_A
DACM_R
28
37
SC1_OUT_L
DACM_L
29
36
SC1_OUT_R
NC
30
35
VREF1
DACM_SUB
31
34
SC2_OUT_L
NC
32
33
SC2_OUT_R
DPL 4519G
I2S_WS
I2S_DA_OUT
Fig. 4–6: 64-pin PSDIP package
Pin numbers refer to the PQFP80 package.
DVSUP
P
N
GND
Fig. 4–7: Output Pin 6
(I2S_DA_OUT)
N
GND
Fig. 4–8: Input/Output Pins 2 and 3
(I2C_CL, I2C_DA)
Fig. 4–9: Input Pins 7, 17, 21, 22, 70, and 80
(I2S_DA_IN1..3, RESETQ, TESTEN, STANDBYQ)
DVSUP
23 kΩ
23 kΩ
GND
ADR_SEL
Fig. 4–10: Input Pin 79 (ADR_SEL)
Micronas
45
DPL 4519G
PRELIMINARY DATA SHEET
DVSUP
AHVSUP
P
0...1.2 mA
N
3.3 kΩ
GND
Fig. 4–11: Input/Output Pins 4, 5, 77, and 78
(I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
Fig. 4–16: Output Pins 24, 25, 27, 28 and 30
(DACA_R/L, DACM_R/L, DACM_SUB)
125 kΩ
P
≈ 3.75 V
Gain=0.5
3−30 pF
Fig. 4–17: Pin 45 (AGNDC)
500 kΩ
N
2.5 V
3−30 pF
Fig. 4–12: Output/Input Pins 71, 72, and 74
(XTALIN, XTALOUT, AUD_CL_OUT)
26 pF
120 kΩ
300 Ω
≈ 3.75 V
0...2 V
Fig. 4–18: Output Pins 33, 34, 36, and 37
(SC_2_OUT_R/L, SC_1_OUT_R/L)
Fig. 4–13: Capacitor Pins 38 and 40
(CAPL_A, CAPL_M)
24 kΩ
≈ 3.75 V
Fig. 4–14: Input Pin 60 (MONO_IN)
40 kΩ
≈ 3.75 V
Fig. 4–15: Input Pins 47, 48, 50, 51, 53, 54, 56, and 57
(SC4-1_IN_L/R)
46
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Min.
Max.
Unit
TA
Ambient Operating Temperature
−
0
701)
°C
TS
Storage Temperature
−
−40
125
°C
VSUP1
First Supply Voltage
AHVSUP
−0.3
9.0
V
VSUP2
Second Supply Voltage
DVSUP
−0.3
6.0
V
VSUP3
Third Supply Voltage
AVSUP
−0.3
6.0
V
dVSUP23
Voltage between AVSUP
and DVSUP
AVSUP,
DVSUP
−0.5
0.5
V
PTOT
Package Power Dissipation
PSDIP64
PQFP80
PLQFP64
1300
1000
9601)
mW
−0.3
VSUP2+0.3
V
VIdig
Input Voltage, all Digital Inputs
IIdig
Input Current, all Digital Pins
−
−20
+20
mA2)
VIana
Input Voltage, all Analog Inputs
SCn_IN_s,3)
MONO_IN
−0.3
VSUP1+0.3
V
IIana
Input Current, all Analog Inputs
SCn_IN_s,3)
MONO_IN
−5
+5
mA2)
IOana
Output Current, all SCART Outputs
SCn_OUT_s3)
4), 5)
4), 5)
IOana
Output Current, all Analog Outputs
except SCART Outputs
DACp_s3)
4)
4)
ICana
Output Current, other pins
connected to capacitors
CAPL_p,3)
AGNDC
4)
4)
1)
2)
3)
4)
5)
PLQFP64: 65 °C
positive value means current flowing into the circuit
“n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A”
The analog outputs are short circuit proof with respect to First Supply Voltage and ground.
Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
Micronas
47
DPL 4519G
PRELIMINARY DATA SHEET
4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C)
4.6.2.1. General Recommended Operating Conditions
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VSUP1
First Supply Voltage
(8-V Operation)
AHVSUP
7.6
8.0
8.7
V
4.75
5.0
5.25
V
First Supply Voltage
(5-V Operation)
VSUP2
Second Supply Voltage
DVSUP
4.75
5.0
5.25
V
VSUP3
Third Supply Voltage
AVSUP
4.75
5.0
5.25
V
tSTBYQ1
STANDBYQ Setup Time before
Turn-off of Second Supply Voltage
STANDBYQ,
DVSUP
1
µs
4.6.2.2. Analog Input and Output Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
CAGNDC
AGNDC-Filter-Capacitor
AGNDC
−20%
3.3
µF
−20%
100
nF
−20%
330
nF
Ceramic Capacitor in Parallel
SCn_IN_s1)
CinSC
DC-Decoupling Capacitor in front of
SCART Inputs
VinSC
SCART Input Level
VinMONO
Input Level, Mono Input
MONO_IN
RLSC
SCART Load Resistance
SCn_OUT_s1)
CLSC
SCART Load Capacitance
CVMA
Main/AUX Volume Capacitor
CAPL_M,
CAPL_A
CFMA
Main/AUX Filter Capacitor
DACM_s,
DACA_s1)
1)
48
Max.
2.0
VRMS
2.0
VRMS
10
kΩ
6.0
1
nF
µF
10
−10%
Unit
+10%
nF
“n” means “1”, “2”, or “3”, “s” means “L” or “R”, “p” means “M” or “A”
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4.6.2.3. Crystal Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
General Crystal Recommendations
fP
Crystal Parallel Resonance Frequency at 12 pF Load Capacitance
18.432
RR
Crystal Series Resistance
8
25
Ω
C0
Crystal Shunt (Parallel) Capacitance
6.2
7.0
pF
CL
External Load Capacitance1)
XTAL_IN,
XTAL_OUT
MHz
PSDIP approx. 1.5
P(L)QFP approx. 3.3
pF
pF
Crystal Recommendations for Master-Slave Applications (DPL Clock must perform synchronization to I2S
clock)
fTOL
Accuracy of Adjustment
−20
+20
ppm
DTEM
Frequency Variation
versus Temperature
−20
+20
ppm
C1
Motional (Dynamic) Capacitance
19
fCL
Required Open Loop Clock
Frequency (Tamb = 25 °C)
AUD_CL_OUT
18.431
24
fF
18.433
MHz
Crystal Recommendations for other Applications (No synchronization to I2S clock possible)
fTOL
Accuracy of Adjustment
−100
+100
ppm
DTEM
Frequency Variation
versus Temperature
−50
+50
ppm
fCL
Required Open Loop Clock
Frequency (Tamb = 25 °C)
18.429
18.435
MHz
AUD_CL_OUT
Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF)
VXCA
1)
External Clock Amplitude
XTAL_IN
0.7
Vpp
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation.
Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are figures based on experience and should serve as “start value”.
To define the capacitor size, reset the DPL without transmitting any further I2C telegrams. Measure the frequency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz
as closely as possible. The higher the capacity, the lower the resulting clock frequency.
Micronas
49
DPL 4519G
PRELIMINARY DATA SHEET
4.6.3. Characteristics
at TA = 0 to 70 °C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values
at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values,
TJ = Junction Temperature
Main (M) = Main Channel, Aux (A) = Aux Channel
4.6.3.1. General Characteristics
Symbol
Parameter
Pin Name
First Supply Current (active)
(AHVSUP = 8 V)
AHVSUP
Min.
Typ.
Max.
Unit
Test Conditions
18
25
mA
12
17
mA
Volume Main and Aux 0 dB
Volume Main and
Aux -30 dB
12
17
mA
8
11
mA
Supply
ISUP1A
First Supply Current (active)
(AHVSUP = 5 V)
ISUP2A
Second Supply Current (active)
(DVSUP = 5 V)
DVSUP
70
85
mA
ISUP3A
Third Supply Current (active)
AVSUP
9
13
mA
ISUP1S
First Supply Current
(AHVSUP = 8 V)
AHVSUP
5.6
7.7
mA
3.7
5.1
mA
First Supply Current
(AHVSUP = 5 V)
Volume Main and Aux 0 dB
Volume Main and
Aux -30 dB
Standby Mode
STANDBYQ = low
Clock
fCLOCK
Clock Input Frequency
DCLOCK
Clock High to Low Ratio
tJITTER
Clock Jitter (Verification not
provided in Production Test)
VxtalDC
DC-Voltage Oscillator
tStartup
Oscillator Startup Time at
VDD Slew-rate of 1 V/µs
XTAL_IN,
XTAL_OUT
VACLKAC
Audio Clock Output AC Voltage
AUD_CL_OUT
VACLKDC
Audio Clock Output DC Voltage
routHF_ACL
HF Output Resistance
50
XTAL_IN
18.432
45
MHz
55
%
50
ps
2.5
0.4
1.2
V
2
1.8
0.4
0.6
140
ms
Vpp
load = 40 pF
VSUP3
Imax = 0.2 mA
Ω
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4.6.3.2. Digital Inputs, Digital Outputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
0.2
VSUP2
Test Conditions
Digital Input Levels
VDIGIL
Digital Input Low Voltage
STANDBYQ
D_CTR_I/O_0/1
VDIGIH
Digital Input High Voltage
ZDIGI
Input Impedance
IDLEAK
Digital Input Leakage Current
VDIGIL
ADR_SEL Input Low Voltage
VDIGIH
ADR_SEL Input High Voltage
0.8
IADRSEL
Input Current
−500
0.5
VSUP2
−1
ADR_SEL
5
pF
1
µA
0.2
VSUP2
0 V < UINPUT< DVSUP
D_CTR_I/O_0/1: tri-state
VSUP2
−220
220
µA
UADR_SEL= DVSS
500
µA
UADR_SEL= DVSUP
0.4
V
IDDCTR = 1 mA
V
IDDCTR = −1 mA
Digital Output Levels
VDCTROL
Digital Output Low Voltage
VDCTROH
Digital Output High Voltage
Micronas
D_CTR_I/O_0
D_CTR_I/O_1
VSUP2
− 0.3
51
DPL 4519G
PRELIMINARY DATA SHEET
4.6.3.3. Reset Input and Power-Up
Symbol
Parameter
Pin Name
Min.
RESETQ
Typ.
Max.
Unit
0.3
0.4
VSUP2
0.45
0.55
VSUP2
5
pF
1
µA
Test Conditions
RESETQ Input Levels
VRHL
Reset High-Low Transition Voltage
VRLH
Reset Low-High Transition Voltage
ZRES
Input Impedance
IRES
Input Pin Leakage Current
-1
0 V < UINPUT< DVSUP
DVSUP
AVSUP
VSUP2 − 10%
t/ms
RESETQ
Low-to-High
Threshold
Note: The reset should
not reach high level
before the oscillator has
started. This requires a
reset delay of >2 ms
0.45×VSUP2
0.3...0.4×VSUP2
High-to-Low
Threshold
0.3 x VSUP2 means
1.5 Volt with
VSUP2 = 5.0 V
t/ms
Reset Delay
>2 ms
Internal
Reset
High
Low
t/ms
Fig. 4–19: Power-up sequence
52
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
4.6.3.4. I2C-Bus Characteristics
Symbol
Parameter
Pin Name
2
VI2CIL
I C-BUS Input Low Voltage
VI2CIH
I2C-BUS Input High Voltage
tI2C1
I2C START Condition Setup Time
Min.
Typ.
I2C_CL,
I2C_DA
2
Max.
Unit
0.3
VSUP2
0.6
VSUP2
120
ns
tI2C2
I C STOP Condition Setup Time
120
ns
tI2C5
I2C-Data Setup Time
before Rising Edge of Clock
55
ns
tI2C6
I2C-Data Hold Time
after Falling Edge of Clock
55
ns
tI2C3
I2C-Clock Low Pulse Time
500
ns
tI2C4
I2C-Clock
500
ns
fI2C
I2C-BUS Frequency
VI2COL
I2C_CL
High Pulse Time
2
I C-Data Output Low Voltage
2
I2C_CL,
I2C_DA
Test Conditions
1.0
MHz
0.4
V
II2COL = 3 mA
1.0
µA
VI2COH = 5 V
II2COH
I C-Data Output
High Leakage Current
tI2COL1
I2C-Data Output Hold Time
after Falling Edge of Clock
15
ns
tI2COL2
I2C-Data Output Setup Time
before Rising Edge of Clock
100
ns
fI2C = 1 MHz
1/FI2C
TI2C4
I2C_CL
TI2C1
TI2C5
TI2C3
TI2C6
TI2C2
I2C_DA as input
TI2COL2
TI2COL1
I2C_DA as output
Fig. 4–20: I2C bus timing diagram
Micronas
53
DPL 4519G
PRELIMINARY DATA SHEET
4.6.3.5. I2S-Bus Characteristics
Symbol
Parameter
Pin Name
VI2SIL
Input Low Voltage
VI2SIH
Input High Voltage
ZI2SI
Input Impedance
I2S_CL
I2S_WS
I2S_CL3
I2S_WS3
I2S_DA_IN1..3
ILEAKI2S
Input Leakage Current
VI2SOL
I2S Output Low Voltage
VI2SOH
I S Output High Voltage
fI2SOWS
I2S-Word Strobe Output Frequency
I2S_WS
fI2SOCL
I2S-Clock
I2S_CL
RI2S10/I2S20
I2S-Clock Output High/Low-Ratio
Output Frequency
Typ.
Max.
Unit
0.2
VSUP2
0.5
Test Conditions
VSUP2
−1
I2S_CL
I2S_WS
I2S_DA_OUT
2
Min.
5
pF
1
µA
0 V < UINPUT< DVSUP
0.4
V
II2SOL = 1 mA
V
II2SOH = −1 mA
VSUP2
− 0.3
48.0
kHz
1.536
3.072
12.288
0.9
1.0
1.1
MHz
Synchronous I2S Interface
ts_I2S
I2S Input Setup Time
before Rising Edge of Clock
th_I2S
I2S Input Hold Time
after Rising Edge of Clock
td_I2S
I2S Output Delay Time
after Falling Edge of Clock
I2S_CL
I2S_WS
I2S_DA_OUT
fI2SWS
I2S-Word Strobe Input Frequency
I2S_WS
fI2SCL
I2S-Clock Input Frequency
I2S_CL
RI2SCL
I2S_DA_IN1/2
I2S_CL
2
I S-Clock Input Ratio
12
ns
40
ns
28
48.0
1.536
0.9
3.072
ns
for details see Fig. 4–21
“I2S timing diagram (synchronous interface)”
CL=30 pF
kHz
12.288
MHz
1.1
Asynchronous I2S Interface
ts_I2S3
I2S3 Input Setup Time
before Rising Edge of Clock
th_I2S3
I2S3 Input Hold Time
after Rising Edge of Clock
fI2S3WS
I2S3-Word Strobe Input Frequency
I2S_WS3
fI2S3CL
I2S3-Clock Input Frequency
I2S_CL3
RI2S3CL
54
2
I S3-Clock Input Ratio
I2S_CL3
I2S_WS3
I2S_DA_IN3
4
ns
40
ns
5
0.9
50
kHz
3.2
MHz
for details see Fig. 4–22
“I2S timing diagram (asynchronous interface)”
1.1
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
1/FI2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1
Detail C
I2S_CL
Detail A
I2S_DA_IN*)
R LSB L MSB
L LSB R MSB
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail B
I2S_DA_OUT R LSB
L MSB
L LSB R MSB
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Data: MSB first, I2S synchronous master
1/FI2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1
Detail C
I2S_CL
Detail A
I2S_DA_IN*)
R LSB L MSB
L LSB R MSB
R LSB L LSB
16,18...32 bit left channel
Detail B
I2S_DA_OUT R LSB
16, 18...32 bit right channel
16, 18...32 bit left channel
L MSB
L LSB R MSB
R LSB L LSB
16, 18...32 bit right channel
Data: MSB first, I2S synchronous slave
Note:
Detail C
1) I2S_DA_IN can be
− I2S_DA_IN1,
− I2S_DA_IN2, or
− I2S_DA_IN2/3
Detail A,B
1/FI2SCL
I2S_CL
I2S_CL
Ts_I2S
Th_I2S
Ts_I2S
I2S_DA_IN1)
I2S_WS as INPUT
Td_I2S
Td_I2S
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4–21: I2S timing diagram (synchronous interface)
Micronas
55
DPL 4519G
PRELIMINARY DATA SHEET
I2S_CL3
1/FI2S3WS
(I2S_CONFIG[10]
= 0)
Right sample (I2S_CONFIG[10] = 0)
Left sample (I S_CONFIG[10] = 1)
Right sample (I2S_CONFIG[10] = 1)
Left sample
I2S_WS3
2
Left aligned (I2S_CONFIG[9] = 0)
I2S_DA_IN3
16,18...32 Bit data & clocks allowed
MSB
MSB
Left aligned (I2S_CONFIG[9] = 1)
16,18...32 Bit data & clocks allowed
I2S_DA_IN3
MSB
MSB
I2S_DA_IN3
LSB
Right aligned (I2S_CONFIG[11] = 1, I2S_CONFIG[9] = 0)
16 Bit data & 16...32 clocks allowed
LSB
1/FI2S3CL
I2S_CL3
Ts_I2S3 Th_I2S3
I2S_DA_IN3
Ts_I2S3
I2S_WS3
Fig. 4–22: I2S timing diagram (asynchronous interface)
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Analog Ground
VAGNDC0
RoutAGN
AGNDC Open Circuit Voltage
Rload ≥10 MΩ
AGNDC
AHVSUP = 8 V
3.8
V
AHVSUP = 5 V
2.5
V
3 V ≤ VAGNDC ≤ 4 V
AGNDC Output Resistance
AHVSUP = 8 V
70
125
180
kΩ
AHVSUP = 5 V
47
83
120
kΩ
Analog Input Resistance
RinSC
SCART Input Resistance
from TA = 0 to 70 °C
SCn_IN_s1)
25
40
58
kΩ
fsignal = 1 kHz, I = 0.05 mA
RinMONO
MONO Input Resistance
from TA = 0 to 70 °C
MONO_IN
15
24
35
kΩ
fsignal = 1 kHz, I = 0.1 mA
1)
56
“n” means “1”, “2”, “3”, or “4”;
“s” means “L” or “R”
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
SCn_IN_s,1)
MONO_IN
Typ.
Max.
Unit
Test Conditions
2.00
2.25
VRMS
fsignal = 1 kHz
1.13
1.51
VRMS
460
500
Ω
Ω
−70
+70
mV
SCn_IN_s,1)
MONO_IN
→
SCn_OUT_s1)
−1.0
+0.5
dB
fsignal = 1 kHz
−0.5
+0.5
dB
with resp. to 1 kHz
20 Hz to 20 000 Hz
SCn_OUT_s1)
1.8
1.9
2.0
VRMS
fsignal = 1 kHz
full scale Digital Input from
I2S
1.17
1.27
1.37
VRMS
2.1
2.1
3.3
4.6
5.0
kΩ
kΩ
fsignal = 1 kHz, I = 0.1 mA
Tj = 27°C
from TA = 0 to 70°C
Audio Analog-to-Digital-Converter
VAICL
Analog Input Clipping Level for
Analog-to-Digital-Conversion
(AHVSUP=8 V)
Analog Input Clipping Level for
Analog-to-Digital-Conversion
(AHVSUP=5 V)
SCART Outputs
RoutSC
SCART Output Resistance
dVOUTSC
Deviation of DC-Level at SCART
Output from AGNDC Voltage
ASCtoSC
Gain from
Analog Input to SCART Output
frSCtoSC
Frequency Response from
Analog Input to SCART Output
VoutSC
Signal Level at SCART-Output
(AHVSUP=8 V)
SCn_OUT_s1)
Signal Level at SCART-Output
(AHVSUP=5 V)
200
200
330
fsignal = 1 kHz, I = 0.1 mA,
Tj = 27°C, TA = 0 to 70°C
Main and Aux Outputs
DACp_s1)
RoutMA
Main/Aux Output Resistance
VoutDCMA
DC-Level at Main/Aux-Output
(AHVSUP=8 V)
1.80
2.04
61
2.28
V
mV
Volume = 0 dB
Volume = -30 dB
DC-Level at Main/Aux-Output
(AHVSUP=5 V)
1.12
1.36
40
1.60
V
mV
Volume = 0 dB
Volume = -30 dB
Signal Level at Main/Aux-Output
(AHVSUP=8 V)
1.23
1.37
1.51
VRMS
Signal Level at Main/Aux-Output
(AHVSUP=5 V)
0.76
0.90
1.04
VRMS
fsignal = 1 kHz
full scale Digital Input from
I2S
Volume = 0 dB
VoutMA
1)
“n” means “1”, “2”, “3”, or “4”;
Micronas
“s” means “L” or “R”;
“p” means “M” or “A”
57
DPL 4519G
PRELIMINARY DATA SHEET
4.6.3.7. Power Supply Rejection
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
PSRR: Rejection of Noise on AHVSUP at 1 kHz
PSRR
1)
AGNDC
AGNDC
80
dB
From Analog Input to I2S Output
MONO_IN,
SCn_IN_s1)
70
dB
From Analog Input to
SCART Output
MONO_IN,
SCn_IN_s1)
SCn_OUT_s1)
70
dB
From I2S Input to SCART Output
SCn_OUT_s1)
60
dB
From I2S Input to Main/Aux Output
DACp_s1)
80
dB
“n” means “1”, “2”, “3”, or “4”;
“s” means “L” or “R”;
“p” means “M” or “A”
4.6.3.8. Analog Performance
Symbol
Parameter
Pin Name
Min.
Typ.
from Analog Input to I2S Output
MONO_IN,
SCn_IN_s1)
90
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s1)
→
SCn_OUT_s1)
from I2S Input to SCART Output
SCn_OUT_s1)
Max.
Unit
Test Conditions
93
dB
Input Level = −20 dB with
resp. to VAICL, fsig = 1 kHz,
A-weighted
20 Hz...20 kHz
93
96
dB
Input Level = −20 dB,
fsig = 1 kHz,
A-weighted
20 Hz...20 kHz
Volume = 0 dB
90
93
dB
90
93
dB
Specifications for AHSUP=8 V
SNR
Signal-to-Noise Ratio
2
from I S Input to Main/Aux-Output
THD
1)
58
DACp_s
1)
Total Harmonic Distortion
from Analog Input to I2S Output
MONO_IN,
SCn_IN_s1)
0.01
0.03
%
Input Level = −3 dBr with
resp. to VAICL, fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s
→
SCn_OUT_s1)
0.01
0.03
%
Input Level = −3 dBr,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from I2S Input to SCART Output
SCn_OUT_s1)
0.01
0.03
%
from I2S Input to Main or Aux Output
DACA_s,
DACM_s1)
0.01
0.03
%
“n” means “1”, “2”, “3”, or “4”;
“s” means “L” or “R”;
“p” means “M” or “A”
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
from Analog Input to I2S Output
MONO_IN,
SCn_IN_s1)
87
from Analog Input to
SCART Output
MONO_IN,
SCn_IN_s1)
→
SCn_OUT_s1)
from I2S Input to SCART Output
SCn_OUT_s1)
from I2S Input to Main/Aux-Output
for Analog Volume at 0 dB
for Analog Volume at −30 dB
DACp_s1)
Max.
Unit
Test Conditions
90
dB
Input Level = −20 dB with
resp. to VAICL, fsig = 1 kHz,
A-weighted
20 Hz...20 kHz
90
93
dB
Input Level = −20 dB,
fsig = 1 kHz,
A-weighted
20 Hz...20 kHz
Volume = 0 dB
87
90
dB
87
75
90
80
dB
dB
Specifications for AHSUP=5 V
SNR
THD
1)
Signal-to-Noise Ratio
Total Harmonic Distortion
0.1
%
Input Level = −3 dBr with
resp. to VAICL, fsig = 1 kHz,
unweighted
20 Hz...20 kHz
MONO_IN,
SCn_IN_s
→
SCn_OUT_s1)
0.1
%
Input Level = −3 dBr,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
from I2S Input to SCART Output
SCn_OUT_s1)
0.1
%
from I2S Input to Main or Aux Output
DACA_s,
DACM_s1)
0.1
%
from Analog Input to I2S Output
MONO_IN,
SCn_IN_s1)
from Analog Input to
SCART Output
“n” means “1”, “2”, “3”, or “4”;
Micronas
“s” means “L” or “R”;
0.03
“p” means “M” or “A”
59
DPL 4519G
Symbol
PRELIMINARY DATA SHEET
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Crosstalk Specifications
XTALK
Crosstalk Attenuation
Input Level = −3 dB,
fsig = 1 kHz, unused analog
inputs connected to ground
by Z < 1 kΩ
between left and right channel within
SCART Input/Output pair (L→R, R→L)
unweighted
20 Hz...20 kHz
SCn_IN → SCn_OUT1)
80
dB
SC1_IN or SC2_IN → I2S Output
80
dB
2
SC3_IN → I S Output
80
dB
I2S Input → SCn_OUT1)
80
dB
unweighted
20 Hz...20 kHz
between left and right channel within
Main or Aux Output pair
I2S Input → DACp1)
75
dB
between SCART Input/Output pairs1)
D = disturbing program
O = observed program
D: MONO/SCn_IN → SCn_OUT
O: MONO/SCn_IN → SCn_OUT1)
100
dB
D: MONO/SCn_IN → SCn_OUT or unsel.
O: MONO/SCn_IN → I2S Output
95
dB
D: MONO/SCn_IN → SCn_OUT
O: I2S Input → SCn_OUT1)
100
dB
D: MONO/SCn_IN → unselected
O: I2S Input → SC1_OUT1)
100
dB
Crosstalk between Main and Aux Output pairs
I2S Input DSP → DACp1)
XTALK
90
dB
60
(unweighted
20 Hz...20 kHz)
same signal source on left
and right disturbing channel, effect on each
observed output channel
(unweighted
20 Hz...20 kHz)
same signal source on left
and right disturbing channel, effect on each
observed output channel
Crosstalk from Main or Aux Output to SCART Output
and vice versa
D = disturbing program
O = observed program
1)
(unweighted
20 Hz...20 kHz)
same signal source on left
and right disturbing channel, effect on each
observed output channel
D: MONO/SCn_IN/DSP → SCn_OUT
O: I2S Input → DACp1)
80
dB
SCART output load resistance 10 kΩ
D: MONO/SCn_IN/DSP → SCn_OUT
O: I2S Input → DACp1)
85
dB
SCART output load resistance 30 kΩ
D: I2S Input → DACp
O: MONO/SCn_IN → SCn_OUT1)
95
dB
D: I2S Input → DACM
O: I2S Input → SCn_OUT1)
95
dB
“n” means “1”, “2”, “3”, or “4”;
“s” means “L” or “R”;
“p” means “M” or “A”
Micronas
DPL 4519G
PRELIMINARY DATA SHEET
5. Appendix A: Application Information
5.1. Phase Relationship of Analog Outputs
The analog output signals: Main, Aux, and SCART2 all
have the same phases. The SCART1 output has opposite phase.
Using the I2S-outputs for other DSPs or D/A converters, care must be taken to adjust for the correct phase.
I2S_IN1/2/3
I2S_OUT1/2
Main
Aux
SCART1-Ch.
Audio
Baseband
Processing
SCART1
SCART1
SCART2
SCART3
SCART2
SCART4
MONO
MONO, SCART1...4
SCART
Output Select
Fig. 5–1: Phase diagram of the DPL 4519G
Micronas
61
DPL 4519G
PRELIMINARY DATA SHEET
5.2. Application Circuit
C s. section 4.6.2.
8 V(5 V)
3.3
µF
100
nF
18.432
MHz
+
+
330 nF
330 nF
AHVSS
CAPL_A (38) 38
10 µF
CAPL_M (40) 40
XTAL_OUT (63) 72
XTAL_IN (62) 71
10 µF
AGNDC (42) 45
330 nF
+
1 µF
1 nF
60 (55) MONO_IN
330 nF
AHVSS
1 µF
right
DACM_R (28) 27
1 nF
56 (52) SC1_IN_L
1 µF
DACM_SUB (31) 30
57 (53) SC1_IN_R
Subwoofer
1 nF
55 (51) ASG
330 nF
left
DACM_L (29) 28
53 (49) SC2_IN_L
54 (50) SC2_IN_R
52 (48) ASG
330 nF
1 µF
50 (46) SC3_IN_L
Center
DACA_L (26) 25
51 (47) SC3_IN_R
330 nF
AHVSS
49 (45) ASG
330 nF
5V
330 nF
1 nF
DPL 4519G
48 (44) SC4_IN_R
80 (7) STANDBYQ
5V
1 µF
DACA_R (25) 24
47 (43) SC4_IN_L
SC1_OUT_L (37) 37
DVSS
79 (6) ADR_SEL
SC1_OUT_R (36) 36
DVSS
3 (10) I2C_DA
SC2_OUT_L (34) 34
2 (9) I2C_CL
Surround
1 nF
SC2_OUT_R (33) 33
100 Ω 22 µF
+
100 Ω 22 µF
+
100 Ω 22 µF
+
100 Ω 22 µF
+
D_CTR_I/O_0 (5) 78
D_CTR_I/O_1 (4) 77
5 (12) I2S_WS
4 (11) I2S_CL
7 (14) I2S_DA_IN1
AUD_CL_OUT (1) 74
17 (20) I2S_DA_IN2
26 (27) VREF2
35 (35) VREF1
39 (39) AHVSUP
62 (56) AVSS
AHVSS
8V
(5 V)
AHVSS
16 (19) DVSS
66 (57) AVSUP
5V
AHVSS
Note:
470
pF
1.5
nF
10
µF
AHVSS
5V
470
pF
1.5
nF
10
µF
AVSS
(from Controller, see section 4.6.3.3.)
13 (18) DVSUP
21 (24) RESETQ
RESETQ
220
pF
470
pF
1.5
nF
10
µF
43 (41) AHVSS
TESTEN (61) 70
6 (13) I2S_DA_OUT
Decoupling capacitors from
− DVSUP to DVSS,
− AVSUP to AVSS, and
− AHVSUP to AHVSS
are recommended as closely
as possible to supply pins (see
application note on page 42).
Note: Pin numbers refer to the PQFP80 package, numbers in brackets refer to the PSDIP64 package.
62
Micronas
PRELIMINARY DATA SHEET
Micronas
DPL 4519G
63
DPL 4519G
PRELIMINARY DATA SHEET
6. Data Sheet History
1. Preliminary data sheet: "DPL 4519G Sound Processor for Digital and Analog Surround Systems",
Oct. 31, 2000, 6251-512-1PD.
First release of the preliminary data sheet.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-512-1PD
64
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
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Micronas GmbH.
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