12-Bit Serial Input Multiplying CMOS Digital-to-Analog Converter DAC8043 FEATURES APPLICATIONS Autocalibration systems Process control and industrial automation Programmable amplifiers and attenuators Digitally controlled filters FUNCTIONAL BLOCK DIAGRAM DAC8043 RFB RFB VREF 12-BIT DAC IOUT 12 LD 12-BIT DAC REGISTER 12 CLK SRI 12-BIT SHIFT REGISTER VDD GND 00271-001 12-bit accuracy in an 8-lead PDIP and SOIC package Fast serial data input Double data buffers Low ±½ LSB maximum INL and ±1 LSB maximum DNL Maximum gain error: 2 LSB Low ±5 ppm/°C maximum tempco ESD resistant Low cost Available in die form Figure 1. GENERAL DESCRIPTION The DAC8043 is a high accuracy 12-bit CMOS multiplying DAC in a space-saving 8-lead PDIP package. Featuring serial data input, double buffering, and excellent analog performance, the DAC8043 is ideal for applications where PC board space is at a premium. In addition, improved linearity and gain error performance permit reduced parts count through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. The circuit consists of a 12-bit serial-in, parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial data is clocked into the input register on the rising edge of the CLK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the digital-to-analog converter (DAC). The fast interface timing of the DAC8043 may reduce timing design considerations while minimizing microprocessor wait states. For applications requiring an asynchronous clear function or more versatile microprocessor interface logic, refer to the AD5443. Operating from a single 5 V power supply, the DAC8043 is the ideal low power, small size, high performance solution to many application problems. It is available in a PDIP package that is compatible with auto-insertion equipment. There is also a 16-lead SOIC package available. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. DAC8043 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Terminology .......................................................................................9 Functional Block Diagram .............................................................. 1 Digital Section................................................................................. 10 General Description ......................................................................... 1 General Circuit Information ..................................................... 10 Revision History ............................................................................... 2 Equivalent Circuit Analysis ...................................................... 11 Specifications..................................................................................... 3 Dynamic Performance ............................................................... 11 Electrical Characteristics ............................................................. 3 Applications Information .............................................................. 12 Wafer Test Limits .......................................................................... 4 Application Tips ......................................................................... 12 Absolute Maximum Ratings ............................................................ 5 Interfacing to the MC6800 ........................................................ 14 Caution .......................................................................................... 5 DAC8043 Interface to the 8085 ................................................ 14 Thermal Resistance ...................................................................... 5 DAC8043 to the 68000 Interface .............................................. 14 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 15 Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 16 REVISION HISTORY 1/11—Rev. D to Rev. E Updated Format .................................................................. Universal Added SOIC_W Models .................................................... Universal Added Table 5.................................................................................... 6 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 3/03—Data Sheet Changed from Rev. C to Rev. D. Deleted 8-Lead CIRDIP and 16-Lead Wide-Body SOL ......Universal Figures renumbered ........................................................... Universal Changes to Absolute Maximum Ratings ....................................... 4 Changes to Ordering Guide ............................................................ 4 Deleted to Dice Characteristics ...................................................... 4 Updated Outline Dimensions ....................................................... 11 Rev. E | Page 2 of 16 DAC8043 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = 5 V; VREF = 10 V; IOUT = GND = 0 V; TA = full temperature range specified under the Absolute Maximum Ratings, unless otherwise noted. Table 1. Parameter STATIC ACCURACY Resolution Nonlinearity 1 Symbol N INL Differential Nonlinearity 2 Gain Error 3 DNL GFSE Gain Tempco ( ΔGain/∆Temp)4 Power Supply Rejection Ratio (ΔGain/ΔVDD) Output Leakage Current 5 TCGFS PSRR Zero Scale Error 6, 7 IZSE Input Resistance 8 AC PERFORMANCE Output Current Settling Time4, 9 Digital-to-Analog Glitch Energy4, 10 ILKG tS Q FT Total Harmonic Distortion4 THD TIMING CHARACTERISTICS4, 14 Data Setup Time Data Hold Time Clock Pulsewidth High Clock Pulsewidth Low Load Pulsewidth LSB Clock Into Input Register to Load DAC Register Time en Min Typ Max Unit ±0.0006 ±½ 1 ±1 2 2 ±5 ±0.002 Bits LSB LSB LSB LSB LSB ppm/°C %/% 11 ±5 ±25 0.03 0.15 15 nA nA LSB LSB kΩ 0.25 2 1 20 μs nVs 0.7 1 mV p-p 12 DAC8043G DAC8043F TA = 25°C TA = full temperature range, all grades ΔVDD = ±5% TA = 25°C TA = full temperature range TA = 25°C TA = full temperature range RIN Feedthrough Error (VREF to IOUT)4, 11 Output Noise Voltage Density4, 12 DIGITAL INPUTS Digital Input High Low Input Leakage Current 13 Input Capacitance4, 11 ANALOG OUTPUTS Output Capacitance4 Conditions 7 TA = 25°C, VREF = 0 V IOUT load = 100 Ω, CEXT = 13 pF, DAC register loaded alternately with all 0s and all 1s VREF = 20 V p-p @ f = 10 kHz, digital input = 0000 0000 0000 TA = 25°C VREF = 6 V rms @ 1 kHz, DAC register loaded with all 1s 10 Hz to 100 kHz between RFB and IOUT –85 dB 17 nV/√Hz VIN = 0 V to +5 V VIN = 0 V 0.8 ±1 8 V V μA pF COUT Digital inputs = VIH Digital inputs = VIL 110 80 pF pF tDS tDH tCH tCL tLD tASB TA = full temperature range TA = full temperature range TA = full temperature range TA = full temperature range TA = full temperature range TA = full temperature range VIN VIL IIL CIN 2.4 Rev. E | Page 3 of 16 40 80 90 120 120 0 ns ns ns ns ns ns DAC8043 Parameter POWER SUPPLY Supply Voltage Supply Current Symbol VDD IDD Conditions Min Typ Max Unit 4.75 5 5.25 500 100 V μA μA Digital inputs = VIH or VIL Digital inputs = 0 V or VDD 1 ±1/2 LSB = ±0.012% of full scale. All grades are monotonic to 12 bits over temperature. Using internal feedback resistor. 4 Guaranteed by design and not tested. 5 Applies to IOUT; all digital inputs = 0 V. 6 VREF = 10 V; all digital inputs = 0 V. 7 Calculated from worst-case RREF: IZSE (in LSBs) = (RREF × ILKG × 4096)/VREF. 8 Absolute temperature coefficient is less than 300 ppm/°C. 9 IOUT load = 100 Ω , CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to ½ LSB; tS = propagation delay (tPD) + 9τ where τ = measured time constant of the final RC decay. 10 VREF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V. 11 All digit inputs = 0 V. 12 Calculations from en = √4K TRB where: K = Boltzmann constant, J/°K, R = resistance, Ω, T = resistor temperature, °K, B = bandwidth, Hz. 13 Digital inputs are CMOS gates; IIN is typically 1 nA at 25°C. 14 Tested at VIN = 0 V or VDD. 2 3 WAFER TEST LIMITS VDD = 5 V, VREF = 10 V; IOUT = GND = 0 V, TA = 25°C. Table 2. DAC8043GBC Limit Parameter1 STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Power Supply Rejection Ratio Output Leakage Current (IOUT) REFERENCE INPUT Input Resistance DIGITAL INPUTS Digital Input High Digital Input Low Input Leakage Current POWER SUPPLY Supply Current 1 Symbol N INL DNL GFSE PSRR ILKG Conditions Min Max Unit ±1 ±1 ±2 ±0.002 ±5 Bits LSB LSB LSB %/% nA 15 kΩ VIN = 0 V to VDD 0.8 ±1 V V μA Digital inputs = VIN or VIL Digital inputs = 0 V or VDD 500 100 μA μA 12 Using internal feedback resistor ΔVDD = ±5% Digital inputs = VIL RIN 7 VIH VIL IIL 2.4 IDD Typ Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult a factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. Rev. E | Page 4 of 16 DAC8043 ABSOLUTE MAXIMUM RATINGS CAUTION TA = 25°C, unless otherwise noted. 1. Table 3. Parameter VDD to GND VREF to GND VRFB to GND Digital Input Voltage Range VIOUT to GND Operating Temperature Range FP Version GP Version Junction Temperature Storage Temperature Lead Temperature (Soldering, 60 sec) Rating −0.3 V to +8 V ±18 V ±18 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V 2. 3. 4. −40°C to +85°C 0°C to 70°C 150°C −65°C to +150°C 300°C Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFB. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use. Use proper antistatic handling procedures. Absolute Maximum Ratings apply to both packaged devices and dice. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. THERMAL RESISTANCE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 8-Lead PDIP 16-Lead SOIC ESD CAUTION Rev. E | Page 5 of 16 θJA 96 92 θJC 37 27 Unit °C/W °C/W DAC8043 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 16 NC NC 2 15 NC VREF 3 14 VDD IOUT 5 1 RFB 2 IOUT 3 GND 4 13 CLK TOP VIEW (Not to Scale) 12 SRI GND 6 11 LD 8 VDD DAC8043 GND 7 10 NC 7 CLK TOP VIEW (Not to Scale) NC 8 9 NC 6 SRI 5 LD 00271-002 VREF DAC8043 NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 2. 8-Lead PDIP 00271-003 RFB 4 Figure 3. 16-Lead Wide-Body SOIC Table 5. Pin Function Descriptions 8-Lead PDIP 1 2 Pin No. 16-Lead SOIC 3 4 Mnemonic VREF RFB 3 4 5 5 6, 7 11 IOUT GND LD 6 12 SRI 7 8 13 14 1, 2, 8, 9, 10, 15, 16 CLK VDD NC Description DAC Reference Voltage Input Pin. DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier output. DAC Current Output. Ground Pin. Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low. 12-Bit Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored. Serial Clock Input. Positive-edge clocks data into shift register. Positive Power Supply Input. Do Not Connect to These Pins. Rev. E | Page 6 of 16 DAC8043 TYPICAL PERFORMANCE CHARACTERISTICS 0 1.0 DIGITAL INPUT = 1111 1111 1111 VDD = 5V VREF = 100mV TA = 25°C –12 –24 0.8 –48 IDD (mA) GAIN (dB) –36 DIGITAL INPUT = 0000 0000 0000 –60 –72 0.6 0.4 –84 –96 0.2 10k 100k FREQUENCY (Hz) 1M 10M 0 00271-004 –120 1k 0 Figure 4. Gain vs. Frequency (Output Amplifier: OP42) 3 4 0.5 VDD = 5V VIN = 6V rms OUTPUT AMPLIFIER: OP42 TA = 25°C 0.4 LINEARITY ERROR (LSB) 0.3 –40 THD (dB) 2 VIN (V) Figure 6. Supply Current vs. Logic Input Voltage 0 –20 1 00271-006 –108 –60 –80 0.2 0.1 0 –0.1 –0.2 –0.3 –100 1k FREQUENCY (Hz) 10k 100k –0.5 00271-005 100 0 Figure 5. Total Harmonic Distortion vs. Frequency (Multiplying Mode) Rev. E | Page 7 of 16 512 1024 1536 2048 2560 3072 DIGITAL INPUT CODE (Decimal) 3584 Figure 7. Linearity Error vs. Digital Input Code 4095 00271-007 –0.4 –120 10 0.50 0.25 0.25 0 –0.25 –0.25 –0.50 –0.50 2 4 6 VREF (V) 8 10 2 4.0 3.0 2.4 2.0 3 5 7 9 VDD (V) 11 13 15 00271-009 1.0 –0.8 1 4 6 VREF (V) 8 Figure 10. DNL Error vs. Reference Voltage Figure 8. Linearity Error vs. Reference Voltage THRESHOLD VOLTAGE (V) 0 Figure 9. Logic Threshold Voltage vs. Supply Voltage Rev. E | Page 8 of 16 10 00271-010 DNL (LSB) 0.50 00271-008 INL (LSB) DAC8043 DAC8043 TERMINOLOGY Integral Nonlinearity (INL) This is the single most important DAC specification. Analog Devices, Inc., measures INL as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed as a percent of full-scale range or in terms of LSBs. Refer to the Analog Devices Glossary of EE Terms for additional digital-to-analog converter definitions. Interface Logic Information The DAC8043 has been designed for ease of operation. The timing diagram (see Figure 12) illustrates the input register loading sequence. Note that the most significant bit (MSB) is loaded first. Once the input register is full, the data is transferred to the DAC register by taking LD momentarily low. Rev. E | Page 9 of 16 DAC8043 DIGITAL SECTION The digital inputs of the DAC8043 (SRI, LD, and CLK) are TTL compatible. The input voltage levels affect the amount of current drawn from the supply; peak supply current occurs as the digital input (VIN) passes through the transition region (see Figure 6). Maintaining the digital input voltage levels as close as possible to the VDD and GND supplies minimizes supply current consumption. The digital inputs of the DAC8043 have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 11 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. High voltage static charges applied to the inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. GENERAL CIRCUIT INFORMATION The DAC8043 is a 12-bit multiplying digital-to-analog converter (DAC) with a very low temperature coefficient. It contains an R-2R resistor ladder network, data input, control logic, and two data registers. VDD The digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift register and then transferred, in parallel, to the 12-bit DAC register. A simplified circuit of the DAC8043 is shown in Figure 13, which has an inverted R-2R ladder network consisting of siliconchrome, highly stable (50 ppm/°C) thin-film resistors, and twelve pairs of NMOS current-steering switches. These switches steer binarily weighted currents into either IOUT or GND; this yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resistance at VREF equal to R. The VREF input may be driven by any reference voltage or current, ac or dc, that is within the limits stated in the Absolute Maximum Ratings section. The twelve output current-steering NMOS FET switches are in series with each R-2R resistor; they can introduce bit errors if all are of the same RON resistance value. They were designed so that the switch on resistance is binarily scaled so that the voltage drop across each switch remains constant. If, for example, Switch S1 of Figure 13 was designed with an on resistance of 10 Ω, Switch S2 for 20 Ω, and so on, a constant 5 mV drop would be maintained across each switch. 00271-011 TL/TTL/CMOS INPUTS Figure 11. Digital Input Protection BIT 1 MSB1 SRI BIT 2 BIT 11 2 11 BIT 12 LSB tDS tDH CLK INPUT tCL 1 tCH LOAD SERIAL DATA INTO INPUT REGISTER tASB 1DATA LOADED MSB FIRST. Figure 12. Write Cycle Timing Diagram Rev. E | Page 10 of 16 LOAD INPUT REGISTER’S DATA INTO DAC REGISTER 00271-012 tLD LD DAC8043 To further ensure accuracy across the full temperature range, permanently on MOS switches were included in series with the feedback resistor and the terminating resistor of the R-2R ladder. The simplified DAC circuit, Figure 13, shows the location of the series switches. These series switches are equivalently scaled to two times Switch S1 (MSB) and to Switch S12 (LSB), respectively, to maintain constant relative voltage drops with varying temperature. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn on these series switches. 10kΩ 10kΩ 10kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ S1 S2 S3 S12 * R V ERROR = VOS 1 + FB RO where: RO is a function of the digital code and = 10 kΩ for more than four bits of Logic 1. = 30 kΩ for any single bit of Logic 1. Therefore, the offset gain varies as follows: At Code 0011 1111 1111, 10 kΩ = 2 VOS V ERROR 1 = VOS 1 + 10 kΩ At Code 0100 0000 0000, GND IOUT 10 kΩ = 4 / 3 VOS V ERROR 2 = VOS 1 + 30 kΩ 10kΩ RFEEDBACK * BIT 3 BIT 12 (LSB) The error difference is 2/3 VOS. DIGITAL INPUTS (SWITCHES SHOWN FOR DIGITAL INPUTS (HIGH)) *THESE SWITCHES PERMANENTLY ON. 00271-013 BIT 1 (MSB) BIT 2 Figure 13. Simplified DAC Circuit EQUIVALENT CIRCUIT ANALYSIS Figure 14 shows an equivalent analog circuit for the DAC8043. The (D × VREF)/R current source is code dependent and is the current generated by the DAC. The current source, ILKG, consists of surface and junction leakages and doubles approximately every 10°C. COUT is the output capacitance; it is the result of the N-channel MOS switches and varies from 80 pF to 110 pF, depending on the digital input code. RO is the equivalent output resistance that also varies with digital input code. R is the nominal R-2R resistor ladder resistance. R R GND 00271-014 R COUT R VREF R R ETC RFB 2R 2R 2R OP77 VOS Figure 15. Simplified Circuit IOUT ILKG Because one LSB has a weight (for VREF = 10 V) of 2.4 mV for the DAC8043, it is clearly important that VOS be minimized, either by using the amplifier’s nulling pins or an external nulling network or by selecting an amplifier with inherently low VOS. Amplifiers with sufficiently low VOS include OP77, OP07, OP27, and OP42. RFB VREF D × VREF R 00271-015 VREF affected by these variations. This variation is best illustrated by using the circuit of Figure 15 and the following equation: Figure 14. Equivalent Analog Circuit DYNAMIC PERFORMANCE Output Impedance The output resistance of the DAC8043, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT terminal, may be between 10 kΩ (the feedback resistor alone when all digital inputs are low) and 7.5 kΩ (the feedback resistor in parallel with approximately 30 kΩ of the R-2R ladder network resistance when any single bit logic is high). Static accuracy and dynamic performance will be The gain and phase stability of the output amplifier, board layout, and power supply decoupling all affect the dynamic performance. The use of a small compensation capacitor may be required when high speed operational amplifiers are used. It may be connected across the feedback resistor of the amplifier to provide the necessary phase compensation to critically damp the output. The output capacitance of the DAC8043 and the RFB resistor form a pole that must be outside the amplifier’s unity gain crossover frequency. The considerations when using high speed amplifiers are: 1. 2. Rev. E | Page 11 of 16 Phase compensation (see Figure 16 and Figure 17). Power supply decoupling at the device socket and the use of proper grounding techniques. DAC8043 APPLICATIONS INFORMATION APPLICATION TIPS In most applications, linearity depends upon the potential of the IOUT and GND pins being equal to each other. In most applications, the DAC is connected to an external op amp with its noninverting input tied to ground (see Figure 16 and Figure 17). The amplifier selected should have a low input bias current and low drift over temperature. The amplifier’s input offset voltage should be nulled to less than 200 μV (less than 10% of 1 LSB). The noninverting input of the operational amplifier should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output error. All grounded pins should tie to a single common ground point, avoiding ground loops. The VDD power supply should have a low noise level with no transients greater than 17 V. Gain error may be trimmed by adjusting R1, as shown in Figure 17. The DAC register must first be loaded with all 1s. R1 may then be adjusted until VOUT = −VREF (4095/4096). In the case of an adjustable VREF, R1 and R2 may be omitted, with VREF adjusted to yield the desired full-scale output. In most applications, the DAC8043’s negligible zero-scale error and very low gain error permit the elimination of the trimming components (R1 and the external R2) without adversely affecting on circuit performance. Table 6. Unipolar Code Table1, 2 Digital Input MSB LSB 1111 1111 1111 Nominal Analog Output (VOUT as Shown in Figure 16 and Figure 17) 1000 0000 0001 2049 − V REF 4096 1000 0000 0000 V REF 2048 − V REF =− 2 4096 0111 1111 1111 2047 − V REF 4096 0000 0000 0001 1 − V REF 4096 0000 0000 0000 0 − V REF =0 4096 Unipolar Operation (2-Quadrant) The circuits shown in Figure 16 and Figure 17 may be used with an ac or dc reference voltage. The output of the circuit ranges between 0 V and approximately −VREF (4095/4096), depending upon the digital input code. The relationship between the digital input and the analog output is shown in Table 6. The limiting parameters for the VREF range are the maximum input voltage range of the op amp or ±25 V, whichever is lowest. 5V VREF 10V VREF SERIAL DATA INPUT VDD 1 RFB 4095 FS = − V REF 4096 15pF 2 IOUT 3 GND 7 6 OP77 VOUT 4 2 Nominal LSB magnitude for Figure 16 and Figure 17 circuits is given by 00271-016 LD Nominal full scale for Figure 16 and Figure 17 circuits is given by +15V DAC8043 CLK –15V 1 −n LSB = VREF or VREF (2 ) 4096 Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant) SERIAL DATA INPUT CLK LD 5V R1 100Ω VREF VDD RFB DAC8043 IOUT GND R2 50Ω 15pF 2 3 +15V 7 OP42 4 –15V 6 VOUT 00271-017 VREF 10V 4095 − V REF 4096 Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming (2-Quadrant) Rev. E | Page 12 of 16 DAC8043 Bipolar Operation (4-Quadrant) scale can be adjusted by loading the DAC register with 1111 1111 1111 and either adjusting the amplitude of VREF or the value of R5 until the desired VOUT is achieved. Figure 19 details a suggested circuit for bipolar, or offset binary, operation. Table 7 shows the digital input to analog output relationship. The circuit uses offset binary coding. Twos complement code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input. Analog/Digital Division The transfer function for the DAC8043 connected in the multiplying mode, as shown in Figure 16, Figure 17, and Figure 19, is Table 7. Bipolar (Offset Binary) Code Table1, 2 Digital Input MSB LSB 1111 1111 1111 Nominal Analog Output (VOUT as Shown in Figure 19) 1000 0000 0001 1 V REF 2048 1000 0000 0000 0111 1111 1111 0 0000 0000 0001 2047 V REF 2048 0000 0000 0000 2048 V REF 2048 where AX assumes a value of 1 for an on bit and 0 for an off bit. 2047 2048 The transfer function is modified when the DAC is connected in the feedback of an operational amplifier, as shown in Figure 18 and becomes VIN VO A1 A2 A3 ... A12 1 2 2 23 24 2 1 V REF 2048 The previous transfer function is the division of an analog voltage (VREF) by a digital word. The amplifier goes to the rails with all bits off because division by zero is infinity. With all bits on the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB, Bit 12, on. DIGITAL INPUT Nominal full scale for Figure 19 circuits is given by 2047 FS V REF 2048 LD SRI CLK VIN Nominal LSB magnitude for Figure 19 circuits is given by RFB 1 LSB V REF 2048 VDD 5V DAC8043 GND 2 3 Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be omitted, adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full VDD VIN R1 100Ω VREF IOUT DAC8043 CONTROL BITS SRI 1/2 OP200 A1 GND CONTROL SERIAL INPUTS DATA INPUT 6 VOUT R4 20kΩ C1 10.33pF RFB OP42 Figure 18. Analog/Digital Divider R2 50Ω 5V VREF IOUT Resistors R3, R4, and R5 must be selected to match within 0.01%, and they all must be of the same (preferably metal foil) type to ensure temperature coefficient matching. Mismatching between R3 and R4 causes offset and full-scale errors, while an R5 to R4 and R3 mismatch results in full-scale error. R5 20kΩ R3 10kΩ 1/2 OP200 A2 ANALOG COMMON Figure 19. Bipolar Operation (4-Quadrant, Offset Binary) Rev. E | Page 13 of 16 VOUT 00271-019 2 00271-018 1 V REF A A A A VO VIN 11 22 33 ... 1212 2 2 2 2 DAC8043 INTERFACING TO THE MC6800 As shown in Figure 20, the DAC8043 may be interfaced to the MC6800 by successively executing memory write instructions while manipulating the data between writes, so that each write presents the next bit. Serial data supplied to the DAC8043 must be present in the right-justified format in Register H and Register L of the microprocessor. A0 In this example, the most significant bits are found in the 0000 and 0001 memory locations. The four MSBs are found in the lower half of 0000 and the eight LSBs in 0001. The data is taken from the DB7 line. ADDRESS BUS (16) 8085 8212 ALE 5V WR The serial data loading is triggered by the CLK pulse, which is asserted by a decoded memory write to the 2000 memory location, R/W, and Φ2. A write to address location 4000 transfers data from the input register to the DAC register. (8) A2 E1 A0 E3 74LS138 ADDRESS DECODER E2 AD0 DATA AD7 DAC8043* *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY. 16-BIT DATA BUS A15 00271-021 CLK LD SRI SOD A0 Figure 21. DAC8043 to 8085 Interface R/W MC6800 (8) A15 E1 Φ2 E3 E2 A0 DAC8043 TO THE 68000 INTERFACE A2 The interface of the DAC8043 to the 68000 microprocessor is shown in Figure 22. Serial data to the DAC is taken from one of the microprocessor’s data bus lines. 74LS138 ADDRESS DECODER DB0 DB7 8-BIT DATA BUS A1 ADDRESS BUS A23 DAC8043* *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY. AS 68000 CS ADDRESS DECODE MICROPROCESSOR Figure 20. DAC8043 to MC6800 Interface DAC8043 INTERFACE TO THE 8085 + VMA The interface of the DAC8043 to the 8085 microprocessor is shown in Figure 21. Note that the SOD line of the microprocessor is used to present data serially to the DAC. CLK VPA 1/4 74HC125 SRI LD DAC8043* UDS Data is clocked into the DAC8043 by executing memory write instructions. The clock input is generated by decoding Address 8000 and WR. Data is loaded into the DAC register with a memory write instruction to Address A000. Rev. E | Page 14 of 16 DB15 DB0 DATA BUS *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY. Figure 22. DAC8043 to 68000 Microprocessor Interface 00271-022 SRI CLK 00271-020 LD DAC8043 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 23. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 24. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. E | Page 15 of 16 1.27 (0.0500) 0.40 (0.0157) 03-27-2007-B 1 DAC8043 ORDERING GUIDE Model 1, 2 DAC8043FP DAC8043FPZ DAC8043FSZ DAC8043GP DAC8043GPZ 1 2 Relative Accuracy ±1 LSB ±1 LSB ±1 LSB ±½ LSB ±½ LSB Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C Z = RoHS Compliant Part. All commercial and industrial temperature range parts are available with burn-in. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00271-0-1/11(E) Rev. E | Page 16 of 16 Package Description 8-Lead PDIP 8-Lead PDIP 16-Lead SOIC_W 8-Lead PDIP 8-Lead PDIP Package Option N-8 N-8 RW-16 N-8 N-8