TI1 DRV8804DW Quad serial interface low-side driver ic Datasheet

DRV8804
SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
www.ti.com
QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC
Check for Samples: DRV8804
FEATURES
•
•
1
•
•
4-Channel Protected Low-Side Driver
– Four NMOS FETs With Overcurrent
Protection
– Integrated Inductive Catch Diodes
– Serial Interface
1.5-A (Single Channel On) / 800-mA (Four
Channels On) Maximum Drive Current per
Channel (at 25°C)
8.2-V to 60-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
APPLICATIONS
•
•
•
•
Relay Drivers
Unipolar Stepper Motor Drivers
Solenoid Drivers
General Low-Side Switch Applications
DESCRIPTION
The DRV8804 provides a 4-channel low side driver with overcurrent protection. It has built-in diodes to clamp
turn-off transients generated by inductive loads and can be used to drive unipolar stepper motors, DC motors,
relays, solenoids, or other loads.
The DRV8804 can supply up to 1.5-A (single channel on) or 800-mA (four channels on) continuous output
current (with adequate PCB heatsinking at 25°C).
A serial interface is provided including a serial data output, which can be daisy-chained to control multiple
devices with one serial interface.
Internal shutdown functions are provided for over current protection, short circuit protection, under voltage
lockout and overtemperature and faults are indicated by a fault output pin.
The DRV8804 is available in a 20-pin thermally-enhanced SOIC package and a 16-pin HTSSOP package
(Eco-friendly: RoHS & no Sb/Br).
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(SOIC) - DW
(HTSSOP) - PWP
(1)
(2)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
Reel of 2000
DRV8804DWR
DRV8804
Tube of 25
DRV8804DW
DRV8804
PACKAGE (2)
Consult Factory
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
DRV8804
SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
8.2V – 60V
Internal
Reference
Regs
UVLO
VM
nENBL
LS Gate
Drive
OCP
&
Gate
Drive
LATCH
8.2V – 60V
Optional
Zener
Int. VCC
VCLAMP
OUT1
Inductive
Load
SDATIN
SDATOUT
Control
Logic
SCLK
RESET
nFAULT
Thermal
Shut down
OCP
&
Gate
Drive
OUT2
Inductive
Load
OCP
&
Gate
Drive
OUT3
OCP
&
Gate
Drive
OUT4
Inductive
Load
Inductive
Load
GND
(multiple pins)
2
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SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
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Table 1. TERMINAL FUNCTIONS
PIN
(HTSSOP)
I/O (1)
5, 6, 7,
14, 15, 16
5, 12,
PPAD
-
Device ground
All pins must be connected to GND.
1
1
-
Device power supply
Connect to motor supply (8.2 V - 60 V).
nENBL
10
8
I
Enable input
Active low enables outputs – internal pulldown
RESET
11
9
I
Reset input
Active-high reset input initializes internal
logic – internal pulldown
LATCH
13
11
I
Latch input
Rising edge latches shift register to output
stage – internal pulldown
SDATIN
18
14
I
Serial data input
Serial data input – internal pulldown
SDATOUT
19
15
O
Serial data output
Serial data output – has weak internal
pullup – see serial interface section for details
SCLK
17
13
I
Serial clock
Serial clock input – internal pulldown
20
16
OD
Fault
Logic low when in fault condition (overtemp,
overcurrent)
OUT1
3
3
O
Output 1
Connect to load 1
OUT2
4
4
O
Output 2
Connect to load 2
OUT3
8
6
O
Output 3
Connect to load 3
OUT4
9
7
O
Output 4
Connect to load 4
VCLAMP
2
2
-
Output clamp voltage
Connect to VM supply, or zener diode to VM
supply
NAME
PIN
(SOIC)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
POWER AND GROUND
GND
VM
CONTROL
STATUS
nFAULT
OUTPUT
(1)
Directions: I = input, O = output, OD = open-drain output
DW (WIDE SOIC) PACKAGE
(TOP SIDE)
VM
VCLAMP
OUT1
OUT2
GND
GND
GND
OUT3
OUT4
nENBL
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
nFAULT
SDATAO
SDATAIN
SCLK
GND
GND
GND
LATCH
NC
RESET
PWP (HTSSOP) PACKAGE
(TOP SIDE)
VM
VCLAMP
OUT1
OUT2
GND
OUT3
OUT4
nENBL
1
16
2
15
3
14
13
4
5
6
7
8
GND
12
11
10
9
nFAULT
SDATAO
SDATAIN
SCLK
GND
LATCH
NC
RESET
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DRV8804
SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE
UNIT
VM
Power supply voltage range
–0.3 to 65
V
VOUTx
Output voltage range
–0.3 to 65
V
VCLAMP
Clamp voltage range
–0.3 to 65
V
SDATOUT,
nFAULT
Output current
20
mA
Peak clamp diode current
1.5
A
1
A
Digital input pin voltage range
–0.5 to 7
V
Digital output pin voltage range
–0.5 to 7
V
Internally limited
A
DC or RMS clamp diode current
SDATOUT,
nFAULT
Peak motor drive output current, t < 1 μS
Continuous total power dissipation
See Dissipation Ratings table
TJ
Operating virtual junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–60 to 150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
DRV8804
THERMAL METRIC
DW
UNITS
20 PINS
θJA
Junction-to-ambient thermal resistance (1)
67.7
θJCtop
Junction-to-case (top) thermal resistance (2)
32.9
(3)
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter (4)
ψJB
Junction-to-board characterization parameter (5)
34.9
(6)
N/A
θJCbot
(1)
(2)
(3)
(4)
(5)
(6)
4
Junction-to-case (bottom) thermal resistance
35.4
8.2
°C/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VM
Power supply voltage range
8.2
60
V
VCLAMP
Output clamp voltage range
8.2
60
V
IOUT
(1)
Continuous output current, single channel on, TA = 25°C, SOIC package (1)
1.5
Continuous output current, four channels on, TA = 25°C, SOIC package (1)
0.8
Continuous output current, single channel on, TA = 25°C, HTSSOP package (1)
1.5
Continuous output current, four channels on, TA = 25°C, HTSSOP package (1)
0.8
A
Power dissipation and thermal limits must be observed.
ELECTRICAL CHARACTERISTICS
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.6
2.1
mA
8.2
V
0.7
V
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V
VUVLO
VM undervoltage lockout
voltage
VM rising
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL
Input low voltage
VIH
Input high voltage
0.6
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Pulldown resistance
2
V
0.45
–20
V
20
μA
100
μA
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
0.5
V
5.5
V
1
µA
SDATAOUT OUTPUT (OPEN-DRAIN OUTPUT WITH INTERNAL PULLUP)
VOL
Output low voltage
IO = 5 mA
VOH
Output high voltage
IO = 100 µA, VM = 24 V
IOH
Output high leakage current
VO = 3.3 V
2.5
4.5
LOW-SIDE FETS
RDS(ON)
FET on resistance
IOFF
Off-state leakage current
VM = 24 V, IO = 700 mA, TJ = 25°C
0.5
VM = 24 V, IO = 700 mA, TJ = 85°C
0.75
–50
0.8
50
Ω
μA
HIGH-SIDE DIODES
VF
Diode forward voltage
VM = 24 V, IO = 700 mA, TJ = 25°C
IOFF
Off-state leakage current
VM = 24 V, TJ = 25°C
tR
Rise time
tF
Fall time
1.2
V
–50
50
μA
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
2.3
3.8
A
OUTPUTS
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tOCP
Overcurrent protection deglitch
time
3.5
µs
tRETRY
Overcurrent protection retry
time
1.2
ms
tTSD
Thermal shutdown temperature
(1)
Die temperature (1)
150
160
180
°C
Not production tested.
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DRV8804
SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
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TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted) (1)
NO.
(1)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
tCYC
Clock cycle time
62
ns
2
tCLKH
Clock high time
25
ns
3
tCLKL
Clock low time
25
ns
4
tSU(SDATIN)
Setup time, SDATIN to SCLK
5
ns
5
tH(SDATIN)
Hold time, SDATIN to SCLK
1
6
tD(SDATOUT)
Delay time, SCLK to SDATOUT
7
tW(LATCH)
Pulse width, LATCH
8
tOE(ENABLE)
Enable time, nENBL to output low
50
9
tD(LATCH)
Delay time, LATCH to output change
50
-
tRESET
RESET pulse width
20
µs
10
tD(RESET)
Reset delay before clock
20
µs
11
tSTARTUP
Startup delay VM applied before clock
55
µs
ns
15
200
ns
ns
ns
ns
Not production tested.
10
RESET
nENBL
VM
7
11
1
LATCH
SCLK
2
3
Data in
valid
SDATIN
OUTx
8
4
SDATOUT
9
5
Data out valid
6
Figure 1. DRV8804 Timing Requirements
6
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SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
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FUNCTIONAL DESCRIPTION
Output Drivers
The DRV8804 contains four protected low-side drivers. Each output has an integrated clamp diode connected to
a common pin, VCLAMP.
VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a zener or TVS
diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be
beneficial when driving loads that require very fast current decay, such as unipolar stepper motors.
In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.
Serial Interface Operation
The DRV8804 is controlled with a simple serial interface. Logically, the interface is shown in Figure 2.
nENBL
LATCH
RESET
SCLK
SDATIN
D
D
Q
OUT1
Q
CLR
CLR
D
D
Q
OUT2
Q
CLR
CLR
D
Q
D
OUT3
Q
CLR
CLR
D
Q
D
OUT4
Q
CLR
CLR
D
Q
SDATOUT
CLR
Figure 2. Serial Interface Operation
Data is shifted into a temporary holding shift register in the part using the SDATIN pin, one bit at each rising
edge of the SCLK pin. Data is simultaneously shifted out of the SDATOUT pin, allowing multiple devices to be
daisy-chained onto one serial port. Note that the SDTAOUT pin has a weak pullup to an internal power supply,
which can support driving another DRV8804 SDATAIN pin at clock frequencies of up to 1 MHz without an
external pullup. To operate at faster than 1-MHz clock frequency, or to interface to devices operating at other
supply voltages, a pullup resistor of approximately 1 kΩ to the chosen logic supply voltage should be used.
A rising edge on the LATCH pin latches the data from the temporary shift register into the output stage.
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nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does
not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic, including the OCP fault. All serial interface
registers are cleared. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so
it is not required to drive RESET at power-up.
Protection Circuits
The DRV8804 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and re-applied.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
8
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SLVSAW4B – JULY 2011 – REVISED NOVEMBER 2011
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THERMAL INFORMATION
Thermal Protection
The DRV8804 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8804 is dominated by the power dissipated in the output FET resistance, or
RDS(ON). Average power dissipation of each FET when running a static load can be roughly estimated by
Equation 1:
P = RDS(ON) · (IOUT)2
(1)
where P is the power dissipation of one FET, RDS(ON) is the resistance of each FET, and IOUT is equal to the
average current drawn by the load. Note that at start-up and fault conditions this current is much higher than
normal running current; these peak currents and their duration also need to be taken into consideration. When
driving more than one load simultaneously, the power in all active output stages must be summed.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
Heatsinking
The DRV8804 package uses a standard SOIC outline, but has the center pins internally fused to the die pad in
order to more efficiently remove heat from the device. The two center leads on each side of the package should
be connected together to as large a copper area on the PCB as is possible to remove heat from the device. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
In general, the more copper area that can be provided, the more power can be dissipated.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
DRV8804DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DRV8804DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8804DWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8804DWR
SOIC
DW
20
2000
346.0
346.0
41.0
Pack Materials-Page 2
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