CS4362
114 dB, 192 kHz 6-Channel D/A Converter
Features
Description
24-Bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Supports PCM or DSD Data Formats
Selectable Digital Filters
Volume Control with Soft Ramp
The CS4362 is a complete 6-channel digital-to-analog
system including digital interpolation, fifth-order deltasigma digital-to-analog conversion, digital de-emphasis,
volume control and analog filtering. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4362 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players.
SACD players, A/V receivers, digital TV’s and VCR’s,
mixing consoles, effects processors and set-top box
systems.
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
Dedicated DSD inputs
Low Clock Jitter Sensitivity
Simultaneous Support for Two Synchronous
Sample Rates for DVD Audio
µC or Stand-Alone Operation
ORDERING INFORMATION
CS4362-KQ -10 to 70
CS4362-BQ -40 to 85
CDB4362
48-pin LQFP
48-pin LQFP
Evaluation Board
I
M1/S CL/CCLK
M3/DS D_S CLK
M 2/SDA/CDIN
M0/A D0/CS V LC
MUTEC[1:6]
6
RST
Control Port/Mode S elect
V olu m e C o nt r o l
VLS
E xt e rn a l
M u t e C o n tr ol
I n t e r p o la t i o n F i lt e r
∆Σ D A C
A n a lo g F i lt e r
A O U T A1+
A O U T A 1-
S C LK1
M ixe r
LRCK1
V olu m e C o nt r o l
I nt e r p o l a t i o n F i lt e r
∆Σ D A C
A n a lo g F i lt e r
A O U T B1+
A O U T B 1-
V o lu m e C o nt r o l
I n t e r p o la t i o n F i lt e r
∆Σ D A C
A n a lo g F i lt e r
A O U T A2+
A O U T A 2-
V olu m e C o nt r o l
I nt e r p o l a t i o n F i lt e r
∆Σ D A C
A n a lo g F i lt e r
A O U T B2+
A O U T B 2-
V o lu m e C o nt r o l
I n t e r p o la t i o n F i lt e r
∆Σ D A C
A n a lo g F i lt e r
A O U T A3+
A O U T A 3-
I nt e r p o l a t i o n F i lt e r
∆Σ D A C
A n a lo g F i lt e r
A O U T B3+
A O U T B 3-
S e ri a l P o rt
S C LK 2
L RCK 2
SD I N1
SD I N2
Mixer
SD I N3
Mixer
M CLK
V olu m e C o nt r o l
÷2
DS Dxx
VQ
6
FILT+
VD
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
G ND
G ND
VA
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAR ‘02
DS257PP2
1
CS4362
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
7.
8.
9.
CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
REGISTER QUICK REFERENCE .......................................................................................... 14
REGISTER DESCRIPTION .................................................................................................... 15
PIN DESCRIPTION ................................................................................................................. 24
APPLICATIONS ...................................................................................................................... 27
5.1 Grounding and Power Supply Decoupling ....................................................................... 27
5.2 Oversampling Modes ....................................................................................................... 27
5.3 Recommended Power-up Sequence ............................................................................... 27
5.4 Analog Output and Filtering ............................................................................................. 27
5.5 Interpolation Filter ............................................................................................................ 27
5.6 Clock Source Selection .................................................................................................... 28
5.7 Using DSD mode ............................................................................................................. 28
CONTROL PORT INTERFACE .............................................................................................. 28
6.1 Enabling the Control Port ................................................................................................. 28
6.2 Format Selection .............................................................................................................. 28
6.3 I2C Format ....................................................................................................................... 29
6.3.1 Writing in I2C Format ........................................................................................... 29
6.3.2 Reading in I2C Format ........................................................................................ 29
6.4 SPI Format ....................................................................................................................... 29
6.4.1 Writing in SPI ...................................................................................................... 29
6.5 Memory Address Pointer (MAP) ...................................................................................... 30
PARAMETER DEFINITIONS.................................................................................................. 38
REFERENCES ........................................................................................................................ 38
PACKAGE DIMENSIONS ....................................................................................................... 39
LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 8
Figure 2. Direct Stream Digital - Serial Audio Input Timing ............................................................. 9
Figure 3. Control Port Timing - I2C Format ................................................................................... 10
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any
kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied
on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining
to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as
the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing
this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property
rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising
or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material
and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained
from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law
and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH
APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use
those components in a standard I2C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
2
CS4362
Figure 4. Control Port Timing - SPI Format................................................................................... 11
Figure 5. Typical Connection Diagram Control Port...................................................................... 12
Figure 6. Typical Connection Diagram Stand-Alone ..................................................................... 13
Figure 7. Control Port Timing, I2C Format .................................................................................... 30
Figure 8. Control Port Timing, SPI Format.................................................................................... 30
Figure 9. Single Speed (fast) Stopband Rejection ........................................................................ 31
Figure 10. Single Speed (fast) Transition Band ............................................................................ 31
Figure 11. Single Speed (fast) Transition Band (detail) ................................................................ 31
Figure 12. Single Speed (fast) Passband Ripple .......................................................................... 31
Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 31
Figure 14. Single Speed (slow) Transition Band........................................................................... 31
Figure 15. Single Speed (slow) Transition Band (detail)............................................................... 32
Figure 16. Single Speed (slow) Passband Ripple......................................................................... 32
Figure 17. Double Speed (fast) Stopband Rejection..................................................................... 32
Figure 18. Double Speed (fast) Transition Band........................................................................... 32
Figure 19. Double Speed (fast) Transition Band (detail)............................................................... 32
Figure 20. Double Speed (fast) Passband Ripple......................................................................... 32
Figure 21. Double Speed (slow) Stopband Rejection ................................................................... 33
Figure 22. Double Speed (slow) Transition Band ......................................................................... 33
Figure 23. Double Speed (slow) Transition Band (detail) ............................................................. 33
Figure 24. Double Speed (slow) Passband Ripple ....................................................................... 33
Figure 25. Quad Speed (fast) Stopband Rejection ....................................................................... 33
Figure 26. Quad Speed (fast) Transition Band ............................................................................. 33
Figure 27. Quad Speed (fast) Transition Band (detail) ................................................................. 34
Figure 28. Quad Speed (fast) Passband Ripple ........................................................................... 34
Figure 29. Quad Speed (slow) Stopband Rejection...................................................................... 34
Figure 30. Quad Speed (slow) Transition Band ............................................................................ 34
Figure 31. Quad Speed (slow) Transition Band (detail) ................................................................ 34
Figure 32. Quad Speed (slow) Passband Ripple .......................................................................... 34
Figure 33. Format 0 - Left Justified up to 24-bit Data.................................................................... 35
Figure 34. Format 1 - I2S up to 24-bit Data................................................................................... 35
Figure 35. Format 2 - Right Justified 16-bit Data .......................................................................... 35
Figure 36. Format 3 - Right Justified 24-bit Data .......................................................................... 35
Figure 37. Format 4 - Right Justified 20-bit Data .......................................................................... 36
Figure 38. Format 5 - Right Justified 18-bit Data .......................................................................... 36
Figure 39. De-Emphasis Curve..................................................................................................... 36
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, or 3) ....................................... 36
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ...................................................... 37
Figure 42. Recommended Output Filter........................................................................................ 37
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Mode............................................................................ 16
Table 2. Digital Interface Formats - DSD Mode ............................................................................ 16
Table 3. ATAPI Decode ................................................................................................................ 21
Table 4. Example Digital Volume Settings .................................................................................... 22
Table 5. Common Clock Frequencies........................................................................................... 26
Table 6. Digital Interface Format, Stand-Alone Mode Options...................................................... 26
Table 7. Mode Selection, Stand-Alone Mode Options .................................................................. 26
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 26
3
CS4362
1.
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth
10 Hz to 20 kHz, unless otherwise specified; Test load R L = 3 kΩ, CL = 100 pF, VA = 5 V, VD = 3.3V (see Figure 5)
For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;
For Double Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;
For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).
Parameters
Symbol
Min
Typ
Max
Unit
CS4362-KQ Dynamic Performance - All PCM modes and DSD (Note 1)
Specified Temperature Range
Dynamic Range (Note 2)
TA
24-bit
unweighted
A-Weighted
16-bit unweighted
(Note 3) A-Weighted
Total Harmonic Distortion + Noise
24-bit
16-bit
(Note 3)
(Note 2) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio
Interchannel Isolation
(1 kHz)
-10
-
70
°C
105
108
-
111
114
94
97
-
dB
dB
dB
dB
-
-100
-91
-51
-94
-74
-34
-94
-
dB
dB
dB
dB
dB
dB
-
114
-
dB
-
90
-
dB
-40
-
85
°C
102
105
-
111
114
94
97
-
dB
dB
dB
dB
-
-100
-91
-51
-94
-74
-34
-91
-
dB
dB
dB
dB
dB
dB
-
114
-
dB
-
90
-
dB
CS4362-BQ Dynamic Performance - All PCM modes and DSD (Note 4)
Specified Temperature Range
Dynamic Range (Note 2)
TA
24-bit
unweighted
A-Weighted
16-bit unweighted
(Note 3) A-Weighted
Total Harmonic Distortion + Noise
24-bit
16-bit
(Note 3)
(Note 2) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio
Interchannel Isolation
(1 kHz)
Notes: 1. CS4362-KQ parts are tested at 25 °C.
2. One-half LSB of triangular PDF dither is added to data.
3. Performance limited by 16-bit quantization noise.
4. CS4362-BQ parts are tested at the extremes of the specified temperature range and Min/Max
performance numbers are guaranteed across the specified temperature range, TA. Typical numbers are
taken at 25 °C.
4
CS4362
ANALOG CHARACTERISTICS (Continued)
Parameters
Analog Output - All PCM modes and DSD
Full Scale Differential Output Voltage (Note 5)
Quiescent Voltage
Max Current from VQ
Interchannel Gain Mismatch
Gain Drift
Output Impedance
AC-Load Resistance
Load Capacitance
(Note 5)
Symbol
Min
Typ
Max
Units
VFS
VQ
IQMAX
88% VA
-
92% VA
50% VA
1
94% VA
-
Vpp
VDC
µA
ZOUT
RL
CL
3
-
0.1
100
100
-
100
dB
ppm/°C
Ω
kΩ
pF
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
normal operation, VA= 5V
VD= 5V
VD= 3.3V
Interface current, VLC=5V (Note 7, 8)
VLS=5V
power-down state (all supplies) (Note 9)
Power Dissipation
(Note 6)
VA = 5 V, VD = 3.3 V
normal operation
power-down (Note 9)
VA = 5 V, VD = 5 V
normal operation
power-down (Note 9)
Package Thermal Resistance
IA
ID
ID
ILC
ILS
Ipd
-
50
38
25
2
84
200
55
60
40
-
mA
mA
mA
µA
µA
µA
-
335
1
440
1
48
15
60
40
410
575
-
mW
mW
mW
mW
°C/Watt
°C/Watt
dB
dB
Power Supplies
Power Supply Current
(Note 6)
Power Supply Rejection Ratio (Note 10)
(1 kHz)
(60 Hz)
θJA
θJC
PSRR
Notes: 5. VFS is tested under load RL and includes attenuation due to ZOUT
6. Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
7. ILC measured with no external loading on the SDA pin.
8. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied
or pulled low. Logic tied to pin 16 needs to be able to sink this current.
9. Power down mode is defined as RST pin = Low with all clock and data lines held static.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
5
CS4362
ANALOG FILTER RESPONSE
Fast Roll-Off
Slow Roll-Off (Note 11)
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note 12)
Passband (Note 13)
to -0.01 dB corner
0
.454
0
0.417
Fs
to -3 dB corner
0
.499
0
0.499
Fs
Frequency Response 10 Hz to 20 kHz
-0.01
+0.01
-0.01
+0.01
dB
StopBand
.547
.583
Fs
StopBand Attenuation
(Note 14)
90
64
dB
Group Delay
12/Fs
6.5/Fs
s
Passband Group Delay Deviation 0 - 20 kHz
±0.41/Fs
±0.14/Fs
s
De-emphasis Error (Note 15)
Fs = 32 kHz
±0.23
±0.23
dB
(Relative to 1kHz)
Fs = 44.1 kHz
±0.14
±0.14
dB
Fs = 48 kHz
±0.09
±0.09
dB
Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96kHz (Note 12)
Passband (Note 13)
to -0.01 dB corner
0
.430
0
.296
Fs
to -3 dB corner
0
.499
0
.499
Fs
Frequency Response 10 Hz to 20 kHz
-0.01
0.01
-0.01
0.01
dB
StopBand
.583
.792
Fs
StopBand Attenuation
(Note 14)
80
70
dB
Group Delay
4.6/Fs
3.9/Fs
s
Passband Group Delay Deviation 0 - 20 kHz
±0.03/Fs
±0.01/Fs
s
Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192kHz (Note 12)
Passband (Note 13)
to -0.01 dB corner
0
.105
0
.104
Fs
to -3 dB corner
0
.490
0
.481
Fs
Frequency Response 10 Hz to 20 kHz
-0.01
0.01
-0.01
0.01
dB
StopBand
.635
.868
Fs
StopBand Attenuation
(Note 14)
90
75
dB
Group Delay
4.7/Fs
4.2/Fs
s
Passband Group Delay Deviation 0 - 20 kHz
±0.01/Fs
±0.01/Fs
s
Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 12)
Passband (Note 13)
to -0.1 dB corner
0
20
kHz
to -3 dB corner
0
120
kHz
Frequency Response 10 Hz to 20 kHz
-.01
0.1
dB
Notes: 11. Slow Roll-Off interpolation filter is only available in control port mode.
12. Filter response is not tested but is guaranteed by design.
13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
14. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs.
Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.
15. De-emphasis is available only in Single Speed Mode; Only 44.1kHz De-emphasis is available in StandAlone Mode
6
CS4362
DIGITAL CHARACTERISTICS
(For KQ TA = -10 to +70 °C; For BQ TA = -40 to +85 °C; VLC = VLS =
1.8 V to 5.5 V)
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Symbol
VIH
Serial Data Port
VIH
Control Port
VIL
Serial Data Port
VIL
Control Port
Min
70% VLS
70% VLC
Typ
-
Max
-
Units
V
V
-
-
20% VLS
20% VLC
V
V
(Note 8)
-
8
3
VA
0
±10
-
µA
pF
mA
V
V
Input Leakage Current
Input Capacitance
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
ABSOLUTE MAXIMUM RATINGS
Iin
VOH
VOL
(GND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
Input Current, Any Pin Except Supplies
Digital Input Voltage
Serial data port interface
Control port interface
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
VD
VLS
VLC
Iin
VIND-S
VIND-C
TA
Tstg
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-55
-65
Max
6.0
6.0
6.0
6.0
±10
VLS+ 0.4
VLC+ 0.4
125
150
Units
V
V
V
V
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
Symbol
VA
VD
VLS
VLC
Min
4.5
3.0
1.8
1.8
Typ
5.0
3.3
5.0
5.0
Max
5.5
5.5
5.5
5.5
Units
V
V
V
V
7
CS4362
SWITCHING CHARACTERISTICS (For KQ TA = -10 to +70 °C; For BQ TA = -40 to +85 °C; VLS =
1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30pF)
Parameters
Symbol
Min
Typ
Max
Units
Single Speed Mode
1.024
-
51.2
MHz
Double Speed Mode
6.400
-
51.2
MHz
Quad Speed Mode
6.400
-
51.2
MHz
40
50
60
%
4
50
100
-
50
100
200
kHz
kHz
kHz
45
50
55
%
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
SCLK Period
tsclkw
2
-----------------MCLK
-
-
ns
tsclkw
4
-----------------MCLK
-
-
ns
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDATA valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDATA hold time
tsdh
20
-
-
ns
0.25
1.00
4.00
MCLK Frequency
(Note 16)
MCLK Duty Cycle
Input Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
LRCK Duty Cycle
SCLK Pulse Width Low
(Note 17)
SCLK rising to LRCK edge delay
LRCK1 to LRCK2 frequency ratio
(Note 18)
Notes: 16. See Table 5 on page 26 for suggested MCLK frequencies
17. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
18. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK
.
LR C K
t s clkh
t slrs
t s lrd
t sclkl
S C LK
t sd lrs
t sd h
S D A TA
Figure 1. Serial Mode Input Timing
8
CS4362
DSD - SWITCHING CHARACTERISTICS (TA= -10 to 70°C; Logic 0 = GND; VLS = 1.8 V to
5.5 V; Logic 1 = VLS Volts; CL = 30 pF)
Parameter
Master Clock Frequency
MCLK Duty Cycle
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
Symbol
(Note 19)
(All DSD modes)
tsclkl
tsclkh
(64x Oversampled)
(128x Oversampled)
DSD_L / _R valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_L or DSD_R hold time
tsdlrs
tsdh
Min
4.096
40
20
20
1.024
2.048
20
20
Typ
50
-
Max
38.4
60
3.2
6.4
-
Unit
MHz
%
ns
ns
MHz
MHz
ns
ns
Note: 19. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The
proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
t s c lk h
t sclkl
DSD_SC LK
t sd lrs
t sd h
D S D _L, D S D_R
Figure 2. Direct Stream Digital - Serial Audio Input Timing
9
CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(For KQ TA = -10 to +70 °C; For BQ TA = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic
1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-
1
µs
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
tack
-
(Note 22)
ns
SDA Hold Time from SCL Falling
(Note 20)
SDA Setup time to SCL Rising
Acknowledge Delay from SCL Falling
(Note 21)
Notes: 20. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
21. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
22.
15
15
15
--------------------- for Single-Speed Mode, --------------------- for Double-Speed Mode, ------------------ for Quad-Speed Mode.
256 × Fs
128 × Fs
64 × Fs
RST
t
irs
R e p e a te d
S top
S t a rt
S ta rt
t rd
t fd
S to p
SDA
t
b uf
t
t
hd st
t
h igh
t fc
hd st
SCL
t
lo w
t
h dd
t s ud
t a ck
t s us t
Figure 3. Control Port Timing - I2C Format
10
t rc
t su sp
CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(For KQ TA = -10 to +70 °C; For BQ TA = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic
1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
MCLK
-----------------2
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
1 ----------------MCLK
-
ns
CCLK High Time
tsch
1 ----------------MCLK
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Edge to CS Falling
(Note 23)
CCLK Rising to DATA Hold Time
(Note 24)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 25)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 25)
tf2
-
100
ns
Notes: 23. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
24. Data must be held for sufficient time to bridge the transition time of CCLK.
25. For FSCK < 1 MHz.
RST
t srs
CS
t sp i t css
t scl
t sch
t csh
C CLK
t r2
t f2
C D IN
t dsu t
dh
Figure 4. Control Port Timing - SPI Format
11
CS4362
+3.3 V to +5 V
+5 V
+
1 µF
0.1 µ F
4
VD
6
7
9
PC M
D igital
A udio
S ource
10
12
8
11
13
+1.8 V to +5 V
M C LK
LR CK 1
SC LK 1
A O UT A1+
LR C K2
A O UT A1-
SC LK 2
SD IN 1
A O UT B1+
SD IN 2
A O UT B1-
A O UT A2-
VLS
C S 4362
A O UT B2+
A O UT B2-
2
1
DS D
Audio
S ource
48
47
46
42
19
15
M icroC ontroller
16
40
38
37
A nalog C onditioning
and M uting
A nalog C onditioning
and M uting
D S DA 1
A O UT A3+
D S DB 1
A O UT A3-
35
36
A nalog C onditioning
and M uting
34
33
A nalog C onditioning
and M uting
29
30
A nalog C onditioning
and M uting
D S DA 2
D S DB 2
A O UT B3+
D S DA 3
A O UT B3-
28
27
A nalog C onditioning
and M uting
D S DB 3
D S D_SC LK
M UT E C1
41
M UT E C2 26
25
M UT EC 3
24
M UT EC 4
23
M UT EC 5
M UT EC 6 22
RS T
SC L/CC LK
M ute
Drive
SD A /CD IN
AD O /CS
2 KΩ
2 KΩ
17
39
SD IN 3
0.1 µ F
3
Note*
18
+1.8 V to +5 V
F ILT + 20
VLC
CMOUT
0.1 µ F
Note*: N ecessary for
control port operation
I 2C
+
21
0.1 µ F + 1 µ F
GND
5
GND
31
Figure 5. Typical Connection Diagram Control Port
12
1 µF
32
VA
A O UT A2+
43
+
0.1 µ F
0.1 µ F
47 µ F
CS4362
+3.3 V to +5 V
+5 V
+
1 µF
4
VD
V LS
Note D SD
+
0.1 µ F
0.1 µ F
1 µF
32
VA
47 K Ω
6
7
9
PCM
Digital
A udio
Source
10
12
8
11
13
M CLK
LRCK1
S CLK 1
A O U TA1+
LRCK2
A O U TA 1-
S CLK 2
M UTE C1
S DIN1
43
A O U TB1+
S DIN3
M UTE C2
V LS
A O U TA2+
A O U TA 23
2
1
48
47
46
DSDA1
M UTE C3
A O U TB2+
DSDB2
A O U TB 2-
DSDA3
M UTE C4
A O U TA 3M UTE C5
42
15
16
17
19
Note
M 3(DS D _SC LK )
M2
A O U TB3+
A O U TB 3-
M1
26
A nalog Conditioning
and M uting
M UTE C6
RS T
FILT+
CM O UT
18
35
36
25
A nalog Conditioning
and M uting
34
33
24
A nalog Conditioning
and M uting
29
30
23
A nalog Conditioning
and M uting
28
27
22
A nalog Conditioning
and M uting
M0
VLC
+1.8 V to +5 V
37
DSDB3
Note D SD
S tand-Alone
M ode
Configuration
38
DSDB1
DSDA2
A O U TA3+
47 K Ω
A nalog Conditioning
and M uting
CS4362
0.1 µ F
DS D
A udio
S ource
40
41
S DIN2
A O U TB 1-
+1.8 V to +5 V
39
20
+
21
0.1 µ F + 1 µF
V LC
0.1 µ F
47 µ F
0.1 µF
Note VLC : If series resistors are
used they m ust be <1k O hm . If
possible tie V LC to the V D supply
to reduce possible excess current
consum ption from V LC.
G ND
5
G ND
31
Note D SD : For DS D operation:
1) LRCK 1 m ust be tied to V LS and
rem ain static high.
2) M 3 P CM stand-alone configuration
pin becom es DS D_S CLK
Figure 6. Typical Connection Diagram Stand-Alone
13
CS4362
2.
Addr
REGISTER QUICK REFERENCE
Function
01h
Mode Control 1
02h
Mode Control 2
default
default
03h
Mode Control 3
default
04h
Filter Control
default
05h
Invert Control
06h
Mixing Control
Pair 1 (AOUTx1)
07h
Vol. Control A1
default
default
default
08h
Vol. Control B1
default
09h
Mixing Control
Pair 2 (AOUTx2)
default
0Ah Vol. Control A2
default
0Bh Vol. Control B2
default
0Ch Mixing Control
Pair 3 (AOUTx3)
default
0Dh Vol. Control A3
default
0Eh Vol. Control B3
default
12h
Chip Revision
default
14
7
6
CPEN
FREEZE
5
4
3
2
1
MCLKDIV Reserved DAC3_DIS DAC2_DIS DAC1_DIS
0
PDN
0
0
0
0
0
Reserved
DIF2
DIF1
DIF0
Reserved
0
0
0
0
0
0
0
0
SZC1
SZC0
SNGLVOL
RMP_UP
MUTEC+/-
AMUTE
MUTEC1
MUTEC0
1
0
0
0
0
1
0
0
Reserved
Reserved
Reserved
FILT_SEL
Reserved
DEM1
DEM0
RMP_DN
0
0
0
0
0
0
0
0
Reserved
Reserved
INV_B3
INV_A3
INV_B2
INV_A2
INV_B1
INV_A1
0
0
1
SDIN3CLK SDIN2CLK SDIN1CLK
0
0
0
0
0
0
0
0
P1_A=B
P1ATAPI4
P1ATAPI3
P1ATAPI2
P1ATAPI1
P1ATAPI0
P1FM1
P1FM0
0
0
1
0
0
1
0
0
A1_MUTE
A1_VOL6
A1_VOL5
A1_VOL4
A1_VOL3
A1_VOL2
A1_VOL1
A1_VOL0
0
0
0
0
0
0
0
0
B1_MUTE
B1_VOL6
B1_VOL5
B1_VOL4
B1_VOL3
B1_VOL2
B1_VOL1
B1_VOL0
0
0
0
0
0
0
0
0
P2_A=B
P2ATAPI4
P2ATAPI3
P2ATAPI2
P2ATAPI1
P2ATAPI0
P2FM1
P2FM0
0
0
1
0
0
1
0
0
A2_MUTE
A2_VOL6
A2_VOL5
A2_VOL4
A2_VOL3
A2_VOL2
A2_VOL1
A2_VOL0
0
0
0
0
0
0
0
0
B2_MUTE
B2_VOL6
B2_VOL5
B2_VOL4
B2_VOL3
B2_VOL2
B2_VOL1
B2_VOL0
0
0
0
0
0
0
0
0
P3_A=B
P3ATAPI4
P3ATAPI3
P3ATAPI2
P3ATAPI1
P3ATAPI0
P3FM1
P3FM0
0
0
1
0
0
1
0
0
A3_MUTE
A3_VOL6
A3_VOL5
A3_VOL4
A3_VOL3
A3_VOL2
A3_VOL1
A3_VOL0
0
0
0
0
0
0
0
0
B3_MUTE
B3_VOL6
B3_VOL5
B3_VOL4
B3_VOL3
B3_VOL2
B3_VOL1
B3_VOL0
0
0
0
0
0
0
0
0
PART3
PART2
PART1
PART0
Reserved
Reserved
Reserved
Reserved
1
1
1
0
-
-
-
-
CS4362
3.
REGISTER DESCRIPTION
Note:
All registers are read/write in I2C mode and write only in SPI, unless otherwise noted.
3.1
Mode Control 1 (address 01h)
7
CPEN
0
3.1.1
6
FREEZE
0
5
MCLKDIV
0
4
Reserved
0
3
DAC3_DIS
0
2
DAC2_DIS
0
1
DAC1_DIS
0
0
PDN
1
CONTROL PORT ENABLE (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean powerup, the user should write this bit within 10 ms following the release of Reset.
3.1.2
FREEZE CONTROLS (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
3.1.3
MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.
3.1.4
DAC PAIR DISABLE (DACX_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power down bit is enabled to eliminate the
possibility of audible artifacts.
15
CS4362
3.1.5
POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation in Control Port mode can occur.
3.2
Mode Control 2 (address 02h)
7
Reserved
0
3.2.1
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
Reserved
0
2
SDIN3CLK
0
1
SDIN2CLK
0
0
SDIN1CLK
0
DIGITAL INTERFACE FORMAT (DIF)
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 33-38.
DIF2
DIF1
DIF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DESCRIPTION
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
Format
FIGURE
0
1
2
3
4
5
33
34
35
36
37
38
Table 1. Digital Interface Formats - PCM Mode
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital Interface Format pins.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIFO
0
1
0
1
0
1
0
1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 2. Digital Interface Formats - DSD Mode
16
CS4362
3.2.2
SERIAL AUDIO DATA CLOCK SOURCE (SDINXCLK)
Default = 0
0 - SDINx clocked by SCLK1 and LRCK1
1 - SDINx clocked by SCLK2 and LRCK2
Function:
The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given
SDINx line. For more details see “Clock Source Selection” on page 28.
3.3
Mode Control 3 (address 03h)
7
SZC1
1
3.3.1
6
SZC0
0
5
SNGLVOL
0
4
RMP_UP
0
3
Reserved
0
2
AMUTE
1
1
MUTEC1
0
0
MUTEC0
0
SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
17
CS4362
3.3.2
SINGLE VOLUME CONTROL (SNGLVOL)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel
Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
3.3.3
SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change
or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
When disabled, an immediate un-mute is performed in these instances.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN
bit.
3.3.4
MUTEC POLARITY (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the
MUTEC pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Note: When the on board mute circuitry is designed for active low, the MUTEC outputs will be high
(un-muted) for the period of time during reset and before this bit is enabled to 1.
3.3.5
AUTO-MUTE (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained
and the Mute Control pin will go active during the mute period. The muting function is affected, similar
to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
18
CS4362
3.3.6
MUTE PIN CONTROL(MUTEC1, MUTEC0)
Default = 00
00 - Six mute control signals
01 - Three mute control signals
10 - One mute control signal
11 - Reserved
Function:
Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins.
When set to ‘00’, there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B
on MUTEC2, etc. When set to ‘01’, there are three mute control signals, one for each stereo pair:
AOUT1A and AOUT1B on MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and
AOUT3B on MUTEC3. When set to ‘10’, there is a single mute control signal on the MUTEC1 pin.
3.4
Filter Control (address 04h)
7
Reserved
0
3.4.1
6
Reserved
0
5
Reserved
0
4
FILT_SEL
0
3
Reserved
0
2
DEM1
0
1
DEM0
0
0
RMP_DN
0
INTERPOLATION FILTER SELECT (FILT_SEL)
Default = 0
0 - Fast roll-off
1 - Slow roll-off
Function:
This Function allows the user to select whether the interpolation filter has a fast or slow roll off. For
filter characteristics please see Section 1.
3.4.2
DE-EMPHASIS CONTROL (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 39)
De-emphasis is only available in Single Speed Mode.
19
CS4362
3.4.3
SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed prior to executing a filter mode change. When this feature is enabled, this
mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control
3 register. When disabled, an immediate mute is performed prior to executing a filter mode change.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP
bit.
3.5
Invert control (address 05h)
7
Reserved
0
3.5.1
6
Reserved
0
5
INV_B3
0
4
INV_A3
0
3
INV_B2
0
2
INV_A2
0
1
INV_B1
0
0
INV_A1
0
INVERT SIGNAL POLARITY (INV_XX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
3.6
Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
7
Px_A=B
0
3.6.1
6
PxATAPI4
0
5
PxATAPI3
1
4
PxATAPI2
0
3
PxATAPI1
0
2
PxATAPI0
1
1
PxFM1
0
0
PxFM0
0
CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel
Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are
determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.
20
CS4362
3.6.2
ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The CS4362 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information.
ATAPI4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
AOUTBx
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
Table 3. ATAPI Decode
21
CS4362
3.6.3
FUNCTIONAL MODE (FM)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode
Function:
Selects the required range of input sample rates or DSD Mode. When DSD mode is selected for any
channel pair then all pairs will switch to DSD mode.
3.7
Volume control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)
7
xx_MUTE
0
3.7.1
6
xx_VOL6
0
5
xx_VOL5
0
4
xx_VOL4
0
3
xx_VOL3
0
2
xx_VOL2
0
1
xx_VOL1
0
0
xx_VOL0
0
MUTE (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output
will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero
Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bits.
3.7.2
VOLUME CONTROL (XX_VOL)
Default = 0 (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from 0 to -127 dB. Volume settings are decoded as shown in Table 4. The volume changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent
to enabling the MUTE bit.
Binary Code
Decimal Value
Volume Setting
0000000
0010100
0101000
0111100
1011010
0
20
40
60
90
0 dB
-20 dB
-40 dB
-60 dB
-90 dB
Table 4. Example Digital Volume Settings
22
CS4362
3.8
Chip Revision (address 12h)
7
PART3
1
3.8.1
6
PART2
1
5
PART1
1
4
PART0
0
3
Reserved
-
2
Reserved
-
1
Reserved
-
0
Reserved
-
PART NUMBER ID (PART) [READ ONLY]
1110 - CS4362
Function:
This read-only register can be used to identify the model number of the device.
23
CS4362
AOUTB1-
AOUTB1+
AOUTA1+
AOUTA1-
M UT EC1
VLS
M3(DSD_SCLK)
TST
TST
DSDB3
DSDA3
DSDB2
4. PIN DESCRIPTION
48 47 46 45 44 4 3 42 41 40 39 38 37
DSDA2
1
36
DSDB1
2
35
AOUTA2+
DSDA1
3
34
AOUTB2+
AOUTA2-
VD
4
33
AOUTB2-
GND
5
32
VA
MCLK
6
31
GND
LRCK1(DSD_EN)
7
30
AOUTA3-
SDIN1
8
29
AOUTA3+
SCLK1
9
28
AOUTB3+
LRCK2
10
27
AOUTB3-
SDIN2
11
26
MUTEC2
SCLK2
12
25
MUTEC3
CS4362
MU TE C 4
M U TEC 5
MU TE C 6
VQ
FILT +
VLC
RST
M0(AD0/CS)
M1(S D A/C D IN )
M2(SC L/C CLK )
TS T
S D IN 3
13 14 15 16 17 1 8 19 20 21 22 23 24
Pin Name
#
Pin Description
VD
4
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages.
GND
5
31
Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK
6
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5
illustrates several standard audio sample rates and the required master clock frequencies.
LRCK1
LRCK2
7
10
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN1
SDIN2
SDIN3
8
11
13
Serial Data Input (Input) - Input for two’s complement serial audio data.
SCLK1
SCLK2
9
12
Serial Clock (Input) - Serial clocks for the serial audio interface.
TST
14
44
45
Test - These pins need to be tied to analog ground.
RST
19
Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low.
VA
32
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages.
VLS
43
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio
interface. Refer to the Recommended Operating Conditions for appropriate voltages.
VLC
18
Control Port Power (Input) - Determines the required signal level for the control port and stand
alone configuration pins. Refer to the Recommended Operating Conditions for appropriate voltages.
24
CS4362
Pin Name
#
Pin Description
VQ
21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be
capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device
performance. However, VQ can be used to bias the analog circuitry assuming there is no AC
signal component and the DC current is less then the maximum specified in the Analog Characteristics and Specifications section.
FILT+
20
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection
Diagram.
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,MUTEC1
MUTEC2
MUTEC3
MUTEC4
MUTEC5
MUTEC6
39,40 Differential Analog Output (Output) - The full scale differential analog output level is specified
37,38 in the Analog Characteristics specification table.
35,36
33,34
29,30
27,28
41
26
25
24
23
22
Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset,
muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These
pins are intended to be used as a control for external mute circuits on the line outputs to prevent
the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and
pops.
Stand Alone Definitions
M0
M1
M2
M3
17
16
15
42
Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables
6 and 7.
Control Port Definitions
SCL/CCLK
15
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external
pull-up resistor to the logic interface voltage in I2C mode as shown in the Typical Connection
Diagram.
SDA/CDIN
16
Serial Control Port Data (Input/Output) - SDA is a data I/O line in I2C mode and is open drain,
requiring an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram; CDIN is the input data line for the control port interface in SPI mode.
AD0/CS
17
Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I2C
mode; CS is the chip select signal for SPI mode.
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
3
2
1
48
47
46
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
DSD_SCLK
42
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.
DSD_EN
7
DSD Enable (Input) - When held at logic ‘1’ the device will enter DSD mode (Stand-Alone mode
only).
DSD Definitions
25
CS4362
Mode
(sample-rate range)
Sample
Rate
(kHz)
MCLK Ratio
Single Speed
(4 to 50 kHz)
256x
8.1920
11.2896
12.2880
128x
8.1920
11.2896
12.2880
64x
11.2896
12.2880
32
44.1
48
MCLK Ratio
Double Speed
(50 to 100 kHz)
Control port
only modes
MCLK (MHz)
64
88.2
96
MCLK Ratio
176.4
Quad Speed
(100 to 200 kHz)
192
384x
12.2880
16.9344
18.4320
192x
12.2880
16.9344
18.4320
96x
16.9344
18.4320
512x
16.3840
22.5792
24.5760
256x
16.3840
22.5792
24.5760
128x
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
192x
33.8688
36.8640
1024x*
32.7680
45.1584
49.1520
512x*
32.7680
45.1584
49.1520
256x*
45.1584
49.1520
Table 5. Common Clock Frequencies
*Note: These modes are only available in control port mode by setting the MCLKDIV bit = 1.
M1
(DIF1)
0
0
M0
(DIF0)
0
1
1
1
0
1
DESCRIPTION
FORMAT
FIGURE
0
1
33
34
2
3
35
36
Left Justified, up to 24-bit data
2
I S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
Table 6. Digital Interface Format, Stand-Alone Mode Options
M3
0
0
1
1
M2
(DEM)
0
1
0
1
DESCRIPTION
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
Single-Speed with 44.1kHz De-Emphasis; see Figure 39
Double-Speed (50 to 100 kHz sample rates)
Quad-Speed (100 to 200 kHz sample rates)
Table 7. Mode Selection, Stand-Alone Mode Options
DSD_Mode
(LRCK1)
1
1
1
1
1
1
1
1
M2
M1
M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options
26
CS4362
5. APPLICATIONS
5.1
Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4362
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figures 5 & 6 show the recommended power arrangement with VA, VD, VLS and VLC connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be placed on each supply pin (see Section 1 for recommended voltages).
5.2
Oversampling Modes
The CS4362 operates in one of three oversampling
modes based on the input sample rate. Mode selection is determined by the M3 and M2 pins in StandAlone mode or the FM bits in Control Port mode.
Single-Speed mode supports input sample rates up
to 50 kHz and uses a 128x oversampling ratio.
Double-Speed mode supports input sample rates up
to 100 kHz and uses an oversampling ratio of 64x.
Quad-Speed mode supports input sample rates up
to 200 kHz and uses an oversampling ratio of 32x.
5.3
Recommended Power-up Sequence
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and VQ
will remain low.
2. Bring RST high. The device will remain in a low
power state with VQ low and will initiate the
Stand-Alone power-up sequence. The control port
will be accessible at this time. If Control Port operation is desired, write the CPEN bit prior to the
completion of the Stand-Alone power-up sequence, approximately 512 LRCK cycles in Sin-
gle-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in QuadSpeed Mode). Writing this bit will halt the StandAlone power-up sequence and initialize the control
port to its default settings. The desired register settings can be loaded while keeping the PDN bit set
to 1.
3. If Control Port Mode is selected via the CPEN
bit, set the PDN bit to 0 which will initiate the power-up sequence.
5.4
Analog Output and Filtering
The application note “Design Notes for a 2-Pole
Filter with Differential Input” discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the
CS4362 evaluation board, CDB4362, as seen in
Figure 42. The CS4362 does not include phase or
amplitude compensation for an external filter.
Therefore, the DAC system phase and amplitude
response will be dependent on the external analog
circuitry.
5.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4362
incorporates selectable interpolation filters for each
mode of operation. A “fast” and a “slow” roll-off
filter is available in each of Single, Double, and
Quad Speed modes. These filters have been designed to accommodate a variety of musical tastes
and styles. The FILT_SEL bit is used to select
which filter is used (see the control port section for
more details).
When in stand-alone mode, only the “fast” roll-off
filter is available.
Filter specifications can be found in Section 1, and
filter response plots can be found in Figures 9 to 32.
27
CS4362
5.6
Clock Source Selection
The CS4362 has two serial clock and two left/right
clock inputs. The SDINxCLK bits in the control
port allow the user to set which SCLK/LRCK pair
is used to latch the data for each SDINx pin. The
clocks applied to LRCK1 and LRCK2 must be derived from the same MCLK and must be exact frequency multiples of each other as specified in the
“Switching Characteristics” on page 8. When using
both SCLK1/LRCK1 and SCLK2/LRCK2, if either SCLK/LRCK pair loses synchronization then
both SCLK/LRCK pairs will go through a retime
period where the device is re-evaluating clock ratios. During the retime period all DAC pairs are
temporarily inactive, outputs are muted, and the
mute control pins will go active according to the
MUTEC bits.
If unused, SCLK2 and LRCK2 should be tied static
low and SDINx bits should all be set to
SCLK1/LRCK1.
In stand-alone mode all DAC pairs use SCLK1 and
LRCK1 for timing and SCLK2/LRCK2 should be
tied to ground.
5.7
Using DSD mode
In stand-alone mode, DSD operation is selected by
holding DSD_EN(LRCK1) high and applying the
DSD data and clocks to the appropriate pins. The
M2:0 pins set the expected DSD rate and MCLK
ratio.
In control-port mode the FM bits set the device into
DSD mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected
DSD rate and MCLK ratio.
During DSD operation, the PCM related pins
should either be tied low or remain active with
clocks (except LRCK1 in Stand-Alone mode).
When the DSD related pins are not being used they
should either be tied static low, or remain active
with clocks (except M3 in Stand-Alone mode).
28
6. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference problems, the control port pins should remain static if
no operation is required.
The CS4362 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written from register 01h to 08h and then from
09h and 11h, allowing block reads or writes of successive registers in two separate sections (the
counter will not auto-increment to register 09h
from register 08h).
6.1
Enabling the Control Port
On the CS4362 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
is done by performing a I2C or SPI write. Once the
control port is enabled, these pins are dedicated to
control port functionality.
To prevent audible artifacts the CPEN bit (see Section 3.1.1) should be set prior to the completion of
the Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; however, setting this bit after the Stand-Alone powerup sequence has completed can cause audible artifacts.
6.2
Format Selection
The control port has 2 formats: SPI and I2C, with
the CS4362 operating as a slave device.
If I2C operation is desired, AD0/CS should be tied
to VLC or GND. If the CS4362 ever detects a high
CS4362
to low transition on AD0/CS after power-up and after the control port is activated , SPI format will be
selected.
6.3
I2C Format
In I2C Format, SDA is a bidirectional data line.
Data is clocked into and out of the part by the clock,
SCL, with a clock to data relationship as shown in
Figure 7. The receiving device should send an acknowledge (ACK) after each byte received. There
is no CS pin. Pin AD0 forms the partial chip address and should be tied to VLC or GND as required. The upper 6 bits of the 7 bit address field
must be 001100.
Note: MCLK is required during all I2C transactions. Please see reference 4 for further details.
6.3.1
Writing in I2C Format
To communicate with the CS4362, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then followed by the data to be written. To write multiple
registers, continue providing a clock and data,
waiting for the CS4362 to acknowledge between
each byte. To end the transaction, send a STOP
condition.
6.3.2
Reading in I2C Format
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the register pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condition.
6.4
SPI Format
In SPI format, CS is the CS4362 chip select signal,
CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip
address is 0011000. CS, CCLK and CDIN are all
inputs and data is clocked in on the rising edge of
CCLK.
Note that the CS4362 is write-only when in SPI
format.
6.4.1
Writing in SPI
Figure 8 shows the operation of the control port in
SPI format. To write to a register, bring CS low.
The first 7 bits on CDIN form the chip address and
must be 0011000. The eighth bit is a read/write indicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. To write multiple registers, keep CS low and
continue providing clocks on CCLK. End the read
transaction by setting CS high.
To communicate with the CS4362, initiate a
START condition of the bus. Next, send the chip
29
CS4362
N o te 1
SDA
001100
ADDR
AD0
R /W
ACK
DATA
1-8
DATA
1 -8
ACK
ACK
SCL
S ta rt
S to p
N o t e : If o p e ra tio n is a w r ite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o i n te r, M A P .
2
Figure 7. Control Port Timing, I C Format
C S
C C L K
C H IP
A D D R E S S
C D IN
M A P
0011000
D A T A
LSB
M S B
R /W
b y te 1
b y te n
M A P = M e m o r y A d d r e s s P o in te r
Figure 8. Control Port Timing, SPI Format
6.5
Memory Address Pointer (MAP)
7
INCR
0
6.5.1
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
Note: When Auto Map Increment is enabled, the register must be written it two separate blocks: from
register 01h to 08h and then from 09h and 11h. The counter will not auto-increment to register 09h from
register 08h
6.5.2
MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
30
CS4362
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 9. Single Speed (fast) Stopband Rejection
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 10. Single Speed (fast) Transition Band
0.02
0
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
Figure 11. Single Speed (fast) Transition Band (detail)
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0.05
Figure 12. Single Speed (fast) Passband Ripple
0
60
80
60
80
100
120
0
100
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 13. Single Speed (slow) Stopband Rejection
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 14. Single Speed (slow) Transition Band
31
CS4362
0.02
0
1
0.015
2
0.01
3
Amplitude (dB)
Amplitude (dB)
0.005
4
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.02
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 15. Single Speed (slow) Transition Band (detail)
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0.05
Figure 16. Single Speed (slow) Passband Ripple
0
60
60
80
80
100
100
120
0
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 17. Double Speed (fast) Stopband Rejection
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 18. Double Speed (fast) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 19. Double Speed (fast) Transition Band (detail)
32
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 20. Double Speed (fast) Passband Ripple
CS4362
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 21. Double Speed (slow) Stopband Rejection
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 22. Double Speed (slow) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
Figure 23. Double Speed (slow) Transition Band (detail)
20
40
40
Amplitude (dB)
Amplitude (dB)
0.1
0.15
0.2
Frequency(normalized to Fs)
0.25
0.3
0.35
0
20
60
60
80
80
100
100
120
0.2
0.05
Figure 24. Double Speed (slow) Passband Ripple
0
120
0
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 25. Quad Speed (fast) Stopband Rejection
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 26. Quad Speed (fast) Transition Band
33
CS4362
0.2
0
1
0.15
2
0.1
3
Amplitude (dB)
Amplitude (dB)
0.05
4
5
6
0
0.05
7
0.1
8
0.15
9
10
0.45
0.2
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 27. Quad Speed (fast) Transition Band (detail)
0
0.05
0.1
0.15
Frequency(normalized to Fs)
0.2
0.25
Figure 28. Quad Speed (fast) Passband Ripple
0
0
20
40
40
Amplitude (dB)
Amplitude (dB)
20
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 29. Quad Speed (slow) Stopband Rejection
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 30. Quad Speed (slow) Transition Band
0.02
0
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 31. Quad Speed (slow) Transition Band (detail)
34
0.02
0
0.02
0.04
0.06
0.08
Frequency(normalized to Fs)
0.1
0.12
Figure 32. Quad Speed (slow) Passband Ripple
CS4362
Left Channel
LRCK
Right Channel
SCLK
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 33. Format 0 - Left Justified up to 24-bit Data
Left Channel
LRCK
Right Channel
SCLK
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 34. Format 1 - I2S up to 24-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
15 14 13 12 11 10 9
8 7
6
5 4
3
2 1
0
15 14 13 12 11 10 9
8
7 6
5
4 3
2 1
0
7 6
5
4 3
2 1
0
32 clocks
Figure 35. Format 2 - Right Justified 16-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
0
23 22 21 20 19 18
7
6
5 4
3
2 1
0
23 22 21 20 19 18
32 clocks
Figure 36. Format 3 - Right Justified 24-bit Data
35
CS4362
LRCK
Right Channel
Left Channel
SCLK
SDINx
1 0
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
2
1 0
32 clocks
Figure 37. Format 4 - Right Justified 20-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
1 0
17 16 15 14 13 12 11 10 9
8 7
6
5
4 3
2 1
0
17 16 15 14 13 12 11 10 9
8
7
6 5
4 3
32 clocks
Figure 38. Format 5 - Right Justified 18-bit Data
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 39. De-Emphasis Curve
L
DAC
AOUTAx-
Channel
Pair x
Control
SDINx
R
DAC
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, or 3)
36
AOUTAx+
AOUTBx+
AOUTBx-
CS4362
A Channel
Volume
Control
Left Channel
Audio Data
Σ
SDINx
Right Channel
Audio Data
MUTE
Aout Ax
MUTE
AoutBx
Σ
B Channel
Volume
Control
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
Figure 42. Recommended Output Filter
37
CS4362
7. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
8. REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4362 Evaluation Board Datasheet
3. “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note
AN48
4. “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
38
CS4362
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
4°
MAX
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
MIN
--0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
MILLIMETERS
NOM
1.40
0.10
0.22
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
4°
MAX
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
Controlling dimension is mm.
JEDEC Designation: MS022
39