PSoC® 5LP: CY8C56LP Family
Datasheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing MCU, memory, analog, and digital
peripheral functions in a single chip. The CY8C56LP family offers a modern method of signal acquisition, signal processing, and
control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC
voltages) to ultrasonic signals. The CY8C56LP family can handle dozens of data acquisition channels and analog inputs on every
general-purpose input/output (GPIO) pin. The CY8C56LP family is also a high performance configurable digital system with some
part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In
addition to communication interfaces, the CY8C56LP family has an easy to configure logic array, flexible routing to all I/O pins, and
a high performance 32-bit ARM® Cortex™-M3 microprocessor core. You can easily create system level designs using a rich library
of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C56LP
family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute
design changes through simple firmware updates.
Features
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• LIN bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
1.024 V±0.1% internal voltage reference across –40 °C to
+85 °C
[2]
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
Up to two SAR ADCs, each 12-bit at 1 Msps
Four 8-bit 8 Msps IDACs or 1 Msps VDACs
Four comparators with 95 ns response time
Four uncommitted opamps with 25 mA drive capability
Four configurable multifunction analog blocks. Example
configurations are PGA, TIA. Mixer and sample and hold
CapSense support
Programming, debug, and trace
JTAG (4 wire), serial-wire debug (SWD) (2 wire), single-wire
viewer (SWV), and TRACEPORT interfaces
Cortex-M3 flash patch and breakpoint (FPB) block
Cortex-M3 Embedded Trace Macrocell™ (ETM™)
generates an instruction trace stream.
Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
used for printf-style debugging
DWT, ETM, and ITM blocks communicate with off-chip debug
and trace systems via the SWV or TRACEPORT
2
Bootloader programming supportable through I C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3 to 62 MHz internal oscillator over full temperature and
voltage range
4 to 25 MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 67 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40 °C to +85 °C degrees industrial temperature
68-pin QFN and 100-pin TQFP package options
32-bit ARM Cortex-M3 CPU core
DC to 67 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles,
20 year retention, and multiple security features
Up to 32-KB flash error correcting code (ECC) or
configuration storage
Up to 64 KB SRAM
2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 M cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AHB[1] bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5 V input to 1.8 V to
5.0 V output
3.1 mA at 6 MHz
Low-power modes including:
• 2 µA sleep mode with real time clock and low voltage detect
(LVD) interrupt
• 300 nA hibernate mode with RAM retention
Versatile I/O system
[2]
28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs )
Any GPIOs to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46 × 16 segments
®
[3]
CapSense support from any GPIO
1.2 V to 5.5 V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger TTL inputs
All GPIOs configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
20 to 24 programmable PLD based universal digital
blocks (UDB)
[2]
Full CAN 2.0b 16 RX, 8 TX buffers
[2]
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator
Four 16-bit configurable timer, counter, and PWM blocks
67-MHz, 24-bit fixed point digital filter block (DFB) to
implement FIR and IIR filters
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 113 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-84935 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 8, 2013
PSoC® 5LP: CY8C56LP Family
Datasheet
Contents
1. Architectural Overview ................................................. 3
2. Pinouts ........................................................................... 5
3. Pin Descriptions ............................................................ 9
4. CPU ............................................................................... 10
4.1 ARM Cortex-M3 CPU ...........................................10
4.2 Cache Controller ..................................................11
4.3 DMA and PHUB ...................................................12
4.4 Interrupt Controller ...............................................14
5. Memory ......................................................................... 16
5.1 Static RAM ...........................................................16
5.2 Flash Program Memory ........................................16
5.3 Flash Security .......................................................16
5.4 EEPROM ..............................................................16
5.5 Nonvolatile Latches (NVLs) ..................................17
5.6 External Memory Interface ...................................18
5.7 Memory Map ........................................................19
6. System Integration ...................................................... 20
6.1 Clocking System ...................................................20
6.2 Power System ......................................................24
6.3 Reset ....................................................................27
6.4 I/O System and Routing .......................................28
7. Digital Subsystem ....................................................... 34
7.1 Example Peripherals ............................................35
7.2 Universal Digital Block ..........................................36
7.3 UDB Array Description .........................................40
7.4 DSI Routing Interface Description ........................41
7.5 CAN ......................................................................42
7.6 USB ......................................................................44
7.7 Timers, Counters, and PWMs ..............................45
7.8 I2C ........................................................................45
7.9 Digital Filter Block .................................................46
8. Analog Subsystem ...................................................... 46
8.1 Analog Routing .....................................................48
8.2 Delta-sigma ADC ..................................................50
8.3 Successive Approximation ADCs .........................51
8.4 Comparators .........................................................51
8.5 Opamps ................................................................53
8.6 Programmable SC/CT Blocks ..............................53
8.7 LCD Direct Drive ..................................................55
Document Number: 001-84935 Rev. *C
8.8 CapSense .............................................................55
8.9 Temp Sensor ........................................................55
8.10 DAC ....................................................................56
8.11 Up/Down Mixer ...................................................56
8.12 Sample and Hold ................................................57
9. Programming, Debug Interfaces, Resources ............ 57
9.1 JTAG Interface .....................................................58
9.2 SWD Interface ......................................................59
9.3 Debug Features ....................................................60
9.4 Trace Features .....................................................60
9.5 SWV and TRACEPORT Interfaces ......................60
9.6 Programming Features .........................................60
9.7 Device Security ....................................................60
10. Development Support ............................................... 61
10.1 Documentation ...................................................61
10.2 Online .................................................................61
10.3 Tools ...................................................................61
11. Electrical Specifications ........................................... 62
11.1 Absolute Maximum Ratings ................................62
11.2 Device Level Specifications ................................63
11.3 Power Regulators ...............................................66
11.4 Inputs and Outputs .............................................69
11.5 Analog Peripherals .............................................77
11.6 Digital Peripherals ..............................................97
11.7 Memory ............................................................102
11.8 PSoC System Resources .................................106
11.9 Clocking ............................................................109
12. Ordering Information ............................................... 113
12.1 Part Numbering Conventions ...........................114
13. Packaging ................................................................. 115
14. Acronyms ................................................................. 117
15. Reference Documents ............................................. 118
16. Document Conventions .......................................... 119
16.1 Units of Measure ..............................................119
17. Revision History ...................................................... 120
18. Sales, Solutions, and Legal Information ............... 120
Page 2 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
1. Architectural Overview
Introducing the CY8C56LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5LP platform. The CY8C56LP family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Clock Tree
IMO
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit
Timer
UDB
Sequencer
Quadrature Decoder
UDB
UDB
UDB
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22 Ω
UDB
8- Bit
Timer
Logic
8- Bit SPI
I 2C Slave
UDB
UDB
FS USB
2.0
4x
Timer
Counter
PWM
12- Bit SPI
UDB
I2C
Master/
Slave
CAN 2.0
16- Bit PRS
Logic
UDB
UDB
UDB
UART
UDB
USB
PHY
GPIOs
32.768 KHz
( Optional)
GPIOs
Xtal
Osc
SIO
System Wide
Resources
Usage Example for UDB
4- 25 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
Memory System
WDT
and
Wake
EEPROM
SRAM
CPU System
Interrupt
Controller
Cortex M3CPU
Program &
Debug
GPIOs
System Bus
Program
GPIOs
Debug &
Trace
EMIF
FLASH
ILO
Cache
Controller
PHUB
DMA
Boundary
Scan
Digital
Filter
Block
LCD Direct
Drive
POR and
LVD
1.71 to
5.5 V
Sleep
Power
1.8 V LDO
SMP
4 x SC / CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
GPIOs
Power Management
System
Analog System
ADCs
2x
SAR
ADC
+
4x
Opamp
-
+
4x DAC
CapSense
1x
Del Sig
ADC
4x
CMP
-
3 per
Opamp
GPIOs
SIOs
Clocking System
0. 5 to 5.5 V
( Optional)
Figure 1-1 illustrates the major components of the CY8C56LP
family. They are:
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
Document Number: 001-84935 Rev. *C
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals. In
addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C56LP family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multi-master;
Full-Speed USB; and Full CAN 2.0.
Page 3 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
For more details on the peripherals see the “Example
Peripherals” section on page 35 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 34 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1% error
over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Analog mixers
Voltage references
ADCs
DACs
DFB
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
Some CY8C56LP devices offer a fast, accurate, configurable
delta-sigma ADC with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
The CY8C56LP family also offers one or two successive
approximation register (SAR) ADCs, depending on device
selected. Featuring 12-bit conversions at up to 1 M samples per
second, they also offer low nonlinearity and offset errors and
SNR better than 70 dB. They are well suited for a variety of
higher speed analog applications.
The output of either ADC can optionally feed the programmable
DFB via DMA without CPU intervention. You can configure the
DFB to perform IIR and FIR digital filters and several user
defined custom functions. The DFB can implement filters with up
to 64 taps. It can perform a 48-bit multiply-accumulate (MAC)
operation in one clock cycle.
Four high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Document Number: 001-84935 Rev. *C
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the “Analog Subsystem” section on page 46 of this
datasheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 67 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. You can enable an ECC
for high reliability applications. A powerful and flexible protection
model secures the user's sensitive information, allowing
selective memory block locking for read and write protection.
Two KB of byte-writable EEPROM is available on-chip to store
application data. Additionally, selected configuration options
such as boot speed and pin drive mode are stored in nonvolatile
memory. This allows settings to activate immediately after power
on reset (POR).
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive, CapSense, flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow VOH to be set independently of VDDIO when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with FS USB the USB physical
interface is also provided (USBIO). When not using USB these
pins may also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the “I/O System and Routing” section on page 28 of this
datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
Page 4 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
very low power internal low-speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in RTC applications. The clocks, together
with programmable clock dividers, provide the flexibility to
integrate most timing requirements.
The CY8C56LP family supports a wide supply operating range
from 1.71 to 5.5 V. This allows operation from regulated supplies
such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or
directly from a wide range of battery types. In addition, it provides
an integrated high efficiency synchronous boost converter that
can power the device from supply voltages as low as 0.5 V. This
enables the device to be powered directly from a single battery.
In addition, you can use the boost converter to generate other
voltages required by the device, such as a 3.3 V supply for LCD
glass drive. The boost’s output is available on the VBOOST pin,
allowing other devices in the application to be powered from the
PSoC.
PSoC supports a wide range of low power modes. These include
a 300 nA hibernate mode with RAM retention and a 2 µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 and Figure 2-4 show the pins that are
powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in Figure 2-1.
Figure 2-1. VDDIO Current Limit
IDDIO X = 100 mA
VDDIO X
I/O Pins
PSoC
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 3.1 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 24 of this datasheet.
PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces for
programming, debug, and test. Using these standard interfaces
you can debug or program the PSoC with a variety of hardware
solutions from Cypress or third party vendors. The Cortex-M3
debug and trace modules include Flash Patch and Breakpoint
(FPB), Data Watchpoint and Trace (DWT), Embedded Trace
Macrocell (ETM), and Instrumentation Trace Macrocell (ITM).
These modules have many features to help solve difficult debug
and trace problems. Details of the programming, test, and
debugging interfaces are discussed in the “Programming, Debug
Interfaces, Resources” section on page 57 of this datasheet.
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins = 100 mA
VDDIO X
I/O Pins
PSoC
VSSD
Note
4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-84935 Rev. *C
Page 5 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P0[5] (GPIO, OPAMP2-)
P0[4] (GPIO, OPAMP2+/SAR0 EXTREF)
VDDIO0
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
55
54
53
52
58
57
56
P15[5] (GPOI)
P15[4] (GPIO)
VDDD
VSSD
VCCD
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
VDDIO2
P2[4] (GPIO, TRACEDATA[0])
P2[3] (GPIO, TRACECLK)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Lines show VDDIO
to I/O supply
association
QFN
P0[3] (GPIO, OPAMP0-/EXTREF0)
P0[2] (GPIO, OPAMP0+/SAR1 EXTREF)
P0[1] (GPIO, OPAMP0OUT)
P0[0] (GPIO, OPAMP2OUT)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO, OPAMP3OUT)
P3[6] (GPIO, OPAMP1OUT)
VDDIO3
(OPAMP1+, GPIO) P3[5]
(OPAMP3+, GPIO) P3[3]
(OPAMP1-, GPIO) P3[4]
28
29
30
31
32
33
34
(MHZ XTAL: XI, GPIO) P15[1]
(IDAC1, GPIO) P3[0]
(IDAC3, GPIO) P3[1]
(OPAMP3-/EXTREF1, GPIO) P3[2]
VDDD
VSSD
VCCD
(MHZ XTAL: XO, GPIO) P15[0]
18
19
20
21
22
23
24
25
26
27
(GPIO) P1[6]
(TOP VIEW)
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
[6] (USBIO, D+, SWDIO) P15[6]
[6](USBIO, D-, SWDCK) P15[7]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(Configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(NTRST, GPIO) P1[5]
VDDIO1
66
65
64
63
62
61
60
59
68
67
P2[5] (GPIO, TRACEDATA[1])
Figure 2-3. 68-pin QFN Part Pinout[5]
Notes
5. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-84935 Rev. *C
Page 6 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
(
(
(
(
( TMS, SWDIO,
( TCK, SWDCK,
(Configurable XRES ,
( TDO, SWV,
( TDI ,
( NTRST,
VSSD
XRES
GPIO)P5[0]
GPIO)P5[1]
GPIO)P5[2]
GPIO)P5[3]
GPIO)P1[0]
GPIO)P1[1]
GPIO)P1[2]
GPIO)P1[3]
GPIO)P1[4]
GPIO)P1[5]
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, OPAMP2-)
P0[4] (GPIO, OPAMP2+ /SAR0 EXTREF)
77
76
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO, IDAC2)
VDDD
VSSD
VCCD
P4[7] (GPIO)
P4[6] (GPIO)
87
86
85
84
83
82
81
80
79
78
90
89
88
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
P2[4] (GPIO, TRACEDATA[0])
P2[3] (GPIO, TRACECLK])
P2[2] (GPIO)
98
97
96
95
94
93
92
91
TQFP
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSB
IND
VBOOST
VBAT
Lines show VDDIO
I/O Supply Association
[7](USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
NC
NC
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
(IDAC1, GPIO) P3[0]
(IDAC3, GPIO) P3[1]
(OPAMP3-/EXTREF1, GPIO) P3[2]
(OPAMP3+, GPIO) P3[3]
(OPAMP1-, GPIO) P3[4]
(OPAMP1+, GPIO) P3[5]
VDDIO3
( GPIO)P6[5]
( GPIO)P6[6]
( GPIO)P6[7]
75
74
26
27
28
29
30
31
32
33
34
35
(I2C0 : SCL, SIO )P12[4]
(I2C0 : SDA, SIO )P12[5]
( GPIO)P6[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDIO1
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
[7](USBIO, D+, SWDIO) P15[6]
(TRACEDATA[1] , GPIO)P2[5]
(TRACEDATA[2] , GPIO)P2[6]
(TRACEDATA[3] , GPIO)P2[7]
100
99
VDDIO2
Figure 2-4. 100-pin TQFP Part Pinout
VDDIO0
P0[3] ( GPIO,OPAMP0-/ EXTREF0)
P0[2] ( GPIO, OPAMP 0+/SAR1 EXTREF)
P0[1] ( GPIO, OPAMPOUT0)
P0[0] ( GPIO, OPAMPOUT2 )
P4[1] ( GPIO)
P4[0] ( GPIO)
P12[3] ( SIO)
P12[2] ( SIO)
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
P15[3] ( GPIO, KHZ XTAL:XI)
P15[2] ( GPIO, KHZ XTAL:XO)
P12[1] ( SIO ,I2C1 : SDA)
P12[0] ( SIO ,I2C1 : SCL)
P3[7] ( GPIO, OPAMPOUT 3 )
P3[6] ( GPIO, OPAMPOUT1)
Figure 2-5 and Figure 2-6 on page 8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 on page 8 and Power
System on page 24. The trace between the two VCCD pins should be as short as possible.
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-84935 Rev. *C
Page 7 of 120
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Datasheet
Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections
VDDD
VDDD
C1
1 UF
VDDD
C2
0.1 UF
VDDD
100
99
98
97
96
95
94
93
92
91
90
89
88 VDDD
VSSD
87
86
85
84
83
82
81
80
79
78
77
76
VCCD
C6
0.1 UF
VSSD
VDDIO0
OA0-, REF0, P0[3]
OA0+, SAR1REF, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
VSSD
VSSD
VDDD
C12
0.1 UF
C8
0.1 UF
C17
1 UF
VSSD
VSSD
VSSA
VDDA
C9
1 UF
C10
0.1 UF
VSSA
VDDIO3
VSSD
VDDA
VSSA
VCCA
VDDD
VSSD
C15
1 UF
C16
0.1 UF
VDDA
VDDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C11
0.1 UF
VCCD
VDDD
OA1OUT, P3[6]
P3[5], OA1+
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
USB D+, P15[6]
USB D-, P15[7]
VDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1-
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWDIO, TMS
P1[1], SWDCK, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
VSSD 14
15
16
17
18
19
20
21
22
23
24
25
VDDIO2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
VDDD
VSSD
VCCD
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+,
SAR0REF,
P0[4]
VSSD
VSSD
VSSD
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-6.
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
VSSA
VDDD
VSSD
P lan e
Document Number: 001-84935 Rev. *C
VSSD
VDDA
VSSA
P lan e
Page 8 of 120
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Datasheet
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3
Low resistance output pin for high current DACs (IDAC).
Opamp0out, Opamp1out, Opamp2out, Opamp3out
High current output of uncommitted opamp[8].
Extref0, Extref1
External reference input to the analog system.
SAR0 EXTREF, SAR1 EXTREF
External references for SAR ADCs
Opamp0–, Opamp1–, Opamp2–, Opamp3–
Inverting input to uncommitted opamp.
Opamp0+, Opamp1+, Opamp2+, Opamp3+
Noninverting input to uncommitted opamp.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense[8].
I2C0: SCL, I2C1: SCL
I2C SCL line providing wake from sleep on an address match. Any
I/O pin can be used for I2C SCL if wake from sleep is not required.
I2C0: SDA, I2C1: SDA
I2C SDA line providing wake from sleep on an address match. Any
I/O pin can be used for I2C SDA if wake from sleep is not required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4 to 25 MHz crystal oscillator pin.
nTRST
Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
SWDCK
Serial Wire Debug Clock programming and debug port connection.
SWDIO
Serial Wire Debug Input and Output programming and debug
port connection.
TCK
JTAG Test Clock programming and debug port connection.
TDI
JTAG Test Data In programming and debug port connection.
TDO
JTAG Test Data Out programming and debug port connection.
TMS
JTAG Test Mode Select programming and debug port connection.
TRACECLK
Cortex-M3 TRACEPORT connection, clocks TRACEDATA pins.
TRACEDATA[3:0].
Cortex-M3 TRACEPORT connections, output data.
SWV.
Single Wire Viewer output.
USBIO, D+
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from VDDD instead of from a
VDDIO. Pins are Do Not Use (DNU) on devices without USB.
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from VDDD instead of from a
VDDIO. Pins are Do Not Use (DNU) on devices without USB.
VBOOST
Power sense connection to boost pump.
VBAT
Battery supply to boost pump.
VCCA
Output of the analog core regulator or the input to the
analog core. Requires a 1uF capacitor to VSSA. The regulator
output is not designed to drive external circuits. Note that if you
use the device with an external core regulator (externally
regulated mode), the voltage applied to this pin must not
exceed the allowable range of 1.71 V to 1.89 V. When using
the internal core regulator, (internally regulated mode, the
default), do not tie any power to this pin. For details see Power
System on page 24.
VCCD.
Output of the digital core regulator or the input to the digital
core. The two VCCD pins must be shorted together, with the
trace between them as short as possible, and a 1uF capacitor to
VSSD. The regulator output is not designed to drive external
circuits. Note that if you use the device with an external core
regulator (externally regulated mode), the voltage applied to
this pin must not exceed the allowable range of 1.71 V to
1.89 V. When using the internal core regulator (internally
regulated mode, the default), do not tie any power to this pin. For
details see Power System on page 24.
VDDA
Supply for all analog peripherals and analog core regulator.
VDDA must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
VDDD
Supply for all digital peripherals and digital core regulator. VDDD
must be less than or equal to VDDA.
VSSA
Ground for all analog peripherals.
VSSB
Ground connection for boost pump.
VSSD
Ground for all digital logic and I/O pins.
Note
8. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-84935 Rev. *C
Page 9 of 120
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Datasheet
XRES (and configurable XRES)
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 17.
VDDIO0, VDDIO1, VDDIO2, VDDIO3
Supply for I/O pins. Each VDDIO must be tied to a valid operating
voltage (1.71 V to 5.5 V), and must be less than or equal to
VDDA.
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C56LP family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt
handling features.
Figure 4-1. ARM Cortex-M3 Block Diagram
Interrupt Inputs
Nested
Vectored
Interrupt
Controller
(NVIC)
I- Bus
JTAG/SWD
D-Bus
Embedded
Trace Module
(ETM)
Instrumentation
Trace Module
(ITM)
S-Bus
Trace Pins:
Debug Block
(Serial and
JTAG)
Flash Patch
and Breakpoint
(FPB)
Trace Port
5 for TRACEPORT or
Interface Unit 1 for SWV mode
(TPIU)
Cortex M3 Wrapper
C-Bus
AHB
32 KB
SRAM
Data
Watchpoint and
Trace (DWT)
Cortex M3 CPU Core
AHB
Bus
Matrix
Bus
Matrix
Cache
256 KB
ECC
Flash
AHB
32 KB
SRAM
Bus
Matrix
AHB Bridge & Bus Matrix
DMA
PHUB
AHB Spokes
GPIO &
EMIF
Prog.
Digital
Prog.
Analog
Special
Functions
Peripherals
The Cortex-M3 CPU subsystem includes these features:
ARM Cortex-M3 CPU
Programmable Nested Vectored Interrupt Controller (NVIC),
tightly integrated with the CPU core
Full featured debug and trace modules, tightly integrated with
the CPU core
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
Cache controller
Peripheral HUB (PHUB)
DMA controller
External Memory Interface (EMIF)
Document Number: 001-84935 Rev. *C
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
4 GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
The Thumb®-2 instruction set, which offers ARM-level
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
Bit-field control
Hardware multiply and divide
Saturation
If-Then
Wait for events and interrupts
Exclusive access and barrier
Special register access
The Cortex-M3 does not support ARM instructions.
Page 10 of 120
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Datasheet
Bit-band support for the SRAM region. Atomic bit-level write
and read operations for SRAM addresses.
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
Extensive interrupt and system exception support.
4.1.2 Cortex-M3 Operating Modes
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
Because the handler mode is only enabled at the privileged level,
there are actually only three states, as shown in Table 4-1.
Privileged
User
Running an exception Handler mode
Not used
Running main program Thread mode
Thread mode
At the user level, access to certain instructions, special registers,
configuration registers, and debugging components is blocked.
Attempts to access them cause a fault exception. At the
privileged level, access to all instructions and registers is
allowed.
The processor runs in the handler mode (always at the privileged
level) when handling an exception, and in the thread mode when
not.
4.1.3 CPU Registers
The Cortex-M3 CPU registers are listed in Table 4-2. Registers
R0-R15 are all 32 bits wide.
Table 4-2. Cortex M3 CPU Registers
Register
R0-R12
Description
General purpose registers R0-R12 have no
special architecturally defined uses. Most
instructions that specify a general purpose
register specify R0-R12.
Low Registers: Registers R0-R7 are acces-
sible by all instructions that specify a general
purpose register.
High Registers: Registers R8-R12 are acces-
R13
sible by all 32-bit instructions that specify a
general purpose register; they are not accessible by all 16-bit instructions.
R13 is the stack pointer register. It is a banked
register that switches between two 32-bit stack
pointers: the Main Stack Pointer (MSP) and the
Process Stack Pointer (PSP). The PSP is used
only when the CPU operates at the user level in
thread mode. The MSP is used in all other
privilege levels and modes. Bits[0:1] of the SP
are ignored and considered to be 0, so the SP is
always aligned to a word (4 byte) boundary.
Document Number: 001-84935 Rev. *C
Register
R14
R15
xPSR
Description
R14 is the Link Register (LR). The LR stores the
return address when a subroutine is called.
R15 is the Program Counter (PC). Bit 0 of the PC
is ignored and considered to be 0, so instructions
are always aligned to a half word (2 byte)
boundary.
The Program status registers are divided into
three status registers, which are accessed either
together or separately:
Application Program Status Register (APSR)
holds program execution status bits such as
zero, carry, negative, in bits[27:31].
Interrupt Program Status Register (IPSR)
holds the current exception number in bits[0:8].
Table 4-1. Operational Level
Condition
Table 4-2. Cortex M3 CPU Registers (continued)
Execution Program Status Register (EPSR)
holds control bits for interrupt continuable and
IF-THEN instructions in bits[10:15] and
[25:26]. Bit 24 is always set to 1 to indicate
Thumb mode. Trying to clear it causes a fault
exception.
PRIMASK
A 1-bit interrupt mask register. When set, it
allows only the nonmaskable interrupt (NMI) and
hard fault exception. All other exceptions and
interrupts are masked.
FAULTMASK A 1-bit interrupt mask register. When set, it
allows only the NMI. All other exceptions and
interrupts are masked.
BASEPRI
A register of up to nine bits that define the
masking priority level. When set, it disables all
interrupts of the same or higher priority value. If
set to 0 then the masking function is disabled.
CONTROL
A 2-bit register for controlling the operating
mode.
Bit 0: 0 = privileged level in thread mode, 1 = user
level in thread mode.
Bit 1: 0 = default stack (MSP) is used, 1 =
alternate stack is used. If in thread mode or user
level then the alternate stack is the PSP. There
is no alternate stack for handler mode; the bit
must be 0 while in handler mode.
4.2 Cache Controller
The CY8C56LP family has 1 KB instruction cache between the
CPU and the flash memory. This improves instruction execution
rate and reduces system power consumption by requiring less
frequent flash access.
Page 11 of 120
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Datasheet
4.3 DMA and PHUB
Transactions can be stalled or canceled
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
Supports transaction size of infinite or 1 to 64k bytes
4.3.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight multi-layer AHB bus parallel access paths (spokes) for
peripheral access
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8, 16, 24, and 32-bit addressing and data
Large transactions may be broken into smaller bursts of 1 to
127 bytes
TDs may be nested and/or chained for complex transactions
4.3.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100% of the bus bandwidth. If a tie occurs
on two DMA requests of the same priority level, a simple round
robin method is used to evenly share the allocated bandwidth.
The round robin allocation can be disabled for each DMA
channel, allowing it to always be at the head of the line. Priority
levels 2 to 7 are guaranteed the minimum bus bandwidth shown
in Table 4-4 after the CPU and DMA priority levels 0 and 1 have
satisfied their requirements.
Table 4-4. Priority Levels
Table 4-3. PHUB Spokes and Peripherals
PHUB Spokes
0
Peripherals
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
4
Analog interface and trim, Decimator
USB,
I2C,
CAN, Timers, Counters, and PWMs
5
DFB
6
UDBs group 1
7
UDBs group 2
Priority Level
% Bus Bandwidth
0
100.0
1
100.0
2
50.0
3
25.0
4
12.5
5
6.2
6
3.1
7
1.5
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.3.2 DMA Features
24 DMA channels
Each channel has one or more Transaction Descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
4.3.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
TDs can be dynamically updated
4.3.4.1 Simple DMA
Eight levels of priority per channel
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-2. For more description on other transfer modes, refer
to the Technical Reference Manual.
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Document Number: 001-84935 Rev. *C
Page 12 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 4-2. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
ADDR 16/32
DATA Phase
CLK
A
B
A
ADDR 16/32
WRITE
B
WRITE
DATA (A)
DATA
READY
DATA (A)
DATA
READY
Basic DMA Read Transfer without wait states
4.3.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.3.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.3.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.3.4.5 Indexed DMA
In an indexed DMA case, an external master requires access to
locations on the system bus as if those locations were shared
memory. As an example, a peripheral may be configured as an
SPI or I2C slave where an address is received by the external
master. That address becomes an index or offset into the internal
system bus memory space. This is accomplished with an initial
“address fetch” TD that reads the target address location from
the peripheral and writes that value into a subsequent TD in the
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
4.3.4.6 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
Document Number: 001-84935 Rev. *C
Basic DMA Write Transfer without wait states
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
4.3.4.7 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.3.4.8 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
Page 13 of 120
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Datasheet
4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5.
Table 4-5. Cortex-M3 Exceptions and Interrupts
Exception
Number
1
2
3
Reset
NMI
Hard fault
–3 (highest)
–2
–1
Exception Table
Address Offset
0x00
0x04
0x08
0x0C
4
MemManage
Programmable
0x10
5
Bus fault
Programmable
0x14
6
Usage fault
Programmable
0x18
7 – 10
11
12
13
14
15
16 – 47
–
SVC
Debug monitor
–
PendSV
SYSTICK
IRQ
–
Programmable
Programmable
–
Programmable
Programmable
Programmable
0x1C – 0x28
0x2C
0x30
0x34
0x38
0x3C
0x40 – 0x3FC
Exception Type
Priority
Bit 0 of each exception vector indicates whether the exception is
executed using ARM or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See “DSI Routing Interface Description” section on
page 41.
The Nested Vectored Interrupt Controller (NVIC) handles
interrupts from the peripherals, and passes the interrupt vectors
to the CPU. It is closely integrated with the CPU for low latency
interrupt handling. Features include:
32 interrupts. Multiple sources for each interrupt.
Configurable number of priority levels: from 3 to 8.
Dynamic reprioritization of interrupts.
Priority grouping. This allows selection of preempting and non
preempting interrupt levels.
Document Number: 001-84935 Rev. *C
Function
Starting value of R13 / MSP
Reset
Non maskable interrupt
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or
masked
Memory management fault, for example, instruction
fetch from a nonexecutable region
Error response received from the bus system; caused
by an instruction prefetch abort or data access error
Typically caused by invalid instructions or trying to
switch to ARM mode
Reserved
System service call via SVC instruction
Debug monitor
Reserved
Deferred request for system service
System tick timer
Peripheral interrupt request #0 – #31
Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. All
interrupt sources may be routed to any interrupt vector using the
UDB interrupt source connections.
Page 14 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Table 4-6. Interrupt Vector Table
Interrupt #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Cortex-M3 Exception #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Document Number: 001-84935 Rev. *C
Fixed Function
Low voltage detect (LVD)
Cache/ECC
Reserved
Sleep (Pwr Mgr)
PICU[0]
PICU[1]
PICU[2]
PICU[3]
PICU[4]
PICU[5]
PICU[6]
PICU[12]
PICU[15]
Comparators Combined
Switched Caps Combined
I2C
CAN
Timer/Counter0
Timer/Counter1
Timer/Counter2
Timer/Counter3
USB SOF Int
USB Arb Int
USB Bus Int
USB Endpoint[0]
USB Endpoint Data
Reserved
LCD
DFB Int
Decimator Int
phub_err_int
eeprom_fault_int
DMA
phub_termout0[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
phub_termout1[6]
phub_termout1[7]
phub_termout1[8]
phub_termout1[9]
phub_termout1[10]
phub_termout1[11]
phub_termout1[12]
phub_termout1[13]
phub_termout1[14]
phub_termout1[15]
UDB
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
udb_intr[22]
udb_intr[23]
udb_intr[24]
udb_intr[25]
udb_intr[26]
udb_intr[27]
udb_intr[28]
udb_intr[29]
udb_intr[30]
udb_intr[31]
Page 15 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
5. Memory
5.1 Static RAM
CY8C56LP Static RAM (SRAM) is used for temporary data
storage. Code can be executed at full speed from the portion of
SRAM that is located in the code space. This process is slower
from SRAM above 0x20000000. The device provides up to 64
KB of SRAM. The CPU or the DMA controller can access all of
SRAM. The SRAM can be accessed simultaneously by the
Cortex-M3 CPU and the DMA controller if accessing different 32
KB blocks.
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
“Device Security” section on page 60). For more information on
how to take full advantage of the security features in PSoC, see
the PSoC 5 TRM.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
5.2 Flash Program Memory
Unprotected
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
256 KB of user program space.
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
Up to an additional 32 KB of flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected. The flash output is 9 bytes wide with 8 bytes of data
and 1 byte of ECC data.
The CPU or DMA controller read both user code and bulk data
located in flash through the cache controller. This provides
higher CPU performance. If ECC is enabled, the cache controller
also performs error checking and correction.
Flash programming is performed through a special interface and
preempts code execution out of flash. Code execution may be
done out of SRAM during flash programming.
The flash programming interface performs flash erasing,
programming and setting code protection levels. Flash in-system
serial programming (ISSP), typically used for production
programming, is possible through both the SWD and JTAG
interfaces. In-system programming, typically used for
bootloaders, is also possible using serial interfaces such as I2C,
USB, UART, and SPI, or any communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Document Number: 001-84935 Rev. *C
External read
Field Upgrade Internal read and write
External read and
write
Full Protection Internal read
External read and
write + internal write
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte addressable nonvolatile
memory. The CY8C56LP has 2 KB of EEPROM memory to store
user data. Reads from EEPROM are random access at the byte
level. Reads are done directly; writes are done by sending write
commands to an EEPROM programming interface. CPU code
execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each. The CPU
can not execute out of EEPROM. There is no ECC hardware
associated with EEPROM. If ECC is required it must be handled
in firmware.
Page 16 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in Table 5-3.
Table 5-2. Device Configuration NVL Register Map
Register Address
7
6
5
4
3
2
1
0
0x00
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT0RDM[1:0]
0x01
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
PRT4RDM[1:0]
0x02
XRESMEN
0x03
PRT15RDM[1:0]
DIG_PHS_DLY[3:0]
ECCEN
DPS[1:0]
CFGSPEED
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding I/O port. 00b (default) - high impedance analog
See “Reset Configuration” on page 34. All pins of the port 01b - high impedance digital
are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
Controls whether pin P1[2] is used as a GPIO or as an
external reset. See “Pin Descriptions” on page 9, XRES
description.
0 (default) - GPIO
1 - external reset
CFGSPEED
Controls the speed of the IMO-based clock during the
device boot process, for faster boot or low-power
operation
0 (default) - 12 MHz IMO
1 - 48 MHz IMO
DPS{1:0]
Controls the usage of various P1 pins as a debug port.
See “Programming, Debug Interfaces, Resources” on
page 57.
00b - 5-wire JTAG
01b (default) - 4-wire JTAG
10b - SWD
11b - debug ports disabled
ECCEN
Controls whether ECC flash is used for ECC or for general 0 (default) - ECC disabled
configuration and data storage. See “Flash Program
1 - ECC enabled
Memory” on page 16.
DIG_PHS_DLY[3:0]
Selects the digital clock phase delay.
See the TRM for details.
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase/write cycles is limited
– see “Nonvolatile Latches (NVL)” on page 103.
Document Number: 001-84935 Rev. *C
Page 17 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
5.6 External Memory Interface
CY8C56LP provides an External Memory Interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals. At 33 MHz, each memory access cycle takes four bus
clock cycles. Figure 5-1 is the EMIF block diagram. The EMIF
supports synchronous and asynchronous memories. The
CY8C56LP only supports one type of external memory device at
a time.
External memory is located in the Cortex-M3 external RAM
space; it can use up to 24 address bits. See Table 5-4 on page
19Memory Map on page 19. The memory can be 8 or 16 bits
wide. Cortex-M3 instructions can be fetched/executed from
external memory, although at a slower rate than from flash.
There is no provision for code security in external memory. If
code must be kept secure, then it should be placed in internal
flash. See Flash Security on page 16 and Device Security on
page 60.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
I/O
PORTs
Data Signals
External_ MEM_ DATA[15:0]
I/O
PORTs
Control Signals
I/O
PORTs
Data,
Address,
and Control
Signals
IO IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
Document Number: 001-84935 Rev. *C
Page 18 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Table 5-5. Peripheral Data Address Map (continued)
5.7 Memory Map
The Cortex-M3 has a fixed address map, which allows
peripherals to be accessed by simple memory access
instructions.
5.7.1 Address Map
The 4 GB address space is divided into the ranges shown in
Table 5-4:
0x00000000 –
0x1FFFFFFF
0x20000000 –
0x3FFFFFFF
Purpose
0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs
0x40005000 – 0x400051FF I/O ports control
0x40005400 – 0x400054FF External Memory Interface
(EMIF) control registers
0x40005800 – 0x40005FFF Analog Subsystem Interface
0x40006000 – 0x400060FF USB Controller
Table 5-4. Address Map
Address Range
Address Range
Size
Use
0.5 GB
Program code. This includes
the exception vector table at
power up, which starts at
address 0.
0.5 GB
Static RAM. This includes a 1
MByte bit-band region
starting at 0x20000000 and a
32 Mbyte bit-band alias
region starting at
0x22000000.
0x40000000 –
0x5FFFFFFF
0.5 GB
Peripherals.
0x60000000 –
0x9FFFFFFF
1 GB
External RAM.
0xA0000000 –
0xDFFFFFFF
1 GB
External peripherals.
0xE0000000 –
0xFFFFFFFF
0.5 GB
Internal peripherals, including
the NVIC and debug and
trace modules.
Table 5-5. Peripheral Data Address Map
Address Range
Purpose
0x00000000 – 0x0003FFFF 256K Flash
0x1FFF8000 – 0x1FFFFFFF 32K SRAM in Code region
0x20000000 – 0x20007FFF 32K SRAM in SRAM region
0x40004000 – 0x400042FF Clocking, PLLs, and oscillators
0x40004300 – 0x400043FF Power management
0x40004500 – 0x400045FF Ports interrupt control
0x40004700 – 0x400047FF Flash programming interface
0x40004800 – 0x400048FF Cache controller
0x40004900 – 0x400049FF
I2
C controller
0x40004E00 – 0x40004EFF Decimator
Document Number: 001-84935 Rev. *C
0x40006400 – 0x40006FFF UDB Working Registers
0x40007000 – 0x40007FFF PHUB Configuration
0x40008000 – 0x400087FF EEPROM
0x4000A000 – 0x4000A400 CAN
0x4000C000 – 0x4000C800 Digital Filter Block
0x40010000 – 0x4001FFFF Digital Interconnect Configuration
0x48000000 – 0x48007FFF Flash ECC Bytes
0x60000000 – 0x60FFFFFF External Memory Interface
(EMIF)
0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,
including NVIC, debug, and trace
The bit-band feature allows individual bits in SRAM to be read or
written as atomic operations. This is done by reading or writing
bit 0 of corresponding words in the bit-band alias region. For
example, to set bit 3 in the word at address 0x20000000, write a
1 to address 0x2200000C. To test the value of that bit, read
address 0x2200000C and the result is either 0 or 1 depending
on the value of the bit.
Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
accesses of words and 16-bit half-words on nonword boundary
addresses can also be done, although they are less efficient.
5.7.2 Address Map and Cortex-M3 Buses
The ICode and DCode buses are used only for accesses within
the Code address range, 0 – 0x1FFFFFFF.
The System bus is used for data accesses and debug accesses
within the ranges 0x20000000 – 0xDFFFFFFF and 0xE0100000
– 0xFFFFFFFF. Instruction fetches can also be done within the
range 0x20000000 – 0x3FFFFFFF, although these can be
slower than instruction fetches via the ICode bus.
The Private Peripheral Bus (PPB) is used within the Cortex-M3
to access system control registers and debug and trace module
registers.
Page 19 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Key features of the clocking system include:
6. System Integration
Seven general purpose clock sources
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 67 MHz clock, accurate to ±1% over voltage and
temperature. Additional internal and external clock sources allow
each design to optimize accuracy, power, and cost. All of the
system clock sources can be used to generate other clock
frequencies in the 16-bit clock dividers and UDBs for anything
the user wants, for example a UART baud rate generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows designers to build clocking
systems with minimal input. The designer can specify desired
clock frequencies and accuracies, and the software locates or
builds a clock that meets the required specifications. This is
possible because of the programmability inherent in PSoC.
3- to 62-MHz IMO, ±1% at 3 MHz
4- to 25-MHz External Crystal Oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 23
DSI signal from an external I/O pin or other logic
24- to 67-MHz fractional Phase-Locked Loop (PLL) sourced
from IMO, MHzECO, or DSI
Clock Doubler
1-kHz, 33-kHz, 100-kHz ILO for Watch Dog Timer (WDT) and
Sleep Timer
32.768-kHz External Crystal Oscillator (kHzECO) for Real
Time Clock (RTC)
IMO has a USB mode that auto locks to USB bus clock requiring
no external crystal for USB. (USB equipped parts only)
Independently sourced clock in all clock dividers
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the CPU bus and CPU clock
Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary
Source
Fmin
Tolerance at Fmin
Fmax
Tolerance at Fmax
Startup Time
IMO
3 MHz
±1% over voltage and temperature
62 MHz
±7%
13 µs max
MHzECO
4 MHz
Crystal dependent
25 MHz
Crystal dependent
5 ms typ, max is
crystal dependent
DSI
0 MHz
Input dependent
66 MHz
Input dependent
Input dependent
PLL
24 MHz
Input dependent
67 MHz
Input dependent
250 µs max
Doubler
12 MHz
Input dependent
48 MHz
Input dependent
1 µs max
ILO
1 kHz
–50%, +100%
100 kHz
–55%, +100%
15 ms max in lowest
power mode
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
500 ms typ, max is
crystal dependent
Document Number: 001-84935 Rev. *C
Page 20 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 6-1. Clocking Subsystem
3-62 MHz
IMO
4-25 MHz
ECO
External IO
or DSI
0-66 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU
Clock
48 MHz
Doubler for
USB
24-67 MHz
PLL
System
Clock Mux
Bus
Clock
Bus Clock Divider
16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±7% at 62 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Phase-Locked Loop)
The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 48 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin). The doubler is typically used to clock the USB.
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 67 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
Document Number: 001-84935 Rev. *C
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the CPU and system
clocks up to the device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low power modes.
6.1.1.4 Internal Low Speed Oscillator
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
The central timewheel is a 1 kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a low
power mode. Firmware can reset the central timewheel.
Page 21 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
The central timewheel can be programmed to wake the system
periodically and optionally issue an interrupt. This enables
flexible, periodic wakeups from low power modes or coarse
timing applications. Systems that require accurate timing should
use Real Time Clock capability instead of the central timewheel.
Figure 6-3. 32kHzECO Block Diagram
32 kHz
Crystal Osc
XCLK32K
The 100-kHz clock (CLK100K) can be used as a low power
system clock to run the CPU. It can also generate time intervals
using the fast timewheel.
The fast timewheel is a 5-bit counter, clocked by the 100-kHz
clock. It features programmable settings and automatically
resets when the terminal count is reached. An optional interrupt
can be generated each time the terminal count is reached. This
enables flexible, periodic interrupts of the CPU at a higher rate
than is allowed using the central timewheel.
The 33 kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768 kHz ECO clock with no need for a crystal.
6.1.2 External Oscillators
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate CPU and system
clocks up to the device's maximum frequency (see
Phase-Locked Loop on page 21). The GPIO pins connecting to
the external crystal and capacitors are fixed. MHzECO accuracy
depends on the crystal chosen.
Figure 6-2. MHzECO Block Diagram
4 - 25 MHz
Crystal Osc
Xi
(Pin P15[1])
External
Components
XCLK_MHZ
Xi
(Pin P15[3])
Xo
(Pin P15[2])
External
Components
32 kHz
crystal
Capacitors
It is recommended that the external 32.768-kHz watch crystal
have a load capacitance (CL) of 6 pF or 12.5 pF. Check the
crystal manufacturer's datasheet. The two external capacitors,
CL1 and CL2, are typically of the same value, and their total
capacitance, CL1CL2 / (CL1 + CL2), including pin and trace
capacitance, should equal the crystal CL value. For more
information, refer to application note AN54439: PSoC 3 and
PSoC 5 External Oscillators. See also pin capacitance
specifications in the “GPIO” section on page 69.
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
Xo
(Pin P15[0])
4 – 25 MHz
crystal
Capacitors
6.1.2.2 32.768 kHz ECO
The 32.768 kHz External Crystal Oscillator (32kHzECO)
provides precision timing with minimal power consumption using
an external 32.768 kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the Real Time Clock (RTC). The RTC uses a 1
second interrupt to implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Document Number: 001-84935 Rev. *C
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
Bus Clock 16-bit divider uses the system clock to generate the
system’s bus clock used for data transfers and the CPU. The
CPU clock is directly derived from the bus clock.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
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Datasheet
many others. If more than eight digital clock dividers are
required, the Universal Digital Blocks (UDBs) and fixed function
Timer/Counter/PWMs can also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADCs and mixers.
The analog clock dividers include skew control to ensure that
critical analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
Document Number: 001-84935 Rev. *C
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
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6.2 Power System
VDDIO pins must have capacitors connected as shown in
Figure 6-4. The two VCCD pins must be shorted together, with
as short a trace as possible, and connected to a 1 µF ±10% X5R
capacitor. The power system also contains a sleep regulator, an
I2C regulator, and a hibernate regulator.
The power system consists of separate analog, digital, and I/O
supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(VCCD) and analog (VCCA) supplies for the internal core logic.
The output pins of the regulators (VCCD and VCCA) and the
Figure 6-4. PSoC Power System
VDDD
1 µF
VDDIO2
VDDD
I/O Supply
VSSD
VCCD
VDDIO 2
VDDIO0
0.1 µF
0.1 µF
I/O Supply
VDDIO0
0.1 µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
VDDA
VDDA
Digital
Regulators
VSSB
VCCA
Analog
Regulator
0.1 µF
1 µF
.
VSSA
Analog
Domain
0.1µF
I/O Supply
VDDIO3
VDDD
VSSD
I/O Supply
VCCD
VDDIO1
Hibernate
Regulator
0.1 µF
0.1 µF
VDDIO1
VDDD
VDDIO3
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-6 on page 8.
You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal
regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx
pins.
You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration,
the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in
this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be
disabled to reduce power consumption.
Document Number: 001-84935 Rev. *C
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6.2.1 Power Modes
PSoC 5LP devices have four different power modes, as shown
in Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5LP power modes, in order of decreasing power
consumption are:
Active
Alternate Active
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins. Figure 6-5 illustrates the allowable transitions
between power modes. Sleep and hibernate modes should not
be entered until all VDDIO supplies are at valid voltage levels.
Sleep
Hibernate
Table 6-2. Power Modes
Power Modes
Description
Active
Primary mode of operation,
all peripherals available
(programmable)
Alternate
Active
Sleep
Hibernate
Entry Condition Wakeup Source
Active Clocks
Regulator
Wakeup, reset, Any interrupt
Any (programmable) All regulators available.
manual register
Digital and analog
entry
regulators can be disabled
if external regulation used.
Any (programmable) All regulators available.
Similar to Active mode, and is Manual register Any interrupt
Digital and analog
typically configured to have entry
regulators can be disabled
fewer peripherals active to
if external regulation used.
reduce power. One possible
configuration is to use the
UDBs for processing, with the
CPU turned off
All subsystems automatically Manual register Comparator,
ILO/kHzECO
Both digital and analog
disabled
entry
PICU, I2C, RTC,
regulators buzzed.
CTW, LVD
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
All subsystems automatically Manual register PICU
entry
active.
disabled
Lowest power consuming
mode with all peripherals and
internal regulators disabled,
except hibernate regulator is
enabled
Configuration and memory
contents retained
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(Typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset
Sources
Active
–
3.1 mA[9]
Yes
All
All
All
–
All
Alternate
Active
–
–
User
defined
All
All
All
–
All
<25 µs
2 µA
No
I2C
Comparator
ILO/kHzECO
Comparator,
PICU, I2C, RTC,
CTW, LVD
XRES, LVD,
WDR
<200 µs
300 nA
No
None
None
None
PICU
XRES
Sleep
Hibernate
Note
9. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 63.
Document Number: 001-84935 Rev. *C
Page 25 of 120
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on the input pins; no GPIO should toggle at a rate greater than
10 kHz while in hibernate mode. If pins must be toggled at a high
rate while in a low power mode, use sleep mode instead.
Figure 6-5. Power Mode Transitions
Active
6.2.1.5 Wakeup Events
Manual
Sleep
Hibernate
Alternate
Active
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Firmware enabled interrupt sources include internally
generated interrupts, power supervisor, central timewheel, and
I/O interrupts. Internal interrupt sources can come from a variety
of peripherals, such as analog comparators and UDBs. The
central timewheel provides periodic interrupts to allow the
system to wake up, poll peripherals, or perform real-time
functions. Reset event sources include the external reset I/O pin
(XRES), WDT, and Precision Reset (PRES).
6.2.2 Boost Converter
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.2 Alternate Active Mode
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
Applications that use a supply voltage of less than 1.71 V, such
as single cell battery supplies, may use the on-chip boost
converter. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides.
For instance, this includes driving 5.0 V LCD glass in a 3.3 V
system. The boost converter accepts an input voltage as low as
0.5 V. With one low cost inductor it produces a selectable output
voltage sourcing enough current to operate the PSoC and other
on-board components.
The boost converter accepts an input voltage VBAT from 0.5 V
to 3.6 V, and can start up with VBAT as low as 0.5 V. The
converter provides a user configurable output voltage of 1.8 to
5.0 V (VBOOST). VBAT is typically less than VBOOST; if VBAT
is greater than or equal to VBOOST, then VBOOST will be the
same as VBAT. The block can deliver up to 75 mA (IBOOST)
depending on configuration.
Four pins are associated with the boost converter: VBAT, VSSB,
VBOOST, and Ind. The boosted output voltage is sensed at the
VBOOST pin and must be connected directly to the chip’s supply
inputs. An inductor is connected between the VBAT and Ind pins.
You can optimize the inductor value to increase the boost
converter efficiency based on input voltage, output voltage,
current and switching frequency.
Figure 6-6. Application for Boost Converter
VDDA
VBOOST
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
To achieve an extremely low current, the hibernate regulator has
limited capacity. This limits the frequency of any signal present
Document Number: 001-84935 Rev. *C
VDDD
Schottky diode
IND
PSoC
22 µF 0.1 µF
10 µH
22 µF
VBAT
VSSB
VSSA
VSSD
Page 26 of 120
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Datasheet
The switching frequency is set to 400 kHz using an oscillator in
the boost converter block. The VBOOST is limited to 4 × VBAT.
Figure 6-7. Resets
VDDD VDDA
The boost converter can be operated in two different modes:
active and sleep. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage.
The boost typically draws 250 µA in active mode and 25 µA in
sleep mode. The boost operating modes must be used in
conjunction with chip power modes to minimize total power
consumption. Table 6-4 lists the boost power modes available in
different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes
Power
Voltage
Level
Monitors
Reset
Pin
External
Reset
Processor
Interrupt
Reset
Controller
System
Reset
Boost Power Modes
Chip –Active or
alternate active mode
Boost must be operated in its active
mode.
Chip –Sleep mode
Boost can be operated in either active
or sleep mode. In boost sleep mode,
the chip must wake up periodically for
boost active-mode refresh.
Chip–Hibernate mode Boost can be operated in either active
or sleep mode. However, it is
recommended not to use the boost with
chip hibernate mode due to the higher
current consumption. In boost sleep
mode, the chip must wake up
periodically for boost active-mode
refresh.
If the boost converter is not used, tie the VBAT, VSSB, and
VBOOST pins to ground and leave the Ind pin unconnected.
6.3 Reset
CY8C56LP has multiple internal and external reset sources
available. The reset sources are:
Power source monitoring - The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull up to VDDIO1. VDDD, VDDA, and VDDIO1 must
all have voltage applied before the part comes out of reset.
Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
Software - The device can be reset under program control.
Document Number: 001-84935 Rev. *C
Watchdog
Timer
Software
Reset
Register
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register shows some of the resets or power voltage
monitoring interrupts. The program may examine this register to
detect and report certain exception conditions. This register is
cleared after a power-on reset. For details see the Technical
Reference Manual.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
IPOR - Initial Power-on-Reset
At initial power on, IPOR monitors the power voltages VDDD,
VDDA, VCCD and VCCA. The trip level is not precise. It is set to
approximately 1 volt, which is below the lowest specified
operating voltage but high enough for the internal circuits to be
reset and to hold their reset state. The monitor generates a
reset pulse that is at least 150 ns wide. It may be much wider
if one or more of the voltages ramps up slowly.
If after the IPOR triggers either VDDX drops back below the
trigger point, in a non-monotonic fashion, it must remain below
that point for at least 10 µs. The hysteresis of the IPOR trigger
point is typically 100 mV.
After boot, the IPOR circuit is disabled and voltage supervision
is handed off to the precise low-voltage reset (PRES) circuit.
PRES - Precise Low-Voltage Reset
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
In normal operating mode, the program cannot disable the
digital PRES circuit. The analog regulator can be disabled,
which also disables the analog portion of the PRES. The PRES
circuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory
Page 27 of 120
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Datasheet
services and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
After PRES has been deasserted, at least 10 µs must elapse
before it can be reasserted.
ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
Interrupt circuits are available to detect when VDDA and
VDDD go outside a voltage range. For AHVI, VDDA is
compared to a fixed trip level. For ALVI and DLVI, VDDA and
VDDD are compared to trip levels that are programmable, as
listed in Table 6-5. ALVI and DLVI can also be configured to
generate a device reset instead of an interrupt.
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Voltage
Available Trip
Interrupt Supply Normal
Range
Settings
1.70 V–5.45 V in 250
DLVI
VDDD 1.71 V–5.5 V
mV increments
ALVI
VDDA 1.71 V–5.5 V
1.70 V–5.45 V in 250
mV increments
AHVI
VDDA 1.71 V–5.5 V
5.75 V
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wakeup
sequence. The interrupt is then recognized and may be
serviced.
The buzz frequency is adjustable, and should be set to be less
than the minimum time that any voltage is expected to be out
of range. For details on how to adjust the buzz frequency, see
the TRM.
6.3.1.2 Other Reset Sources
XRES - External Reset
PSoC 5LP has either a single GPIO pin that is configured as
an external reset or a dedicated XRES pin. Either the
dedicated XRES pin or the GPIO pin, if configured, holds the
part in reset while held active (low). The response to an XRES
is the same as to an IPOR reset.
The external reset is active low. It includes an internal pull up
resistor. XRES is active during sleep and hibernate modes.
After XRES has been deasserted, at least 10 µs must elapse
before it can be reasserted.
SRES - Software Reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Another register bit exists to disable this function.
WRES - Watchdog Timer Reset
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
Note
10. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-84935 Rev. *C
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Note IPOR disables the watchdog function. The program must
enable the watchdog function at an appropriate point in the
code by setting a register bit. When this bit is set, it cannot be
cleared again except by an IPOR power on reset event.
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the VDDIO pins.
There are two types of I/O pins on every device; those with USB
provide a third type. Both General Purpose I/O (GPIO) and
Special I/O (SIO) provide similar digital functionality. The primary
differences are their analog capability and drive strength.
Devices that include USB also provide two USBIO pins that
support specific USB functionality as well as limited GPIO
capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense[10], and LCD segment drive,
while SIO pins are used for voltages in excess of VDDA and for
programmable output voltages.
Features supported by both GPIO and SIO:
User programmable port reset state
Separate I/O supplies and voltages for up to four groups of I/O
Digital peripherals use DSI to connect the pins
Input or output or both for CPU and DMA
Eight drive modes
Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
Dedicated port interrupt vector for each port
Slew rate controlled digital output drive mode
Access port control and configuration registers on either port
basis or pin basis
Separate port read (PS) and write (DR) data registers to avoid
read modify write errors
Special functionality on a pin by pin basis
Additional features only provided on the GPIO pins:
LCD segment drive on LCD equipped devices
[10]
CapSense
Analog input and output capability
Continuous 100 µA clamp current capability
Standard drive strength down to 1.71 V
Additional features only provided on SIO pins:
Higher drive strength than GPIO
Hot swap capability (5 V tolerance at any operating VDD)
Programmable and regulated high input and output drive
levels down to 1.2 V
No analog input, CapSense, or LCD capability
Overvoltage tolerance up to 5.5 V
SIO can act as a general purpose analog comparator
Page 28 of 120
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Datasheet
USBIO features:
Full speed USB 2.0 compliant I/O
Highest drive strength for general purpose use
Input, output, or both for CPU and DMA
Input, output, or both for digital peripherals
Digital output (CMOS) drive mode
Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges
Figure 6-8. GPIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
Vddio Vddio
PRT[x]DR
0
Digital System Output
In
1
Vddio
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Analog
Slew
Cntl
PIN
OE
1
Capsense Global Control
0
1
0
1
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global
PRT[x]AMUX
Analog Mux
LCD
Display
Data
PRT[x]LCD_COM_SEG
Logic & MUX
PRT[x]LCD_EN
LCD Bias Bus
Document Number: 001-84935 Rev. *C
5
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Datasheet
Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Buffer
Thresholds
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
Driver
Vhigh
PRT[x]DR
0
Digital System Output
In
1
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Slew
Cntl
PIN
OE
Figure 6-10. USBIO Block Diagram
Digital Input Path
Naming Convention
‘y’ = Pin Number
USB Receiver Circuitry
PRT[15]DBL_SYNC_IN
PRT[15]PS[6,7]
USBIO_CR1[0,1]
Digital System Input
PICU[15]INTTYPE[y]
PICU[15]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[15]INTSTAT
Digital Output Path
PRT[15]SYNC_OUT
USBIO_CR1[5]
USB or I/O
USBIO_CR1[2]
Vddd
USB SIE Control for USB Mode
PRT[15]DR1[7,6]
Digital System Output
PRT[15]BYP
1
In
Drive
Logic
D+ Open
Drain
PRT[15]DM0[7]
D- Open
Drain
PRT[15]DM1[7]
Document Number: 001-84935 Rev. *C
0
PRT[15]DM0[6]
PRT[15]DM1[6]
D+ pin only
D+ 1.5 k
Vddd
5k
Vddd Vddd
1.5 k
PIN
D+ 5 k
D- 5 k
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Datasheet
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in Table 6-6. Three configuration bits
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers. Figure 6-11 depicts a simplified pin view based on
each of the eight drive modes. Table 6-6 shows the I/O pin’s drive
state based on the port data register value or digital array signal
if bypass mode is selected. Note that the actual I/O pin voltage
is determined by a combination of the selected drive mode and
the load at the pin. For example, if a GPIO pin is configured for
resistive pull up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage
unmeasured at the pin is a low logic state.
Figure 6-11. Drive Mode
Vddio
DR
PS
0.
Pin
High Impedance
Analog
DR
PS
Pin
1. High Impedance
Digital
DR
PS
Pin
2. Resistive
Pull-Up
Vddio
DR
PS
Pin
4. Open Drain,
Drives Low
DR
PS
Vddio
DR
PS
3. Resistive
Pull-Down
Vddio
Pin
5. Open Drain,
Drives High
DR
PS
Vddio
Pin
6. Strong Drive
Pin
DR
PS
Pin
7. Resistive
Pull-Up and Pull-Down
Table 6-6. Drive Modes
Diagram
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
0
High impedance analog
Drive Mode
0
0
0
High Z
High Z
1
High Impedance digital
0
0
1
High Z
High Z
2
Resistive pull up[11]
0
1
0
Res High (5K)
Strong Low
3
Resistive pull down[11]
0
1
1
Strong High
Res Low (5K)
4
Open drain, drives low
1
0
0
High Z
Strong Low
5
Open drain, drive high
1
0
1
Strong High
High Z
6
Strong drive
1
1
0
Strong High
Strong Low
7
Resistive pull up and pull down[11]
1
1
1
Res High (5K)
Res Low (5K)
Note
11. Resistive pull up and pull down are not available with SIO in regulated output mode.
Document Number: 001-84935 Rev. *C
Page 31 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the
PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7,
6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO
and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table 6-7 shows the drive
mode configuration for the USBIO pins.
Table 6-7. USBIO Drive Modes (P15[7] and P15[6])
PRT15.DM1[7,6]
Pull up enable
PRT15.DM0[7,6]
Drive Mode enable
0
0
High Z
Strong Low
Open Drain, Strong Low
0
1
Strong High
Strong Low
Strong Outputs
1
0
Res High (5k)
Strong Low
Resistive Pull Up, Strong Low
1
1
Strong High
Strong Low
Strong Outputs
PRT15.DR[7,6] = 1
High impedance analog
PRT15.DR[7,6] = 0
Description
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
6.4.2 Pin Registers
Registers to configure and interact with pins come in two forms
that may be used interchangeably.
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
High impedance digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Resistive pull up or resistive pull down
Resistive pull up or pull down, respectively, provides a series
resistance in one of the data states and strong drive in the
other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common
application for these modes. Resistive pull up and pull down
are not available with SIO in regulated output mode.
Open drain, drives high and open drain, drives low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for digital
input and output in these modes. A common application for
these modes is driving the I2C bus signal lines.
Strong drive
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal
circumstances. This mode is often used to drive digital output
signals or external FETs.
Resistive pull up and pull down
Similar to the resistive pull up and resistive pull down modes
except the pin is always in series with a resistor. The high data
state is pull up while the low data state is pull down. This mode
is most often used when other signals that may cause shorts
can drive the bus. Resistive pull up and pull down are not
available with SIO in regulated output mode.
Document Number: 001-84935 Rev. *C
6.4.3 Bidirectional Mode
High speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRTxDM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The
bidirectional capability is useful for processor busses and
communications interfaces such as the SPI Slave MISO pin that
requires dynamic hardware control of the output buffer.
The auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRTxSLW registers.
6.4.5 Pin Interrupts
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to “1” and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
Page 32 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
While level sensitive interrupts are not directly supported;
Universal Digital Blocks (UDB) provide this functionality to the
system when needed.
6.4.6 Input Buffer Mode
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
6.4.7 I/O Power Supplies
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (VDDA) pin. This feature
allows users to provide different I/O voltage levels for different
pins on the device. Refer to the specific device package pinout
to determine VDDIO capability for a given port and pin. The SIO
port pins support an additional regulated high output capability,
as described in Adjustable Output Level.
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the VDDIO supply voltage to which
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, select pins provide direct connections to specific
analog features such as the high current DACs or uncommitted
opamps.
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders[12]. See the
“CapSense” section on page 55 for more information.
which is based on an internally generated reference. Typically a
voltage DAC (VDAC) is used to generate the reference (see
Figure 6-12). The “DAC” section on page 56 has more details on
VDAC use and reference routing to the SIO pins. Resistive pull
up and pull down drive modes are not available with SIO in
regulated output mode.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from VDDIO.
The reference sets the pins voltage threshold for a high logic
level (see Figure 6-12). Available input thresholds are:
0.5 × VDDIO
0.4 × VDDIO
0.5 × VREF
VREF
Typically a voltage DAC (VDAC) generates the VREF reference.
“DAC” section on page 56 has more details on VDAC use and
reference routing to the SIO pins.
Figure 6-12. SIO Reference for Input and Output
Input Path
Digital
Input
Vinref
Reference
Generator
SIO_Ref
Voutref
Output Path
Driver
Vhigh
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the “LCD Direct Drive” section on
page 55 for details.
6.4.11 Adjustable Output Level
PIN
Digital
Output
Drive
Logic
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective VDDIO. SIO pins are individually configurable to
output either the standard VDDIO level or the regulated output,
Note
12. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-84935 Rev. *C
Page 33 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
6.4.13 SIO as Comparator
6.4.17 Low Power Functionality
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the Adjustable Input Level
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
In all low power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low power modes.
The digital input path in Figure 6-9 on page 30 illustrates this
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a SIO pin’s
protection diode.
Powering the device up or down while connected to an
operational I2C bus may cause transient states on the SIO pins.
The overall I2C bus design should take this into account.
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage tolerance feature at any
operating VDD.
There are no current limitations for the SIO pins as they present
a high impedance load to the external circuit.
The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the VDDIO supply.
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the VDDIO supply
voltage to which the GPIO belongs.
6.4.18 Special Pin Functionality
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in “Pinouts” on page 5. The special
features are:
Digital
4 to 25 MHz crystal oscillator
32.768 kHz crystal oscillator
2
Wake from sleep on I C address match. Any pin can be used
2
for I C if wake from sleep is not required.
JTAG interface pins
SWD interface pins
SWV interface pins
TRACEPORT interface pins
External reset
Analog
Opamp inputs and outputs
High current IDAC outputs
External reference inputs
6.4.19 JTAG Boundary Scan
The device supports standard JTAG boundary scan chains on all
pins for board level test.
7. Digital Subsystem
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
A common application for this feature is connection to a bus such
as I2C where different devices are running from different supply
voltages. In the I2C case, the PSoC chip is configured into the
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull up to pull the I2C bus voltage above the PSoC pin
supply. For example, the PSoC chip could operate at 1.8 V, and
an external device could run from 5 V. Note that the SIO pin’s
VIH and VIL levels are determined by the associated VDDIO
supply pin.
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture. You
do not need to interact directly with the programmable digital
system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
The SIO pin must be in one of the following modes: 0 (high
impedance analog), 1 (high impedance digital), or 4 (open drain
drives low). See Figure 6-11 for details. Absolute maximum
ratings for the device must be observed for all I/O pins.
functionality of the digital programmable system. UDBs are a
collection of uncommitted logic (PLD) and structural logic
(Datapath) optimized to create all common embedded
peripherals and customized functionality that are application or
design specific.
6.4.16 Reset Configuration
While reset is active all I/Os are reset to and held in the High
Impedance Analog state. After reset is released, the state can be
reprogrammed on a port-by-port basis to pull down or pull up. To
ensure correct reset operation, the port reset configuration data
is stored in special nonvolatile registers. The stored reset data is
automatically transferred to the port reset configuration registers
at reset release.
Document Number: 001-84935 Rev. *C
The main components of the digital programmable system are:
Universal Digital Blocks (UDB) - These form the core
Universal Digital Block array - UDB blocks are arrayed within
a matrix of programmable interconnect. The UDB array
structure is homogeneous and allows for flexible mapping of
digital functions onto the array. The array supports extensive
and flexible routing interconnects between UDBs and the
Digital System Interconnect.
Page 34 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Digital System Interconnect (DSI) - Digital signals from
Universal Digital Blocks (UDBs), fixed function peripherals, I/O
pins, interrupts, DMA, and other system core signals are
attached to the Digital System Interconnect to implement full
featured device connectivity. The DSI allows any digital function
to any pin or other feature routability when used with the
Universal Digital Block array.
Figure 7-1. CY8C56LP Digital Programmable Architecture
Timers
Counters
Logic
NOT
OR
XOR
AND
7.1.2 Example Analog Components
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
IO Port
The following is a sample of the analog components available in
PSoC Creator for the CY8C56LP family. The exact amount of
hardware resources (SC/CT blocks, routing, RAM, flash) used
by a component varies with the features selected in PSoC
Creator for the component.
Amplifiers
TIA
PGA
opamp
UDB Array
UDB
DSI Routing Interface
IO Port
UDB Array
DSI Routing Interface
ADCs
IO Port
IO Port
Digital Core System
and Fixed Function Peripherals
Digital Core System
and Fixed Function Peripherals
Delta-Sigma
Successive Approximation (SAR)
DACs
Current
Voltage
PWM
7.1 Example Peripherals
Comparators
The flexibility of the CY8C56LP family’s Universal Digital Blocks
(UDBs) and Analog Blocks allow the user to create a wide range
of components (peripherals). The most common peripherals
were built and characterized by Cypress and are shown in the
PSoC Creator component catalog, however, users may also
create their own custom components using PSoC Creator. Using
PSoC Creator, users may also create their own components for
reuse within their organization, for example sensor interfaces,
proprietary algorithms, and display interfaces.
Mixers
The number of components available through PSoC Creator is
too numerous to list in the datasheet, and the list is always
growing. An example of a component available for use in
CY8C56LP family, but, not explicitly called out in this datasheet
is the UART component.
7.1.1 Example Digital Components
The following is a sample of the digital components available in
PSoC Creator for the CY8C56LP family. The exact amount of
hardware resources (UDBs, routing, RAM, flash) used by a
component varies with the features selected in PSoC Creator for
the component.
Communications
I2C
UART
SPI
Functions
EMIF
PWMs
Document Number: 001-84935 Rev. *C
7.1.3 Example System Function Components
The following is a sample of the system function components
available in PSoC Creator for the CY8C56LP family. The exact
amount of hardware resources (UDBs, DFB taps, SC/CT blocks,
routing, RAM, flash) used by a component varies with the
features selected in PSoC Creator for the component.
CapSense
LCD Drive
LCD Control
Filters
7.1.4 Designing with PSoC Creator
7.1.4.1 More Than a Typical IDE
A successful design tool allows for the rapid development and
deployment of both simple and complex designs. It reduces or
eliminates any learning curve. It makes the integration of a new
design into the production stream straightforward.
PSoC Creator is that design tool.
PSoC Creator is a full featured Integrated Development
Environment (IDE) for hardware and software design. It is
optimized specifically for PSoC devices and combines a modern,
powerful software development platform with a sophisticated
graphical design tool. This unique combination of tools makes
PSoC Creator the most flexible embedded design platform
available.
Page 35 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Graphical design entry simplifies the task of configuring a
particular part. You can select the required functionality from an
extensive catalog of components and place it in your design. All
components are parameterized and have an editor dialog that
allows you to tailor functionality to your needs.
PSoC Creator automatically configures clocks and routes the I/O
to the selected pins and then generates APIs to give the
application complete control over the hardware. Changing the
PSoC device configuration is as simple as adding a new
component, setting its parameters, and rebuilding the project.
At any stage of development you are free to change the
hardware configuration and even the target processor. To
retarget your application (hardware and software) to new
devices, even from 8- to 32-bit families, just select the new
device and rebuild.
You also have the ability to change the C compiler and evaluate
an alternative. Components are designed for portability and are
validated against all devices, from all families, and against all
supported tool chains Switching compilers is as easy as editing
the from the project options and rebuilding the application with
no errors from the generated APIs or boot code.
7.1.4.2 Component Catalog
The component catalog is a repository of reusable design
elements that select device functionality and customize your
PSoC device. It is populated with an impressive selection of
content; from simple primitives such as logic gates and device
registers, through the digital timers, counters and PWMs, plus
analog components such as ADCs, DACs, and filters, and
communication protocols, such as I2C, USB, and CAN. See
“Example Peripherals” section on page 35 for more details about
available peripherals. All content is fully characterized and
carefully documented in datasheets with code examples, AC/DC
specifications, and user code ready APIs.
7.1.4.3 Design Reuse
The symbol editor gives you the ability to develop reusable
components that can significantly reduce future design time. Just
draw a symbol and associate that symbol with your proven
design. PSoC Creator allows for the placement of the new
symbol anywhere in the component catalog along with the
content provided by Cypress. You can then reuse your content
as many times as you want, and in any number of projects,
without ever having to revisit the details of the implementation.
7.1.4.4 Software Development
Anchoring the tool is a modern, highly customizable user
interface. It includes project management and integrated editors
for C and assembler source code, as well the design entry tools.
Project build control leverages compiler technology from top
commercial vendors such as ARM® Limited, Keil™, and
CodeSourcery (GNU). Free versions of Keil C51 and GNU C
Compiler (GCC) for ARM, with no restrictions on code size or end
product distribution, are included with the tool distribution.
Upgrading to more optimizing compilers is a snap with support
for the professional Keil C51 product and ARM RealView™
compiler.
Document Number: 001-84935 Rev. *C
7.1.4.5 Nonintrusive Debugging
With JTAG (4-wire) and SWD (2-wire) debug connectivity
available on all devices, the PSoC Creator debugger offers full
control over the target device with minimum intrusion.
Breakpoints and code execution commands are all readily
available from toolbar buttons and an impressive lineup of
windows—register, locals, watch, call stack, memory and
peripherals—make for an unparalleled level of visibility into the
system.
PSoC Creator contains all the tools necessary to complete a
design, and then to maintain and extend that design for years to
come. All steps of the design flow are carefully integrated and
optimized for ease-of-use and to maximize productivity.
7.2 Universal Digital Block
The Universal Digital Block (UDB) represents an evolutionary
step to the next generation of PSoC embedded digital peripheral
functionality. The architecture in first generation PSoC digital
blocks provides coarse programmability in which a few fixed
functions with a small number of options are available. The new
UDB architecture is the optimal balance between configuration
granularity and efficient implementation. A cornerstone of this
approach is to provide the ability to customize the devices digital
operation to match application requirements.
To achieve this, UDBs consist of a combination of uncommitted
logic (PLD), structured logic (Datapath), and a flexible routing
scheme to provide interconnect between these elements, I/O
connections, and other peripherals. UDB functionality ranges
from simple self contained functions that are implemented in one
UDB, or even a portion of a UDB (unused resources are
available for other functions), to more complex functions that
require multiple UDBs. Examples of basic functions are timers,
counters, CRC generators, PWMs, dead band generators, and
communications functions, such as UARTs, SPI, and I2C. Also,
the PLD blocks and connectivity provide full featured general
purpose programmable logic within the limits of the available
resources.
Figure 7-2. UDB Block Diagram
PLD
Chaining
Clock
and Reset
Control
Status and
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
Datapath
Datapath
Chaining
Routing Channel
Page 36 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
The main component blocks of the UDB are:
PLD blocks - There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or
combinational sum-of-products logic. PLDs are used to
implement state machines, state bits, and combinational logic
equations. PLD configuration is automatically generated from
graphical primitives.
Datapath Module - This 8-bit wide datapath contains structured
logic to implement a dynamically configurable ALU, a variety
of compare configurations and condition generation. This block
also contains input/output FIFOs, which are the primary parallel
data interface between the CPU/DMA system and the UDB.
Status and Control Module - The primary role of this block is to
provide a way for CPU firmware to interact and synchronize
with UDB operation.
Clock and Reset Module - This block provides the UDB clocks
and reset selection and control.
One 12C4 PLD block is shown in Figure 7-3. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
7.2.2 Datapath Module
The datapath contains an 8-bit single cycle ALU, with associated
compare and condition generation logic. This datapath block is
optimized to implement embedded functions, such as timers,
counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
7.2.1 PLD Module
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, look up tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
Figure 7-3. PLD 12C4 Structure
IN0
TC
TC
TC
TC
TC
TC
TC
TC
IN1
TC
TC
TC
TC
TC
TC
TC
TC
IN2
TC
TC
TC
TC
TC
TC
TC
TC
IN3
TC
TC
TC
TC
TC
TC
TC
TC
IN4
TC
TC
TC
TC
TC
TC
TC
TC
IN5
TC
TC
TC
TC
TC
TC
TC
TC
IN6
TC
TC
TC
TC
TC
TC
TC
TC
IN7
TC
TC
TC
TC
TC
TC
TC
TC
IN8
TC
TC
TC
TC
TC
TC
TC
TC
IN9
TC
TC
TC
TC
TC
TC
TC
TC
IN10
TC
TC
TC
TC
TC
TC
TC
TC
IN11
TC
TC
TC
TC
TC
TC
TC
TC
AND
Array
SELIN
(carry in)
OUT0
MC0
T
T
T
T
T
T
T
T
OUT1
MC1
T
T
T
T
T
T
T
T
OUT2
MC2
T
T
T
T
T
T
T
T
OUT3
MC3
T
T
T
T
T
T
T
T
SELOUT
(carry out)
Document Number: 001-84935 Rev. *C
OR
Array
Page 37 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 7-4. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
F1
F0
A0
A1
D0
D1
D1
Data Registers
D0
To/From
Previous
Datapath
A1
Conditions: 2 Compares,
2 Zero Detect, 2 Ones
Detect Overflow Detect
6
Datapath Control
Input from
Programmable
Routing
Control Store RAM
8 Word X 16 Bit
FIFOs
Input
Muxes
Chaining
Output
Muxes
6
Output to
Programmable
Routing
To/From
Next
Datapath
Accumulators
A0
PI
Parallel Input/Output
(To/From Programmable Routing)
PO
ALU
Shift
Mask
7.2.2.6 Working Registers
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
configurations. The address input to this RAM controls the
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
Table 7-1. Working Datapath Registers
Name
Function
Description
A0 and A1 Accumulators
These are sources and sinks for
the ALU and also sources for the
compares.
D0 and D1 Data Registers
These are sources for the ALU
and sources for the compares.
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumulators or ALU. Each FIFO is four
bytes deep.
ALU
The ALU performs eight general-purpose functions. They are:
Increment
Decrement
Add
Subtract
Logical AND
Logical OR
Logical XOR
Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register
Independent of the ALU operation, these functions are available:
7.2.2.7 Dynamic Datapath Configuration RAM
Shift left
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
x 16-bit configuration RAM, which stores eight unique 16-bit wide
Shift right
Document Number: 001-84935 Rev. *C
Nibble swap
Bitwise OR mask
Page 38 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
7.2.2.8 Conditionals
7.2.2.12 Chaining
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These
conditions are the primary datapath outputs, a selection of which
can be driven out to the UDB routing matrix. Conditional
computation can use the built in chaining to neighboring UDBs
to operate on wider data widths without the need to use routing
resources.
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
7.2.2.9 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.10 Built in CRC/PRS
The datapath has built in support for single cycle Cyclic
Redundancy Check (CRC) computation and Pseudo Random
Sequence (PRS) generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be
implemented in conjunction with PLD logic, or built in chaining
may be use to extend the function into neighboring UDBs.
7.2.2.11 Input/Output FIFOs
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
Figure 7-5. Example FIFO Configurations
System Bus
System Bus
F0
D0/D1
A0/A1/ALU
A0/A1/ALU
A0/A1/ALU
F1
F0
F1
System Bus
System Bus
TX/RX
Dual Capture
Document Number: 001-84935 Rev. *C
F0
F1
D0
A0
D1
A1
7.2.2.13 Time Multiplexing
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.14 Datapath I/O
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the
configuration for the datapath operation to perform in each cycle,
and the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated
conditions, and the serial data outputs. Outputs can be routed to
other UDB blocks, device peripherals, interrupt and DMA
controller, I/O pins, and so on.
7.2.3 Status and Control Module
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Figure 7-6. Status and Control Registers
System Bus
8-bit Status Register
(Read Only)
8-bit Control Register
(Write/Read)
Routing Channel
Dual Buffer
Page 39 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
Figure 7-7. Digital System Interface Structure
System Connections
HV
B
UDB
7.2.3.15 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
7.2.3.16 Clock Generation
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
HV
A
UDB
HV
A
HV
B
UDB
HV
B
HV
A
UDB
HV
A
HV
B
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
HV
B
UDB
HV
A
UDB
HV
A
HV
B
UDB
HV
B
HV
A
UDB
HV
A
HV
B
System Connections
7.3 UDB Array Description
Figure 7-7 shows an example of a 16 UDB array. In addition to
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
Document Number: 001-84935 Rev. *C
7.3.1 UDB Array Programmable Resources
Figure 7-8 shows an example of how functions are mapped into
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Page 40 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8-Bit
Timer
Sequencer
Figure 7-8. Function Mapping Example in a Bank of UDBs
Quadrature Decoder
UDB
UDB
HV
A
16-Bit
PWM
16-Bit PYRS
UDB
HV
B
Figure 7-9. Digital System Interconnect
Timer
Counters
CAN
Interrupt
Controller
I2C
DMA
Controller
I/O Port
Pins
Global
Clocks
UDB
HV
A
HV
B
Digital System Routing I/F
UDB
UDB
UDB
8-Bit
Timer Logic
UDB
8-Bit SPI
I2C Slave
12-Bit SPI
UDB
UDB
HV
B
UDB ARRAY
UDB
HV
A
UDB
HV
B
Digital System Routing I/F
HV
A
Logic
UDB
UDB
UART
UDB
UDB
12-Bit PWM
Global
Clocks
I/O Port
Pins
EMIF
DeltaSigma
ADC
SAR
ADC
SC/CT
Blocks
DACS
Comparators
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-9 illustrates the concept of the digital system
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
Interrupt and DMA routing is very flexible in the CY8C56LP
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-10 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
Figure 7-10. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX
Signals in this category include:
Interrupt requests from all digital peripherals in the system.
Fixed Function IRQs
0
DMA requests from all digital peripherals in the system.
1
IRQs
Digital peripheral data signals that need flexible routing to I/Os.
UDB Array
Digital peripheral data signals that need connections to UDBs.
Connections to the interrupt and DMA controllers.
2
Edge
Detect
3
DRQs
DMA termout (IRQs)
Connection to I/O pins.
Connection to analog system digital signals.
0
Fixed Function DRQs
1
Edge
Detect
Document Number: 001-84935 Rev. *C
Interrupt
Controller
DMA
Controller
2
Page 41 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-13. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from
UDB Array Digital System Interface
Figure 7-11. I/O Pin Synchronization Routing
OE
PIN 0
DO
OE
PIN1
DI
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
7.5 CAN
Figure 7-12. I/O Pin Output Connectivity
8 IO Data Output Connections from the
UDB Array Digital System Interface
DO
PIN 0
DO
PIN1
DO
PIN2
DO
PIN3
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
The CAN peripheral is a fully functional Controller Area Network
(CAN) supporting communication baud rates up to 1 Mbps. The
CAN controller implements the CAN2.0A and CAN2.0B
specifications as defined in the Bosch specification and
conforms to the ISO-11898-1 standard. The CAN protocol was
originally designed for automotive applications with a focus on a
high level of fault detection. This ensures high communication
reliability at a low cost. Because of its success in automotive
applications, CAN is used as a standard communication protocol
for motion oriented machine control networks (CANOpen) and
factory automation applications (DeviceNet). The CAN controller
features allow the efficient implementation of higher level
protocols without affecting the performance of the
microcontroller CPU. Full configuration support is provided in
PSoC Creator.
Port i
Document Number: 001-84935 Rev. *C
Page 42 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 7-14. CAN Bus System Implementation
CAN Node 1
CAN Node 2
CAN Node n
PSoC
CAN
Drivers
CAN Controller
En
Tx Rx
CAN Transceiver
CAN_H
CAN_L
CAN_H
CAN_L
CAN_H
CAN_L
CAN Bus
7.5.1 CAN Features
CAN2.0A/B protocol implementation - ISO 11898 compliant
Standard and extended frames with up to 8 bytes of data per
frame
Message filter capabilities
Remote Transmission Request (RTR) support
Programmable bit rate up to 1 Mbps
Listen Only mode
SW readable error counter and indicator
Sleep mode: Wake the device from sleep with activity on the
Rx pin
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
Enhanced interrupt controller
CAN receive and transmit buffers status
CAN controller error status including BusOff
Document Number: 001-84935 Rev. *C
Receive path
16 receive buffers each with its own message filter
Enhanced hardware message filter implementation that
covers the ID, IDE and RTR
DeviceNet addressing support
Multiple receive buffers linkable to build a larger receive
message array
Automatic transmission request (RTR) response handler
Lost received message notification
Transmit path
Eight transmit buffers
Programmable transmit priority
Round robin
Fixed priority
Message transmissions abort capability
7.5.2 Software Tools Support
CAN Controller configuration integrated into PSoC Creator:
CAN Configuration walkthrough with bit timing analyzer
Receive filter setup
Page 43 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 7-15. CAN Controller Block Diagram
TxMessage0
TxReq
TxAbort
Tx Buffer
Status
TxReq
Pending
TxMessage1
TxReq
TxAbort
Bit Timing
Priority
Arbiter
TxMessage6
TxReq
TxAbort
TxInterrupt
Request
(if enabled)
TxMessage7
TxReq
TxAbort
RxInterrupt
Request
(if enabled)
RxMessage0
Acceptance Code 0
Acceptance Mask 0
RxMessage1
Acceptance Code 1
Acceptance Mask 1
RxMessage
Handler
RxMessage14
Acceptance Code 14
Acceptance Mask 14
RxMessage15
Acceptance Code 15
Acceptance Mask 15
ErrInterrupt
Request
(if enabled)
7.6 USB
PSoC includes a dedicated FS (12 Mbps) USB 2.0 transceiver
supporting all four USB transfer types: control, interrupt, bulk,
and isochronous. PSoC Creator provides full configuration
support. USB interfaces to hosts through two dedicated USBIO
pins, which are detailed in the “I/O System and Routing” section
on page 28.
USB includes the following features:
Manual Memory Management with No DMA Access
Manual Memory Management with Manual DMA Access
Automatic Memory Management with Automatic DMA
Access
WakeUp
Request
Error Detection
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
Interrupts on bus and each endpoint event, with device wakeup
USB Reset, Suspend, and Resume operations
Bus powered and self powered modes
Figure 7-16. USB
Arbiter
System Bus
Three memory modes
Rx
CRC Check
requiring no external crystal for USB (USB equipped parts only)
One bidirectional control endpoint 0 (EP0)
Dedicated 8-byte buffer for EP0
Rx
CAN
Framer
Internal 48 MHz oscillator that auto locks to USB bus clock,
Eight unidirectional data endpoints
Shared 512-byte buffer for the eight data endpoints
Tx
CRC
Generator
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
RTR RxMessages
0-15
Rx Buffer
Status
RxMessage
Available
Tx
CAN
Framer
512 X 8
SRAM
D+
SIE
(Serial Interface
Engine)
Interrupts
External 22 Ω
Resistors
USB
I/O
D–
48 MHz
IMO
Internal 3.3 V regulator for transceiver
Document Number: 001-84935 Rev. *C
Page 44 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
7.7 Timers, Counters, and PWMs
7.8 I2C
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows you to choose the timer, counter, and PWM
features that they require. The tool set utilizes the most optimal
resources available.
The I2C peripheral provides a synchronous two wire interface
designed to interface the PSoC device with a two wire I2C serial
communication bus. It is compatible[13] with I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O may be implemented with GPIO or SIO in open-drain modes.
Additional I2C interfaces can be instantiated using Universal
Digital Blocks (UDBs) in PSoC Creator, as required.
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
16-bit Timer/Counter/PWM (down count only)
Selectable clock source
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Period reload on start, reset, and terminal count
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
Count while enable signal is asserted mode
I2C features include:
Slave and master, transmitter, and receiver operation
Byte processing for low CPU overhead
Support for bus speeds up to 1 Mbps
7 or 10-bit addressing (10-bit addressing requires firmware
support)
Free run mode
One Shot mode (stop at end of period)
SMBus operation (through firmware support - SMBus
Complementary PWM outputs with deadband
PWM output kill
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low power modes on address match
Figure 7-17. Timer/Counter/PWM
Timer / Counter /
PWM 16-bit
I2C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from low
power modes on a 7-bit hardware address match. If wakeup
functionality is required, I2C pin connections are limited to the
two special sets of SIO pins.
Interrupt or polling CPU interface
Timer capture mode
Clock
Reset
Enable
Capture
Kill
To eliminate the need for excessive CPU intervention and
overhead, I2C specific support is provided for status detection
and generation of framing bits. I2C operates as a slave, a master,
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I2C interfaces through the
DSI routing and allows direct connections to any GPIO or SIO
pins.
Glitch filtering (active and alternate-active modes only)
IRQ
TC / Compare!
Compare
Data transfers follow the format shown in Figure 7-18. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
Note
13. The I2C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I2C Block has a digital
glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical
Specifications in “Inputs and Outputs” section on page 69 for details.
Document Number: 001-84935 Rev. *C
Page 45 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 7-18. I2C Complete Transfer Timing
SDA
1-7
SCL
START
Condition
ADDRESS
8
9
R/W
ACK
1-7
8
DATA
7.9 Digital Filter Block
Some devices in the CY8C56LP family of devices have a
dedicated HW accelerator block used for digital filtering. The
DFB has a dedicated multiplier and accumulator that calculates
a 24-bit by 24-bit multiply accumulate in one system clock cycle.
This enables the mapping of a direct form FIR filter that
approaches a computation rate of one FIR tap for each clock
cycle. The MCU can implement any of the functions performed
by this block, but at a slower rate that consumes significant MCU
bandwidth.
The PSoC Creator interface provides a wizard to implement FIR
and IIR digital filters with coefficients for LPF, BPF, HPF, Notch
and arbitrary shape filters. 64 pairs of data and coefficients are
stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of
either FIR or IIR formulation.
Figure 7-19. DFB Application Diagram (pwr/gnd not shown)
BUSCLK
read_data
Data
Source
(PHUB)
write_data
Digital
Routing
Digital Filter
Block
addr
9
1-7
ACK
8
DATA
9
ACK
STOP
Condition
The DFB processes this data and passes the result to another
on chip resource such as a DAC or main memory through DMA
on the system bus.
Data movement in or out of the DFB is typically controlled by the
system DMA controller but can be moved directly by the MCU.
8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses
High resolution Delta-Sigma ADC
Two successive approximation (SAR) ADCs
Four 8-bit DACs that provide either voltage or current output
System
Bus
Data
Dest
(PHUB)
DMA
Request
DMA
CTRL
Four comparators with optional connection to configurable LUT
outputs
Four configurable switched capacitor/continuos time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer
Four opamps for internal use and connection to GPIO that can
be used as high current output buffers
The typical use model is for data to be supplied to the DFB over
the system bus from another on-chip system data source such
as an ADC. The data typically passes through main memory or
is directly transferred from another chip resource through DMA.
Document Number: 001-84935 Rev. *C
CapSense subsystem to enable capacitive touch sensing
Precision reference for generating an accurate analog voltage
for internal analog blocks
Page 46 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 8-1. Analog Subsystem Block Diagram
SAR
ADC
DAC
DAC
DelSig
ADC
SAR
ADC
DAC
Op
Amp
SC/CT Block
SC/CT Block
SC/CT Block
SC/CT Block
Op
Amp
Comparators
CMP
CMP
CMP
Op
Amp
R
O
U
T
I
N
G
Precision
Reference
DAC
Op
Amp
GPIO
Port
A
N
A
L
O
G
CMP
A
N
A
L
O
G
GPIO
Port
R
O
U
T
I
N
G
CapSense Subsystem
Analog
Interface
DSI
Array
Clock
Distribution
Config &
Status
Registers
PHUB
CPU
Decimator
The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and
various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries
that allow you to configure the various analog blocks to perform application specific functions (PGA, transimpedance amplifier, voltage
DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the
communication between the analog peripheral and CPU/Memory.
Document Number: 001-84935 Rev. *C
Page 47 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8.1 Analog Routing
8.1.2 Functional Description
The PSoC 5LP family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the PSoC 5LP family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in PSoC 5LP, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2.
For information on how to make pin selections for optimal analog
routing, refer to the application note, AN58304 - PSoC® 3 and
PSoC® 5 - Pin Selection for Analog Designs.
8.1.1 Features
Flexible, configurable analog routing architecture
16 Analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
Each GPIO is connected to one analog global and one analog
mux bus
8 Analog local buses (abus) to route signals between the
different analog blocks
Multiplexers and switches for input and output selection of the
analog blocks
Document Number: 001-84935 Rev. *C
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in
PSoC 5LP, four in the left half (abusl [0:3]) and four in the right
half (abusr [0:3]) as shown in Figure 8-2. Using the abus saves
the analog globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2,
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
Page 48 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 8-2. CY8C56LP Analog Interconnect
Vssd
*
*
*
*
*
AGL[6]
AGL[7]
AGL[4]
AGL[5]
swinp
01 2 3 456 7 0123
*
GPIO
P3[5]
GPIO
swinp P3[4]
GPIO
swinn P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
*P15[1]
GPXT
*P15[0]
swinn
swfol
swfol
opamp1
opamp3
3210 76543210
swfol
swfol
swinn
*
refbufl_
cmp
vref_cmp1
(0.256V)
bg_vda_res_en
+
- comp2
sc0
Vin
Vref
out
vssa
sc0_bgref
(1.024V)
sc2_bgref
(1.024V)
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
sc1
Vin
Vref
out
SC/CT
Vin
Vref
out
sc2
out
ref
in
Vssa
sc1_bgref
(1.024V)
sc3_bgref
(1.024V)
Vin
Vref
out
sc3
v0
DAC0
i0
DAC1
v1
i1
v2
DAC2
i2
DAC3
v3
i3
VIDAC
USB IO
USB IO
* P15[6]
+
DSM0
-
vssa
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
*P1[7]
GPIO
*P1[6]
dsm0_qtz_vref2 (1.2V)
dsm0_qtz_vref1 (1.024V)
Vdda/3
Vdda/4
ExVrefL
refmux[2:0]
Vp (+)
Vn (-) SAR0
Vrefhi_out
refs
SAR_vref1 (1.024V)
SAR_vref2 (1.2V)
ExVrefR
(+) Vp
SAR1 (-) Vn
Vrefhi_out
refs
SAR_vref1 (1.024V)
SAR_vref2 (1.2V)
SAR ADC
Vdda
Vdda/2
ExVrefL1
ExVrefL2
01 23456 7 0123
3210 76543210
LPF
AGL[3]
AGL[2]
*
*
*
Vbat
Vssd
Ind
Vssb
Vboost
*
*
*
Large ( ~200 Ohms)
*
Switch Resistance
Small ( ~870 Ohms )
GPIO
P5[0]
GPIO
P5[1]
GPIO
P5[2]
GPIO
P5[3]
GPIO
P1[0]
GPIO
P1[1]
GPIO
P1[2]
GPIO
P1[3]
GPIO
P1[4]
GPIO
P1[5]
GPIO
P2[5]
GPIO
P2[6]
GPIO
P2[7]
SIO
P12[4]
SIO
P12[5]
GPIO
P6[4]
GPIO
P6[5]
GPIO
P6[6]
GPIO
P6[7]
*
*
Connection
*
Mux Group
Switch Group
XRES
*
AGL[1]
AGL[0]
AMUXBUSL
AGR[3]
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
Notes:
* Denotes pins on all packages
LCD signals are not shown.
AGR[0]
AMUXBUSR
VBE
Vss ref
Vddio1
AGR[3]
AGR[2]
AGR[1]
TS
ADC
AMUXBUSR
ANALOG ANALOG
BUS
GLOBALS
*
AGL[1]
AGL[2]
AGL[3]
AMUXBUSL
AGL[0]
ANALOG ANALOG
GLOBALS
BUS
*
AMUXBUSL
:
Vdda
Vdda/2
en_resvda
refmux[2:0]
refmux[2:0]
*
en_resvda
DSM
vcm
refs
qtz_ref
vref_vss_ext
*
vssd
dsm0_vcm_vref1 (0.8V)
dsm0_vcm_vref2 (0.7V)
Vssd
Vddd
* P15[7]
dac_vref (0.256V)
vcmsel[1:0]
Vccd
ABUSR0
ABUSR1
ABUSR2
ABUSR3
ABUSL0
ABUSL1
ABUSL2
ABUSL3
*
*
Vddio2
refbufr
*
*
Vddd
i1
AGR[4]
AMUXBUSR
CAPSENSE
out
ref
in refbufl
refsel[1:0]
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3] *
GPIO
P2[4] *
+
-
i3
cmp0_vref
(1.024V)
bg_vda_swabusl0
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
Vssd
comp3
ExVrefR
cmp1_vref
Vdda
Vdda/2
Vccd
comp1 +
-
COMPARATOR
cmp_muxvn[1:0]
abuf_vref_int
(1.024V)
swin
AGR[7]
AGR[6]
AGR[5]
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
cmp1_vref
cmp0_vref
(1.024V)
out1
comp0
+
-
swout
in1
out0
swin
i2
*
LPF
in0
abuf_vref_int
(1.024V)
refbufr_
cmp
swout
i0
cmp1_vref
*
*
opamp2
*
*
opamp0
*
*
*
*
AMUXBUSL
*
AGR[6]
AGR[7]
ExVrefL2
swinp
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
*
AGR[4]
AGR[5]
AGL[6]
AGL[7]
ExVrefL
ExVrefL1
*
*
AMUXBUSR
AMUXBUSL
AGL[4]
AGL[5]
Vddio3
GPIO
P3[6]
GPIO
P3[7]
SIO
P12[0]
SIO
P12[1]
GPIO
P15[2]
GPIO
P15[3]
swinp
*
Vcca
Vssa
Vdda
SIO
P12[2]
SIO
P12[3]
GPIO
P4[0]
GPIO
P4[1]
GPIO
P0[0]
GPIO
P0[1]
GPIO
P0[2]
GPIO
P0[3]
Vddio0
swinn
Rev #60
10-Feb-2012
To preserve detail of this image, this image is best viewed with a PDF display program or printed on 11” × 17” paper.
Document Number: 001-84935 Rev. *C
Page 49 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8.2 Delta-sigma ADC
Figure 8-4. Delta-sigma ADC Block Diagram
Some CY8C36 devices offer a delta-sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for measurement applications. The
converter can be configured to output 12-bit resolution at data
rates of up to 192 ksps. At a fixed clock rate, resolution can be
traded for faster data rates as shown in Table 8-1 and Figure 8-3.
Positive
Input Mux
(Analog Routing)
Input
Buffer
Negative
Input Mux
Delta
Sigma
Modulator
Decimator
12 to 20 Bit
Result
EOC
SOC
Table 8-1. Delta-sigma ADC Performance
Bits
Maximum Sample Rate
(sps)
SINAD (dB)
12
192 k
66
8
384 k
43
Resolution and sample rate are controlled by the Decimator.
Data is pipelined in the decimator; the output is a function of the
last four samples. When the input multiplexer is switched, the
output data is not valid until after the fourth sample after the
switch.
Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V
1,000,000
100,000
8.2.2 Operational Modes
The ADC can be configured by the user to operate in one of four
modes: Single Sample, Multi Sample, Continuous, or Multi
Sample (Turbo). All four modes are started by either a write to
the start bit in a control register or an assertion of the Start of
Conversion (SoC) signal. When the conversion is complete, a
status bit is set and the output signal End of Conversion (EoC)
asserts high and remains high until the value is read by either the
DMA controller or the CPU.
Sample rates, sps
8.2.2.1 Single Sample
10,000
1,000
Continuous
Multi-Sample
100
7
8
9
10
11
12
13
Resolution, bits
8.2.1 Functional Description
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
block diagram is shown in Figure 8-4. The signal from the input
muxes is delivered to the delta-sigma modulator either directly or
through the input buffer. The delta-sigma modulator performs the
actual analog to digital conversion. The modulator over-samples
the input and generates a serial data stream output. This high
speed data stream is not useful for most applications without
some type of post processing, and so is passed to the decimator
through the Analog Interface block. The decimator converts the
high speed serial data stream into parallel ADC results. The
modulator/decimator frequency response is [(sin x)/x]4.
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
first three conversions prime the decimator. The ADC result is
valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status or configure the
external EoC signal to generate an interrupt or invoke a DMA
request. When the transfer is done the ADC reenters the standby
state where it stays until another SoC event.
8.2.2.2 Continuous
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
8.2.2.3 Multi Sample
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
More information on output formats is provided in the Technical
Reference Manual.
Document Number: 001-84935 Rev. *C
Page 50 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8.2.3 Start of Conversion Input
8.3.2 Conversion Signals
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
Writing a start bit or assertion of a Start of Frame (SOF) signal is
used to start a conversion. SOF can be used in applications
where the sampling period is longer than the conversion time, or
when the ADC needs to be synchronized to other hardware. This
signal is optional and does not need to be connected if the SAR
ADC is running in a continuous mode. A digital clock or UDB
output can be used to drive this input. When the SAR is first
powered up or awakened from any of the sleeping modes, there
is a power up wait time of 10 µs before it is ready to start the first
conversion.
8.2.4 End of Conversion Output
The EoC signal goes high at the end of each ADC conversion.
This signal may be used to trigger either an interrupt or DMA
request.
8.3 Successive Approximation ADCs
The CY8C56LP family of devices has one or two Successive
Approximation (SAR) ADCs, depending on device selected.
These ADCs are 12-bit at up to 1 Msps, with single-ended or
differential inputs, making them useful for a wide variety of
sampling and control applications.
8.3.1 Functional Description
When the conversion is complete, a status bit is set and the
output signal End of Frame (EOF) asserts and remains asserted
until the value is read by either the DMA controller or the CPU.
The EOF signal may be used to trigger an interrupt or a DMA
request.
8.3.3 Operational Modes
A ONE_SHOT control bit is used to set the SAR ADC conversion
mode to either continuous or one conversion per SOF signal.
DMA transfer of continuous samples, without CPU intervention,
is supported.
In a SAR ADC an analog input signal is sampled and compared
with the output of a DAC. A binary search algorithm is applied to
the DAC and used to determine the output bits in succession
from MSB to LSB. A block diagram of one SAR ADC is shown in
Figure 8-5.
8.4 Comparators
Figure 8-5. SAR ADC Block Diagram
Input offset factory trimmed to less than 5 mV
vrefp
vrefn
Rail-to-rail common mode input range (VSSA to VDDA)
S/H
DAC
array
D0:D11
vin
comparator
SAR
digital
D0:D11
autozero
reset
clock
clock
POWER
GROUND
power
filtering
The CY8C56LP family of devices contains four comparators.
Comparators have these features:
vrefp
vrefn
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low power
Comparator outputs can be routed to look up tables to perform
simple logic functions and then can also be routed to digital
blocks
The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
The input is connected to the analog globals and muxes. The
frequency of the clock is 18 times the sample rate; the clock rate
ranges from 1 to 18 MHz.
Document Number: 001-84935 Rev. *C
8.4.1 Input and Output Interface
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
Page 51 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 8-6. Analog Comparator
From
Analog
Routing
From
Analog
Routing
ANAIF
+
comp0
_
+
comp1
_
+
comp3
_
+
_
From
Analog
Routing
From
Analog
Routing
comp2
4
4
LUT0
4
4
4
LUT1
4
LUT2
4
4
LUT3
UDBs
8.4.2 LUT
The CY8C56LP family of devices contains four LUTs. The LUT
is a two input, one output lookup table that is driven by any one
or two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-2.
Document Number: 001-84935 Rev. *C
Table 8-2. LUT Function vs. Program Word and Inputs
Control Word
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Output (A and B are LUT inputs)
FALSE (‘0’)
A AND B
A AND (NOT B)
A
(NOT A) AND B
B
A XOR B
A OR B
A NOR B
A XNOR B
NOT B
A OR (NOT B)
NOT A
(NOT A) OR B
A NAND B
TRUE (‘1’)
Page 52 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8.5 Opamps
The CY8C56LP family of devices contain four general purpose
opamps.
Figure 8-7. Opamp
GPIO
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
8.6 Programmable SC/CT Blocks
Analog
Global Bus
Opamp
Analog
Global Bus
VREF
Analog
Internal Bus
GPIO
=
GPIO
Analog Switch
The opamp is uncommitted and can be configured as a gain
stage or voltage follower on external or internal signals.
See Figure 8-8. In any configuration, the input and output signals
can all be connected to the internal global signals and monitored
with an ADC, or comparator. The configurations are
implemented with switches between the signals and GPIO pins.
The CY8C56LP family of devices contains four switched
capacitor/continuous time (SC/CT) blocks. Each switched
capacitor/continuous time block is built around a single rail-to-rail
high bandwidth opamp.
Switched capacitor is a circuit design technique that uses
capacitors plus switches instead of resistors to create analog
functions. These circuits work by moving charge between
capacitors by opening and closing different switches.
Nonoverlapping in phase clock signals control the switches, so
that not all switches are ON simultaneously.
The PSoC Creator tool offers a user friendly interface, which
allows you to easily program the SC/CT blocks. Switch control
and clock phase control configuration is done by PSoC Creator
so users only need to determine the application use parameters
such as gain, amplifier polarity, VREF connection, and so on.
The same opamps and block interfaces are also connectable to
an array of resistors which allows the construction of a variety of
continuous time functions.
Figure 8-8. Opamp Configurations
a) Voltage Follower
The opamp and resistor array is programmable to perform
various analog functions including
Naked Operational Amplifier - Continuous Mode
Opamp
Vout to Pin
Vin
Unity-Gain Buffer - Continuous Mode
Programmable Gain Amplifier (PGA) - Continuous Mode
Transimpedance Amplifier (TIA) - Continuous Mode
Up/Down Mixer - Continuous Mode
b) External Uncommitted
Opamp
Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode
First Order Analog to Digital Modulator - Switched Cap Mode
Opamp
Vout to GPIO
Vp to GPIO
Vn to GPIO
8.6.1 Naked Opamp
The Naked Opamp presents both inputs and the output for
connection to internal or external signals. The opamp has a unity
gain bandwidth greater than 6.0 MHz and output drive current up
to 650 µA. This is sufficient for buffering internal signals (such as
DAC outputs) and driving external loads greater than 7.5 kohms.
8.6.2 Unity Gain
c) Internal Uncommitted
Opamp
The Unity Gain buffer is a Naked Opamp with the output directly
connected to the inverting input for a gain of 1.00. It has a -3 dB
bandwidth greater than 6.0 MHz.
Vn
To Internal Signals
Opamp
Vout to Pin
Vp
GPIO Pin
Document Number: 001-84935 Rev. *C
Page 53 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8.6.3 PGA
Table 8-4. Feedback Resistor Settings
The PGA amplifies an external or internal signal. The PGA can
be configured to operate in inverting mode or noninverting mode.
The PGA function may be configured for both positive and
negative gains as high as 50 and 49 respectively. The gain is
adjusted by changing the values of R1 and R2 as illustrated in
Figure 8-9. The schematic in Figure 8-9 shows the configuration
and possible resistor settings for the PGA. The gain is switched
from inverting and non inverting by changing the shared select
value of the both the input muxes. The bandwidth for each gain
case is listed in Table 8-3.
Configuration Word
Nominal Rfb (KΩ)
000b
20
001b
30
Table 8-3. Bandwidth
Gain
Bandwidth
1
6.0 MHz
24
340 kHz
48
220 kHz
50
215 kHz
010b
40
011b
60
100b
120
101b
250
110b
500
111b
1000
Figure 8-10. Continuous Time TIA Schematic
R fb
Figure 8-9. PGA Resistor Settings
Vin
Vref
0
1
R1
R2
V ref
20 k or 40 k
0
Vin
1
V out
20 k to 980 k
S
Vref
I in
The TIA configuration is used for applications where an external
sensor's output is current as a function of some type of stimulus
such as temperature, light, magnetic flux etc. In a common
application, the voltage DAC output can be connected to the
VREF TIA input to allow calibration of the external sensor bias
current by adjusting the voltage DAC output voltage.
The PGA is used in applications where the input signal may not
be large enough to achieve the desired resolution in the ADC, or
dynamic range of another SC/CT block such as a mixer. The gain
is adjustable at runtime, including changing the gain of the PGA
prior to each ADC sample.
8.6.4 TIA
The Transimpedance Amplifier (TIA) converts an internal or
external current to an output voltage. The TIA uses an internal
feedback resistor in a continuous time configuration to convert
input current to output voltage. For an input current Iin, the output
voltage is VREF - Iin x Rfb, where VREF is the value placed on the
non inverting input. The feedback resistor Rfb is programmable
between 20 KΩ and 1 MΩ through a configuration register.
Table 8-4 shows the possible values of Rfb and associated
configuration settings.
Document Number: 001-84935 Rev. *C
Page 54 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8.7 LCD Direct Drive
8.7.1 LCD Segment Pin Driver
The PSoC Liquid Crystal Display (LCD) driver system is a highly
configurable peripheral designed to allow PSoC to directly drive
a broad range of LCD glass. All voltages are generated on chip,
eliminating the need for external components. With a high
multiplex ratio of up to 1/16, the CY8C56LP family LCD driver
system can drive a maximum of 736 segments. The PSoC LCD
driver module was also designed with the conservative power
budget of portable devices in mind, enabling different LCD drive
modes and power down modes to conserve power.
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.7.2 Display Data Flow
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
Key features of the PSoC LCD segment system are:
8.7.3 UDB and LCD Segment Control
LCD panel direct driving
Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
Internal bias voltage generation through internal resistor ladder
8.7.4 LCD DAC
Type A (standard) and Type B (low power) waveform support
Wide operating voltage range support (2 V to 5 V) for LCD
panels
Up to 62 total common and segment outputs
Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
Up to 62 front plane/segment outputs for direct drive
Drives up to 736 total segments (16 backplane x 46 front plane)
Up to 64 levels of software controlled contrast
Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
Adjustable LCD refresh rate from 10 Hz to 150 Hz
Ability to invert LCD display for negative image
Three LCD driver drive modes, allowing power optimization
Figure 8-11. LCD System
8.8 CapSense
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense. Specific
resource usage is detailed in the CapSense component in PSoC
Creator.
A capacitive sensing method using a delta-sigma modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
LCD
DAC
Global
Clock
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
8.9 Temp Sensor
UDB
LCD Driver
Block
DMA
PIN
Die temperature is used to establish programming parameters
for writing flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
Display
RAM
PHUB
Document Number: 001-84935 Rev. *C
Page 55 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
8.10 DAC
Source and sink option for current output
The CY8C56LP parts contain four Digital to Analog Convertors
(DACs). Each DAC is 8-bit and can be configured for either
voltage or current output. The DACs support CapSense, power
supply regulation, and waveform generation. Each DAC has the
following features.
8 Msps conversion rate for current output
Adjustable voltage or current output in 255 steps
1 Msps conversion rate for voltage output
Monotonic in nature
Data and strobe inputs can be provided by the CPU or DMA,
or routed directly from the DSI
Programmable step size (range selection)
Dedicated low-resistance output pin for high-current mode
Eight bits of calibration to correct ± 25% of gain error
Figure 8-12. DAC Block Diagram
I
Reference
Source
source Range
1x , 8x , 64x
Vout
Scaler
R
Iout
3R
I sink Range
1x , 8x , 64x
8.10.1 Current DAC
The current DAC (IDAC) can be configured for the ranges 0 to
31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be
configured to source or sink current.
8.10.2 Voltage DAC
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.02 V and 0 to 4.08 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
frequency components at odd integer multiples of the local
oscillator frequency. The local oscillator frequency is provided by
the selected clock source for the mixer.
Continuous time up and down mixing works for applications with
input signals and local oscillator frequencies up to 1 MHz.
Figure 8-13. Mixer Configuration
C2 = 1.7 pF
C1 = 850 fF
Rmix 0 20 k or 40 k
8.11 Up/Down Mixer
In continuous time mode, the SC/CT block components are used
to build an up or down mixer. Any mixing application contains an
input signal frequency and a local oscillator frequency. The
polarity of the clock, Fclk, switches the amplifier between
inverting or noninverting gain. The output is the product of the
input and the switching function from the local oscillator, with
frequency components at the local oscillator plus and minus the
signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level
Document Number: 001-84935 Rev. *C
sc_clk
Rmix 0 20 k or 40 k
Vin
0
Vref
Vout
1
sc_clk
Page 56 of 120
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Datasheet
8.12 Sample and Hold
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some
applications require multiple signals to be sampled
simultaneously, such as for power calculations (V and I). PSoC
Creator offers a sample and hold component to support this
function.
Φ1
C1
C2
Φ1
n
Φ1
Φ2
Data Watchpoint and Trigger (DWT) block for implementing
watchpoints, trigger resources, and system profiling
V ref
V out
Φ2
debugging
Φ2
Φ1
V ref
C3
C4
Φ2
Vref
8.12.1 Down Mixer
The S+H can be used as a mixer to down convert an input signal.
This circuit is a high bandwidth passive sample network that can
sample input signals up to 14 MHz. This sampled value is then
held using the opamp with a maximum clock rate of 4 MHz. The
output frequency is at the difference between the input frequency
and the highest integer multiple of the Local Oscillator that is less
than the input.
8.12.2 First Order Modulator - SC Mode
A first order modulator is constructed by placing the switched
capacitor block in an integrator mode and using a comparator to
provide a 1-bit feedback to the input. Depending on this bit, a
reference voltage is either subtracted or added to the input
signal. The block output is the output of the comparator and not
the integrator in the modulator case. The signal is downshifted
and buffered and then processed by a decimator to make a
delta-sigma converter or a counter to make an incremental
converter. The accuracy of the sampled data from the first-order
modulator is determined from several factors.
The main application for this modulator is for a low frequency
ADC with high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement
Document Number: 001-84935 Rev. *C
Embedded Trace Macrocell (ETM) for instruction trace
Instrumentation Trace Macrocell (ITM) for support of printf-style
Φ1
Φ2
JTAG or SWD access
breakpoints and code patches
Φ2
Φ1
The Cortex-M3 has internal debugging components, tightly
integrated with the CPU, providing the following features:
Flash Patch and Breakpoint (FPB) block for implementing
Figure 8-14. Sample and Hold Topology
(Φ1 and Φ2 are opposite phases of a clock)
Vi
9. Programming, Debug Interfaces,
Resources
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Four interfaces are available: JTAG, SWD, SWV, and
TRACEPORT. JTAG and SWD support all programming and
debug features of the device. JTAG also supports standard JTAG
scan chains for board level test and chaining multiple JTAG
devices to a single JTAG connection. The SWV and
TRACEPORT provide trace output from the DWT, ETM, and
ITM. TRACEPORT is faster but uses more pins. SWV is slower
but uses only one pin.
For more information on PSoC 5 programming, refer to the
application note PSoC 5 Device Programming Specifications.
Cortex-M3 debug and trace functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All Cortex-M3 debug and trace modules are disabled by default
and can only be enabled in firmware. If not enabled, the only way
to reenable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables them. Disabling debug and trace features, robust flash
protection, and hiding custom analog and digital functionality
inside the PSoC device provide a level of security not possible
with multichip application solutions. Additionally, all device
interfaces can be permanently disabled (Device Security) for
applications concerned about phishing attacks due to a
maliciously reprogrammed device. Permanently disabling
interfaces is not recommended in most applications because the
designer then cannot access the device later. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Page 57 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG clock frequency can
be up to 12 MHz, or 1/3 of the CPU clock frequency for 8 and
16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit
transfers, whichever is least. By default, the JTAG pins are
enabled on new devices but the JTAG interface can be disabled,
allowing these pins to be used as General Purpose I/O (GPIO)
instead. The JTAG interface is used for programming the flash
memory, debugging, I/O scan chains, and JTAG device chaining.
Figure 9-1. JTAG Interface Connections between PSoC 5LP and Programmer
VDD
Host Programmer
PSoC 5
VDD
VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3, 4
TCK
TMS
TCK (P1[1]
5
TMS (P1[0])
5
TDO
TDI (P1[4])
TDI
TDO (P1[3])
nTRST 6
nTRST (P1[5]) 6
XRES
XRES or P1[2] 4
GND
VSSD, VSSA
GND
1
The voltage levels of Host Programmer and the PSoC 5 voltage domains involved in Programming should be same.
The Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by VDDIO1. So, VDDIO1 of PSoC 5 should be at same
voltage level as host VDD. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same
voltage level as host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.
3
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
4
For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by
using the TMS,TCK,TDI, TDO pins of PSoC 5, and writing to a specific register. But this requires that the DPS setting
in NVL is not equal to “Debug Ports Disabled”.
5
By default, PSoC 5 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is
unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD
Protocol has to be used for acquiring the PSoC 5 device initially. After switching from SWD to JTAG mode, the TMS
pin will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.
6
nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 5
as the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.
Document Number: 001-84935 Rev. *C
Page 58 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
9.2 SWD Interface
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D- pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or for programming the flash
memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
Figure 9-2. SWD Interface Connections between PSoC 5LP and Programmer
VDD
Host Programmer
VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3
VDD
SWDCK
SWDCK (P1[1] or P15[7])
SWDIO
SWDIO (P1[0] or P15[6])
XRES or P1[2]
XRES
GND
PSoC 5
GND
3
VSSD, VSSA
1
The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in
programming should be the same. XRES pin (XRES_N or P1[2]) is powered by VDDIO1. The USB SWD
pins are powered by VDDD. So for Programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1
of PSoC 5 should be at the same voltage level as Host VDD. Rest of PSoC 5 voltage domains
( VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD
pins are powered by VDDIO1. So VDDIO1 of PSoC 5 should be at same voltage level as host VDD for
Port 1 SWD programming. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not
be at the same voltage level as host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.
3
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require
external interface circuitry to toggle power which will depend on the programming setup. The power
supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or
equal to all other supplies.
Document Number: 001-84935 Rev. *C
Page 59 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
9.3 Debug Features
The CY8C56LP supports the following debug features:
Table 9-1. Debug Configurations
Debug and Trace Configuration
GPIO Pins Used
Halt and single-step the CPU
All debug and trace disabled
View and change CPU and peripheral registers, and RAM
JTAG
4 or 5
SWD
2
SWV
1
addresses
Six program address breakpoints and two literal access
breakpoints
TRACEPORT
0
5
Data watchpoint events to CPU
JTAG + TRACEPORT
Patch and remap instruction from flash to SRAM
SWD + SWV
3
Debugging at the full speed of the CPU
SWD + TRACEPORT
7
Compatible with PSoC Creator and MiniProg3 programmer and
debugger
Standard JTAG programming and debugging interfaces make
CY8C56LP compatible with other popular third-party tools (for
example, ARM / Keil)
9.4 Trace Features
The following trace features are supported:
Instruction trace
Data watchpoint on access to data address, address range, or
data value
Trace trigger on data watchpoint
Debug exception trigger
Code profiling
Counters for measuring clock cycles, folded instructions,
load/store operations, sleep cycles, cycles per instruction,
interrupt overhead
Interrupt events trace
Software event monitoring, “printf-style” debugging
9.5 SWV and TRACEPORT Interfaces
The SWV and TRACEPORT interfaces provide trace data to a
debug host via the Cypress MiniProg3 or an external trace port
analyzer. The 5 pin TRACEPORT is used for rapid transmission
of large trace streams. The single pin SWV mode is used to
minimize the number of trace pins. SWV is shared with a JTAG
pin. If debugging and tracing are done at the same time then
SWD may be used with either SWV or TRACEPORT, or JTAG
may be used with TRACEPORT, as shown in Table 9-1.
Document Number: 001-84935 Rev. *C
9 or 10
9.6 Programming Features
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. Designers can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 5LP offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0x50536F43) to a Write Once Latch (WOL).
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0x50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also
permanently gates off the ability to erase or alter the contents of
the latch. Matching all bits is intentionally not required, so that
single (or few) bit failures do not deassert the WOL output. The
state of the NVL bits after wafer processing is truly random with
no tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0x50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
The user can write the key into the WOL to lock out external
access only if no flash protection is set (see “Flash Security”
section on page 16). However, after setting the values in the
WOL, a user still has access to the part until it is reset. Therefore,
a user can write the key into the WOL, program the flash
protection data, and then reset the part to lock it.
Page 60 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
If the device is protected with a WOL setting, Cypress cannot
perform failure analysis and, therefore, cannot accept RMAs
from customers. The WOL can be read out via Serial Wire Debug
(SWD) port to electrically identify protected parts. The user can
write the key in WOL to lock out external access only if no flash
protection is set. For more information on how to take full
advantage of the security features in PSoC see the PSoC 5
TRM.
10. Development Support
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
A suite of documentation, to ensure that you can find answers to
your questions quickly, supports the CY8C56LP family. This
section contains a list of some of the key documents.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component datasheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
The CY8C56LP family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit
psoc.cypress.com/getting-started to find out more.
10.1 Documentation
Technical Reference Manual: PSoC Creator makes designing
with PSoC as easy as dragging a peripheral onto a schematic,
but, when low level details of the PSoC device are required, use
the technical reference manual (TRM) as your guide.
Note Visit www.arm.com for detailed documentation about the
Cortex-M3 CPU.
10.2 Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging
interfaces, the CY8C56LP family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Document Number: 001-84935 Rev. *C
Page 61 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
11. Electrical Specifications
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC
Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example
Peripherals” section on page 35 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications
Parameter
Description
Min
Typ
Max
Units
–55
25
100
°C
Analog supply voltage relative to
VSSA
–0.5
–
6
V
VDDD
Digital supply voltage relative to
VSSD
–0.5
–
6
V
VDDIO
I/O supply voltage relative to VSSD
–0.5
–
6
V
VCCA
Direct analog core voltage input
–0.5
–
1.95
V
VCCD
Direct digital core voltage input
VSSA
Analog ground voltage
VGPIO[14]
DC input voltage on GPIO
VSIO
DC input voltage on SIO
VIND
Voltage at boost converter input
TSTG
Storage temperature Ft
VDDA
Conditions
Extended duration storage
temperatures above 100 °C
degrade reliability.
–0.5
–
1.95
V
VSSD –0.5
–
VSSD +
0.5
V
Includes signals sourced by VDDA
and routed internal to the pin.
VSSD –0.5
–
VDDIO +
0.5
V
Output disabled
VSSD –0.5
–
7
V
Output enabled
VSSD –0.5
–
6
V
0.5
–
5.5
V
VSSD –0.5
–
5.5
V
–
–
100
mA
VBAT
Boost converter supply
IVDDIO
Current per VDDIO supply pin
IGPIO
GPIO current
–30
–
41
mA
ISIO
SIO current
–49
–
28
mA
IUSBIO
USBIO current
–56
–
59
mA
LU
Latch up current[15]
–140
–
140
mA
ESDHBM
Electrostatic discharge voltage
Human Body Model
2000
–
–
V
ESDCDM
Electrostatic discharge voltage
Charge Device Model
500
–
–
V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Notes
14. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin ≤ VDDIO ≤ VDDA.
15. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
Document Number: 001-84935 Rev. *C
Page 62 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
11.2 Device Level Specifications
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. Unless otherwise specified, all charts and graphs show typical values.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Parameter
Description
Analog supply voltage and input to
VDDA
analog core regulator
Analog supply voltage, analog
VDDA
regulator bypassed
Digital supply voltage relative to VSSD
VDDD
Digital supply voltage, digital regulator
VDDD
bypassed
I/O supply voltage relative to VSSIO
VDDIO[17]
Direct analog core voltage input
VCCA
(Analog regulator bypass)
Direct digital core voltage input (Digital
VCCD
regulator bypass)
Active Mode
Sum of digital and analog IDDD + IDDA.
IDD[18]
IDDIOX for I/Os not included.
IMO enabled, bus clock and CPU clock
enabled. CPU executing complex
program from flash.
Conditions
Analog core regulator enabled
Min
1.8
Typ
–
Max
5.5
Units
V
Analog core regulator disabled
1.71
1.8
1.89
V
Digital core regulator enabled
Digital core regulator disabled
1.8
1.71
–
1.8
VDDA[16]
1.89
V
V
Analog core regulator disabled
1.71
1.71
–
1.8
VDDA[16]
1.89
V
V
Digital core regulator disabled
1.71
1.8
1.89
V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.9
1.9
2
3.1
3.1
3.2
5.4
5.4
5.6
8.9
8.9
9.1
15.5
15.4
15.7
18
18
18.5
3.8
3.8
3.8
5
5
5
7
7
7
10.5
10.5
10.5
17
17
17
19.5
19.5
19.5
mA
VDDX = 2.7 V to 5.5 V;
FCPU = 3 MHz[19]
VDDX = 2.7 V to 5.5 V;
FCPU = 6 MHz
VDDX = 2.7 V to 5.5 V;
FCPU = 12 MHz[19]
VDDX = 2.7 V to 5.5 V;
FCPU = 24 MHz[19]
VDDX = 2.7 V to 5.5 V;
FCPU = 48 MHz[19]
VDDX = 2.7 V to 5.5 V;
FCPU = 62 MHz
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
Notes
16. The power supplies can be brought up in any sequence however once stable VDDA must be greater than or equal to all other supplies.
17. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin ≤ VDDIO ≤ VDDA.
18. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device datasheet and component datasheets.
19. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
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Table 11-2. DC Specifications (continued)
Parameter
Description
IDD[20]
Sleep Mode[21]
Conditions
VDD = VDDIO = 4.5–5.5 V
CPU = OFF
RTC = ON (= ECO32K ON, in
low-power mode)
Sleep timer = ON (= ILO ON at
1 kHz)[22]
VDD = VDDIO = 2.7–3.6 V
WDT = OFF
2
I C Wake = OFF
Comparator = OFF
POR = ON
VDD = VDDIO = 1.71–1.95 V
Boost = OFF
SIO pins in single ended input, unregulated output mode
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
VDD = VDDIO = 2.7–3.6 V[23] T = 25 °C
Comparator = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
I2C Wake = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated output mode
I2C Wake = ON
VDD = VDDIO = 2.7–3.6 V[23] T = 25 °C
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated output mode
Hibernate Mode
VDD = VDDIO = 4.5–5.5 V
T = –40 °C
T = 25 °C
Hibernate mode current
T = 85 °C
All regulators and oscillators off.
=
V
=
2.7–3.6
V
T = –40 °C
V
DD
DDIO
SRAM retention
GPIO interrupts are active
T = 25 °C
Boost = OFF
T = 85 °C
SIO pins in single ended input, unregVDD = VDDIO = 1.71–1.95 V T = –40 °C
ulated output mode
T = 25 °C
T = 85 °C
Analog current consumption while
VDDA ≤ 3.6 V
IDDAR[23]
device is reset
VDDA > 3.6 V
[23]
Digital current consumption while
VDDD ≤ 3.6 V
IDDDR
device is reset
VDDD > 3.6 V
[23]
Current consumption while device
IDD_PROG
programming. Sum of digital, analog,
and IOs: IDDD + IDDA + IDDIOX.
Min
Typ
Max
Units
–
–
–
–
–
–
–
–
–
–
1.9
2.4
5
1.7
2
4.2
1.6
1.9
4.2
3
3.1
3.6
16
3.1
3.6
16
3.1
3.6
16
4.2
µA
µA
–
1.7
3.6
µA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.2
0.24
2.6
0.11
0.3
2
0.9
0.11
1.8
0.3
1.4
1.1
0.7
15
2
2
15
2
2
15
2
2
15
0.6
3.3
3.1
3.1
21
µA
mA
mA
mA
mA
mA
Notes
20. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device datasheet and component datasheets.
21. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.
22. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
23. Based on device characterization (Not production tested).
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Datasheet
Figure 11-1. IDD vs Frequency at 25 °C
Table 11-3. AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FCPU
CPU frequency
1.71 V ≤ VDDD ≤ 5.5 V
DC
–
67.01
MHz
FBUSCLK
Bus frequency
1.71 V ≤ VDDD ≤ 5.5 V
DC
–
67.01
MHz
[24]
SVDD
VDD ramp rate
–
–
0.066
V/µs
TIO_INIT[24]
Time from VDDD/VDDA/VCCD/VCCA ≥
IPOR to I/O ports set to their reset
states
–
–
10
µs
TSTARTUP[24]
Time from VDDD/VDDA/VCCD/VCCA ≥ VCCA/VDDA = regulated from VDDA/VDDD, no
PRES to CPU executing code at reset PLL used, fast IMO boot mode (48 MHz typ.)
vector
VCCA/VCCD = regulated from VDDA/VDDD, no
PLL used, slow IMO boot mode (12 MHz typ.)
–
–
33
µs
–
–
66
µs
–
–
25
µs
–
–
200
µs
TSLEEP[24]
Wakeup from sleep mode –
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
THIBERNATE[24] Wakeup form hibernate mode – Application of external interrupt to
beginning of execution of next CPU
instruction
Note
24. Based on device characterization (not production tested).
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Datasheet
11.3 Power Regulators
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.3.1 Digital Core Regulator
Table 11-4. Digital Core Regulator DC Specifications
Parameter
Description
VDDD
Input voltage
Output voltage
VCCD
Regulator output capacitor
Conditions
±10%, X5R ceramic or better. The two VCCD
pins must be shorted together, with as short
a trace as possible, see Power System on
page 24
Figure 11-2. Analog and Digital Regulators, VCC vs VDD,
10 mA Load
Min
1.8
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Figure 11-3. Digital Regulator PSRR vs Frequency and VDD
90
80
PSRR, dB
P
70
60
50
40
30
20
10
0
0.1
1
10
Frequency, kHz
4.5
3.6
100
1000
2.7
11.3.2 Analog Core Regulator
Table 11-5. Analog Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDA
Output voltage
VCCA
Regulator output capacitor
Conditions
±10%, X5R ceramic or better
Min
1.8
–
–
Typ
–
1.80
1
Max
5.5
–
–
Units
V
V
µF
Figure 11-4. Analog Regulator PSRR vs Frequency and VDD
70
60
PSRR, dB
P
50
40
30
20
10
0
0.1
1
10
Frequency, kHz
4.5
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3.6
100
1000
2.7
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Datasheet
11.3.3 Inductive Boost Regulator.
Table 11-6. Inductive Boost Regulator DC Specifications[25]
Unless otherwise specified, operating conditions are: LBOOST = 10 μH, CBOOST = 22 μF || 0.1 μF, 2 < VBAT:VOUT ≤ 4.
Parameter
VBAT
Description
Input voltage, includes
IOUT
startup voltage[26]
Load current, steady
state[26]
Conditions
IOUT < 7.5 mA, VOUT = 1.8 V nominal
External diode required if VBAT < 0.9 V
Min
0.5
0.6
Typ
–
–
Max
0.6
3.6
Units
V
V
VBAT = 1.6 – 3.6 V, VOUT = 1.6 – 3.6 V
–
–
75
mA
VBAT = 1.6 – 3.6 V, VOUT = 3.6 – 5.0 V, external
–
–
50
mA
diode
VBAT = 0.5 – 1.6 V, VOUT = 1.6 – 3.6 V
–
–
15
mA
VBAT = 0.5 – 1.6 V, VOUT = 3.6 – 5.0 V, external
–
–
15
mA
–
–
700
mA
–
–
250
25
–
–
µA
µA
1.71
1.81
1.90
2.28
2.57
2.85
3.14
3.42
4.75
–
1.8
1.90
2.00
2.40
2.70
3.00
3.30
3.60
5.00
–
1.89
2.00
2.10
2.52
2.84
3.15
3.47
3.78
5.25
4
V
V
V
V
V
V
V
V
V
ratio
diode
ILPK
Inductor peak current
IQ
Quiescent current
Boost active mode
Boost sleep mode, IOUT < 1 µA
VOUT
Boost output
1.8 V nominal
1.9 V nominal
2.0 V nominal
2.4 V nominal
2.7 V nominal
3.0 V nominal
3.3 V nominal
3.6 V nominal, External diode required
5.0 V nominal, External diode required
voltage[27]
VOUT : VBAT
Ratio of VOUT to VBAT
RegLOAD
Load regulation
–
–
5
%
RegLINE
Line regulation
–
–
5
%
Notes
25. Based on device characterization (Not production tested).
26. For VBAT ≤ 0.9 V or VOUT ≥ 3.6 V, an external diode is required.
27. If powering the PSoC from boost with VBAT = 0.5 V, the IMO must be 3 MHz at startup.
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Datasheet
Table 11-7. Inductive Boost Regulator AC Specifications
Parameter
VRIPPLE
Description
Ripple voltage
(peak-to-peak)[28]
Conditions
LBOOST = 10 μH, CBOOST = 22 μF || 0.1 μF, 2 <
VBAT:VOUT ≤ 4, Iout = 10 mA
Min
–
Typ
–
Max
100
Units
mV
Min
4.7
–
–
–
1
Typ
10
10
22
22
–
Max
22
–
–
–
–
Units
µH
µF
µF
µF
A
20
–
–
V
Table 11-8. Recommended External Components for Boost Circuit
Parameter
LBOOST
CBOOST
Description
Boost inductor
Filter capacitor[28]
Conditions
IF
External Schottky
diode average forward
current
LBOOST = 4.7 µH
LBOOST = 10 µH
LBOOST = 22 µH
VR
Figure 11-5. Efficiency vs IOUT VBOOST = 3.3 V,
LBOOST = 10 µH[29]
Figure 11-6. Efficiency vs IOUT VBOOST = 3.3 V, LBOOST =
22 µH[29]
90
90
Vbat = 2.8
Vbat = 2.4
Vbat = 1.8
88
Efficiency, %
Efficiency, %
88
86
84
86
84
Vbat = 2.8
82
82
80
80
Vbat = 2.4
Vbat = 1.8
0
10
20
30
40
IOUT, mA
50
60
70
0
10
20
30
40
50
60
IOUT, mA
Notes
28. Based on device characterization (Not production tested).
29. Typical example. Actual efficiency may vary depending on external component selection, PCB layout, and other design parameters.
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PSoC® 5LP: CY8C56LP Family
Datasheet
11.4 Inputs and Outputs
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. Unless otherwise specified, all charts and graphs show typical values.
When the power supplies ramp up, there are low-impedance connections between each GPIO pin and its VDDIO supply. This causes
the pin voltages to track VDDIO until both VDDIO and VDDA reach the IPOR voltage, which can be as high as 1.45 V. At that point the
low-impedance connections no longer exist, and the pins change to their normal NVL settings.
Also, if VDDA is less than VDDIO, a low-impedance path may exist between a GPIO and VDDA, causing the GPIO to track VDDA until
VDDA becomes greater than or equal to VDDIO.
11.4.1 GPIO
Table 11-9. GPIO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
VIH
Input voltage high threshold
CMOS Input, PRT[x]CTL = 0
0.7 × VDDIO
–
–
V
VIL
Input voltage low threshold
CMOS Input, PRT[x]CTL = 0
–
–
0.3 × VDDIO
V
VIH
Input voltage high threshold
LVTTL Input, PRT[x]CTL = 1,VDDIO < 2.7 V 0.7 x VDDIO
–
–
V
VIH
Input voltage high threshold
LVTTL Input, PRT[x]CTL = 1, VDDIO ≥ 2.7 V
–
–
V
2.0
VIL
Input voltage low threshold
LVTTL Input, PRT[x]CTL = 1,VDDIO < 2.7 V
–
–
0.3 × VDDIO
V
VIL
Input voltage low threshold
LVTTL Input, PRT[x]CTL = 1, VDDIO ≥ 2.7 V
–
–
0.8
V
VOH
Output voltage high
IOH = 4 mA at 3.3 VDDIO
VDDIO – 0.6
–
–
V
IOH = 1 mA at 1.8 VDDIO
VDDIO – 0.5
–
–
V
IOL = 8 mA at 3.3 VDDIO
–
–
0.6
V
IOL = 3 mA at 3.3 VDDIO
–
–
0.4
V
VOL
Output voltage low
IOL = 4 mA at 1.8 VDDIO
Rpullup
Pull up resistor
Rpulldown Pull down resistor
–
–
0.6
V
3.5
5.6
8.5
kΩ
3.5
5.6
8.5
kΩ
IIL
Input leakage current
(absolute value)[30]
25 °C, VDDIO = 3.0 V
–
–
2
nA
CIN
Input capacitance[30]
GPIOs not shared with opamp outputs,
MHz ECO or kHzECO
–
5
9
pF
GPIOs shared with MHz ECO or
kHzECO[31]
–
5
9
pF
GPIOs shared with opamp outputs
–
10
20
pF
GPIOs shared with SAR inputs
–
10
20
pF
VH
Input voltage hysteresis
(Schmitt–Trigger)[30]
–
40
–
mV
Idiode
Current through protection
diode to VDDIO and VSSIO
–
–
100
µA
Rglobal
Resistance pin to analog
global bus
25 °C, VDDIO = 3.0 V
–
320
–
Ω
Rmux
Resistance pin to analog mux 25 °C, VDDIO = 3.0 V
bus
–
220
–
Ω
Notes
30. Based on device characterization (Not production tested).
31. For information on designing with PSoC 3 oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator.
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Datasheet
Figure 11-7. GPIO Output High Voltage and Current
Figure 11-8. GPIO Output Low Voltage and Current
Table 11-10. GPIO AC Specifications[32]
Conditions
Min
Typ
Max
Units
TriseF
Parameter
Rise time in Fast Strong Mode
3.3 V VDDIO Cload = 25 pF
–
–
12
ns
TfallF
Fall time in Fast Strong Mode
3.3 V VDDIO Cload = 25 pF
–
–
12
ns
TriseS
Rise time in Slow Strong Mode
3.3 V VDDIO Cload = 25 pF
–
–
60
ns
Fall time in Slow Strong Mode
3.3 V VDDIO Cload = 25 pF
–
–
60
ns
TfallS
Description
GPIO output operating frequency
Fgpioout
Fgpioin
2.7 V < VDDIO < 5.5 V, fast strong drive mode
90/10% VDDIO into 25 pF
–
–
33
MHz
1.71 V < VDDIO < 2.7 V, fast strong drive mode
90/10% VDDIO into 25 pF
–
–
20
MHz
3.3 V < VDDIO < 5.5 V, slow strong drive mode
90/10% VDDIO into 25 pF
–
–
7
MHz
1.71 V < VDDIO < 3.3 V, slow strong drive mode
90/10% VDDIO into 25 pF
–
–
3.5
MHz
GPIO input operating frequency
90/10% VDDIO
–
–
66
MHz
Figure 11-9. GPIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-10. GPIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Note
32. Based on device characterization (Not production tested).
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Datasheet
11.4.2 SIO
Table 11-11. SIO DC Specifications
Parameter
Description
Vinmax
Maximum input voltage
Vinref
Input voltage reference (Differential
input mode)
Conditions
Min
Typ
Max
Units
All allowed values of VDDIO and
VDDD, see Section 11.1
–
–
5.5
V
0.5
–
0.52 ×VDDIO
V
VDDIO > 3.7
1
–
VDDIO–1
V
VDDIO < 3.7
1
–
VDDIO – 0.5
V
Output voltage reference (Regulated output mode)
Voutref
Input voltage high threshold
VIH
0.7 × VDDIO
–
–
V
SIO_ref + 0.2
–
–
V
CMOS input
–
–
0.3 × VDDIO
V
Hysteresis disabled
–
–
SIO_ref – 0.2
V
VDDIO – 0.4
–
–
V
SIO_ref – 0.65
–
SIO_ref + 0.2
V
GPIO mode
CMOS input
Differential input mode[33]
Hysteresis disabled
Input voltage low threshold
VIL
GPIO mode
Differential input
mode[33]
Output voltage high
VOH
VOL
Unregulated mode
IOH = 4 mA, VDDIO = 3.3 V
Regulated mode[33]
IOH = 1 mA
Output voltage low
IOH = 0.1 mA
SIO_ref – 0.3
–
SIO_ref + 0.2
V
no load, IOH = 0
SIO_ref – 0.1
–
SIO_ref + 0.1
V
VDDIO = 3.30 V, IOL = 25 mA
–
–
0.8
V
VDDIO = 3.30 V, IOL = 20 mA
–
–
0.4
V
VDDIO = 1.80 V, IOL = 4 mA
Rpullup
Rpulldown
IIL
–
–
0.4
V
Pull up resistor
3.5
5.6
8.5
kΩ
Pull down resistor
3.5
5.6
8.5
kΩ
Input leakage current (absolute
value)[34]
VIH < VDDSIO
25 °C, VDDSIO = 3.0 V, VIH = 3.0 V
–
–
14
nA
VIH > VDDSIO
25 °C, VDDSIO = 0 V, VIH = 3.0 V
–
–
10
µA
–
–
7
pF
Single ended mode (GPIO mode)
–
115
–
mV
Differential mode
–
50
–
mV
–
–
100
µA
CIN
Input capacitance[34]
VH
Input voltage hysteresis
(Schmitt–Trigger)[34]
Idiode
Current through protection diode to
VSSIO
Notes
33. See Figure 6-9 on page 30 and Figure 6-12 on page 33 for more information on SIO reference.
34. Based on device characterization (Not production tested).
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Datasheet
Figure 11-11. SIO Output High Voltage and Current,
Unregulated Mode
Figure 11-12. SIO Output Low Voltage and Current,
Unregulated Mode
Figure 11-13. SIO Output High Voltage and Current, Regulated Mode
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Table 11-12. SIO AC Specifications[35]
Parameter
TriseF
TfallF
TriseS
TfallS
Fsioout
Fsioin
Description
Rise time in Fast Strong Mode
(90/10%)
Fall time in Fast Strong Mode
(90/10%)
Rise time in Slow Strong Mode
(90/10%)
Fall time in Slow Strong Mode
(90/10%)
SIO output operating frequency
2.7 V < VDDIO < 5.5 V, Unregulated
output (GPIO) mode, fast strong
drive mode
1.71 V < VDDIO < 2.7 V, Unregulated output (GPIO) mode, fast
strong drive mode
3.3 V < VDDIO < 5.5 V, Unregulated
output (GPIO) mode, slow strong
drive mode
1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow
strong drive mode
2.7 V < VDDIO < 5.5 V, Regulated
output mode, fast strong drive mode
1.71 V < VDDIO < 2.7 V, Regulated
output mode, fast strong drive mode
1.71 V < VDDIO < 5.5 V, Regulated
output mode, slow strong drive
mode
SIO input operating frequency
1.71 V < VDDIO < 5.5 V
Conditions
Cload = 25 pF, VDDIO = 3.3 V
Min
–
Typ
–
Max
12
Units
ns
Cload = 25 pF, VDDIO = 3.3 V
–
–
12
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
75
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
60
ns
90/10% VDDIO into 25 pF
–
–
33
MHz
90/10% VDDIO into 25 pF
–
–
16
MHz
90/10% VDDIO into 25 pF
–
–
5
MHz
90/10% VDDIO into 25 pF
–
–
4
MHz
Output continuously switching into
25 pF
Output continuously switching into
25 pF
Output continuously switching into
25 pF
–
–
20
MHz
–
–
10
MHz
–
–
2.5
MHz
–
–
66
MHz
90/10% VDDIO
Figure 11-14. SIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-15. SIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Note
35. Based on device characterization (Not production tested).
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11.4.3 USBIO
For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 63.
Table 11-13. USBIO DC Specifications
Parameter
Rusbi
Description
Conditions
USB D+ pull-up resistance[36]
[36]
Min
Typ
Max
Units
With idle bus
0.900
–
1.575
kΩ
While receiving traffic
Rusba
USB D+ pull-up resistance
1.425
–
3.090
kΩ
Vohusb
Static output high[36]
15 kΩ ±5% to VSS, internal pull-up
enabled
2.8
–
3.6
V
Volusb
Static output low[36]
15 kΩ ±5% to VSS, internal pull-up
enabled
–
–
0.3
V
Vihgpio
Input voltage high, GPIO mode[36]
VDDD = 1.8 V
1.5
–
–
V
VDDD = 3.3 V
2
–
–
V
VDDD = 5.0 V
2
–
–
V
VDDD = 1.8 V
–
–
0.8
V
VDDD = 3.3 V
–
–
0.8
V
Vilgpio
Input voltage low, GPIO
mode[36]
VDDD = 5.0 V
Vohgpio
Volgpio
VDI
Output voltage high, GPIO mode[36]
Output voltage low, GPIO
mode[36]
Differential input sensitivity
–
–
0.8
V
IOH = 4 mA, VDDD = 1.8 V
1.6
–
–
V
IOH = 4 mA, VDDD = 3.3 V
3.1
–
–
V
IOH = 4 mA, VDDD = 5.0 V
4.2
–
–
V
IOL = 4 mA, VDDD = 1.8 V
–
–
0.3
V
IOL = 4 mA, VDDD = 3.3 V
–
–
0.3
V
IOL = 4 mA, VDDD = 5.0 V
–
–
0.3
V
|(D+)–(D–)|
–
–
0.2
V
Vcm
Differential input common mode range
0.8
–
2.5
V
Vse
Single ended receiver threshold
0.8
–
2
V
Rps2
PS/2 pull-up resistance[36]
In PS/2 mode, with PS/2 pull-up
enabled
3
–
7
kΩ
Rext
External USB series resistor [36]
In series with each USB pin
21.78
(–1%)
22
22.22
(+1%)
Ω
Zo
USB driver output impedance[36]
Including Rext
28
–
44
Ω
CIN
USB transceiver input capacitance
–
–
20
pF
IIL
Input leakage current (absolute
value)[36]
–
–
2
nA
25 °C, VDDD = 3.0 V
Note
36. Based on device characterization (Not production tested).
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Page 74 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 11-16. USBIO Output High Voltage and Current,
GPIO Mode
Figure 11-17. USBIO Output Low Voltage and Current,
GPIO Mode
Table 11-14. USBIO AC Specifications[37]
Parameter
Description
Tdrate
Full–speed data rate average bit rate
Tjr1
Receiver data jitter tolerance to next transition
Conditions
Min
Typ
Max
Units
12 – 0.25%
12
12 + 0.25%
MHz
–8
–
8
ns
Tjr2
Receiver data jitter tolerance to pair transition
–5
–
5
ns
Tdj1
Driver differential jitter to next transition
–3.5
–
3.5
ns
Tdj2
Driver differential jitter to pair transition
–4
–
4
ns
Tfdeop
Source jitter for differential transition to SE0
transition
–2
–
5
ns
Tfeopt
Source SE0 interval of EOP
160
–
175
ns
Tfeopr
Receiver SE0 interval of EOP
82
–
–
ns
Tfst
Width of SE0 interval during differential
transition
–
–
14
ns
Fgpio_out
GPIO mode output operating frequency
3 V ≤ VDDD ≤ 5.5 V
–
–
20
MHz
VDDD = 1.71 V
–
–
6
MHz
VDDD > 3 V, 25 pF load
–
–
12
ns
VDDD = 1.71 V, 25 pF load
–
–
40
ns
VDDD > 3 V, 25 pF load
–
–
12
ns
VDDD = 1.71 V, 25 pF load
–
–
40
ns
Tr_gpio
Tf_gpio
Rise time, GPIO mode, 10%/90% VDDD
Fall time, GPIO mode, 90%/10% VDDD
Note
37. Based on device characterization (Not production tested).
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PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 11-18. USBIO Output Rise and Fall Times, GPIO Mode,
VDDD = 3.3 V, 25 pF Load
Table 11-15. USB Driver AC Specifications[38]
Parameter
Tr
Description
Conditions
Transition rise time
Tf
Transition fall time
TR
Rise/fall time matching
Vcrs
Output signal crossover voltage
VUSB_5, VUSB_3.3, see USB DC
Specifications on page 100
Min
Typ
Max
Units
–
–
20
ns
–
–
20
ns
90%
–
111%
1.3
–
2
V
11.4.4 XRES
Table 11-16. XRES DC Specifications
Min
Typ
Max
Units
VIH
Parameter
Input voltage high threshold
Description
Conditions
0.7 × VDDIO
–
–
V
VIL
Input voltage low threshold
–
–
0.3 ×
VDDIO
V
8.5
kΩ
Rpullup
Pull up resistor
3.5
5.6
CIN
Input capacitance
–
3
VH
Input voltage hysteresis
(Schmitt-trigger)
–
100
–
mV
Idiode
Current through protection diode to
VDDIO and VSSIO
–
–
100
µA
Min
Typ
Max
Units
1
–
–
µs
pF
Table 11-17. XRES AC Specifications[38]
Parameter
TRESET
Description
Reset pulse width
Conditions
Note
38. Based on device characterization (Not production tested).
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Page 76 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
11.5 Analog Peripherals
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.5.1 Opamp
Table 11-18. Opamp DC Specifications
Parameter
Description
VI
Input voltage range
Vos
Input offset voltage
TCVos
Ge1
Cin
Vo
Iout
Idd
CMRR
PSRR
Conditions
Min
VSSA
–
–
Operating temperature –40 °C to
70 °C
Input offset voltage drift with temperature Power mode = high
–
Gain error, unity gain buffer mode
Rload = 1 kΩ
–
Input capacitance
Routing from pin
–
Output voltage range
1 mA, source or sink, power mode VSSA + 0.05
= high
25
Output current capability, source or sink VSSA + 500 mV ≤ Vout ≤ VDDA
–500 mV, VDDA > 2.7 V
16
VSSA + 500 mV ≤ Vout ≤ VDDA
–500 mV, 1.7 V = VDDA ≤ 2.7 V
Quiescent current[39]
Power mode = min
–
Power mode = low
–
Power mode = med
–
Power mode = high
–
Common mode rejection ratio[39]
80
Power supply rejection ratio[39]
VDDA ≥ 2.7 V
85
VDDA < 2.7 V
70
Figure 11-19. Opamp Voffset Histogram, 3388 samples/847
parts, 25 °C, VDDA = 5 V
Typ
–
–
–
–
–
–
–
Max
VDDA
2.5
2
Units
V
mV
mV
±30
µV / °C
±0.1
%
18
pF
VDDA – 0.05
V
–
–
mA
–
–
mA
250
250
330
1000
–
–
–
400
400
950
2500
–
–
–
uA
uA
uA
uA
dB
dB
dB
Figure 11-20. Opamp Voffset vs Temperature, VDDA = 5V
Note
39. Based on device characterization (Not production tested).
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PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 11-22. Opamp Output Voltage vs Load Current and
Temperature, High Power Mode, 25 °C, VDDA = 2.7 V
Figure 11-21. Opamp Voffset vs Vcommon and
VDDA 25 °C
Figure 11-23. Opamp Operating Current vs VDDA and Power
Mode
Table 11-19. Opamp AC Specifications[40]
Parameter
Description
GBW
Gain-bandwidth product
SR
Slew rate, 20% - 80%
en
Input noise density
Conditions
Power mode = minimum, 15 pF load
Power mode = low, 15 pF load
Power mode = medium, 200 pF load
Power mode = high, 200 pF load
Power mode = minimum, 15 pF load
Power mode = low, 15 pF load
Power mode = medium, 200 pF load
Power mode = high, 200 pF load
Power mode = high, VDDA = 5 V,
at 100 kHz
Min
1
2
1
3
1.1
1.1
0.9
3
–
Typ
–
–
–
–
–
–
–
–
45
Max
–
–
–
–
–
–
–
–
–
Units
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
nV/sqrtHz
Note
40. Based on device characterization (Not production tested).
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Page 78 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Figure 11-25. Opamp Step Response, Rising
Figure 11-24. Opamp Noise vs Frequency,
Power Mode = High, VDDA = 5 V
nV/sqrtHz
1000
100
10
0.01
0.1
1
10
100
1000
Frequency, kHz
Figure 11-26. Opamp Step Response, Falling
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Datasheet
11.5.2 Delta-Sigma ADC
Unless otherwise specified, operating conditions are:
Operation in continuous sample mode
fclk = 6.144 MHz
Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
Unless otherwise specified, all charts and graphs show typical values
Table 11-20. 12-bit Delta-sigma ADC DC Specifications
Parameter
Description
Conditions
Resolution
Number of channels, single ended
Number of channels, differential
Monotonic
Ge
Gain error
Gd
Gain drift
Vos
Input offset voltage
TCVos
INL12
DNL12
INL8
DNL8
Rin_Buff
Temperature coefficient, input offset
voltage
Input voltage range, single ended[41]
Input voltage range, differential unbuffered[41]
Input voltage range, differential,
buffered[41]
Integral non linearity[41]
Differential non linearity[41]
Integral non linearity[41]
Differential non linearity[41]
ADC input resistance
Rin_ADC12 ADC input resistance
Differential pair is formed using a
pair of GPIOs.
Yes
Buffered, buffer gain = 1,
Range = ±1.024 V, 25 °C
Buffered, buffer gain = 1,
Range = ±1.024 V
Buffered, 16-bit mode, full voltage
range, 25 °C
Buffered, 16-bit mode, VDDA = 1.7 V,
25 °C
Buffer gain = 1, 12-bit,
Range = ±1.024 V
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Input buffer used
Input buffer bypassed, 12 bit, Range
= ±1.024 V
ADC external reference input voltage, see
also internal reference in Voltage
Pins P0[3], P3[2]
Reference on page 82
Current Consumption
IDD_12
Current consumption, 12 bit[41]
192 ksps, unbuffered
IBUFF
Buffer current consumption[41]
Vextref
Min
8
Typ
–
Units
bits
–
Max
12
No. of
GPIO
No. of
GPIO/2
–
–
–
–
–
–
–
–
±0.4
%
–
–
50
ppm/°C
–
–
±0.2
mV
–
–
±0.1
mV
–
–
0.55
µV/°C
VSSA
–
VDDA
V
VSSA
–
VDDA
V
VSSA
–
VDDA – 1
V
–
–
–
–
10
–
–
–
–
–
±1
±1
±1
±1
–
LSB
LSB
LSB
LSB
MΩ
–
148[42]
–
kΩ
0.9
–
1.3
V
–
–
–
–
1.4
2.5
mA
mA
–
–
–
Notes
41. Based on device characterization (not production tested).
42. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to
the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
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Datasheet
Table 11-21. Delta-sigma ADC AC Specifications
Parameter
Description
Conditions
Startup time
Total harmonic distortion[43]
THD
Min
Typ
Max
Units
–
–
4
Samples
Buffer gain = 1, 12-bit,
Range = ±1.024 V
–
–
0.0032
%
12-Bit Resolution Mode
SR12
Sample rate, continuous, high power[43]
Range = ±1.024 V, unbuffered
4
–
192
ksps
BW12
Input bandwidth at max sample rate[43]
Range = ±1.024 V, unbuffered
–
44
–
kHz
Range = ±1.024 V, unbuffered
66
–
–
dB
[43]
SINAD12int Signal to noise ratio, 12-bit, internal reference
8-Bit Resolution Mode
SR8
Sample rate, continuous, high power[43]
Range = ±1.024 V, unbuffered
8
–
384
ksps
BW8
Input bandwidth at max sample rate[43]
Range = ±1.024 V, unbuffered
–
88
–
kHz
Range = ±1.024 V, unbuffered
43
–
–
dB
SINAD8int
Signal to noise ratio, 8-bit, internal
reference[43]
Table 11-22. Delta-sigma ADC Sample Rates, Range = ±1.024 V
Continuous
Resolution,
Bits
Min
Max
8
8000
9
6400
10
11
12
Multi-Sample
Min
Max
384000
1911
91701
307200
1543
74024
5566
267130
1348
64673
4741
227555
1154
55351
4000
192000
978
46900
Figure 11-27. Delta-sigma ADC IDD vs sps, Range = ±1.024 V,
Continuous Sample Mode, Input Buffer Bypassed
1.4
1.2
Current, mA
1.0
0.8
16 bit
06
0.6
12 bit
0.4
0.2
0.0
1
10
100
Sample rate, Ksps
1000
Note
43. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
Page 81 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
11.5.3 Voltage Reference
Table 11-23. Voltage Reference Specifications
Parameter
VREF
Description
Precision reference voltage
Conditions
Initial trimming
Min
Typ
Max
Units
1.023
(–0.1%)
1.024
1.025
(+0.1%)
V
Temperature drift[44]
–
–
30
ppm/°C
Long term drift[44]
–
100
–
ppm/Khr
Thermal cycling drift (stability)[44]
–
100
–
ppm
Units
bits
Figure 11-28. Vref vs Temperature
Figure 11-29. Vref Long-term Drift
11.5.3 SAR ADC
Table 11-24. SAR ADC DC Specifications
Parameter
Description
Conditions
Min
–
–
Typ
–
–
Differential pair is formed using a
pair of neighboring GPIO.
–
–
Yes
–
–
–
VSSA
VSSA
70
70
–
–
–
–
–
–
–
–
–
–
Max
12
No of
GPIO
No of
GPIO/2
–
±0.1
±2
1
VDDA
VDDA
–
–
+2/–1.5
–
–
±1.2
LSB
–
–
±1.3
LSB
Resolution
Number of channels – single-ended
Number of channels – differential
Ge
VOS
IDD
PSRR
CMRR
INL
Monotonicity[44]
External reference
Gain error[45]
Input offset voltage
Current consumption[44]
Input voltage range – single-ended[44]
Input voltage range – differential[44]
Power supply rejection ratio[44]
Common mode rejection ratio
VDDA 1.71 to 5.5 V, 1 Msps, VREF
Integral non linearity[44]
1 to 5.5 V, bypassed at ExtRef pin
VDDA 2.0 to 3.6 V, 1 Msps, VREF 2
to VDDA, bypassed at ExtRef pin
VDDA 1.71 to 5.5 V, 500 ksps, VREF
1 to 5.5 V, bypassed at ExtRef pin
%
mV
mA
V
V
dB
dB
LSB
Notes
44. Based on device characterization (Not production tested).
45. For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential
mode.
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PSoC® 5LP: CY8C56LP Family
Datasheet
Table 11-24. SAR ADC DC Specifications (continued)
Parameter
Description
DNL
Differential non linearity[46]
RIN
Conditions
VDDA 1.71 to 5.5 V, 1 Msps, VREF
1 to 5.5 V, bypassed at ExtRef pin
VDDA 2.0 to 3.6 V, 1 Msps, VREF 2
to VDDA, bypassed at ExtRef pin
No missing codes
VDDA 1.71 to 5.5 V, 500 ksps, VREF
1 to 5.5 V, bypassed at ExtRef pin
No missing codes
Input resistance[46]
Figure 11-30. SAR ADC DNL vs Output Code,
Bypassed Internal Reference Mode
Min
–
Typ
–
Max
+2/–1
Units
LSB
–
–
1.7/–0.99
LSB
–
–
+2/–0.99
LSB
–
180
–
kΩ
Figure 11-31. SAR ADC INL vs Output Code,
Bypassed Internal Reference Mode
Figure 11-32. SAR ADC IDD vs sps, VDDA = 5 V, Continuous
Sample Mode, External Reference Mode
Note
46. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
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PSoC® 5LP: CY8C56LP Family
Datasheet
Table 11-25. SAR ADC AC Specifications[47]
Parameter
Description
Fclk
SAR clock frequency
Tc
Conversion time
Conditions
One conversion requires 18 SAR
clocks. Maximum sample rate is 1
Msps
Min
Typ
Max
Units
1
–
18
MHz
1
–
18
µs
Startup time
–
–
10
µs
SINAD
Signal-to-noise ratio
68
–
–
dB
THD
Total harmonic distortion
–
–
0.02
%
Figure 11-33. SAR ADC Noise Histogram, 1000 samples,
700 ksps, Internal Reference No Bypass, VIN = VREF/2
Figure 11-34. SAR ADC Noise Histogram, 1000
samples, 700 ksps, Internal Reference Bypassed, VIN =
VREF/2
Figure 11-35. SAR ADC Noise Histogram, 1000 samples,
700 ksps, External Reference, VIN = VREF/2
Note
47. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
Page 84 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
11.5.4 Analog Globals
Table 11-26. Analog Globals DC Specifications
Parameter
Rppag
Rppmuxbus
Description
Resistance pin-to-pin through
P2[4], AGL0, DSM INP, AGL1,
P2[5][48]
Resistance pin-to-pin through
P2[3], amuxbusL, P2[4][48]
Conditions
VDDA = 3.0 V
VDDA = 1.71 V
VDDA = 3.0 V
VDDA = 1.71 V
Min
–
–
Typ
1500
1200
Max
2200
1700
Units
Ω
Ω
–
–
700
600
1100
900
Ω
Ω
Min
106
Typ
–
Max
–
Units
dB
–
26
–
MHz
Min
–
Typ
Table 11-27. Analog Globals AC Specifications
Parameter
BWag
Description
Inter-pair crosstalk for analog
routes[49, 50]
Analog globals 3 db bandwidth[50]
Conditions
VDDA = 3.0 V, 25 °C
11.5.5 Comparator
Table 11-28. Comparator DC Specifications[51]
Parameter
VOS
VOS
VOS
TCVos
VHYST
VICM
CMRR
ICMP
Description
Input offset voltage in fast mode
Conditions
Factory trim, VDDA > 2.7 V,
VIN ≥ 0.5 V
Input offset voltage in slow mode Factory trim, Vin ≥ 0.5 V
Input offset voltage in fast mode
Custom trim
Input offset voltage in slow mode[51] Custom trim
Input offset voltage in ultra low
power mode
Temperature coefficient, input offset VCM = VDDA / 2, fast mode
voltage
VCM = VDDA / 2, slow mode
Hysteresis
Hysteresis enable mode
Input common mode voltage
High current / fast mode
Low current / slow mode
Ultra low power mode
Common mode rejection ratio
High current mode/fast mode
Low current mode/slow mode
Ultra low power mode
–
–
–
–
–
–
–
–
–
±12
Max
10
Units
mV
9
4
4
–
mV
mV
mV
mV
µV/°C
VSSA
VSSA
VSSA
63
15
10
–
–
–
–
–
–
–
50
–
–
6
85
20
32
VDDA
VDDA
VDDA –
1.15
–
400
100
–
Min
–
Typ
75
Max
110
Units
ns
–
155
200
ns
–
55
–
µs
mV
V
V
V
dB
µA
µA
µA
Table 11-29. Comparator AC Specifications[51]
Parameter
TRESP
Description
Conditions
Response time, high current mode 50 mV overdrive, measured
pin-to-pin
Response time, low current mode 50 mV overdrive, measured
pin-to-pin
Response time, ultra low power
50 mV overdrive, measured
mode
pin-to-pin
Notes
48. Based on device characterization (Not production tested).
49. This value is calculated, not measured.
50. Pin P6[4] to del-sig ADC input; calculated, not measured.
51. The recommended procedure for using a custom trim value for the on-chip comparators are found in the TRM.
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PSoC® 5LP: CY8C56LP Family
Datasheet
11.5.6 Current Digital-to-analog Converter (IDAC)
All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 9 for details). See the IDAC
component data sheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-30. IDAC DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
–
–
8
bits
Range = 2.04 mA, code = 255,
VDDA ≥ 2.7 V, Rload = 600 Ω
–
2.04
–
mA
Range = 2.04 mA, High mode,
code = 255, VDDA ≤ 2.7 V, Rload =
300 Ω
–
2.04
–
mA
Range = 255 µA, code = 255, Rload
= 600 Ω
–
255
–
µA
Range = 31.875 µA, code = 255,
Rload = 600 Ω
–
31.875
–
µA
–
–
Yes
Resolution
IOUT
Output current at code = 255
Monotonicity
Ezs
Zero scale error
Eg
Gain error
TC_Eg
INL
Temperature coefficient of gain
error
Integral nonlinearity
Range = 2.04 mA
–
0
±1
LSB
–
–
±2.5
%
Range = 255 µA
–
–
±2.5
%
Range = 31.875 µA
–
–
±3.5
%
Range = 2.04 mA
–
–
0.045
% / °C
Range = 255 µA
–
–
0.045
% / °C
Range = 31.875 µA
–
–
0.05
% / °C
Sink mode, range = 255 µA, Codes
8 – 255, Rload = 2.4 kΩ,
Cload = 15 pF
–
±0.9
±1
LSB
Source mode, range = 255 µA,
Codes 8 – 255, Rload = 2.4 kΩ,
Cload = 15 pF
–
±1.2
±1.6
LSB
Source mode, range = 31.875 µA,
Codes 8 - 255, Rload = 20 kΩ,
Cload = 15 pF[52]
–
±0.9
±2
LSB
Sink mode, range = 31.875 µA,
Codes 8 - 255, Rload = 20 kΩ,
Cload = 15 pF[52]
–
±0.9
±2
LSB
Source mode, range = 2.04 mA,
Codes 8 - 255, Rload = 600 Ω,
Cload = 15 pF[52]
–
±0.9
±2
LSB
Sink mode, range = 2.04 mA,
Codes 8 - 255, Rload = 600 Ω,
Cload = 15 pF[52]
–
±0.6
±1
LSB
Note
52. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
Page 86 of 120
PSoC® 5LP: CY8C56LP Family
Datasheet
Table 11-30. IDAC DC Specifications (continued)
Parameter
DNL
Description
Differential nonlinearity
Conditions
Min
Typ
Max
Units
Sink mode, range = 255 µA,
Rload = 2.4 kΩ, Cload = 15 pF
–
±0.3
±1
LSB
Source mode, range = 255 µA,
Rload = 2.4 kΩ, Cload = 15 pF
–
±0.3
±1
LSB
Source mode, range = 31.875 µA,
Rload = 20 kΩ, Cload = 15 pF[53]
–
±0.2
±1
LSB
Sink mode, range = 31.875 µA,
Rload = 20 kΩ, Cload = 15 pF[53]
–
±0.2
±1
LSB
Source mode, range = 2.0 4 mA,
Rload = 600 Ω, Cload = 15 pF[53]
–
±0.2
±1
LSB
Sink mode, range = 2.0 4 mA,
Rload = 600 Ω, Cload = 15 pF[53]
–
±0.2
±1
LSB
Vcompliance
Dropout voltage, source or sink
mode
Voltage headroom at max current,
Rload to VDDA or Rload to VSSA,
Vdiff from VDDA
1
–
–
V
IDD
Operating current, code = 0
Slow mode, source mode, range =
31.875 µA
–
44
100
µA
Slow mode, source mode, range =
255 µA,
–
33
100
µA
Slow mode, source mode, range =
2.04 mA
–
33
100
µA
Slow mode, sink mode, range =
31.875 µA
–
36
100
µA
Slow mode, sink mode, range =
255 µA
–
33
100
µA
Slow mode, sink mode, range =
2.04 mA
–
33
100
µA
Fast mode, source mode, range =
31.875 µA
–
310
500
µA
Fast mode, source mode, range =
255 µA
–
305
500
µA
Fast mode, source mode, range =
2.04 mA
–
305
500
µA
Fast mode, sink mode, range =
31.875 µA
–
310
500
µA
Fast mode, sink mode, range =
255 µA
–
300
500
µA
Fast mode, sink mode, range =
2.04 mA
–
300
500
µA
Note
53. Based on device characterization (Not production tested).
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Datasheet
Figure 11-36. IDAC INL vs Input Code, Range = 255 µA,
Source Mode
Figure 11-37. IDAC INL vs Input Code, Range = 255 µA, Sink
Mode
1.5
1
INL,, LSB
0.5
0
-0.5
-1
-1.5
0
32
64
96
128
160
192
224
256
Code, 8-bit
Figure 11-38. IDAC DNL vs Input Code, Range = 255 µA,
Source Mode
Figure 11-39. IDAC DNL vs Input Code, Range = 255 µA, Sink
Mode
Figure 11-40. IDAC INL vs Temperature, Range = 255 µA, Fast
Mode
Figure 11-41. IDAC DNL vs Temperature, Range = 255 µA,
Fast Mode
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Datasheet
Figure 11-42. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Source Mode
Figure 11-43. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Sink Mode
Figure 11-44. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Source Mode
Figure 11-45. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Sink Mode
Table 11-31. IDAC AC Specifications[54]
Parameter
Description
FDAC
Update rate
TSETTLE
Settling time to 0.5 LSB
Current noise
Conditions
Min
Typ
Max
Units
–
–
8
Msps
Range = 31.875 µA, full scale
transition, fast mode, 600 Ω 15-pF
load
–
–
125
ns
Range = 255 µA, full scale
transition, fast mode, 600 Ω 15-pF
load
–
–
125
ns
Range = 255 µA, source mode, fast
mode, Vdda = 5 V, 10 kHz
–
340
–
pA/sqrtHz
Note
54. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
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Datasheet
Figure 11-46. IDAC Step Response, Codes 0x40 - 0xC0,
255 µA Mode, Source Mode, Fast Mode, VDDA = 5 V
Figure 11-47. IDAC Glitch Response, Codes 0x7F - 0x80,
255 µA Mode, Source Mode, Fast Mode, VDDA = 5 V
Figure 11-48. IDAC PSRR vs Frequency
Figure 11-49. IDAC Current Noise, 255 µA Mode,
Source Mode, Fast Mode, VDDA = 5 V
100000
60
Current Noise is proportional to Scale * Code
50
pA
A/sqrtHz
PSRR, dB
P
10000
40
30
20
1000
100
10
0
0.1
1
10
100
1000
10
10000
0.01
Frequency, kHz
255 ȝA, code 0x7F
255 ȝA, code 0xFF
0.1
1
10
Frequency, kHz
Code 0xFF
100
1000
Code 0x40
11.5.7 Voltage Digital to Analog Converter (VDAC)
See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-32. VDAC DC Specifications
Parameter
Description
Conditions
Resolution
Min
Typ
Max
Units
–
8
–
bits
INL1
Integral nonlinearity
1 V scale
–
±2.1
±2.5
LSB
INL4
Integral nonlinearity[55]
4 V scale
–
±2.1
±2.5
LSB
DNL1
Differential nonlinearity
1 V scale
–
±0.3
±1
LSB
nonlinearity[55]
DNL4
Differential
4 V scale
–
±0.3
±1
LSB
Rout
Output resistance
1 V scale
–
4
–
kΩ
4 V scale
–
16
–
kΩ
VOUT
Output voltage range, code = 255
1 V scale
–
1.02
–
V
4 V scale, VDDA = 5 V
–
4.08
–
V
Note
55. Based on device characterization (Not production tested).
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Datasheet
Table 11-32. VDAC DC Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
Monotonicity
–
–
Yes
–
VOS
Zero scale error
–
0
±0.9
LSB
Eg
Gain error
1 V scale
–
–
±2.5
%
4 V scale
–
–
±2.5
%
TC_Eg
IDD
Temperature coefficient, gain error 1 V scale
–
–
0.03
%FSR / °C
4 V scale
–
–
0.03
%FSR / °C
Slow mode
–
–
100
µA
Fast mode
–
–
500
µA
Operating current[56]
Figure 11-50. VDAC INL vs Input Code, 1 V Mode
Figure 11-51. VDAC DNL vs Input Code, 1 V Mode
Figure 11-52. VDAC INL vs Temperature, 1 V Mode
Figure 11-53. VDAC DNL vs Temperature, 1 V Mode
Note
56. Based on device characterization (Not production tested).
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Datasheet
Figure 11-54. VDAC Full Scale Error vs Temperature, 1 V
Mode
Figure 11-55. VDAC Full Scale Error vs Temperature, 4 V
Mode
Figure 11-56. VDAC Operating Current vs Temperature, 1V
Mode, Slow Mode
Figure 11-57. VDAC Operating Current vs Temperature, 1 V
Mode, Fast Mode
Table 11-33. VDAC AC Specifications[57]
Parameter
Description
Min
Typ
Max
Units
1 V scale
Conditions
–
–
1000
ksps
4 V scale
–
–
250
ksps
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.8
3.2
µs
Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF
25%
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.7
3
µs
Range = 1 V, fast mode, VDDA =
5 V, 10 kHz
–
750
–
nV/sqrtHz
FDAC
Update rate
TsettleP
Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF
75%
TsettleN
Voltage noise
Note
57. Based on device characterization (Not production tested).
Document Number: 001-84935 Rev. *C
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Datasheet
Figure 11-58. VDAC Step Response, Codes 0x40 - 0xC0, 1 V
Mode, Fast Mode, VDDA = 5 V
Figure 11-59. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V
Mode, Fast Mode, VDDA = 5 V
1
0.8
Vou
ut, V
0.6
0.4
0.2
0
0
0.5
1
Time, μs
1.5
2
Figure 11-60. VDAC PSRR vs Frequency
Figure 11-61. VDAC Voltage Noise, 1 V Mode, Fast Mode,
VDDA = 5 V
100000
50
Voltage Noise is proportional to Scale * Code
10000
30
nV/sqrrtHz
PSRR, dB
P
40
20
10
1000
100
0
0.1
1
10
Frequency, kHz
4 V, code 0x7F
Document Number: 001-84935 Rev. *C
100
4 V, code 0xFF
1000
10
0.01
0.1
1
10
Frequency, kHz
Code 0xFF
100
1000
Code 0x40
Page 93 of 120
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Datasheet
11.5.8 Mixer
The mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full electrical specifications
and APIs.
Table 11-34. Mixer DC Specifications
Parameter
VOS
G
Description
Min
Typ
Max
Units
–
–
15
mV
Quiescent current
–
0.9
2
mA
Gain
–
0
–
dB
Min
Typ
Max
Units
–
–
4
MHz
Input offset voltage
Conditions
High power mode, VIN = 1.024 V,
VREF = 1.024 V
Table 11-35. Mixer AC Specifications[58]
Parameter
Description
Conditions
fLO
Local oscillator frequency
fin
Input signal frequency
Down mixer mode
–
–
14
MHz
fLO
Local oscillator frequency
Up mixer mode
–
–
1
MHz
fin
Input signal frequency
Up mixer mode
SR
Slew rate
Down mixer mode
–
–
1
MHz
3
–
–
V/µs
11.5.9 Transimpedance Amplifier
The TIA is created using a SC/CT analog block; see the TIA component datasheet in PSoC Creator for full electrical specifications
and APIs.
Table 11-36. Transimpedance Amplifier (TIA) DC Specifications
Parameter
VIOFF
Rconv
Description
Conditions
Min
Typ
Max
Units
–
–
10
mV
R = 20K; 40 pF load
–25
–
+35
%
R = 30K; 40 pF load
–25
–
+35
%
R = 40K; 40 pF load
–25
–
+35
%
R = 80K; 40 pF load
–25
–
+35
%
R = 120K; 40 pF load
–25
–
+35
%
R = 250K; 40 pF load
–25
–
+35
%
R= 500K; 40 pF load
–25
–
+35
%
R = 1M; 40 pF load
–25
–
+35
%
–
1.1
2
mA
Input offset voltage
Conversion
Quiescent
resistance[59]
current[58]
Table 11-37. Transimpedance Amplifier (TIA) AC Specifications[58]
Parameter
BW
Description
Input bandwidth (–3 dB)
Min
Typ
Max
Units
R = 20K; –40 pF load
Conditions
1200
–
–
kHz
R = 120K; –40 pF load
240
–
–
kHz
R = 1M; –40 pF load
25
–
–
kHz
Notes
58. Based on device characterization (Not production tested).
59. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component datasheets. External precision
resistors can also be used.
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Datasheet
11.5.10 Programmable Gain Amplifier
The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full electrical specifications
and APIs.
Unless otherwise specified, operating conditions are:
Operating temperature = 25 °C for typical values
Unless otherwise specified, all charts and graphs show typical values
Table 11-38. PGA DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Vin
Input voltage range
Power mode = minimum
Vssa
–
VDDA
V
Vos
Input offset voltage
Power mode = high,
gain = 1
–
–
10
mV
TCVos
Input offset voltage drift
with temperature
Power mode = high,
gain = 1
–
–
±30
µV/°C
Ge1
Gain error, gain = 1
–
–
±0.15
%
Ge16
Gain error, gain = 16
–
–
±2.5
%
Ge50
Gain error, gain = 50
–
–
±5
%
Vonl
DC output nonlinearity
–
–
±0.01
% of
FSR
Gain = 1
Cin
Input capacitance
–
–
7
pF
Voh
Output voltage swing
Power mode = high,
gain = 1, Rload = 100 kΩ
to VDDA / 2
VDDA – 0.15
–
–
V
Vol
Output voltage swing
Power mode = high,
gain = 1, Rload = 100 kΩ
to VDDA / 2
–
–
VSSA + 0.15
V
Vsrc
Output voltage under load
Iload = 250 µA, VDDA ≥
2.7 V, power mode = high
–
–
300
mV
Idd
Operating current[60]
Power mode = high
–
1.5
1.65
mA
PSRR
Power supply rejection
ratio
48
–
–
dB
Figure 11-62. PGA Voffset Histogram, 4096 samples/
1024 parts
Note
60. Based on device characterization (Not production tested).
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Datasheet
Table 11-39. PGA AC Specifications[61]
Parameter
BW1
Description
–3 dB bandwidth
SR1
Slew rate
en
Input noise density
Conditions
Power mode = high,
gain = 1, input = 100 mV
peak-to-peak
Power mode = high,
gain = 1, 20% to 80%
Power mode = high,
VDDA = 5 V, at 100 kHz
Figure 11-63. Bandwidth vs. Temperature, at Different Gain
Settings, Power Mode = High
Typ
8
Max
–
Units
MHz
3
–
–
V/µs
–
43
–
nV/sqrtHz
Figure 11-64. Noise vs. Frequency, Vdda = 5 V,
Power Mode = High
1000
nV/sq
qrtHz
10
BW, MHz
Min
6.7
1
100
0.1
-40
-20
0
20
40
60
Gain = 24
10
0.01
Temperature, °C
Gain = 1
80
0.1
1
10
Frequency, kHz
Gain = 48
100
1000
11.5.11 Temperature Sensor
Table 11-40. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +85 °C
Min
–
Typ
±5
Max
–
Units
°C
Min
–
Typ
81
Max
–
Units
μA
–
2
260
–
–
5
µA
V
–
–
9.1 × VDDA
500
–
5000
mV
pF
–
355
–
–
20
710
mV
µA
11.5.12 LCD Direct Drive
Table 11-41. LCD Direct Drive DC Specifications[61]
Parameter
Description
ICC
LCD Block (no glass)
ICC_SEG
VBIAS
IOUT
Conditions
Device sleep mode with wakeup at
400 Hz rate to refresh LCD, bus,
clock = 3MHz, Vddio = Vdda = 3 V, 8
commons, 16 segments, 1/5 duty
cycle, 40 Hz frame rate, no glass
connected
Current per segment driver
Strong drive mode
LCD bias range (VBIAS refers to the main VDDA ≥ 3 V and VDDA ≥ VBIAS
output voltage(V0) of LCD DAC)
LCD bias step size
VDDA ≥ 3 V and VDDA ≥ VBIAS
LCD capacitance per segment/
Drivers may be combined
common driver
Maximum segment DC offset
Vdda ≥ 3V and Vdda ≥ Vbias
Output drive current per segment driver) VDDIO = 5.5 V, strong drive mode
Note
61. Based on device characterization (Not production tested).
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Datasheet
Table 11-42. LCD Direct Drive AC Specifications[62]
Parameter
Description
fLCD
LCD frame rate
Conditions
Min
10
Typ
50
Max
150
Units
Hz
11.6 Digital Peripherals
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.6.1 Timer
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for
more information, see the Timer component datasheet in PSoC Creator.
Table 11-43. Timer DC Specifications[62]
Parameter
Description
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
48 MHz
–
260
–
µA
67 MHz
–
350
–
µA
Min
Typ
Max
Units
Operating frequency
DC
–
67.01
MHz
Capture pulse width (Internal)[63]
15
–
–
ns
Capture pulse width (external)
30
–
–
ns
Timer resolution[63]
15
–
–
ns
Table 11-44. Timer AC Specifications[62]
Parameter
Description
Enable pulse
Conditions
width[63]
Enable pulse width (external)
15
–
–
ns
30
–
–
ns
Reset pulse width[63]
15
–
–
ns
Reset pulse width (external)
30
–
–
ns
11.6.2 Counter
The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in
UDBs; for more information, see the Counter component datasheet in PSoC Creator.
Table 11-45. Counter DC Specifications[62]
Parameter
Description
Block current consumption
Conditions
Min
Typ
Max
Units
16-bit counter, at listed input clock
frequency
–
–
–
µA
–
15
–
µA
3 MHz
12 MHz
–
60
–
µA
48 MHz
–
260
–
µA
67 MHz
–
350
–
µA
Notes
62. Based on device characterization (Not production tested).
63. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock.
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Datasheet
Table 11-46. Counter AC Specifications[64]
Parameter
Description
Conditions
Min
Typ
Max
Units
Operating frequency
DC
–
67.01
MHz
Capture pulse[65]
15
–
–
ns
Resolution
15
–
–
ns
Pulse width[65]
15
–
–
ns
Pulse width (external)
30
Enable pulse width[65]
15
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width[65]
15
–
–
ns
Reset pulse width (external)
30
–
–
ns
[65]
ns
11.6.3 Pulse Width Modulation
The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented
in UDBs; for more information, see the PWM component datasheet in PSoC Creator.
Table 11-47. PWM DC Specifications[64]
Parameter
Description
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
3 MHz
Min
Typ
Max
Units
–
–
–
µA
–
15
–
µA
12 MHz
–
60
–
µA
48 MHz
–
260
–
µA
67 MHz
–
350
–
µA
Min
Typ
Max
Units
DC
–
67.01
MHz
Table 11-48. PWM AC Specifications[64]
Parameter
Description
Conditions
Operating frequency
width[65]
15
–
–
ns
Pulse width (external)
30
–
–
ns
Pulse
Kill pulse width[65]
15
–
–
ns
Kill pulse width (external)
30
–
–
ns
Enable pulse width[65]
15
–
–
ns
Enable pulse width (external)
30
–
–
ns
Reset pulse width[65]
15
–
–
ns
Reset pulse width (external)
30
–
–
ns
Min
Typ
Max
Units
11.6.4 I2C
Table 11-49. Fixed I2C DC Specifications[64]
Parameter
Description
Block current consumption
Conditions
Enabled, configured for 100 kbps
–
–
250
µA
Enabled, configured for 400 kbps
–
–
260
µA
Notes
64. Based on device characterization (Not production tested).
65. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock.
Document Number: 001-84935 Rev. *C
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Datasheet
Table 11-50. Fixed I2C AC Specifications[68]
Parameter
Description
Conditions
Min
–
Conditions
Min
–
Conditions
Min
Typ
Max
Units
–
–
1
Mbit
Bit rate
Typ
–
Max
1
Units
Mbps
11.6.5 Controller Area Network
Table 11-55. CAN DC Specifications[66, 67]
Parameter
Description
IDD
Block current consumption
Typ
–
Max
200
Units
µA
Table 11-56. CAN AC Specifications[66, 67]
Parameter
Description
Bit rate
Minimum 8 MHz clock
11.6.6 Digital Filter Block
Table 11-1. DFB DC Specifications[68]
Parameter
Description
DFB operating current
Conditions
64-tap FIR at FDFB
500 kHz (6.7 ksps)
1 MHz (13.4 ksps)
10 MHz (134 ksps)
48 MHz (644 ksps)
67 MHz (900 ksps)
Min
Typ
Max
Units
–
–
–
–
–
0.16
0.33
3.3
15.7
21.8
0.27
0.53
5.3
25.5
35.6
mA
mA
mA
mA
mA
Conditions
Min
DC
Typ
–
Max
67.01
Units
MHz
Table 11-2. DFB AC Specifications[68]
Parameter
FDFB
Description
DFB operating frequency
Notes
66. Based on device characterization (Not production tested).
67. Refer to ISO 11898 specification for details.
Document Number: 001-84935 Rev. *C
Page 99 of 120
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Datasheet
11.6.7 USB
Table 11-3. USB DC Specifications
Parameter
VUSB_5
Description
Device supply for USB operation
Conditions
USB configured, USB regulator
enabled
USB configured, USB regulator
VUSB_3.3
bypassed
VUSB_3
USB configured, USB regulator
bypassed[68]
VDDD = 5 V, FCPU = 1.5 MHz
IUSB_Configured Device supply current in device
active mode, bus clock and IMO = VDDD = 3.3 V, FCPU = 1.5 MHz
24 MHz
VDDD = 5 V, connected to USB
IUSB_Suspended Device supply current in device
sleep mode
host, PICU configured to wake on
USB resume signal
VDDD = 5 V, disconnected from
USB host
VDDD = 3.3 V, connected to USB
host, PICU configured to wake on
USB resume signal
VDDD = 3.3 V, disconnected from
USB host
Min
4.35
Typ
–
Max
5.25
Units
V
3.15
–
3.6
V
2.85
–
3.6
V
–
–
10
8
–
–
mA
mA
–
0.5
–
mA
–
0.3
–
mA
–
0.5
–
mA
–
0.3
–
mA
Note
68. Rise/fall time matching (TR) not guaranteed, see Table 11-15 on page 76.
Document Number: 001-84935 Rev. *C
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Datasheet
11.6.8 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-4. UDB AC Specifications[69]
Parameter
Description
Conditions
Min
Typ
Max
Units
FMAX_TIMER Maximum frequency of 16-bit timer in
a UDB pair
–
–
67.01
MHz
FMAX_ADDER Maximum frequency of 16-bit adder in
a UDB pair
–
–
67.01
MHz
–
–
67.01
MHz
–
–
67.01
MHz
Datapath Performance
FMAX_CRC
Maximum frequency of 16-bit
CRC/PRS in a UDB pair
PLD Performance
FMAX_PLD
Maximum frequency of a two-pass
PLD function in a UDB pair
Clock to Output Performance
tCLK_OUT
Propagation delay for clock in to data 25 °C, VDDD ≥ 2.7 V
out, see Figure 11-57.
–
20
25
ns
tCLK_OUT
Propagation delay for clock in to data Worst-case placement, routing,
out, see Figure 11-57.
and pin selection
–
–
55
ns
Figure 11-57. Clock to Output Performance
Note
69. Based on device characterization (Not production tested).
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Datasheet
11.7 Memory
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.7.1 Flash
Table 11-5. Flash DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
1.71
–
5.5
V
Table 11-6. Flash AC Specifications
Min
Typ
Max
Units
TWRITE
Parameter
Row write time (erase + program)
–
15
20
ms
TERASE
Row erase time
–
10
13
ms
Row program time
–
5
7
ms
Bulk erase time (256 KB)
–
–
140
ms
Sector erase time (16 KB)
–
–
15
ms
TBULK
TPROG
Description
Conditions
overhead[70]
Total device programming time
No
–
5
7.5
seconds
Flash data retention time, retention
period measured from last erase cycle
Average ambient temp.
TA ≤ 55 °C, 100 K erase/program
cycles
20
–
–
years
Average ambient temp.
TA ≤ 85 °C, 10 K erase/program
cycles
10
–
–
11.7.2 EEPROM
Table 11-7. EEPROM DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
1.71
–
5.5
V
Min
Typ
Max
Units
Single row erase/write cycle time
–
10
20
ms
EEPROM data retention time, retention Average ambient temp, TA ≤ 25 °C,
period measured from last erase cycle 1M erase/program cycles
20
–
–
years
Average ambient temp, TA ≤ 55 °C,
100 K erase/program cycles
20
–
–
Average ambient temp. TA ≤ 85 °C,
10 K erase/program cycles
10
–
–
Erase and program voltage
Table 11-8. EEPROM AC Specifications
Parameter
TWRITE
Description
Conditions
Note
70. See PSoC 5 Device Programming Specifications for a description of a low-overhead method of programming PSoC 5 flash.
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11.7.3 Nonvolatile Latches (NVL)
Table 11-9. NVL DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
1.71
–
5.5
V
Table 11-10. NVL AC Specifications
Parameter
Description
NVL endurance
NVL data retention time
Min
Typ
Max
Units
Programmed at 25 °C
Conditions
1K
–
–
program/
erase
cycles
Programmed at 0 °C to 70 °C
100
–
–
program/
erase
cycles
Average ambient temp. TA ≤ 55 °C
20
–
–
years
Average ambient temp. TA ≤ 85 °C
10
–
–
years
Conditions
Min
Typ
Max
Units
1.2
–
–
V
Min
Typ
Max
Units
DC
–
67.01
MHz
11.7.4 SRAM
Table 11-11. SRAM DC Specifications
Parameter
VSRAM
Description
SRAM retention
voltage[71]
Table 11-12. SRAM AC Specifications
Parameter
FSRAM
Description
SRAM operating frequency
Conditions
Note
71. Based on device characterization (Not production tested).
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11.7.5 External Memory Interface
Figure 11-58. Asynchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
Bus Clock
EM_Addr
EM_CE
EM_WE
EM_OE
Twr_setup
Trd_hold
Trd_setup
EM_Data
Write Cycle
Read Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Table 11-65. Asynchronous Write and Read Timing Specifications[72]
Parameter
Description
[73]
Fbus_clock
Bus clock frequency
period[74]
Tbus_clock
Bus clock
Twr_Setup
Time from EM_data valid to rising edge of
EM_WE and EM_CE
Trd_setup
Trd_hold
Conditions
Min
Typ
Max
Units
–
–
33
MHz
30.3
–
–
ns
Tbus_clock – 10
–
–
ns
Time that EM_data must be valid before rising
edge of EM_OE
5
–
–
ns
Time that EM_data must be valid after rising
edge of EM_OE
5
–
–
ns
Notes
72. Based on device characterization (Not production tested).
73. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 69.
74. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
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Figure 11-67. Synchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
Bus Clock
EM_Clock
EM_Addr
EM_CE
EM_ADSC
EM_WE
EM_OE
Twr_setup
Trd_hold
Trd_setup
EM_Data
Write Cycle
Read Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Table 11-66. Synchronous Write and Read Timing Specifications[75]
Parameter
Description
[76]
Conditions
Min
Typ
Max
Units
Fbus_clock
Bus clock frequency
–
–
33
MHz
Tbus_clock
Bus clock period[77]
30.3
–
–
ns
Twr_Setup
Time from EM_data valid to rising edge of
EM_Clock
Tbus_clock – 10
–
–
ns
Trd_setup
Time that EM_data must be valid before rising
edge of EM_OE
5
–
–
ns
Trd_hold
Time that EM_data must be valid after rising
edge of EM_OE
5
–
–
ns
Notes
75. Based on device characterization (Not production tested).
76. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 69.
77. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
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11.8 PSoC System Resources
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.8.1 POR with Brown Out
For brown out detect in regulated mode, VDDD and VDDA must be ≥ 2.0 V. Brown out detect is not available in externally regulated
mode.
Table 11-67. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications
Parameter
Description
PRESR
Rising trip voltage
PRESF
Falling trip voltage
Conditions
Factory trim
Min
Typ
Max
Units
1.64
–
1.68
V
1.62
–
1.66
V
Min
Typ
Max
Units
Power On Reset (POR) with Brown Out AC Specifications[78]
Parameter
PRES_TR[79]
Description
Conditions
Response time
–
–
0.5
µs
–
5
–
V/sec
Min
Typ
Max
Units
LVI_A/D_SEL[3:0] = 0000b
1.68
1.73
1.77
V
LVI_A/D_SEL[3:0] = 0001b
1.89
1.95
2.01
V
LVI_A/D_SEL[3:0] = 0010b
2.14
2.20
2.27
V
VDDD/VDDA droop rate
Sleep mode
11.8.2 Voltage Monitors
Table 11-68. Voltage Monitors DC Specifications
Parameter
LVI
Description
Conditions
Trip voltage
LVI_A/D_SEL[3:0] = 0011b
2.38
2.45
2.53
V
LVI_A/D_SEL[3:0] = 0100b
2.62
2.71
2.79
V
LVI_A/D_SEL[3:0] = 0101b
2.87
2.95
3.04
V
LVI_A/D_SEL[3:0] = 0110b
3.11
3.21
3.31
V
LVI_A/D_SEL[3:0] = 0111b
3.35
3.46
3.56
V
LVI_A/D_SEL[3:0] = 1000b
3.59
3.70
3.81
V
LVI_A/D_SEL[3:0] = 1001b
3.84
3.95
4.07
V
LVI_A/D_SEL[3:0] = 1010b
4.08
4.20
4.33
V
LVI_A/D_SEL[3:0] = 1011b
4.32
4.45
4.59
V
LVI_A/D_SEL[3:0] = 1100b
4.56
4.70
4.84
V
LVI_A/D_SEL[3:0] = 1101b
4.83
4.98
5.13
V
LVI_A/D_SEL[3:0] = 1110b
5.05
5.21
5.37
V
LVI_A/D_SEL[3:0] = 1111b
HVI
Trip voltage
5.30
5.47
5.63
V
5.57
5.75
5.92
V
Min
Typ
Max
Units
–
–
1
µs
Voltage Monitors AC Specifications
Parameter
LVI_tr[79]
Description
Response time
Conditions
Notes
78. Based on device characterization (Not production tested).
79. This value is calculated, not measured.
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Datasheet
11.8.3 Interrupt Controller
Table 11-69. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Delay from interrupt signal input to ISR
code execution from main line code[80]
–
–
12
Tcy CPU
Delay from interrupt signal input to ISR
code execution from ISR code
(tail-chaining)[80]
–
–
6
Tcy CPU
11.8.4 JTAG Interface
Figure 11-68. JTAG Interface Timing
(1/f_TCK)
TCK
T_TDI_setup
T_TDI_hold
TDI
T_TDO_valid
T_TDO_hold
TDO
T_TMS_setup
T_TMS_hold
TMS
Table 11-70. JTAG Interface AC Specifications[81]
Parameter
f_TCK
Description
TCK frequency
Conditions
3.3 V ≤ VDDD ≤ 5 V
1.71 V ≤ VDDD < 3.3 V
T_TDI_setup
TDI setup before TCK high
T_TMS_setup
TMS setup before TCK high
T_TDI_hold
TDI, TMS hold after TCK high
T = 1/f_TCK max
Min
Typ
Max
Units
–
–
12[82]
MHz
–
–
7[82]
MHz
(T/10) – 5
–
–
ns
T/4
–
–
T/4
–
–
T_TDO_valid
TCK low to TDO valid
T = 1/f_TCK max
–
–
2T/5
T_TDO_hold
TDO hold after TCK high
T = 1/f_TCK max
T/4
–
–
T_nTRST
Minimum nTRST pulse width
f_TCK = 2 MHz
8
–
–
ns
Notes
80. ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU.
81. Based on device characterization (Not production tested).
82. f_TCK must also be no more than 1/3 CPU clock frequency.
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11.8.5 SWD Interface
Figure 11-69. SWD Interface Timing
(1/f_S W D C K )
SW DCK
T_SW D I_setup T_S W D I_hold
S W D IO
(P S oC input)
T_S W D O _valid
T_S W D O _hold
S W D IO
(P S oC output)
Table 11-71. SWD Interface AC Specifications[83]
Parameter
Description
Conditions
Min
Typ
Max
Units
MHz
3.3 V ≤ VDDD ≤ 5 V
–
–
12[84]
1.71 V ≤ VDDD < 3.3 V
–
–
7[84]
MHz
–
–
5.5[84]
MHz
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T/4
–
–
T_SWDI_hold
T/4
–
–
f_SWDCK
SWDCLK frequency
1.71 V ≤ VDDD < 3.3 V, SWD over
USBIO pins
SWDIO input hold after SWDCK high
T_SWDO_valid SWDCK high to SWDIO output
T = 1/f_SWDCK max
T = 1/f_SWDCK max
–
–
T/2
T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max
1
–
–
ns
Min
Typ
Max
Units
MHz
Mbit
11.8.6 TPIU Interface
Table 11-72. TPIU Interface AC Specifications[83]
Parameter
Description
Conditions
TRACEPORT (TRACECLK) frequency
–
–
33[85]
SWV bit rate
–
–
33[85]
Notes
83. Based on device characterization (Not production tested).
84. f_SWDCK must also be no more than 1/3 CPU clock frequency.
85. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see Table 11-10 on page 70.
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Datasheet
11.9 Clocking
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. Unless otherwise specified, all charts and graphs show typical values.
11.9.1 Internal Main Oscillator
Table 11-73. IMO DC Specifications[86]
Parameter
Description
Conditions
Min
Typ
Max
Units
62.6 MHz
–
–
600
µA
48 MHz
–
–
500
µA
–
–
500
µA
–
–
300
µA
Supply current
Icc_imo
24 MHz – USB mode
24 MHz – non USB mode
With oscillator locking to USB bus
12 MHz
–
–
200
µA
6 MHz
–
–
180
µA
3 MHz
–
–
150
µA
Figure 11-70. IMO Current vs. Frequency
Note
86. Based on device characterization (Not production tested).
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Datasheet
Table 11-74. IMO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
62.6 MHz
–7
–
7
%
48 MHz
–5
–
5
%
24 MHz – Non USB mode
–4
–
4
%
IMO frequency stability (with factory trim)
FIMO
24 MHz – USB mode
–0.25
–
0.25
%
12 MHz
–3
–
3
%
6 MHz
–2
–
2
%
3 MHz
–1
–
1
%
–
–
13
µs
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
1.6
–
ns
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
12
–
ns
Tstart_imo Startup
time[87]
With oscillator locking to USB bus
From enable (during normal system
operation)
Jitter (peak to peak)[87]
Jp–p
Jitter (long term)[87]
Jperiod
Figure 11-71. IMO Frequency Variation vs. Temperature
Figure 11-72. IMO Frequency Variation vs. VCC
Note
87. Based on device characterization (Not production tested).
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Datasheet
11.9.2 Internal Low-Speed Oscillator
Table 11-75. ILO DC Specifications
Parameter
Description
Operating current
Conditions
[88]
Min
Typ
Max
Units
FOUT = 1 kHz
–
–
1.7
µA
FOUT = 33 kHz
–
–
2.6
µA
FOUT = 100 kHz
–
–
2.6
µA
Power down mode
–
–
15
nA
Min
Typ
Max
Units
–
–
2
ms
100 kHz
45
100
200
kHz
1 kHz
0.5
1
2
kHz
ICC
Leakage current[88]
Table 11-76. ILO AC Specifications[89]
Parameter
Tstart_ilo
Description
Conditions
Startup time, all frequencies
Turbo mode
ILO frequencies
FILO
Figure 11-74. ILO Frequency Variation vs. VDD
50
20
25
10
% Variiation
% Variiation
Figure 11-73. ILO Frequency Variation vs. Temperature
0
100 kHz
-25
1 kHz
-50
-20
0
20
40
60
Temperature, °C
100 kHz
-10
1 kHz
-40
0
80
-20
1.5
2.5
3.5
4.5
5.5
VDDD, V
Notes
88. This value is calculated, not measured.
89. Based on device characterization (Not production tested).
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11.9.3 MHz External Crystal Oscillator
For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and
PSoC 5 External Oscillators.
Table 11-77. MHzECO AC Specifications
Parameter
F
Description
Conditions
Crystal frequency range
Min
Typ
Max
Units
4
–
25
MHz
Min
Typ
Max
Units
–
0.25
1.0
µA
–
–
1
µW
Min
Typ
Max
Units
–
32.768
–
kHz
–
1
–
s
Min
Typ
Max
Units
11.9.4 kHz External Crystal Oscillator
Table 11-78. kHzECO DC Specifications[90]
Parameter
Description
ICC
Operating current
DL
Drive level
Conditions
Low power mode; CL = 6 pF
Table 11-79. kHzECO AC Specifications[90]
Parameter
Description
F
Frequency
TON
Startup time
Conditions
High power mode
11.9.5 External Clock Reference
Table 11-80. External Clock Reference AC Specifications[90]
Parameter
Description
Conditions
External frequency range
0
–
33
MHz
Input duty cycle range
Measured at VDDIO/2
30
50
70
%
Input edge rate
VIL to VIH
0.5
–
–
V/ns
Min
Typ
Max
Units
In = 3 MHz, Out = 67 MHz
–
400
–
µA
In = 3 MHz, Out = 24 MHz
–
200
–
µA
Min
Typ
Max
Units
1
–
48
MHz
1
–
3
MHz
11.9.6 Phase–Locked Loop
Table 11-81. PLL DC Specifications
Parameter
IDD
Description
PLL operating current
Conditions
Table 11-82. PLL AC Specifications
Parameter
Fpllin
Description
PLL input
PLL intermediate frequency[92]
Fpllout
Conditions
frequency[91]
Output of prescaler
PLL output frequency[91]
24
–
67
MHz
Lock time at startup
–
–
250
µs
(rms)[90]
–
–
250
ps
Jperiod–rms Jitter
Notes
90. Based on device characterization (Not production tested).
91. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
92. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
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12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C56LP device includes: up to 256K flash, 64K SRAM, 2K EEPROM, a
precision on–chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, JTAG/SWD programming and debug,
external memory interface, boost, and more. In addition to these features, the flexible UDBs and analog subsection support a wide
range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the
components required by your application. All CY8C56LP derivatives incorporate device and flash security in user-selectable security
levels; see the TRM for details.
Table 12-1. CY8C56LP Family with ARM Cortex-M3 CPU
I/O[95]
Package
SIO
USBIO
2x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
–
72
62
8
2
100-TQFP
0x2E10A069
2x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
✔
72
62
8
2
100-TQFP
0x2E10D069
CY8C5668LTI-LP014
67 256 64 2
✔
2x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
–
48
38
8
2
68-QFN
0x2E10E069
FS USB
✔
✔
DFB
67 256 64 2
67 256 64 2
DAC
CY8C5668AXI-LP010
CY8C5668AXI-LP013
ADCs
GPIO
JTAG ID[96]
Total I/O
CAN 2.0b
16-bit Timer/PWM
UDBs[94]
CapSense
SC/CT Analog Blocks[93]
Opamps
Digital
Comparators
LCD Segment Drive
Analog
EEPROM (KB)
SRAM (KB)
Flash (KB)
Part Number
CPU Speed (MHz)
MCU Core
CY8C5667AXI-LP006
67 128 32 2
✔
2x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
–
72
62
8
2
100-TQFP
0x2E106069
CY8C5667LTI-LP008
67 128 32 2
✔
2x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
–
48
38
8
2
68-QFN
0x2E108069
CY8C5667LTI-LP009
67 128 32 2
✔
2x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
✔
48
38
8
2
68-QFN
0x2E109069
CY8C5666AXI-LP001
67
64 16 2
✔ 12-bit Del-Sig,
1x12-bit SAR
4
4 4 4 ✔ ✔ 20
4
–
–
70
62
8
0
100-TQFP
0x2E101069
CY8C5666AXI-LP004
67
64 16 2
✔ 12-bit Del-Sig,
1x12-bit SAR
4
4 4 4 ✔ ✔ 20
4
✔
–
72
62
8
2
100-TQFP
0x2E104069
CY8C5666LTI-LP005
67
64 16 2
✔ 12-bit Del-Sig,
1x12-bit SAR
4
4 4 4 ✔ ✔ 20
4
✔
–
48
38
8
2
68-QFN
0x2E105069
CY8C5667AXI-LP040
67 128 32 2
✔ 12-bit Del-Sig,
1x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
–
72
62
8
2
100-TQFP
0x2E128069
CY8C5668AXI-LP034
67 256 64 2
✔ 12-bit Del-Sig,
1x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
–
72
62
8
2
100-TQFP
0x2E122069
CY8C5667LTI-LP041
67 128 32 2
✔ 12-bit Del-Sig,
1x12-bit SAR
4
4 4 4 ✔ ✔ 24
4
✔
–
48
38
8
2
68-QFN
0x2E129069
Notes
93. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 35 for more information on how analog blocks
can be used.
94. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 35 for more information on how UDBs can be used.
95. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 28 for details on the functionality of each of
these types of I/O.
96. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-84935 Rev. *C
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Datasheet
12.1 Part Numbering Conventions
PSoC 5LP devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9,
A, B, …, Z) unless stated otherwise.
CY8Cabcdefg-LPxxx
a: Architecture
3: PSoC 3
5: PSoC 5
b: Family group within architecture
2: CY8C52LP family
4: CY8C54LP family
6: CY8C56LP family
8: CY8C58LP family
c: Speed grade
6: 67 MHz
d: Flash capacity
5: 32 KB
6: 64 KB
7: 128 KB
8: 256 KB
ef: Package code
Two character alphanumeric
AX: TQFP
LT: QFN
PV: SSOP
g: Temperature range
C: commercial
I: industrial
A: automotive
xxx: Peripheral set
Three character numeric
No meaning is associated with these three characters
Examples
CY8C
5 6 6 8 A X/PV I - LPx x x
Cypress Prefix
5: PSoC 5
6: CY8C56LP Family
Architecture
Family Group within Architecture
6: 67 MHz
Speed Grade
8: 256 KB
Flash Capacity
AX: TQFP, PV: SSOP
Package Code
I: Industrial
Temperature Range
Peripheral Set
All devices in the PSoC 5LP CY8C56LP family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to
lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity.
Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of
life” requirements.
Document Number: 001-84935 Rev. *C
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Datasheet
13. Packaging
Table 13-1. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
–
100
°C
TJA
Package θJA (68-pin QFN)
–
15
–
°C/Watt
TJA
Package θJA (100-pin TQFP)
–
34
–
°C/Watt
TJC
Package θJC (68-pin QFN)
–
13
–
°C/Watt
TJC
Package θJC (100-pin TQFP)
–
10
–
°C/Watt
Table 13-2. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at
Peak Temperature
68-pin QFN
260 °C
30 seconds
100-pin TQFP
260 °C
30 seconds
Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
68-pin QFN
MSL 3
100-pin TQFP
MSL 3
Document Number: 001-84935 Rev. *C
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Datasheet
Figure 13-1. 68-pin QFN 8 × 8 with 0.4 mm Pitch Package Outline (Sawn Version)
001-09618 *E
Figure 13-2. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline
51-85048 *G
Document Number: 001-84935 Rev. *C
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Datasheet
Table 14-1. Acronyms Used in this Document (continued)
14. Acronyms
Acronym
Table 14-1. Acronyms Used in this Document
Acronym
Description
Description
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
IC
integrated circuit
ALU
arithmetic logic unit
IDAC
current DAC, see also DAC, VDAC
AMUXBUS
analog multiplexer bus
IDE
integrated development environment
API
application programming interface
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
CMRR
2C,
I
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
common-mode rejection ratio
IPOR
initial power-on reset
CPU
central processing unit
IPSR
interrupt program status register
CRC
cyclic redundancy check, an error-checking
protocol
IRQ
interrupt request
DAC
digital-to-analog converter, see also IDAC, VDAC
ITM
instrumentation trace macrocell
DFB
digital filter block
LCD
liquid crystal display
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DNU
do not use
LVD
low-voltage detect, see also LVI
DR
port write data registers
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
Document Number: 001-84935 Rev. *C
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
Page 117 of 120
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Datasheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PHUB
peripheral hub
SOF
start of frame
PHY
physical layer
SPI
PICU
port interrupt control unit
Serial Peripheral Interface, a communications
protocol
PLA
programmable logic array
SR
slew rate
PLD
programmable logic device, see also PAL
SRAM
static random access memory
PLL
phase-locked loop
SRES
software reset
PMDD
package material declaration datasheet
SWD
serial wire debug, a test protocol
POR
power-on reset
SWV
single-wire viewer
PRES
precise low-voltage reset
TD
transaction descriptor, see also DMA
PRS
pseudo random sequence
THD
total harmonic distortion
PS
port read data register
TIA
transimpedance amplifier
PSoC®
Programmable System-on-Chip™
TRM
technical reference manual
PSRR
power supply rejection ratio
TTL
transistor-transistor logic
PWM
pulse-width modulator
TX
transmit
RAM
random-access memory
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
universal digital block
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
RX
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
remote transmission request
VDAC
voltage DAC, see also DAC, IDAC
receive
WDT
watchdog timer
SAR
successive approximation register
WOL
write once latch, see also NVL
SC/CT
switched capacitor/continuous time
WRES
watchdog timer reset
2C
serial clock
SCL
I
SDA
I2C serial data
S/H
sample and hold
SIO
special input/output, GPIO with advanced
features. See GPIO.
SNR
signal-to-noise ratio
SOC
start of conversion
Document Number: 001-84935 Rev. *C
XRES
external reset I/O pin
XTAL
crystal
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 5 Registers TRM
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PSoC® 5LP: CY8C56LP Family
Datasheet
16. Document Conventions
16.1 Units of Measure
Table 16-1. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibels
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohours
kHz
kilohertz
kΩ
kilohms
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
MΩ
megaohms
Msps
megasamples per second
µA
microamperes
µF
microfarads
µH
microhenrys
µs
microseconds
µV
microvolts
µW
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts
Ω
ohms
pF
picofarads
ppm
parts per million
ps
picoseconds
s
seconds
sps
samples per second
sqrtHz
square root of hertz
V
volts
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Datasheet
17. Revision History
Description Title: PSoC® 5LP: CY8C56LP Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-84935
Revision
ECN
Submission
Date
Orig. of
Change
**
3825653
12/07/2012
MKEA
Datasheet for new CY8C56LP family.
*A
3897878
02/07/2013
MKEA
Removed Preliminary status.
Updated characterization footnotes in Electrical Specifications.
Changed number of opamps in Ordering Information
Updated conditions for SAR ADC INL and DNL specifications in Table 11-24
Updated Table 11-76 (ILO AC Specifications).
Changed “UDB Configuration" to "UDB Working Registers” in Table 5-5.
Removed references to CAN.
Updated VIDAC INL spec.
*B
3902085
02/12/2013
MKEA
Changed Hibernate wakeup time from 125 µs to 200 µs in Table 6-3 and Table 11-3.
*C
3917994
01/08/2013
MKEA
Added Controller Area Network (CAN) content.
Added CY8C5667AXI-LP040, CY8C5668AXI-LP034, and CY8C5667LTI-LP041
parts in Ordering Information.
Description of Change
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
Clocks & Buffers
psoc.cypress.com/solutions
cypress.com/go/clocks
Interface
PSoC 1 | PSoC 3 | PSoC 5LP
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-84935 Rev. *C
®
®
®
®
Revised March 8, 2013
®
Page 120 of 120
CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.