Cirrus CS42448-CQZR 108 db, 192 khz 6-in, 8-out codec Datasheet

CS42448
108 dB, 192 kHz 6-in, 8-out CODEC
FEATURES
GENERAL DESCRIPTION
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The CS42448 CODEC provides six multi-bit analog-to-digital and eight multi-bit digital-to-analog Delta-sigma
converters. The CODEC is capable of operation with either
differential or single-ended inputs and outputs, in a 64-pin
LQFP package.
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Six 24-bit A/D, Eight 24-bit D/A Converters
ADC Dynamic Range
– 105 dB Differential
– 102 dB Single-ended
DAC Dynamic Range
– 108 dB Differential
– 105 dB Single-ended
ADC/DAC THD+N
– -98 dB Differential
– -95 dB Single-ended
Compatible with Industry-standard Time
Division Multiplexed (TDM) Serial Interface
System Sampling Rates up to 192 kHz
Programmable ADC High-pass Filter for DC
Offset Calibration
Logarithmic Digital Volume Control
I²C & SPI™ Host Control Port
Supports Logic Levels Between 5 V and
1.8 V
Popguard® Technology
Interrupt
Reset
Auxilliary Serial
Audio Input
Input Master
Clock
Level Translator
Serial Audio
Input
All eight DAC channels provide digital volume control and
can operate with differential or single-ended outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42448 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as
A/V receivers, DVD receivers, and automotive audio
systems.
ORDERING INFORMATION
See page 67.
Digital Supply =
3.3 V to 5 V
Register
Configuration
Analog Supply =
3.3 V to 5 V
Internal Voltage
Reference
External
Mute Control
ADC Overflow
& Clock Error
Interrupt
PCM or TDM Serial
Interface
I2C/SPI
Software Mode
Control Data
Level Translator
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Six fully differential, or single-ended, inputs are available on
stereo ADC1, ADC2, and ADC3. When operating in Singleended Mode, an internal MUX before ADC3 allows selection from up to four single-ended inputs. Digital volume
control is provided for each ADC channel, with selectable
overflow detection.
Digital
Filters
High Pass
Filter
High Pass
Filter
Multibit
DAC1-4 and
Analog Filters
∆Σ
Modulators
Digital
Filters
Multibit
Oversampling
ADC1&2
Digital
Filters
Multibit
Oversampling
ADC3
8
Differential or
Single-Ended
Outputs
8
4
4
4:2*
Serial Audio
Output
Volume
Controls
Mute
Control
Differential or
Single-Ended
Analog Inputs
2
2
*Optional MUX allows selection from up to 4 single-ended inputs.
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
FEB ‘05
DS648PP2
TABLE OF CONTENTS
1 PIN DESCRIPTION .................................................................................................................... 6
1.1 Digital I/O Pin Characteristics ............................................................................................ 8
2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 9
3 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 10
SPECIFIED OPERATING CONDITIONS ............................................................................... 10
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
ANALOG INPUT CHARACTERISTICS (CS42448-CQZ) ....................................................... 11
ANALOG INPUT CHARACTERISTICS (CS42448-DQZ) ....................................................... 12
ADC DIGITAL FILTER CHARACTERISTICS ......................................................................... 13
ANALOG OUTPUT CHARACTERISTICS (CS42448-CQZ) ................................................... 14
ANALOG OUTPUT CHARACTERISTICS (CS42448-DQZ) ................................................... 16
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ................ 18
SWITCHING SPECIFICATIONS - ADC/DAC PORT .............................................................. 19
SWITCHING CHARACTERISTICS - AUX PORT................................................................... 21
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE......................................... 22
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................... 23
DC ELECTRICAL CHARACTERISTICS................................................................................. 24
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ....................................... 24
4 APPLICATIONS ....................................................................................................................... 25
4.1 Overview .......................................................................................................................... 25
4.2 Analog Inputs ................................................................................................................... 25
4.2.1 Line Level Inputs ................................................................................................. 25
4.2.2 ADC3 Analog Input ............................................................................................. 26
4.2.3 High Pass Filter and DC Offset Calibration ......................................................... 27
4.3 Analog Outputs ................................................................................................................ 27
4.3.1 Initialization ......................................................................................................... 27
4.3.2 Output Transient Control ..................................................................................... 27
4.3.3 Popguard® .......................................................................................................... 29
4.3.4 Mute Control ........................................................................................................ 29
4.3.5 Line-level Outputs and Filtering .......................................................................... 29
4.3.6 Digital Volume Control ........................................................................................ 30
4.3.7 De-Emphasis Filter .............................................................................................. 30
4.4 System Clocking .............................................................................................................. 31
4.5 CODEC Digital Interface Formats .................................................................................... 31
4.5.1 I²S ........................................................................................................................ 33
4.5.2 Left-Justified ........................................................................................................ 33
4.5.3 Right Justified ..................................................................................................... 33
4.5.4 OLM #1 ............................................................................................................... 33
4.5.5 OLM #2 ............................................................................................................... 34
4.5.6 TDM .................................................................................................................... 34
4.5.7 I/O Channel Allocation ........................................................................................ 35
4.6 AUX Port Digital Interface Formats .................................................................................. 36
4.6.1 I²S ........................................................................................................................ 36
4.6.2 Left Justified ........................................................................................................ 36
4.7 Control Port Description and Timing ................................................................................ 37
4.7.1 SPI Mode ............................................................................................................ 37
4.7.2 I2C Mode ............................................................................................................. 38
4.8 Interrupts .......................................................................................................................... 39
4.9 Recommended Power-up Sequence ............................................................................... 39
4.10 Reset and Power-up ..................................................................................................... 39
4.11 Power Supply, Grounding, and PCB layout ................................................................... 40
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DS648PP2
5 REGISTER QUICK REFERENCE ........................................................................................... 41
6 REGISTER DESCRIPTION ..................................................................................................... 43
6.1 Memory Address Pointer (MAP) ....................................................................................... 43
6.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 43
6.3 Power Control (address 02h)............................................................................................ 44
6.4 Functional Mode (address 03h)........................................................................................ 45
6.5 Interface Formats (address 04h) ...................................................................................... 46
6.6 ADC Control & DAC De-emphasis (address 05h) ............................................................ 48
6.7 Transition Control (address 06h) ...................................................................................... 49
6.8 DAC Channel Mute (address 07h) ................................................................................... 51
6.9 AOUTX Volume Control (addresses 08h- 0Fh) ............................................................ 51
6.10 DAC Channel Invert (address 10h) ................................................................................ 52
6.11 AINX Volume Control (address 11h-16h) ....................................................................... 52
6.12 ADC Channel Invert (address 17h) ................................................................................ 52
6.13 Status Control (address 18h).......................................................................................... 53
6.14 Status (address 19h) (Read Only)................................................................................. 53
6.15 Status Mask (address 1Ah) ............................................................................................ 54
6.16 MUTEC Pin Control (address 1Bh) ................................................................................ 54
7 APPENDIX A: EXTERNAL FILTERS ...................................................................................... 55
7.1 ADC Input Filter ............................................................................................................... 55
7.1.1 Passive Input Filter ............................................................................................. 56
7.1.2 Passive Input Filter w/Attenuation ....................................................................... 56
7.2 DAC Output Filter ............................................................................................................ 58
8 APPENDIX B: ADC FILTER PLOTS ....................................................................................... 59
9 APPENDIX C: DAC FILTER PLOTS ....................................................................................... 61
10 PARAMETER DEFINITIONS ................................................................................................. 63
11 REFERENCES ....................................................................................................................... 64
12 PACKAGE INFORMATION ................................................................................................... 65
12.1 Thermal Characteristics ................................................................................................ 65
13 ORDERING INFORMATION ................................................................................................. 66
14 REVISION HISTORY ............................................................................................................. 67
DS648PP2
3
LIST OF FIGURES
Figure 1. Typical Connection Diagram ............................................................................................ 9
Figure 2. Output Test Load ........................................................................................................... 17
Figure 3. Maximum Loading.......................................................................................................... 17
Figure 4. Serial Audio Interface Slave Mode Timing ..................................................................... 19
Figure 5. TDM Serial Audio Interface Timing ................................................................................ 19
Figure 6. Serial Audio Interface Master Mode Timing ................................................................... 20
Figure 7. Serial Audio Interface Slave Mode Timing ..................................................................... 21
Figure 8. Control Port Timing - I²C Format.................................................................................... 22
Figure 9. Control Port Timing - SPI Format................................................................................... 23
Figure 10. Full-Scale Input ............................................................................................................ 26
Figure 11. ADC3 Input Topology................................................................................................... 26
Figure 12. Audio Output Initialization Flow Chart .......................................................................... 28
Figure 13. Full-Scale Output ......................................................................................................... 30
Figure 14. De-Emphasis Curve ..................................................................................................... 30
Figure 15. I²S Format .................................................................................................................... 33
Figure 16. Left Justified Format..................................................................................................... 33
Figure 17. Right Justified Format .................................................................................................. 33
Figure 18. One Line Mode #1 Format ........................................................................................... 33
Figure 19. One Line Mode #2 Format ........................................................................................... 34
Figure 20. TDM Format ................................................................................................................. 34
Figure 21. AUX I²S Format............................................................................................................ 36
Figure 22. AUX Left Justified Format ............................................................................................ 36
Figure 23. Control Port Timing in SPI Mode.................................................................................. 37
Figure 24. Control Port Timing, I²C Write ...................................................................................... 38
Figure 25. Control Port Timing, I²C Read...................................................................................... 38
Figure 26. Single to Differential Active Input Filter ........................................................................ 55
Figure 27. Single-Ended Active Input Filter................................................................................... 55
Figure 28. Passive Input Filter....................................................................................................... 56
Figure 29. Passive Input Filter w/Attenuation................................................................................ 57
Figure 30. Active Analog Output Filter .......................................................................................... 58
Figure 31. Passive Analog Output Filter........................................................................................ 58
Figure 32. SSM Stopband Rejection ............................................................................................. 59
Figure 33. SSM Transition Band ................................................................................................... 59
Figure 34. SSM Transition Band (Detail)....................................................................................... 59
Figure 35. SSM Passband Ripple ................................................................................................. 59
Figure 36. DSM Stopband Rejection............................................................................................. 59
Figure 37. DSM Transition Band ................................................................................................... 59
Figure 38. DSM Transition Band (Detail) ...................................................................................... 60
Figure 39. DSM Passband Ripple ................................................................................................. 60
Figure 40. QSM Stopband Rejection............................................................................................. 60
Figure 41. QSM Transition Band................................................................................................... 60
Figure 42. QSM Transition Band (Detail) ...................................................................................... 60
Figure 43. QSM Passband Ripple................................................................................................. 60
Figure 44. SSM Stopband Rejection ............................................................................................. 61
Figure 45. SSM Transition Band ................................................................................................... 61
Figure 46. SSM Transition Band (detail) ....................................................................................... 61
Figure 47. SSM Passband Ripple ................................................................................................. 61
Figure 48. DSM Stopband Rejection............................................................................................. 61
Figure 49. DSM Transition Band ................................................................................................... 61
Figure 50. DSM Transition Band (detail) ....................................................................................... 62
Figure 51. DSM Passband Ripple ................................................................................................. 62
4
DS648PP2
Figure 52. QSM Stopband Rejection ............................................................................................ 62
Figure 53. QSM Transition Band................................................................................................... 62
Figure 54. QSM Transition Band (detail)....................................................................................... 62
Figure 55. QSM Passband Ripple................................................................................................. 62
DS648PP2
5
LIST OF TABLES
Table 1. I/O Power Rails ........................................................................................................................ 8
Table 2. Single-Speed Mode Common Frequencies ........................................................................... 31
Table 3. Double-Speed Mode Common Frequencies ......................................................................... 31
Table 4. Quad-Speed Mode Common Frequencies ............................................................................ 31
Table 5. I²S, LJ, RJ Clock Ratios ......................................................................................................... 32
Table 6. OLM#1 Clock Ratios .............................................................................................................. 32
Table 7. OLM#2 Clock Ratios .............................................................................................................. 32
Table 8. TDM Clock Ratios .................................................................................................................. 32
Table 9. Serial Audio Interface Channel Allocations............................................................................ 35
Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats .................... 45
Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats ........................................... 46
Table 12. DAC Digital Interface Formats ............................................................................................. 47
Table 13. ADC Digital Interface Formats ............................................................................................. 47
Table 14. Example AOUT Volume Settings......................................................................................... 51
Table 15. Example AIN Volume Settings............................................................................................. 52
Table 16. Revision History ................................................................................................................... 67
6
DS648PP2
AIN3-
AIN3+
AIN4-
AIN4+
FILT+_DAC
VA
FILT+_ADC
AIN5-/AIN5B
AGND
AIN5+/AIN5A
AIN6-/AIN6B
AIN6+/AIN6A
INT
DGND
SCL/CCLK
SDA/CDOUT
1 PIN DESCRIPTION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AD0/CS
1
48
AD1/CDIN
2
47
AIN2-
RST
3
46
AIN1+
AIN2+
VLC
4
45
AIN1-
ADC_LRCK
5
44
VA
VD
6
43
VQ
DGND
7
42
AGND
VLS
8
41
AOUT8-
ADC_SCLK
9
40
AOUT8+
CS42448
MCLK
10
39
AOUT7+
ADC_SDOUT3
11
38
AOUT7-
ADC_SDOUT2
12
37
AOUT6-
ADC_SDOUT1
13
36
AOUT6+
DAC_SDIN4
14
35
MUTEC
DAC_SDIN3
15
34
AOUT5+
DAC_SDIN2
16
33
AOUT5-
AOUT4-
AOUT4+
AOUT3-
AOUT3+
AOUT2-
AOUT2+
AOUT1+
AOUT1-
VD
DGND
AUX_SDIN
AUX_SCLK
AUX_LRCK
DAC_LRCK
DAC_SCLK
DAC_SDIN1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Name
#
Pin Description
AD0/CS
1
Address Bit [0]/ Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select
the chip in SPI mode.
AD1/CDIN
2
Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I2C Mode. Input for SPI data.
RST
3
Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low.
VLC
4
Control Port Power (Input) - Determines the required signal level for the control port. See “Digital
I/O Pin Characteristics” on page 9.
ADC_LRCK
5
ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active
on the ADC serial audio data line. Signals the start of a new TDM frame in the TDM digital interface format.
VD
6, 24 Digital Power (Input) - Positive terminal of the power supply for the digital section.
DGND
7, 23, Digital Ground (Input) - Ground terminal of the power supply for the digital section.
62
VLS
8
Serial Port Interface Power (Input) - Determines the required signal level for the serial interfaces.
See “Digital I/O Pin Characteristics” on page 9.
ADC_SCLK
9
ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface. Input frequency
must be 256xFs in the TDM digital interface format.
MCLK
10
Master Clock (Input) - Clock source for the Delta-Sigma modulators and digital filters.
ADC_SDOUT1
ADC_SDOUT2
ADC_SDOUT3
13
12
11
Serial Audio Data Output (Output) - Outputs for two’s complement serial audio data.
DS648PP2
7
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
17
16
15
14
DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
DAC_SCLK
18
DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface. Input frequency
must be 256xFs in the TDM digital interface format.
DAC_LRCK
19
DAC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active
on the DAC serial audio data line. Signals the start of a new TDM frame in the TDM digital interface format.
AUX_LRCK
20
Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active
on the Auxiliary serial audio data line. Derived from the ADC serial port and equals Fs.
AUX_SCLK
21
Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.
AUX_SDIN
22
Auxiliary Serial Input (Input) - Provides an additional serial input for two’s complement serial
audio data. Used only in the TDM digital interface format.
AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,-
26,25 Differential Analog Output (Output) - The full-scale analog output level is specified in the Analog
27,28 Characteristics table. Each leg of the differential outputs may also be used single-ended.
30,29
31,32
34,33
36,37
AGND
42,56 Analog Ground (Input) -
VQ
43
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
VA
44,53 Analog Power (Input) - Positive power supply for the analog section. See “Digital I/O Pin Characteristics” on page 9.
AIN1 +,AIN2 +,AIN3 +,AIN4 +,AIN5 +,AIN6 +,-
46,45 Differential Analog Input (Input) - Signals are presented differentially or single-ended to the
48,47 Delta-Sigma modulators. The full-scale input level is specified in the Analog Characteristics speci50,49 fication table. See below for a description of AIN5-AIN6 in Single-Ended Mode.
52,51
58,57
60,59
AIN5 A,B
AIN6 A,B
58,57 Single-Ended Analog Input (Input) - When stereo ADC3 is in Single-Ended Mode, an internal
60,59 analog mux allows selection between 2 channels for both analog inputs AIN5 and AIN6 (see section 4.2.2 for details). The unused leg of each input is internally connected to common mode. The
full-scale input level is specified in the Analog Characteristics table.
MUTEC
35
Mute Control (Output) - Used as a control for external mute circuits to prevent the clicks and pops
that can occur in any single supply system.
FILT+_DAC
54
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits
of the DAC.
FILT+_ADC
55
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits
of the ADC.
INT
61
Interrupt (Output) - Signals either an ADC overflow condition has occurred in one or more of the
ADC inputs, or a clocking error has occurred in the DAC/ADC as specified in the Interrupt register.
SCL/CCLK
63
Serial Control Port Clock (Input) - Serial clock for the control port interface.
SDA/CDOUT
64
Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Output for SPI data.
8
DS648PP2
1.1
Digital I/O Pin Characteristics
Various pins on the CS42448 are powered from separate power supply rails. The logic level for each input
should adhere to the corresponding power rail and should not exceed the maximum ratings.
Power
Rail
VLC
VLS
VA
Pin Name
RST
SCL/CCLK
SDA/CDOUT
I/O
Input
Input
Input/
Output
AD0/CS
Input
AD1/CDIN
Input
INT
Output
MCLK
Input
ADC_LRCK
Input/
Output
ADC_SCLK
Input/
Output
ADC_SDOUT1-3 Input/
(ADC3_SINGLE) Output
DAC_LRCK
Input/
Output
DAC_SCLK
Input/
Output
DAC_SDIN1-4 Input
AUX_LRCK
Output
AUX_SCLK
Output
AUX_SDIN
Input
MUTEC
Output
Driver
Receiver
1.8 V - 5.0 V, CMOS/Open Drain
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS, with Hysteresis
1.8 V - 5.0 V, CMOS, with Hysteresis
1.8 V - 5.0 V, CMOS/Open Drain
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
-
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
3.3 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
1.8 V - 5.0 V, CMOS
-
Table 1. I/O Power Rails
DS648PP2
9
2 TYPICAL CONNECTION DIAGRAM
+3.3 V to +5 V
10 µF
0.1 µF
+
0.1 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
6
VD
8
VA
VLS
0.01 µF
22
CS5341
A/D
Converter
21
20
AUX_SDIN
AUX_SCLK
AUX_LRCK
CS8416
Receiver
S/PDIF
optional
connection
OSC
+
+3.3 V to +5 V
10 µF
0.1 µF
44
53
24
VD
0.1 µF
VA
AOUT1+
AOUT1-
26
AOUT2+
AOUT2-
27
AOUT3+
AOUT3-
30
AOUT4+
AOUT4-
34
AOUT5+
AOUT5-
34
AOUT6+
AOUT6-
36
AOUT7+
AOUT7-
39
AOUT8+
AOUT8-
40
25
Analog Output Filter 2
Analog Output Filter2
28
Analog Output Filter 2
29
Analog Output Filter 2
33
Analog Output Filter 2
33
Analog Output Filter 2
37
Analog Output Filter 2
38
Analog Output Filter 2
41
RMCK
MUTEC
10
9
5
+1.8 V
to +5.0 V
13
12
11
Digital Audio
Processor
18
MCLK
AIN1+
46
AIN1-
45
AIN2+
48
AIN2-
47
DAC_SCLK
AIN3+
50
DAC_LRCK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
AIN3-
49
ADC_SCLK
ADC_LRCK
ADC_SDOUT1
ADC_SDOUT2
ADC_SDOUT3
19
17
16
15
14
61
3
MicroController
63
64
**
2 kΩ
+1.8 V
to +5 V
Mute
Drive
(optional)
35
AIN4+
52
AIN4-
51
AIN5+/AIN5A
58
AIN5-/AIN5B
57
INT
RST
AIN6+/AIN6A
SCL/CCLK
AIN6-/AIN6B
60
59
SDA/CDOUT
2
AD1/CDIN
1
AD0/CS
**
2 kΩ
4
VLC
0.1 µF
** Resistors are required for
I2C control port operation
VQ
FILT+_ADC
FILT+_DAC
Input
Filter 1
Analog Input 1
Input
Filter 1
Analog Input 2
Input
Filter 1
Analog Input 3
Input
Filter 1
Analog Input 4
Input
Filter 1
Analog Input 5
Input
Filter 1
Analog Input 6
Input
Filter 1
Analog Input 5A
Input
Filter 1
Analog Input 5B
Input
Filter 1
Analog Input 6A
Input
Filter 1
Analog Input 6B
43
55
54
+
+
DGND DGND DGND
7
23
62
AGND
56
AGND
0.1 µF
100 µF
0.1 µF
+
22 µF
0.1 µF
4.7 µF
42
Connect DGND and AGND near CODEC
1. See the ADC Input Filter section in the Appendix.
2. See the DAC Output Filter section in the Appendix.
Figure 1. Typical Connection Diagram
10
DS648PP2
3 CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25° C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
Parameters
DC Power Supply
Analog
3.3 V
5.0 V
3.3 V
5.0 V
(Note 1)
Digital
Symbol
Min
Typ
Max
Units
VA
3.14
4.75
3.14
4.75
1.71
2.37
3.14
4.75
1.71
2.37
3.14
4.75
3.3
5
3.3
5
1.8
2.5
3.3
5
1.8
2.5
3.3
5
3.47
5.25
3.47
5.25
1.89
2.63
3.47
5.25
1.89
2.63
3.47
5.25
V
V
V
V
V
V
V
V
V
V
V
V
-10
-40
-
+70
+85
°C
°C
VD
Serial Audio Interface
1.8 V (Note 2)
2.5 V
3.3 V
5.0 V
VLS
Control Port Interface
1.8 V
2.5 V
3.3 V
5.0 V
VLC
-CQZ
-DQZ
TA
Ambient Temperature
Commercial
Automotive
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Input Current
Analog Input Voltage
Digital Input Voltage
(Note 4)
Ambient Operating Temperature
(power applied)
Storage Temperature
Analog
Digital
Serial Port Interface
Control Port Interface
(Note 3)
(Note 4)
Serial Port Interface
Control Port Interface
CS42448-CQZ
CS42448-DQZ
Symbol
VA
VD
VLS
VLC
Iin
VIN
VIND-S
VIND-C
TA
Tstg
Min
-0.3
-0.3
-0.3
-0.3
AGND-0.7
-0.3
-0.3
-20
-50
-65
Max
6.0
6.0
6.0
6.0
±10
VA+0.7
VLS+ 0.4
VLC+ 0.4
+85
+95
+150
Units
V
V
V
V
mA
V
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
Notes: 1. Analog input/output performance will slightly degrade at VA = 3.3 V.
2. The ADC_SDOUT may not meet timing requirements in TDM, Double-Speed Mode.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR
latch-up.
4. The maximum over/under voltage is limited by the input current.
DS648PP2
11
ANALOG INPUT CHARACTERISTICS (CS42448-CQZ)
(Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz
through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.)
Differential
Parameter
Single Speed Mode
Dynamic Range
Fs=48 kHz
A-weighted
unweighted
Total Harmonic Distortion + Noise
-1 dB
(Note 5)
-20 dB
-60 dB
Double Speed Mode
Dynamic Range
Fs=96 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
-1 dB
(Note 5)
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
Quad Speed Mode
Dynamic Range
Fs=192 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
-1 dB
(Note 5)
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
All Speed Modes
ADC1-3 Interchannel Isolation
ADC3 MUX Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Analog Input
Full-scale Input Voltage
Differential Input Impedance (Note 6)
Single-Ended Input Impedance (Note 7)
Common Mode Rejection Ratio (CMRR)
12
Single-Ended
Min
Typ
Max
Min
Typ
Max
Unit
99
96
-
105
102
-98
-82
-42
-92
-
96
93
-
102
99
-95
-79
-39
-89
-
dB
dB
dB
dB
dB
99
96
-
105
102
99
-98
-82
-42
-90
-92
-
96
93
102
99
96
-95
-79
-39
-90
-89
-
dB
dB
dB
dB
dB
dB
dB
99
96
-
105
102
99
-98
-82
-42
-87
-92
-
96
93
102
99
96
-95
-79
-39
-87
-
dB
dB
dB
dB
dB
dB
dB
-
90
90
-
-
90
90
-
dB
dB
-
0.1
±100
-
-
0.1
±100
-
dB
ppm/°C
-
-
-89
-
1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA
18
18
82
-
Vpp
kΩ
kΩ
dB
DS648PP2
ANALOG INPUT CHARACTERISTICS (CS42448-DQZ)
(Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz
through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.)
Differential
Parameter
Single Speed Mode
Dynamic Range
Fs=48 kHz
A-weighted
unweighted
Total Harmonic Distortion + Noise
-1 dB
(Note 5)
-20 dB
-60 dB
Double Speed Mode
Dynamic Range
Fs=96 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
-1 dB
(Note 5)
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
Quad Speed Mode
Dynamic Range
Fs=192 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
-1 dB
(Note 5)
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
All Speed Modes
ADC1-3 Interchannel Isolation
ADC3 MUX Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Analog Input
Full-scale Input Voltage
Differential Input Impedance (Note 6)
Single-Ended Input Impedance (Note 7)
Common Mode Rejection Ratio (CMRR)
Single-Ended
Min
Typ
Max
Min
Typ
Max
Unit
97
94
-
105
102
-98
-82
-42
-90
-
94
91
-
102
99
-95
-79
-39
-87
-
dB
dB
dB
dB
dB
97
94
-
105
102
99
-98
-82
-42
-87
-90
-
94
91
-
102
99
96
-95
-79
-39
-87
-87
-
dB
dB
dB
dB
dB
dB
dB
97
94
-
105
102
99
-98
-82
-42
-87
-90
-
94
91
-
102
99
96
-95
-79
-39
-87
-87
-
dB
dB
dB
dB
dB
dB
dB
-
90
85
-
-
90
85
-
dB
dB
-
0.1
±100
-
-
0.1
±100
-
dB
ppm/°C
1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA
18
18
82
-
Vpp
kΩ
kΩ
dB
Notes: 5. Referred to the typical full-scale voltage.
6. Measured between AINx+ and AINx-.
7. Measured between AINxx and AGND.
DS648PP2
13
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 8, 9)
Min
Typ
Max
Unit
0
-
0.4896
Fs
-
-
0.08
dB
0.5688
-
-
Fs
70
-
-
dB
-
12/Fs
-
s
0
-
0.4896
Fs
-
-
0.16
dB
0.5604
-
-
Fs
69
-
-
dB
-
9/Fs
-
s
0
-
0.2604
Fs
-
-
0.16
dB
0.5000
-
-
Fs
60
-
-
dB
-
5/Fs
-
s
Single Speed Mode (Note 9)
Passband (Frequency Response)
to -0.1 dB corner
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay
Double Speed Mode (Note 9)
Passband (Frequency Response)
to -0.1 dB corner
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay
Quad Speed Mode (Note 9)
Passband (Frequency Response)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay
to -0.1 dB corner
High Pass Filter Characteristics
Frequency Response
-3.0 dB
-0.13 dB
-
1
20
-
Hz
Hz
Phase Deviation
@ 20 Hz
-
10
-
Deg
Passband Ripple
-
-
0
dB
Filter Settling Time
-
105/Fs
0
s
Notes: 8. Filter response is guaranteed by design.
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 32 to 43) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
14
DS648PP2
ANALOG OUTPUT CHARACTERISTICS (CS42448-CQZ)
(Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is
10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test
load: RL = 3 kΩ, CL = 10 pF.)
Parameter
Single-Speed Mode
Fs = 48 kHz
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
Double-Speed Mode
Fs = 96 kHz
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
Quad-Speed Mode
Fs = 192 kHz
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
DS648PP2
Min
Differential
Typ
102
99
-
108
105
99
96
-
99
96
-
105
102
96
93
-
dB
dB
dB
dB
-
-98
-85
-45
-93
-76
-36
-92
-
-
-95
-82
-42
-90
-73
-33
-89
-
dB
dB
dB
dB
dB
dB
102
99
-
108
105
99
96
-
99
96
-
105
102
96
93
-
dB
dB
dB
dB
-
-98
-85
-45
-93
-76
-36
-92
-
-
-95
-82
-42
-90
-73
-33
-89
-
dB
dB
dB
dB
dB
dB
102
99
-
108
105
99
96
-
99
96
-
105
102
96
93
-
dB
dB
dB
dB
-
-98
-85
-45
-93
-76
-36
-92
-
-
-95
-82
-42
-90
-73
-33
-89
-
dB
dB
dB
dB
dB
dB
Max
Min
Single-Ended
Typ
Max
Unit
15
All Speed Modes
Interchannel Isolation
(1 kHz)
Analog Output
Full Scale Output
1.235•VA
Interchannel Gain Mismatch
Gain Drift
Output Impedance
DC Current draw from an AOUT pin
-
100
-
-
100
-
dB
1.300•VA 1.365•VA 0.618•VA 0.650•VA 0.683•VA
Vpp
0.1
0.25
0.1
0.25
dB
±100
±100
ppm/°C
100
100
Ω
10
10
µA
(Note 10)
AC-Load Resistance (RL)
(Note 12)
3
-
-
3
-
-
kΩ
Load Capacitance (CL)
(Note 12)
-
-
100
-
-
100
pF
16
DS648PP2
ANALOG OUTPUT CHARACTERISTICS (CS42448-DQZ)
(Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is
10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test
load: RL = 3 kΩ, CL = 10 pF.)
Parameter
Single-Speed Mode
Fs = 48 kHz
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
Double-Speed Mode
Fs = 96 kHz
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
Quad-Speed Mode
Fs = 192 kHz
Dynamic Range
18 to 24-Bit
A-weighted
unweighted
16-Bit
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
DS648PP2
Min
Differential
Typ
100
97
-
108
105
99
96
-
97
94
-
105
102
96
93
-
dB
dB
dB
dB
-
-98
-85
-45
-93
-76
-36
-90
-
-
-95
-82
-42
-90
-73
-33
-87
-
dB
dB
dB
dB
dB
dB
100
97
-
108
105
99
96
-
97
94
-
105
102
96
93
-
dB
dB
dB
dB
-
-98
-85
-45
-93
-76
-36
-90
-
-
-95
-82
-42
-90
-73
-33
-87
-
dB
dB
dB
dB
dB
dB
100
97
-
108
105
99
96
-
97
94
-
105
102
96
93
-
dB
dB
dB
dB
-
-98
-85
-45
-93
-76
-36
-90
-
-
-95
-82
-42
-90
-73
-33
-87
-
dB
dB
dB
dB
dB
dB
Max
Min
Single-Ended
Typ
Max
Unit
17
All Speed Modes
Interchannel Isolation
(1 kHz)
Analog Output
Full Scale Output
1.210•VA
Interchannel Gain Mismatch
Gain Drift
Output Impedance
DC Current draw from an AOUT pin
-
100
-
-
100
-
dB
1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA
Vpp
0.1
0.25
0.1
0.25
dB
±100
±100
ppm/°C
100
100
Ω
10
10
µA
(Note 10)
AC-Load Resistance (RL)
(Note 12)
3
-
-
3
-
-
kΩ
Load Capacitance (CL)
(Note 12)
-
-
100
-
-
100
pF
Notes: 10. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin
due to typical leakage through the electrolytic DC blocking capacitors.
11. One-half LSB of triangular PDF dither is added to data.
12. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and
maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit
topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing
this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See
Appendix A for a recommended output filter.
DAC1-4
AOUTxx
3.3 µF
Analog
Output
+
RL
CL
Capacitive Load -- C L (pF)
125
100
75
Safe Operating
Region
50
25
AGND
2.5
3
Figure 2. Output Test Load
18
5
10
15
20
Resistive Load -- RL (kΩ )
Figure 3. Maximum Loading
DS648PP2
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Min
Typ
Max
Unit
0
0
-
0.4780
0.4996
Fs
Fs
-0.2
-
+0.08
dB
0.5465
-
-
Fs
50
-
-
dB
-
10/Fs
-
s
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
to -0.1 dB corner
to -3 dB corner
0
0
-
0.4650
0.4982
Fs
Fs
-0.2
-
+0.7
dB
0.5770
-
-
Fs
55
-
-
dB
-
5/Fs
-
s
0
0
-
0.397
0.476
Fs
Fs
-0.2
-
+0.05
dB
Parameter (Note 8, 13)
Single Speed Mode
Passband (Frequency Response)
to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 14)
Group Delay
De-emphasis Error (Note 15)
+1.5/+0
dB
+0.05/-0.25 dB
-0.2/-0.4
dB
Double Speed Mode
Passband (Frequency Response)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 14)
Group Delay
Quad Speed Mode
Passband (Frequency Response)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 14)
Group Delay
0.7
-
-
Fs
51
-
-
dB
-
2.5/Fs
-
s
Notes: 13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 44 to 55) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
14. Single and Double Speed Mode Measurement Bandwidth is from Stopband to 3 Fs.
Quad Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs.
15. De-emphasis is only available in Single Speed Mode.
DS648PP2
19
SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS,
ADC_SDOUT CLOAD = 15 pF.)
Parameters (Note 20)
Symbol
Min
Max
Units
1
-
ms
0.512
50
MHz
45
55
%
4
50
100
50
100
200
kHz
kHz
kHz
Slave Mode
RST pin Low Pulse Width
(Note 16)
MCLK Frequency
MCLK Duty Cycle
(Note 17)
Input Sample Rate (LRCK)
Fs
Fs
Fs
Single-Speed Mode
Double-Speed Mode (Note 18)
Quad-Speed Mode (Note 19)
LRCK Duty Cycle
45
55
%
SCLK Duty Cycle
45
55
%
SCLK High Time
tsckh
8
-
ns
SCLK Low Time
tsckl
8
-
ns
LRCK Rising Edge to SCLK Rising Edge
tfss
tlcks
5
-
ns
SCLK Rising Edge to LRCK Falling Edge
tfsh
16
-
ns
SCLK Falling Edge to ADC_SDOUT Output Valid
tdpd
-
35
ns
DAC_SDIN Setup Time Before SCLK Rising Edge
tds
3
-
ns
DAC_SDIN Hold Time After SCLK Rising Edge
tdh
5
-
ns
DAC_SDIN Hold Time After SCLK Rising Edge
tdh1
5
-
ns
ADC_SDOUT Hold Time After SCLK Rising Edge
tdh2
10
-
ns
ADC_SDOUT Valid Before SCLK Rising Edge
tdval
15
-
ns
LRCK
LRCK
(input)
tlcks
t sckh
tsckl
tfss
tfsh
tsckh
tsckl
SCLK
SCLK
(input)
tds
DAC_SDINx
t dh
MSB
tds
MSB-1
DAC_SDIN1
tdh2
MSB
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
20
ADC_SDOUT1
MSB-1
MSB
tdpd
ADC_SDOUTx
tdh1
MSB
tdval
MSB-1
Figure 5. TDM Serial Audio Interface Timing
DS648PP2
Symbol
Min
Max
Units
Fs
-
MCLK / 256
kHz
LRCK Duty Cycle
45
55
%
SCLK Frequency
-
64 x Fs
MHz
SCLK Duty Cycle
45
55
%
Parameters (Note 20)
Master Mode
Output Sample Rate (LRCK)
All Speed Modes
LRCK Edge to SCLK Rising Edge
tlcks
-
5
ns
SCLK Falling Edge to ADC_SDOUT Output Valid
tdpd
-
35
ns
DAC_SDIN Setup Time Before SCLK Rising Edge
tds
3
-
ns
DAC_SDIN Hold Time After SCLK Rising Edge
tdh1
5
-
ns
Notes: 16. After powering up the CS42448, RST should be held low after the power supplies and clocks are settled.
17. See Table 10 on page 46 and Table 11 on page 47 for suggested MCLK frequencies.
18. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only.
19. ADC - I²S, Left-Justified, Right-Justified interface formats only. DAC - I²S, Left-Justified, Right-Justified
and Time Division Multiplexed interface formats only.
20. “LRCK” and “SCLK” shall refer to the ADC and DAC left/right clock and serial clock, respectively.
LRCK
tlcks
SCLK
tds
DAC_SDINx
tdh
MSB
MSB-1
MSB
MSB-1
tdpd
ADC_SDOUTx
Figure 6. Serial Audio Interface Master Mode Timing
DS648PP2
21
SWITCHING CHARACTERISTICS - AUX PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS.)
Parameters
Symbol
Min
Max
Units
Master Mode
Output Sample Rate (AUX_LRCK)
All Speed Modes
Fs
-
ADC_LRCK
kHz
AUX_SCLK Frequency
-
64·ADC_LRCK
kHz
AUX_SCLK Duty Cycle
45
55
%
AUX_LRCK Edge to SCLK Rising Edge
tlcks
-
5
ns
AUX_SDIN Setup Time Before SCLK Rising Edge
tds
3
-
ns
AUX_SDIN Hold Time After SCLK Rising Edge
tdh
5
-
ns
AUX_LRCK
tlcks
tsckh
tsckl
AUX_SCLK
tds
AUX_SDIN
tdh
MSB
MSB-1
Figure 7. Serial Audio Interface Slave Mode Timing
22
DS648PP2
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
SDA Hold Time from SCL Falling
(Note 21)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
(Note 22)
trc
-
1
µs
Fall Time SCL and SDA
(Note 22)
tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Notes: 21. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
22. Guaranteed by design.
RST
t
irs
Stop
R e p e a te d
Sta rt
Start
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 8. Control Port Timing - I²C Format
DS648PP2
23
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF)
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
0
6.0
MHz
RST Rising Edge to CS Falling
tsrs
20
-
ns
CS Falling to CCLK Edge
tcss
20
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
tdh
15
-
ns
CCLK Falling to CDOUT Stable
tpd
-
50
ns
Rise Time of CDOUT
tr1
-
25
ns
Fall Time of CDOUT
tf1
-
25
ns
CCLK Rising to DATA Hold Time
(Note 23)
Rise Time of CCLK and CDIN
(Note 24)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 24)
tf2
-
100
ns
Notes: 23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For fsck <1 MHz.
RST
tsrs
CS
tcsh
tcss
tsch
tscl
tr2
CCLK
tf2
tdsu
tdh
MSB
CDIN
tpd
CDOUT
MSB
Figure 9. Control Port Timing - SPI Format
24
DS648PP2
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
VA = 5.0 V
IA
-
80
-
mA
VLS = VLC = VD = 3.3 V
IDT
-
60.6
-
mA
-
600
850
mW
-
60
40
-
dB
dB
-
1.25
-
mW
Nominal Voltage
Output Impedance
DC current source/sink (Note 29)
-
0.5•VA
23
-
10
kΩ
FILT+_ADC Nominal Voltage
FILT+_DAC Nominal Voltage
-
VA
VA
-
V
V
Normal Operation (Note 25)
Power Supply Current
(Note 26)
Power Dissipation
All Supplies = 5 V
Power Supply Rejection Ratio
(Note 27)
1 kHz
60 Hz
PSRR
Power-down Mode (Note 28)
Power Dissipation
All Supplies = VA = 5 V
VQ Characteristics
V
µA
Notes: 25. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to the DAC and AUX port, and a
1 kHz, -1 dB analog input to the ADC port sampled at the highest Fs for each speed mode. DAC outputs
are open, unless otherwise specified.
26. IDT measured with no external loading on pin 64 (SDA).
27. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
28. Power Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input.
29. Guaranteed by design. The DC current draw represents the allowed current draw from the VQ pin due
to typical leakage through the electrolytic de-coupling capacitors.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 30)
Symbol
Min
VLS-1.0
VLC-1.0
VA-1.0
Typ
-
Max
-
Units
V
V
V
-
-
0.4
0.4
0.4
V
V
V
High-Level Output Voltage at Io=2 mA
Serial Port
Control Port
MUTEC
VOH
Low-Level Output Voltage at Io=2 mA
Serial Port
Control Port
MUTEC
VOL
High-Level Input Voltage
Serial Port
Control Port
VIH
0.7xVLS
0.7xVLC
-
-
V
V
Serial Port
Control Port
VIL
-
-
0.2xVLS
0.2xVLC
V
V
-
3
±10
10
-
µA
pF
mA
Low-Level Input Voltage
Input Leakage Current
Input Capacitance (Note 22)
MUTEC Drive Current
Iin
Notes: 30. See “Digital I/O Pin Characteristics” on page 9 for serial and control port power rails.
DS648PP2
25
4 APPLICATIONS
4.1
Overview
The CS42448 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital
converters (ADC), implemented using multi-bit delta-sigma techniques, and 8 digital-to-analog converters
(DAC) also implemented using multi-bit delta-sigma techniques.
Other functions integrated within the CODEC include independent digital volume controls for each DAC,
digital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC highpass filters, an on-chip voltage reference and Popguard® technology that minimizes the effects of output
transients on power-up and power-down.
All serial data is transmitted through two independent serial ports: the DAC serial port and the ADC serial
port. Each serial port can be configured independently to operate at different sample and clock rates, but
both must run synchronous to each other.
The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Multiplexed (TDM) interface format. In the One-Line Mode (OLM) interface format, the CS42448 will allow up
to 6 ADC channels on one data line and up to 8 DAC channels on 2 data lines.
The CS42448 features an Auxiliary Port used to accommodate an additional two channels of PCM data
on the ADC_SDOUT data line in the TDM digital interface format. See “AUX Port Digital Interface Formats” on page 37 for details.
The CS42448 operates in one of three oversampling modes based on the input sample rate. When operating the CODEC as a slave, mode selection is determined automatically based on the MCLK frequency
setting. When operating as a master, mode selection is determined by the ADC and DAC FM bits in register “Functional Mode (address 03h)” on page 46. Single-Speed mode (SSM) supports input sample
rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode (QSM) supports input
sample rates up to 200 kHz and uses an oversampling ratio of 32x (NOTE: QSM for the ADC is only supported in the I²S, Left-Justified, Right-Justified interface formats. QSM for the DAC is supported in the I²S,
Left-Justified, Right-Justified and Time Division Multiplexed interface formats).
All functions can be configured through software via a serial control port operable in SPI mode or in I²C
mode.
Figure 1 on page 10 shows the recommended connections for the CS42448. See section “Register Description” on page 44 for the default register settings and options.
4.2
Analog Inputs
4.2.1 Line Level Inputs
AINx+ and AINx- are the line level differential analog inputs internally biased to VQ, approximately VA/2. Figure 10 on page 27 shows the full-scale analog input levels. The CS42448 also
accommodates single-ended signals on all inputs, AIN1-AIN6. See “ADC Input Filter” on
page 56 for the recommended input filters.
For single-ended operation on ADC1-ADC3 (AIN1 to AIN6), the ADCx_SINGLE bit in the register “ADC Control & DAC De-emphasis (address 05h)” on page 49 must be set appropriately (see
Figure 27 on page 56 for required external components).
The gain/attenuation of the signal can be adjusted for each AINx independently through the
“AINX Volume Control (address 11h-16h)” on page 53.
26
DS648PP2
The ADC output data is in 2’s complement binary format. For inputs above positive full scale or
below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the
ADC Overflow bit in the register “Status (address 19h) (Read Only)” on page 54 to be set to a ‘1’.
5.0 V
3.9 V
VA
2.5 V
AINx+
2.5 V
AINx-
1.1 V
3.9 V
1.1 V
Full-Scale Differential Input Level =
(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS
Figure 10. Full-Scale Input
4.2.2 ADC3 Analog Input
ADC3 accommodates differential as well as single-ended inputs. In Single-Ended mode, an internal MUX selects from up to 4 single-ended inputs.
AIN5A
ADC3
Single-Ended Input Filter
AIN5_MUX
AIN5B
ADC3 SINGLE
Single-Ended Input Filter
1
0
1
58
AIN5+/-
Differential
Input Filter
0
+
AIN5
57
0
VQ
-
1
AIN6_MUX
1
0
1
60
AIN6+/-
Differential
Input Filter
0
AIN6
59
0
VQ
AIN6A
AIN6B
+
-
1
Single-Ended Input Filter
Single-Ended Input Filter
Figure 11. ADC3 Input Topology
Single-Ended mode is selected using the ADC3_SINGLE bit. Analog input selection is then
made via the AINx_MUX bits. See register “ADC Control & DAC De-emphasis (address 05h)”
DS648PP2
27
on page 49 for all bit selections. Refer to Figure 11 on page 27 for the internal ADC3 analog input
topology.
4.2.3 High Pass Filter and DC Offset Calibration
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high pass filter is disabled during normal operation, the current value of the
DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by:
1) Running the CS42448 with the high pass filter enabled until the filter settles. See the Digital
Filter Characteristics for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
The high pass filter for ADC1/ADC2 can be enabled and disabled. The high pass filter for ADC3
can be independently enabled and disabled. The high pass filters are controlled using the
HPF_FREEZE bit in the register “ADC Control & DAC De-emphasis (address 05h)” on page 49.
4.3
Analog Outputs
4.3.1 Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 12 on page 29. The
CS42448 enters a Power-Down state upon initial power-up. The interpolation & decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference,
multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RST pin is brought high. The control
port is accessible once RST is high and the desired register settings can be loaded per the interface descriptions in the “Control Port Description and Timing” on page 38.
Once MCLK is valid, VQ will ramp up to VA/2, and the internal voltage references, FILT+_ADC
and FILT+_DAC, will begin powering up to normal operation. Power is applied to the D/A converters and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage,
VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine
the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal operation begins.
4.3.2 Output Transient Control
The CS42448 uses Popguard® technology to minimize the effects of output transients during
power-up and power-down. This technique eliminates the audio transients commonly produced
by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation. See “Popguard®” on page 30 for details.
A Mute Control pin is also available for use with an optional mute circuit to mask output transients on the analog outputs. See “Mute Control” on page 30 for details.
When changing clock ratio or sample rate it is recommended that zero data (or near zero data)
be present on DAC_SDINx for at least 10 LRCK samples before the change is made. During the
clocking change the DAC outputs will always be in a zero data state. If no zero audio is present
at the time of switching, a slight click or pop may be heard as the DAC output automatically goes
to it’s zero data state.
28
DS648PP2
No Power
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
PDN bit = '1'b?
Yes
Power-Down Mode
1. VQ = 0 V.
2. Aout bias = VQ.
3. No audio signal generated.
4. Control Port Registers retain
settings.
No
Power-Down (Power Applied)
1. VQ = 0 V.
2. Aout = VQ.
3. No audio signal generated.
4. Control Port Registers reset
to default.
PopGuard®
Power-Up Ramp
1. VQ ramp up to VA/2.
2. Aout bias = VQ.
400 ms delay
Power-Down Ramp
1. VQ ramp down to 0 V.
2. Aout bias = VQ.
250 ms delay
Yes
RST = Low?
No
Control Port
Active
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
No
Control Port
Access Detected?
Yes
No
No Power Transition
1. VQ = 0 V.
2. Aout bias = VQ.
3. Audible pops.
Hardware Mode not supported.
Codec will power up in an
unknown state once all clocks
and data are valid. It is
recommended that the user
setup up the codec via the
control port before applying
MCLK.
Valid
MCLK/LRCK
Ratio?
Software Mode
Registers setup to
desired settings.
Yes
No
Valid MCLK
Applied?
2000 LRCK delay
Yes
Power-Down Transition
1. VQ = 0 V.
2. Aout bias = VQ.
3. Audible pops.
RST = Low
ERROR: Power removed
Normal Operation
1. VQ = VA/2.
2. Aout bias = VQ.
3. Audio signal generated per register settings.
PDN bit set
to '1'b
ERROR: MCLK/LRCK ratio change
ERROR: MCLK removed
Analog Output Mute
1. VQ = VA/2.
2. Aout bias = VQ.
3. DAC outputs muted.
4. No audio signal generated.
Analog Output Freeze
1. VQ = VA/2.
2. Aout bias = VQ + last audio sample.
3. DAC Modulators stop operation.
4. Audible pops.
Figure 12. Audio Output Initialization Flow Chart
DS648PP2
29
4.3.3 Popguard®
4.3.3a
Power-up
When the device is initially powered-up, the audio outputs, AOUTxx, are clamped to VQ
which is initially low. After the RST pin is brought high and MCLK is applied, the outputs
begin to ramp with VQ towards the nominal quiescent voltage. This ramp takes approximately 400 ms to complete. The gradual voltage ramping allows time for the external
DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage.
Once valid DAC_LRCK, DAC_SCLK and DAC_SDINx are applied, audio output begins
approximately 2000 sample periods later.
4.3.3b
Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, the PDN bit in register “Power
Control (address 02h)” on page 45 must be set to ‘1’ for a period of about 250 ms before
removing power. During this time, voltage on VQ and the audio outputs discharge gradually to AGND. If power is removed before this 250 ms time period has passed a transient will occur when the VA supply drops below that of VQ. There is no minimum time
for a power cycle. Power may be re-applied at any time.
4.3.4 Mute Control
The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The use
of external mute circuits is not mandatory but may be desired for designs requiring the absolute
minimum in extraneous clicks and pops.
MUTEC is in high impedance mode during power up or when the CS42448 is in power down
mode by setting the PDN bit in the register “Power Control (address 02h)” on page 45 to a ‘1’.
Once out of power-down mode the pin can be controlled by the user via the control port (see
“MUTEC Pin Control (address 1Bh)” on page 55), or automatically asserted to the active state
when zero data is present on all DAC inputs, when all DAC outputs are muted or when serial
port clock errors occur.
To prevent large transients on the output, it is recommended to mute the DAC outputs before
the Mute Control pin is asserted.
4.3.5 Line-level Outputs and Filtering
The CS42448 contains on-chip buffer amplifiers capable of producing line level differential as
well as single-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC
level of approximately VQ.
The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise
can be attenuated using an off-chip low pass filter.
See “DAC Output Filter” on page 59 for recommended output filter. The active filter configuration
accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins.
Also shown is a passive filter configuration which minimizes costs and the number of components.
Figure 13 shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately VA/2.
30
DS648PP2
5.0 V
4.125 V
VA
AOUTx+
2.5 V
0.875 V
4.125 V
AOUTx-
2.5 V
0.875 V
Full-Scale Differential Output Level =
(AOUTx+) - (AOUTx-) = 6.5 VPP = 2.3 VRMS
Figure 13. Full-Scale Output
4.3.6 Digital Volume Control
Each DAC’s output level is controlled via the Volume Control registers operating over the range
of 0 to -127.5 dB attenuation with 0.5 dB resolution. See “AOUTX Volume Control (addresses
08h- 0Fh)” on page 52. Volume control changes are programmable to ramp in increments of
0.125 dB at the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See
“Transition Control (address 06h)” on page 50.
Each output can be independently muted via mute control bits in the register “DAC Channel
Mute (address 07h)” on page 52. When enabled, each AOUTx_MUTE bit attenuates the corresponding DAC to its maximum value (-127.5 dB). When the AOUTx_MUTE bit is disabled, the
corresponding DAC returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits.
4.3.7 De-Emphasis Filter
The CS42448 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The
filter response is shown in Figure 14. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction.
De-emphasis is only available in Single Speed Mode. Please see “DAC De-Emphasis Control
(DAC_DEM)” on page 49 for de-emphasis control.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 14. De-Emphasis Curve
DS648PP2
31
4.4
System Clocking
The CODEC (ADC & DAC) serial audio interface ports operate both as a slave or master. The serial ports
accept externally generated clocks in slave mode and will generate synchronous clocks derived from an
input master clock in master mode. In the TDM format the ADC and DAC serial ports will only operate as
a slave. In OLM #2 the serial ports will accept or output a 256Fs SCLK. See the registers “DAC Functional
Mode (DAC_FM[1:0])” on page 46 and “ADC Functional Mode (ADC_FM[1:0])” on page 46 for setting up
master/slave mode.
The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must
be an integer multiple of, and synchronous with, the system sample rate, Fs.
The required integer ratios, along with some common frequencies, are illustrated in tables 2 to 4. The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency
(MFreq[2:0])” on page 46.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
1024x
32.7680
45.1584
49.1520
384x
24.5760
33.8688
36.8640
512x
32.7680
45.1584
49.1520
Table 2. Single-Speed Mode Common Frequencies
Sample Rate
(kHz)
64
88.2
96
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
MCLK (MHz)
256x
16.3840
22.5792
24.5760
Table 3. Double-Speed Mode Common Frequencies
Sample Rate
(kHz)
176.4
192
64x
11.2896
12.2880
96x
16.9344
18.4320
MCLK (MHz)
128x
22.5792
24.5760
192x
33.8688
36.8640
256x
45.1584
49.1520
Table 4. Quad-Speed Mode Common Frequencies
4.5
CODEC Digital Interface Formats
The ADC and DAC serial ports support the I²S, Left-Justified, Right-Justified, One-Line Mode (OLM) and
TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 15-20. Data is
clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. The
serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronously derived from the master clock and
be equal to 256x, 128x, 64x, 48x or 32x Fs depending on the interface format selected and desired speed
mode. One Line Mode #1 and One Line Mode #2 will operate in master or slave mode. Refer to Table 5
for required clock ratios. The SCLK to sample rate (LRCK) ratios are shown in Tables 5 - 8.
32
DS648PP2
I²S, Left-Justified, Right-Justified
Ratio
MCLK/LRCK
SSM
DSM
256x, 384x, 512x, 128x, 192x, 256x,
768x, 1024x
384x, 512x
QSM
64x, 96x, 128x,
192x, 256x
SCLK/LRCK
(Slave Mode)
32x, 48x, 64x
32x, 48x, 64x
32x, 48x, 64x
SCLK/LRCK
(Master Mode)
64x
64x
64x
Table 5. I²S, LJ, RJ Clock Ratios
OLM #1
SSM
MCLK/LRCK
DSM
256x, 384x, 512x, 256x, 384x, 512x
768x, 1024x
QSM
N/A
SCLK/LRCK
(Slave Mode)
128x
128x
N/A
SCLK/LRCK
(Master Mode)
128x
128x
N/A
Table 6. OLM#1 Clock Ratios
OLM #2
SSM
MCLK/LRCK
DSM
256x, 384x, 512x, 256x, 384x, 512x
768x, 1024x
QSM
N/A
SCLK/LRCK
(Slave Mode)
256x
256x
N/A
SCLK/LRCK
(Master Mode)
256x
256x
N/A
Table 7. OLM#2 Clock Ratios
TDM
SSM
MCLK/LRCK
DSM
256x, 384x, 512x, 256x, 384x, 512x
768x, 1024x
QSM (DAC only)
256x
SCLK/LRCK
(Slave Mode)
256X
256X
256X
SCLK/LRCK
(Master Mode)
N/A
N/A
N/A
Table 8. TDM Clock Ratios
DS648PP2
33
4.5.1 I²S
ADC/DAC_LRCK
L eft C h a n n el
Rig ht C h a n n el
ADC/DAC_SCLK
DAC_SDINx
ADC_SDOUTx
MSB
M SB
LS B
MSB
LS B
AOUT 2, 4, 6 or 8
AIN 2, 4, or 6
AOUT 1, 3, 5 or 7
AIN 1, 3, or 5
Figure 15. I²S Format
4.5.2 Left-Justified
ADC/DAC_LRCK
L eft C h a n n el
Rig ht C h a n n el
ADC/DAC_SCLK
DAC_SDINx
ADC_SDOUTx
MSB
LS B
M SB
MSB
LS B
AOUT 2, 4, 6 or 8
AIN 2, 4, or 6
AOUT 1, 3, 5 or 7
AIN 1, 3, or 5
Figure 16. Left Justified Format
4.5.3 Right Justified
ADC/DAC_LRCK
L eft C h a n n el
R ig ht C h a n n el
ADC/DAC_SCLK
DAC_SDINx
ADC_SDOUTx
M SB
MSB
LSB
LSB
AOUT 2, 4, 6 or 8
AIN 2, 4, or 6
AOUT 1, 3, 5 or 7
AIN 1, 3, or 5
Figure 17. Right Justified Format
4.5.4 OLM #1
OLM #1 serial audio interface format operates in single or double-speed mode only and will master or slave ADC/DAC_SCLK at 128 Fs.
ADC/DAC_LRCK
64 clks
64 clks
Left Channel
Right Channel
ADC/DAC_SCLK
DAC_SDIN1
DAC_SDIN4
MSB
LSB MSB
LSB MSB
LSB
AOUT1
AOUT3
AOUT5
20 clks
20 clks
20 clks
MSB
LSB MSB
LSB MSB
LSB
AOUT2
AOUT4
AOUT6
20 clks
20 clks
20 clks
AOUT7
AOUT8
20 clks
20 clks
AIN1
AIN3
AIN5
AIN2
AIN4
AIN6
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
ADC_SDOUT1
MSB
Figure 18. One Line Mode #1 Format
34
DS648PP2
4.5.5 OLM #2
OLM #2 serial audio interface format operates in single or double-speed mode and will master
or slave ADC/DAC_SCLK at 256Fs.
128 clks
128 clks
Left Channel
ADC/DAC_LRCK
Right Channel
ADC/DAC_SCLK
MSB
DAC_SDIN1
DAC_SDIN4
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB
AOUT1
AOUT3
AOUT5
AOUT2
AOUT4
AOUT6
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
AOUT7
AOUT8
24 clks
24 clks
AIN1
AIN3
AIN5
AIN2
AIN4
AIN6
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
ADC_SDOUT1
MSB
Figure 19. One Line Mode #2 Format
4.5.6 TDM
Data is received most significant bit (MSB) first, on the second rising edge of the DAC_SCLK
occurring after a DAC_LRCK rising edge. All data is valid on the rising edge of DAC_SCLK. The
AIN1 MSB is transmitted early but is guaranteed valid for a specified time after SCLK rises. All
other bits are transmitted on the falling edge of ADC_SCLK. Each time slot is 32 bits wide, with
the valid data sample left justified within the time slot. Valid data lengths are 16, 18, 20, or 24.
ADC/DAC_SCLK must operate at 256Fs. ADC/DAC_LRCK identifies the start of a new frame
and is equal to the sample rate, Fs.
ADC/DAC_LRCK is sampled as valid on the rising ADC/DAC_SCLK edge preceding the most
significant bit of the first data sample and must be held valid for at least 1 ADC/DAC_SCLK period.
NOTE: The ADC does not meet the timing requirements for proper operation in Quad-Speed
Mode.
256 clks
Bit or Word Wide
ADC/DAC_LRCK
ADC/DAC_SCLK
DAC_SDIN1
LSB MSB
LSB MSB
AOUT1
32 clks
ADC_SDOUT1
MSB
LSB MSB
AOUT2
LSB MSB
AOUT3
LSB MSB
AOUT4
LSB MSB
AOUT5
LSB MSB
AOUT6
LSB MSB
LSB MSB
AOUT7
AOUT8
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AUX1
AUX2
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 20. TDM Format
DS648PP2
35
4.5.7 I/O Channel Allocation
Digital
Input/Output
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
ADC_SDOUT1
ADC_SDOUT2
ADC_SDOUT3
Interface
Format
I²S, LJ, RJ
OLM
TDM
I²S, LJ, RJ
OLM
TDM
I²S, LJ, RJ
OLM
TDM
I²S, LJ, RJ
OLM
TDM
I²S, LJ, RJ
OLM
TDM
I²S, LJ, RJ
OLM
TDM
I²S, LJ, RJ
OLM
TDM
Analog Output/Input Channel Allocation
from/to Digital I/O
AOUT 1,2
AOUT 1,2,3,4,5,6
AOUT 1,2,3,4,5,6,7,8
AOUT 3,4
Not Used
Not Used
AOUT 5,6
Not Used
Not Used
AOUT 7,8
AOUT 7,8
Not Used
AIN 1,2
AIN 1,2,3,4,5,6
AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)
AIN 3,4
Not Used
Not Used
AIN 5,6
Not Used
Not Used
Table 9. Serial Audio Interface Channel Allocations
36
DS648PP2
4.6
AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or
S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate at 64xFs, where Fs is equal to the ADC sample rate (ADC_LRCK). If the AUX_SDIN signal is not
being used, it should be tied to AGND via a pull-down resistor.
The AUX port will operate in either the Left Justified or I²S digital interface format with bit depths ranging
from 16 to 24 bits. Settings for the AUX port are made through the register “Interface Formats (address
04h)” on page 47.
4.6.1 I²S
AUX_LRCK
L eft C h a n n el
R ig ht C h a n n el
AUX_SCLK
AUX_SDIN
MSB
M SB
LS B
MSB
LS B
AUX2
AUX1
Figure 21. AUX I²S Format
4.6.2 Left Justified
AUX_LRCK
L e ft C h a n n el
R ig ht C h a n n el
AUX_SCLK
AUX_SDIN
MSB
LS B
M SB
LS B
MSB
AUX2
AUX1
Figure 22. AUX Left Justified Format
DS648PP2
37
4.7
Control Port Description and Timing
The control port is used to access the registers allowing the CS42448 to be configured for the desired
operational modes and formats. The operation of the control port may be completely asynchronous with
respect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port has 2 modes: SPI and I²C, with the CS42448 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C
mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.7.1 SPI Mode
In SPI mode, CS is the CS42448 chip select signal, CCLK is the control port bit clock (input into
the CS42448 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK
and out on the falling edge.
Figure 23 shows the operation of the control port in SPI mode. To write to a register, bring CS
low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is
a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory
Address Pointer (MAP), which is set to the address of the register that is to be updated. The next
eight bits are the data which will be placed into the register designated by the MAP. During
writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a
47 kΩ resistor, if desired.
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR
is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP
will autoincrement after each byte is read or written, allowing block reads or writes of successive
registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle
which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR)
may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set
the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the adCS
CC LK
C H IP
ADDRESS
C D IN
1001111
MAP
MSB
R/W
C H IP
ADDRESS
DATA
b y te 1
High Impedance
CDOUT
LSB
1001111
R/W
b y te n
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 23. Control Port Timing in SPI Mode
38
DS648PP2
dressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is
set to 1, the data for successive registers will appear consecutively.
4.7.2 I2C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock,
SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the
pins is sensed while the CS42448 is being reset.
The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising
transition while the clock is high. All other transitions of SDA occur while the clock is low. The
first byte sent to the CS42448 after a Start condition consists of a 7 bit chip address field and a
R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at
10010. To communicate with a CS42448, the chip address field, which is the first byte sent to
the CS42448, should match 10010 followed by the settings of the AD1 and AD0. The eighth bit
of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address
Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42448 after each input byte is read, and is input
to the CS42448 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
MAP BYTE
0 AD1 AD0 0
INCR
6
5
4
3
2
1
0
ACK
7
6
ACK
1
DATA +n
DATA +1
DATA
0
7
6
1
0
7
6
1
0
ACK
ACK
STOP
START
Figure 24. Control Port Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
STOP
MAP BYTE
0 AD1 AD0 0
INCR
6
ACK
START
5
4
3
2
1
CHIP ADDRESS (READ)
1
0
0
0
ACK
1
DATA
0 AD1 AD0 1
7
ACK
START
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 25. Control Port Timing, I²C Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble.
As shown in Figure 25, the write operation is aborted after the acknowledge for the MAP byte
by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10010xx0 (chip address & write operation).
Receive acknowledge bit.
DS648PP2
39
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
4.8
Interrupts
The CS42448 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may be configured as an active low or active high
CMOS driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple peripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Status
(address 19h) (Read Only)” on page 54. Each source may be masked off through mask register bits. In
addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option
of level sensitive or edge sensitive modes within the microcontroller, many different configurations are
possible, depending on the needs of the system designer.
4.9
Recommended Power-up Sequence
1) Hold RST low until the power supply is stable. In this state, the control port is reset to its default settings and VQ will remain low.
2) Bring RST high. The device will initially be in a low power state with VQ low. All features will
default as described in the “Register Quick Reference” on page 42.
3) Perform a write operation to the Power Control register (“Power Control (address 02h)” on
page 45) to set bit 0 to a ‘1’b. This will place the device in a power down state.
4) Load the desired register settings while keeping the PDN bit set to ‘1’b.
5) Start MCLK to the appropriate frequency, as discussed in section 4.4 on page 32. The device
will initiate the power up sequence.
6) Set the PDN bit in the power control register to ‘0’b. VQ will ramp to approximately VA/2 according to the Popguard® specification in section Note 4.3.3 on page 30.
7) Apply ADC/DAC_LRCK, ADC/DAC_SCLK and DAC_SDINx. Following approximately 2000
sample periods, the device is initialized and ready for normal operation.
4.10
Reset and Power-up
It is recommended that reset be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power glitch related issues.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the ADC/DAC_FILT+
40
DS648PP2
pins. A time delay of approximately 400 ms is required after applying power to the device or after exiting
a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
4.11
Power Supply, Grounding, and PCB layout
As with any high resolution converter, the CS42448 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power
arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run
from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead.
In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42448
as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on
the same side of the board as the CS42448 to minimize inductance effects. All signals, especially clocks,
should be kept away from the ADC/DAC_FILT+, VQ pins in order to avoid unwanted coupling into the
modulators. The ADC/DAC_FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from ADC/DAC_FILT+ and AGND. The CDB42448 evaluation board
demonstrates the optimum layout and power supply arrangements.
For optimal heat dissipation from the package, it is recommended that the area directly under the part be
filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the backside ground is also recommended.
DS648PP2
41
5 REGISTER QUICK REFERENCE
NOTE: The default value in all “Reserved” registers must be preserved.
Addr Function
01h
7
6
5
4
3
2
1
0
Chip_ID3
Chip_ID2
Chip_ID1
Chip_ID0
Rev_ID3
Rev_ID2
Rev_ID1
Rev_ID0
0
0
0
1
0
0
0
1
Power Control
p 45
default
PDN_ADC3
PDN_ADC2
PDN_ADC1
PDN_DAC4
PDN_DAC3
0
0
0
0
0
0
0
0
Functional
Mode
p 46
default
DAC_FM1
DAC_FM0
ADC_FM1
ADC_FM0
MFreq2
MFreq1
MFreq0
Reserved
1
1
1
1
0
0
0
0
Interface
Formats
p 47
default
FREEZE
AUX_DIF
DAC_DIF2
DAC_DIF1
DAC_DIF0
ADC_DIF2
ADC_DIF1
ADC_DIF0
0
0
1
1
0
1
1
0
ADC Control ADC1-2_HPF
FREEZE
(w/DAC_DEM)
p 49
default
0
ADC3_HPF
FREEZE
DAC_DEM
ADC1
SINGLE
ADC2
SINGLE
ADC3
SINGLE
AIN5_MUX
AIN6_MUX
0
0
0
0
0
0
0
Transition
Control
p 50
default
DAC_SNG
VOL
DAC_SZC1
DAC_SZC0
AMUTE
MUTE
ADC_SP
ADC_SNG
VOL
ADC_SZC1
ADC_SZC0
0
0
0
1
0
0
0
0
AOUT8
MUTE
AOUT7
MUTE
AOUT6
MUTE
AOUT5
MUTE
AOUT4
MUTE
AOUT3
MUTE
AOUT2
MUTE
AOUT1
MUTE
0
0
0
0
0
0
0
0
Vol. Control
AOUT1
p 52
default
AOUT1
VOL7
AOUT1
VOL6
AOUT1
VOL5
AOUT1
VOL4
AOUT1
VOL3
AOUT1
VOL2
AOUT1
VOL1
AOUT1
VOL0
0
0
0
0
0
0
0
0
Vol. Control
AOUT2
p 52
default
AOUT2
VOL7
AOUT2
VOL6
AOUT2
VOL5
AOUT2
VOL4
AOUT2
VOL3
AOUT2
VOL2
AOUT2
VOL1
AOUT2
VOL0
0
0
0
0
0
0
0
0
Vol. Control
AOUT3
p 52
default
AOUT3
VOL7
AOUT3
VOL6
AOUT3
VOL5
AOUT3
VOL4
AOUT3
VOL3
AOUT3
VOL2
AOUT3
VOL1
AOUT3
VOL0
0
0
0
0
0
0
0
0
Vol. Control
AOUT4
p 52
default
AOUT4
VOL7
AOUT4
VOL6
AOUT4
VOL5
AOUT4
VOL4
AOUT4
VOL3
AOUT4
VOL2
AOUT4
VOL1
AOUT4
VOL0
0
0
0
0
0
0
0
0
Vol. Control
AOUT5
p 52
default
AOUT5
VOL7
AOUT5
VOL6
AOUT5
VOL5
AOUT5
VOL4
AOUT5
VOL3
AOUT5
VOL2
AOUT5
VOL1
AOUT5
VOL0
0
0
0
0
0
0
0
0
Vol. Control
AOUT6
p 52
default
AOUT6
VOL7
AOUT6
VOL6
AOUT6
VOL5
AOUT6
VOL4
AOUT6
VOL3
AOUT6
VOL2
AOUT6
VOL1
AOUT6
VOL0
0
0
0
0
0
0
0
0
Vol. Control
AOUT7
p 52
default
AOUT7
VOL7
AOUT7
VOL6
AOUT7
VOL5
AOUT7
VOL4
AOUT7
VOL3
AOUT7
VOL2
AOUT7
VOL1
AOUT7
VOL0
0
0
0
0
0
0
0
0
Vol. Control
AOUT8
p 52
default
AOUT8
VOL7
AOUT8
VOL6
AOUT8
VOL5
AOUT8
VOL4
AOUT8
VOL3
AOUT8
VOL2
AOUT8
VOL1
AOUT8
VOL0
0
0
0
0
0
0
0
0
ID
p 44
02h
03h
04h
05h
06h
07h
Channel
Mute
p 52
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
42
default
default
DAC Chan- INV_AOUT8
nel Invert
p 53
default
0
INV_AOUT7
0
PDN_DAC2 PDN_DAC1
INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2
0
0
0
0
0
PDN
INV_AOUT1
0
DS648PP2
Addr Function
7
6
5
4
3
2
1
0
11h
Vol. Control
AIN1
p 52
default
AIN1
VOL7
AIN1
VOL6
AIN1
VOL5
AIN1
VOL4
AIN1
VOL3
AIN1
VOL2
AIN1
VOL1
AIN1
VOL0
0
0
0
0
0
0
0
0
12h
Vol. Control
AIN2
p 53
default
AIN2
VOL7
AIN2
VOL6
AIN2
VOL5
AIN2
VOL4
AIN2
VOL3
AIN2
VOL2
AIN2
VOL1
AIN2
VOL0
0
0
0
0
0
0
0
0
13h
Vol. Control
AIN3
p 52
default
AIN3
VOL7
AIN3
VOL6
AIN3
VOL5
AIN3
VOL4
AIN3
VOL3
AIN3
VOL2
AIN3
VOL1
AIN3
VOL0
0
0
0
0
0
0
0
0
14h
Vol. Control
AIN4
p 53
default
AIN4
VOL7
AIN4
VOL6
AIN4
VOL5
AIN4
VOL4
AIN4
VOL3
AIN4
VOL2
AIN4
VOL1
AIN4
VOL0
0
0
0
0
0
0
0
0
15h
Vol. Control
AIN5
p 52
default
AIN5
VOL7
AIN5
VOL6
AIN5
VOL5
AIN5
VOL4
AIN5
VOL3
AIN5
VOL2
AIN5
VOL1
AIN5
VOL0
0
0
0
0
0
0
0
0
16h
Vol. Control
AIN6
p 53
default
AIN6
VOL7
AIN6
VOL6
AIN6
VOL5
AIN6
VOL4
AIN6
VOL3
AIN6
VOL2
AIN6
VOL1
AIN6
VOL0
0
0
0
0
0
0
0
0
17h
ADC Channel Invert
p 53
default
Reserved
Reserved
INV_A6
INV_A5
INV_A4
INV_A3
INV_A2
INV_A1
0
0
0
0
0
0
0
0
18h
Status Control
p 54
default
Reserved
Reserved
Reserved
Reserved
INT1
INT0
Reserved
Reserved
0
0
0
0
0
0
0
0
19h
Status
Reserved
Reserved
Reserved
DAC_CLK
Error
ADC_CLK
Error
ADC3
OVFL
ADC2
OVFL
ADC1
OVFL
1Ah
Status Mask
1Bh
MUTEC
p 55
default
p 54
p 55
DS648PP2
default
default
0
0
0
X
X
X
X
X
Reserved
Reserved
Reserved
DAC_CLK
Error_M
ADC_CLK
Error_M
ADC3
OVFL_M
ADC2
OVFL_M
ADC1
OVFL_M
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MCPolarity
MUTEC Active
0
0
0
0
0
0
0
0
43
6 REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which
are read only. See the following bit definition tables for bit assignment information. The default state of
each bit after a power-up sequence or reset is listed in each bit description.
6.1
MEMORY ADDRESS POINTER (MAP)
Not a register
7
6
5
4
3
2
1
0
INCR
MAP6
MAP5
MAP4
MAP3
MAP2
MAP1
MAP0
6.1.1
INCREMENT(INCR)
Default = 1
Function:
Memory address pointer auto increment control
0 - MAP is not incremented automatically.
1 - Internal MAP is automatically incremented after each read or write.
6.1.2
MEMORY ADDRESS POINTER (MAP[6:0])
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control
port.
6.2
CHIP I.D. AND REVISION REGISTER (ADDRESS 01H) (READ ONLY)
7
Chip_ID3
6
Chip_ID2
6.2.1
5
Chip_ID1
4
Chip_ID0
3
Rev_ID3
2
Rev_ID2
1
Rev_ID1
0
Rev_ID0
CHIP I.D. (CHIP_ID[3:0])
Default = 0001
Function:
I.D. code for the CS42448. Permanently set to 0001.
6.2.2
CHIP REVISION (REV_ID[3:0])
Default = 0001
Function:
CS42448 revision level. Revision A is coded as 0001.
44
DS648PP2
6.3
POWER CONTROL (ADDRESS 02H)
7
6
5
4
3
2
1
0
PDN_ADC3
PDN_ADC2
PDN_ADC1
PDN_DAC4
PDN_DAC3
PDN_DAC2
PDN_DAC1
PDN
6.3.1
POWER DOWN ADC PAIRS(PDN_ADCX)
Default = 0
0 - Disable
1 - Enable
Function:
When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3
- AIN5/AIN6) will remain in a reset state.
6.3.2
POWER DOWN DAC PAIRS (PDN_DACX)
Default = 0
0 - Disable
1 - Enable
Function:
When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4;
DAC3 - AOUT5/AOUT6; and DAC4 - AOUT7/AOUT8) will remain in a reset state. It is advised that
any change of these bits be made while the DACs are muted or the power down bit (PDN) is enabled
to eliminate the possibility of audible artifacts.
6.3.3
POWER DOWN (PDN)
Default = 0
0 - Disable
1 - Enable
Function:
The entire device will enter a low-power state when this function is enabled. The contents of the control registers are retained in this mode.
DS648PP2
45
6.4
FUNCTIONAL MODE (ADDRESS 03H)
7
6
5
4
3
2
1
0
DAC_FM1
DAC_FM0
ADC_FM1
ADC_FM0
MFreq2
MFreq1
MFreq0
Reserved
6.4.1
DAC FUNCTIONAL MODE (DAC_FM[1:0])
Default = 11
Master Mode
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
Slave Mode
11 - (Auto-detect sample rates)
Function:
Selects the required range of sample rates for the DAC serial port.
6.4.2
ADC FUNCTIONAL MODE (ADC_FM[1:0])
Default = 11
Master Mode
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
Slave Mode
11 - (Auto-detect sample rates)
Function:
Selects the required range of sample rates for the ADC serial port.
6.4.3
MCLK FREQUENCY (MFREQ[2:0])
Default = 000
Function:
Sets the appropriate frequency for the supplied MCLK. For TDM and OLM #2 operation,
ADC/DAC_SCLK must equal 256Fs. For OLM #1 operation, ADC/DAC_SCLK must equal 128Fs.
MCLK can be equal to or greater than the higher frequency of ADC_SCLK or DAC_SCLK.
MFreq2
MFreq1
MFreq0
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Description
1.0290 MHz to 12.8000 MHz
1.5360 MHz to 19.2000 MHz
2.0480 MHz to 25.6000 MHz
3.0720 MHz to 38.4000 MHz
4.0960 MHz to 51.2000 MHz
SSM
256
384
512
768
1024
Ratio (xFs)
DSM
QSM
128
64
192
96
256
128
384
192
512
256
Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats
46
DS648PP2
MFreq2
MFreq1
MFreq0
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Description
1.0290 MHz to 12.8000 MHz
1.5360 MHz to 19.2000 MHz
2.0480 MHz to 25.6000 MHz
3.0720 MHz to 38.4000 MHz
4.0960 MHz to 51.2000 MHz
SSM
256
384
512
768
1024
Ratio (xFs)
DSM
QSM
N/A
N/A
N/A
N/A
256
N/A
384
N/A
512
256
Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats
6.5
INTERFACE FORMATS (ADDRESS 04H)
7
6
5
4
3
2
1
0
FREEZE
AUX_DIF
DAC_DIF2
DAC_DIF1
DAC_DIF0
ADC_DIF2
ADC_DIF1
ADC_DIF0
6.5.1
FREEZE CONTROLS (FREEZE)
Default = 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to the channel
mutes, the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect
until the FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
6.5.2
AUXILIARY DIGITAL INTERFACE FORMAT (AUX_DIF)
Default = 0
0 - Left Justified
1 - I²S
Function:
This bit selects the digital interface format used for the AUX Serial Port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in Figures 21-22.
6.5.3
DAC DIGITAL INTERFACE FORMAT (DAC_DIF[2:0])
Default = 110
Function:
These bits select the digital interface format used for the DAC Serial Port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in the section “CODEC Digital Interface Formats” on page 32.
Refer to Table 9. “Serial Audio Interface Channel Allocations” on page 36.
DS648PP2
47
DAC_DIF2
DAC_DIF1
DAC_DIF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Description
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 24-bit data
Right Justified, 16-bit data
One-Line #1, 20-bit
One-Line #2, 24-bit
TDM Mode, 24-bit (slave only)
Reserved
Format
Figure
0
1
2
3
4
5
6
-
16 on page 34
15 on page 34
17 on page 34
17 on page 34
18 on page 34
19 on page 35
20 on page 35
-
Table 12. DAC Digital Interface Formats
6.5.4
ADC DIGITAL INTERFACE FORMAT (ADC_DIF[2:0])
Default = 110
Function:
These bits select the digital interface format used for the ADC serial port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in the section “CODEC Digital Interface Formats” on page 32. Refer to Table
9. “Serial Audio Interface Channel Allocations” on page 36.
NOTE: The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format.
ADC_DIF2
ADC_DIF1
ADC_DIF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Description
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 24-bit data
Right Justified, 16-bit data
One-Line #1, 20-bit
One-Line #2, 24-bit
TDM Mode, 24-bit (slave only)
Reserved
Format
Figure
0
1
2
3
4
5
6
-
16 on page 34
15 on page 34
17 on page 34
17 on page 34
18 on page 34
19 on page 35
20 on page 35
-
Table 13. ADC Digital Interface Formats
48
DS648PP2
6.6
ADC CONTROL & DAC DE-EMPHASIS (ADDRESS 05H)
7
6
5
4
3
2
1
0
ADC1-2_HPF
FREEZE
ADC3_HPF
FREEZE
DAC_DEM
ADC1
SINGLE
ADC2
SINGLE
ADC3
SINGLE
AIN5_MUX
AIN6_MUX
6.6.1
ADC1-2 HIGH PASS FILTER FREEZE (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC
offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital
Filter Characteristics” on page 14.
6.6.2
ADC3 HIGH PASS FILTER FREEZE (ADC3_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value
will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Characteristics” on page 14.
6.6.3
DAC DE-EMPHASIS CONTROL (DAC_DEM)
Default = 0
0 - No De-Emphasis
1 - De-Emphasis Enabled (Auto-Detect Fs)
Function:
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless
of this register setting, at any other sample rate.
6.6.4
ADC1 SINGLE-ENDED MODE (ADC1 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC1
1 - Enabled; Single-Ended input to ADC1
Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1.
+6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be
driven to the common mode of the ADC. See Figure 27 on page 56 for a graphical description.
6.6.5
ADC2 SINGLE-ENDED MODE (ADC2 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC2
1 - Enabled; Single-Ended input to ADC2
DS648PP2
49
Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2.
+6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be
driven to the common mode of the ADC. See Figure 27 on page 56 for a graphical description.
6.6.6
ADC3 SINGLE-ENDED MODE (ADC3 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC
1 - Enabled; Single-Ended input to ADC
Function:
When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differential input. When enabled, this bit allows the user to choose between 4 single-ended inputs to ADC3,
using the AIN5_MUX and AIN6_MUX bits. See Figure 11 on page 27 and Figure 27 on page 56 for
graphical descriptions.
6.6.7
ANALOG INPUT CH. 5 MULTIPLEXER (AIN5_MUX)
Default = 0
0 - Single-Ended Input AIN5A
1 - Single-Ended Input AIN5B
Function:
ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX
bit selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in single-ended mode.
This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 27 for a graphical
description.
6.6.8
ANALOG INPUT CH. 6 MULTIPLEXER (AIN6_MUX)
Default = 0
0 - Single-Ended Input AIN6A
1 - Single-Ended Input AIN6B
Function:
ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX
bit selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in single-ended mode.
This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 27 for a graphical
description.
6.7
TRANSITION CONTROL (ADDRESS 06H)
7
6
5
4
DAC_SNGVOL
DAC_SZC1
DAC_SZC0
AMUTE
6.7.1
3
2
MUTE ADC_SP ADC_SNGVOL
1
0
ADC_SZC1
ADC_SZC0
SINGLE VOLUME CONTROL (DAC_SNGVOL, ADC_SNGVOL)
Default = 0
50
DS648PP2
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
registers when this function is disabled. When enabled, the volume on all channels is determined by
the AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored.
6.7.2
SOFT RAMP AND ZERO CROSS CONTROL (ADC_SZC[1:0], DAC_SZC[1:0])
Default = 00
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all volume level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or
muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change
will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of
1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing.
The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7
ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross
function is independently monitored and implemented for each channel.
6.7.3
AUTO-MUTE (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converters of the CS42448 will mute the output following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute.
Detection and muting is done independently for each channel. The quiescent voltage on the output
will be retained and the MUTEC pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).
DS648PP2
51
6.7.4
MUTE ADC SERIAL PORT (MUTE ADC_SP)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the ADC Serial Port will be muted.
6.8
DAC CHANNEL MUTE (ADDRESS 07H)
7
6
5
4
3
2
1
0
AOUT8_MUTE
AOUT7_MUTE
AOUT6_MUTE
AOUT5_MUTE
AOUT4_MUTE
AOUT3_MUTE
AOUT2_MUTE
AOUT1_MUTE
6.8.1
INDEPENDENT CHANNEL MUTE (AOUTX_MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The respective Digital-to-Analog converter outputs of the CS42448 will mute when enabled. The quiescent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and
Zero Cross bits (DAC_SZC[1:0]). When all channels are muted, the MUTEC pin will become active.
6.9
AOUTX VOLUME CONTROL (ADDRESSES 08H- 0FH)
7
6
5
4
3
2
1
0
AOUTx_VOL7
AOUTx_VOL6
AOUTx_VOL5
AOUTx_VOL4
AOUTx_VOL3
AOUTx_VOL2
AOUTx_VOL1
AOUTx_VOL0
6.9.1
VOLUME CONTROL (AOUTX_VOL[7:0])
Default = 00h
Function:
The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB increments from 0 dB to -127.5 dB. Volume settings are decoded as shown in Table 14. The volume
changes are implemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0]). All volume
settings less than -127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel.
Binary Code
Volume Setting
00000000
00101000
01010000
01111000
10110100
0 dB
-20 dB
-40 dB
-60 dB
-90 dB
Table 14. Example AOUT Volume Settings
52
DS648PP2
6.10
DAC CHANNEL INVERT (ADDRESS 10H)
7
6
5
4
3
2
1
0
INV_AOUT8
INV_AOUT7
INV_AOUT6
INV_AOUT5
INV_AOUT4
INV_AOUT3
INV_AOUT2
INV_AOUT1
6.10.1 INVERT SIGNAL POLARITY (INV_AOUTX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
6.11
AINX VOLUME CONTROL (ADDRESS 11H-16H)
7
6
5
4
3
2
1
0
AINx_VOL7
AINx_VOL6
AINx_VOL5
AINx_VOL4
AINx_VOL3
AINx_VOL2
AINx_VOL1
AINx_VOL0
6.11.1 AINX VOLUME CONTROL (AINX_VOL[7:0])
Default = 00h
Function:
The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero
Cross bits (ADC_SZC[1:0]) from +24 to -64 dB. Levels are decoded in two’s complement, as shown
in Table 15.
Binary Code
Volume Setting
0111 1111
···
0011 0000
···
0000 0000
1111 1111
1111 1110
···
1000 0000
+24 dB
···
+24 dB
···
0 dB
-0.5 dB
-1 dB
···
-64 dB
Table 15. Example AIN Volume Settings
6.12
ADC CHANNEL INVERT (ADDRESS 17H)
7
6
5
4
3
2
1
0
Reserved
Reserved
INV_AIN6
INV_AIN5
INV_AIN4
INV_AIN3
INV_AIN2
INV_AIN1
6.12.1 INVERT SIGNAL POLARITY (INV_AINX)
Default = 0
0 - Disabled
1 - Enabled
DS648PP2
53
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
6.13
STATUS CONTROL (ADDRESS 18H)
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
INT1
INT0
Reserved
Reserved
6.13.1 INTERRUPT PIN CONTROL (INT[1:0])
Default = 00
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Function:
Determines how the Interrupt pin (INT) will indicate an interrupt condition.
For DAC and ADC clock errors, the INT pin is set to “Level Active Mode” and will become active during
the clock error. For the ADCx_OVFL error, the INT pin is set to Level Active Mode and will become
active during the overflow error.
6.14
STATUS (ADDRESS 19H) (READ ONLY)
7
6
5
Reserved
Reserved
Reserved
4
3
DAC_CLK Error ADC_CLK Error
2
1
0
ADC3_OVFL
ADC2_OVFL
ADC1_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the register
was last read. A”0” means the associated error condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always
be “0” in this register.
6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to DAC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes active during the error condition. See “System Clocking” on page 32 for valid clock ratios.
6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to ADC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes active during the error condition. See “System Clocking” on page 32 for valid clock ratios.
54
DS648PP2
6.14.3 ADC OVERFLOW (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42448 ADC signal path of each of
the associated ADC’s. These status flags become active on the arrival of the error condition.
6.15
STATUS MASK (ADDRESS 1AH)
7
6
5
4
3
Reserved
Reserved
Reserved
DAC_CLK
Error_M
ADC_CLK
Error_M
2
1
0
ADC3_OVFL_M ADC2_OVFL_M ADC1_OVFL_M
Default = 00000
Function:
The bits of this register serve as a mask for the error sources found in the register “Status (address
19h) (Read Only)” on page 54. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the
corresponding bits in the Status register.
6.16
MUTEC PIN CONTROL (ADDRESS 1BH)
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MCPolarity
MUTEC
ACTIVE
6.16.1 MUTEC POLARITY SELECT (MCPOLARITY)
Default = 0
0 - Active low
1 - Active high
Function:
Determines the polarity of the MUTEC pin.
6.16.2 MUTE CONTROL ACTIVE (MUTEC ACTIVE)
Default = 0
0 - MUTEC pin is not active.
1 - MUTEC pin is active.
Function:
The MUTEC pin will go high or low (depending on the MUTEC Polarity Select bit) when this bit is enabled.
DS648PP2
55
7 APPENDIX A: EXTERNAL FILTERS
7.1
ADC Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will
reject signals within the stopband of the filter. However, there is no rejection for input signals which are
multiples of the digital passband frequency (n × 6.144 MHz), where n=0,1,2,... Refer to Figures 26 and 27
for a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to
providing the optimum source impedance for the modulators. Refer to Figures 28 and 29 for low cost, low
component count passive input filters. The use of capacitors which have a large voltage coefficient (such
as general-purpose ceramics) must be avoided since these can degrade signal linearity.
634 Ω
470 pF
C0G
4.7 µF
ADC1-3
91 Ω
-
AINx+
+
100 k Ω
634 Ω
634 Ω
VA
2700 pF
C0G
470 pF
C0G
10 k Ω
100 k Ω
91 Ω
-
AINx-
+
100 k Ω
0.1 µF
100 µF
332 Ω
Figure 26. Single to Differential Active Input Filter
634 Ω
VA
100 kΩ
470 pF
-
4.7 µF
C0G
ADC1-2
91 Ω
AIN1+,2+,3+,4+
+
100 kΩ
2700 pF
C0G
100 kΩ
4.7 µF
AIN1-,2-,3-,4-
634 Ω
VA
100 kΩ
470 pF
-
4.7 µF
C0G
ADC3
91 Ω
AIN5A,6A
+
100 kΩ
2700 pF
C0G
100 kΩ
634 Ω
VA
100 kΩ
470 pF
-
4.7 µF
C0G
91 Ω
AIN5B,6B
+
100 kΩ
100 kΩ
2700 pF
C0G
Figure 27. Single-Ended Active Input Filter
56
DS648PP2
7.1.1 Passive Input Filter
The passive filter implementation shown in Figure 28 will attenuate any noise energy at
6.144 MHz but will not provide optimum source impedance for the ADC modulators. Full analog
performance will therefore not be realized using a passive filter. Figure 28 illustrates the unity
gain, passive input filter solution. In this topology the distortion performance is affected, but the
dynamic range performance is not limited.
150 Ω
ADC1-2
10 µF
AIN1+,2+,3+,4+
2700 pF
100 kΩ
C0G
AIN1-,2-,3-,44.7 µF
150 Ω
ADC3
10 µF
AIN5A,6A
2700 pF
100 kΩ
C0G
150 Ω
10 µF
AIN5B,6B
2700 pF
100 kΩ
C0G
Figure 28. Passive Input Filter
7.1.2 Passive Input Filter w/Attenuation
Some applications may require signal attenuation prior to the ADC. The full-scale input voltage
will scale with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is
approximately 2.8 Vpp, or 1 Vrms (most consumer audio line-level outputs range from 1.5 to
2 Vrms).
Figure 29 shows a passive input filter with 6 dB of signal attenuation. Due to the relatively high
input impedance on the analog inputs, the full distortion performance cannot be realized. Also,
the resistor divider circuit will determine the input impedance into the input filter. In the circuit
shown in Figure 29, the input impedance is approximately 5 kΩ. By doubling the resistor values,
the input impedance will increase to 10 kΩ. However, in this case the distortion performance will
drop due to the increase in series resistance on the analog inputs.
DS648PP2
57
10 µF
2.5 kΩ
ADC1-2
AIN1+,2+,3+,4+
2.5 k Ω
2700 pF
C0G
AIN1-,2-,3-,44.7 µF
10 µF
2.5 kΩ
ADC3
AIN5A,6A
2.5 k Ω
2700 pF
C0G
10 µF
2.5 kΩ
AIN5B,6B
2.5 k Ω
2700 pF
C0G
Figure 29. Passive Input Filter w/Attenuation
58
DS648PP2
7.2
DAC Output Filter
The CS42448 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external
analog circuitry. Shown below is the recommended active and passive output filters.
1800 pF
DAC1-4
4.75 kΩ
390 pF
C0G
AOUTx -
5.49 kΩ
2.94 kΩ
1.65 kΩ
887 Ω
AOUTx +
C0G
+
562Ω
47.5 k Ω
1200 pF
5600 pF
C0G
22 µF
C0G
1.87 kΩ
22 µF
Figure 30. Active Analog Output Filter
DAC1-4
3.3 µF
AOUTx+
560 Ω
+
10 kΩ
C
C=
R ext
Rext+ 560
4 πFSRext560
Figure 31. Passive Analog Output Filter
DS648PP2
59
0
0
-10
-10
-20
-20
-30
-30
-40
-40
Amplitude (dB)
Amplitude (dB)
8 APPENDIX B: ADC FILTER PLOTS
-50
-60
-70
-80
-90
-100
-50
-60
-70
-80
-90
-100
-110
-110
-120
-120
-130
-130
-140
0.40
-140
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.42
0
0.10
-1
0.08
-2
0.06
-3
0.04
-4
-5
-6
0.50
0.52
0.54
0.56
0.58
0.60
-7
0.00
-0.02
-0.04
-8
-0.06
-9
-0.08
-0.10
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (normalized to Fs)
Figure 34. SSM Transition Band (Detail)
Figure 35. SSM Passband Ripple
0
0
-10
-10
-20
-20
-30
-30
-40
-40
Amplitude (dB)
Amplitude (dB)
0.48
0.02
Frequency (normalized to Fs)
-50
-60
-70
-80
-90
-100
-50
-60
-70
-80
-90
-100
-110
-110
-120
-120
-130
-130
-140
-140
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (normalized to Fs)
Figure 36. DSM Stopband Rejection
60
0.46
Figure 33. SSM Transition Band
Amplitude (dB)
Amplitude (dB)
Figure 32. SSM Stopband Rejection
-10
0.45
0.44
Frequency (normalized to Fs)
Frequency (normalized to Fs)
1.0
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 37. DSM Transition Band
DS648PP2
‘
0
0 .10
-1
0 .0 8
0 .0 6
Amplitude (dB)
Amplitude (dB)
-2
-3
-4
-5
-6
-7
0 .0 4
0 .0 2
0 .0 0
-0 .0 2
-0 .0 4
-0 .0 6
-8
-0 .0 8
-9
-10
0.46
-0 .10
0 .0 0
0.47
0.48
0.49
0.50
0.51
0.52
0 .10
0 .15
0 .2 0
0 .2 5
0 .3 0
0 .3 5 0 .4 0
0 .4 5
0 .50
Fr e que ncy (norm alize d to Fs )
Frequency (normalized to Fs)
Figure 38. DSM Transition Band (Detail)
Figure 39. DSM Passband Ripple
0
0
-10
-2 0
-3 0
-4 0
-10
-2 0
-3 0
Amplitude (dB)
Amplitude (dB)
0 .0 5
-50
-6 0
-70
-8 0
-9 0
-10 0
-110
-4 0
-50
-6 0
-70
-8 0
-9 0
-10 0
-110
-12 0
-13 0
-14 0
-12 0
-13 0
-14 0
0 .0
0 .1
0 .2
0 .3
0 .4
0 .5
0 .6
0 .7
0 .8
0 .9
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
1.0
Fre que ncy (norm alize d to Fs )
Fre que ncy (norm alize d to Fs )
Figure 40. QSM Stopband Rejection
Figure 41. QSM Transition Band
0 .10
-2
0 .0 8
-3
0 .0 6
Amplitude (dB)
Amplitude (dB)
0
-1
-4
-5
-6
-7
-8
0 .0 4
0 .0 2
0 .0 0
-0 .0 2
-0 .0 4
-0 .0 6
-9
-0 .0 8
-10
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 42. QSM Transition Band (Detail)
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-0 .10
0 .0 0 0 .0 3 0 .0 5 0 .0 8 0 .10
0 .13
0 .15 0 .18 0 .2 0 0 .2 3 0 .2 5 0 .2 8
Fr e que ncy (norm alize d to Fs )
Figure 43. QSM Passband Ripple
61
9 APPENDIX C: DAC FILTER PLOTS
Figure 45. SSM Transition Band
Figure 46. SSM Transition Band (detail)
Figure 47. SSM Passband Ripple
0
0
-10
-10
-20
-20
-30
-30
-40
-40
Amplitude dB
Amplitude dB
Figure 44. SSM Stopband Rejection
-50
-60
-70
-80
-90
-90
-100
-100
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (normalized to Fs)
Figure 48. DSM Stopband Rejection
62
-60
-70
-80
0.0
-50
1.0
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 49. DSM Transition Band
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0
0.30
-1
0.25
0.20
-2
0.15
-3
0.10
Amplitude dB
Amplitude dB
-4
-5
-6
-7
0.05
0.00
-0.05
-0.10
-0.15
-8
-0.20
-9
-0.25
-0.30
-10
0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.00
0.55
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 50. DSM Transition Band (detail)
Figure 51. DSM Passband Ripple
0
0
-10
-10
-20
-30
-20
Amplitude (dB)
Amplitude (dB)
-40
-50
-60
-30
-40
-70
-50
-80
-90
-60
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
1
Figure 52. QSM Stopband Rejection
0.35
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
0.7
0.75
Figure 53. QSM Transition Band
0
0.2
-5
0.15
-10
0.1
0.05
-20
Amplitude (dB)
Amplitude (dB)
-15
-25
-30
0
-0.05
-35
-0.1
-40
-0.15
-45
-0.2
-50
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
0.7
Figure 54. QSM Transition Band (detail)
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0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
Figure 55. QSM Passband Ripple
63
10 PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel.
Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
64
DS648PP2
11 REFERENCES
1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997.
http://www.cirrus.com/products/papers/meas/meas.html
2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997.
4) Cirrus Logic, A Stereo 16-bit delta-sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del
Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th
Convention of the Audio Engineering Society, November 1988.
5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters,
and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of
the Audio Engineering Society, October 1989.
6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling delta-sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989.
7) Cirrus Logic, How to Achieve Optimum Performance from delta-sigma A/D and D/A Converters,by
Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.
8) Cirrus Logic, A Fifth-Order Delta-sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori,
K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
9) Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
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65
12 PACKAGE INFORMATION
64L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.461
0.390
0.461
0.390
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
0.55
0.004
0.008
0.472 BSC
0.393 BSC
0.472 BSC
0.393 BSC
0.020 BSC
0.024
4°
MAX
0.063
0.006
0.011
0.484
0.398
0.484
0.398
0.024
0.030
7.000°
MILLIMETERS
NOM
1.40
0.10
0.20
12.0 BSC
10.0 BSC
12.0 BSC
10.0 BSC
0.50 BSC
0.60
4°
MIN
--0.05
0.17
11.70
9.90
11.70
9.90
0.40
0.45
0.00°
MAX
1.60
0.15
0.27
12.30
10.10
12.30
10.10
0.60
0.75
7.00°
Controlling dimension is mm.
JEDEC Designation: MS026
12.1
Thermal Characteristics
Parameter
Junction to Ambient Thermal Impedance
66
2 Layer Board
4 Layer Board
Symbol
Min
Typ
Max
Units
θJA
θJA
-
50
37
-
°C/Watt
°C/Watt
DS648PP2
13 ORDERING INFORMATION
Product
Description
CS42448
6-in, 8-out CODEC for Sur64L-LQFP
round Sound Apps
CDB42448 CS42448 Evaluation Board
DS648PP2
Package
-
Pb-Free
YES
-
Grade
Temp Range
Container
Rail
Commercial -10° to +70° C
Tape & Reel
Rail
Automotive -40° to +85° C
Tape & Reel
-
Order #
CS42448-CQZ
CS42448-CQZR
CS42448-DQZ
CS42448-DQZR
CDB42448
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14 REVISION HISTORY
Revision
Date
Changes
A1
July 2004
Initial Release
A2
October 2004
Corrected I²C Address in section 4.7.2 on page 39.
Corrected Chip I.D. in section 6.2.1 on page 44.
PP1
January 2005
Initial Preliminary Product (PP) Release subject to legal notice below.
Added pin numbers to “Typical Connection Diagram” on page 10.
Changed ADC TDM, Double-Speed Mode parameters. See Note 2 on page 11
and Note 18 on page 21.
Added ADC3 MUX Interchannel Isolation characteristic in section “Characteristics and Specifications” beginning on page 11.
Changed SCLK Falling Edge to ADC_SDOUT Output Valid (tdpd) maximum
specification to 35 ns in section “Characteristics and Specifications” beginning
on page 11.
Changed ADC Passband Ripple maximum specifications for SSM, DSM &
QSM in section “Characteristics and Specifications” beginning on page 11.
Changed DAC Frequency Response specifications for SSM, DSM & QSM in
section “Characteristics and Specifications” beginning on page 11.
Changed ADC Quad-Speed Mode parameters. See Note 19 on page 21.
Added section “De-Emphasis Filter” on page 31.
Added SCLK/LRCK & MCLK/LRCK ratio parameters in Tables 5 - 8 on page
33.
Corrected section “TDM” on page 35.
Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB
to -64 dB) in register “AINx Volume Control (AINx_VOL[7:0])” on page 53.
Removed the “Error Mode (MODE[1:0])” control bits from register “Status Control (address 18h)” on page 54. See “Interrupt Pin Control (INT[1:0])” on
page 54, “ADC CLOCK ERROR (ADC_CLK Error)” on page 54 and “ADC
Overflow (ADCX_OVFL)” on page 55 for the Active Mode setting.
PP2
February 2005
Corrected Figures 27-29.
Added section “Ordering Information” on page 67.
Table 16. Revision History
68
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Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com/
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic,
Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version
of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the
terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of
liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale
of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information,
Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property
rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying
such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE
BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF
CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND
MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER
OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES,
BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE
USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard® are trademarks of Cirrus Logic, Inc. All other brand and product names in this
document may be trademarks or service marks of their respective owners.
SPI is a registered trademark of Motorola, Inc.
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70
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