SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 FEATURES D UL1950 Recognized D DIP-18 and SO-10 Packages D 55W/in 3 (3.3W/cm3) Power Density D Device-to-Device Synchronization D Thermal Protection D 1000Vrms Isolation D 400kHz Switching D 125 FITS at 55°C D Short-Circuit Protection D 12V, 24V Inputs D 5V Outputs APPLICATIONS D Point-of-Use Power Conversion D Digital Interface Power D Ground Loop Elimination D Power-Supply Noise Reduction DESCRIPTION The DCR02 family is a series of high-efficiency, input-isolated, output-regulated DC/DC converters. In addition to 2W nominal, galvanically-isolated output power capability, this range of converters offers very low output noise and high accuracy. The DCR02 family is implemented in standard molded IC packaging, providing standard JEDEC outlines suitable for high-volume assembly. The DCR is manufactured using the same technology as standard IC packages, thereby achieving very high reliability. VREC SYNC ENABLE VS Input LDO Controller R egulator ERROR VOUT 0VIN 0VOUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2000−2004, Texas Instruments Incorporated ! "# $ " %&$ ' !$ $"# %$"$ % ( # " ) # *+' !$ %$ , $ + $ , " %# ' www.ti.com www.ti.com SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DIP−18 NVE −40°C to +70°C DCR021205P DCR021205P Rail, 20 SO−10(2) DVS −40°C to +70°C DCR021205P−U DCR021205P−U Rail, 20 SO−10(2) DVS −40°C to +70°C DCR021205P−U DCR021205P−U/700 Tape and Reel, 700 DIP−18 NVE −40°C to +70°C DCR022405P DCR022405P Rail, 20 SO−10(2) DVS −40°C to +70°C DCR022405P−U DCR022405P−U Rail, 20 SO−10(2) DVS −40°C to +70°C DCR022405P−U DCR022405P−U/700 Tape and Reel, 700 DCR021205 DCR022405 (1) For the most current package and ordering information, refer to our web site at www.ti.com. (2) SO−10 packages have 18 pins, but only 10 pins are active. SUPPLEMENTAL ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) DCR02 12 05 (P) Basic Model Number: 1W Product Voltage Input: 12V In Voltage Output: 5V Out Package Code: P = 18-Pin Plastic DIP P-U = SO-10 Input Voltage 29 V −60 to +125 °C Terminal Functions TERMINAL NAME VS 1 18 SYNC NC 2 17 0VIN DCR02 12 ERROR 0VOUT 8 11 ENABLE VO 9 10 DNC NO. I/O DESCRIPTION VS 1 I NC 2 VREC 7 O Rectified output 0VOUT 8 O Output ground VO 9 O Voltage output DNC 10 Voltage input No connection Do not connect ENABLE 11 O Output voltage enable ERROR 12 O Error flag active low 0VIN 17 I Input ground SYNC 18 I Synchronization input NOTE: I = input and O = output. 2 V Lead Temperature (soldering, 10s) +270 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. NVE and DVS PACKAGES (TOP VIEW) 7 UNIT 15 DCR0224 Storage Temperature PIN ASSIGNMENTS VREC DCR02 SERIES DCR0212 www.ti.com SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = nominal, IOUT = 10mA, COUT = 0.1µF ceramic, and CIN = 2.2µF ceramic, unless otherwise noted(1). DCR02 SERIES PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output Setpoint DCR021205 5 V DCR022405 5 V Setpoint accuracy Maximum Output Current 0.5 % 400 mA DCR022405 400 mA Output short-circuit protected Line regulation 2.0 DCR021205 Duration Infinite DCR021205 1 mV/V DCR022405 1 mV/V Over line and load 10mA to 400mA load, over input voltage range 1.0 Versus temperature −40°C to +70°C 1.0 % 20MHz bandwidth, 50% load(1) 100MHz bandwidth, 50% load(1) 18 mVPP mVPP 20MHz bandwidth, 50% load(1) 100MHz bandwidth, 50% load(1) 18 DCR0212 ripple DCR0212 noise Ripple and noise DCR0224 ripple DCR0224 noise 2.5 20 % 25 mVPP mVPP 12 V Input DCR021205 Nominal voltage, VS DCR022405 24 Voltage range −10 DCR021205 Supply current DCR022405 % IO = 0mA IO = 10mA 15 mA 23 mA IO = 400mA IO = 0mA 250 mA 15 mA IO = 10mA IO = 400mA 17 mA 129 mA 20MHz bandwidth, 100% load(1) Reflected ripple current V +10 8 mAPP Isolation Voltage 1s flash test 1 60s test, UL1950(2) 1 Input/output capacitance kVrms kVrms 25 pF Output Enable Control Logic high input voltage 2.0 Logic high input current 2.0 < VENABLE < VREC Logic low input voltage VREC 100 −0.2 Logic low input current 0 < VENABLE < 0.5 V nA 0.5 100 V nA Error Flag Logic high open collector leakage Logic low output voltage VERROR = 5V Sinking 2mA 10 µA 0.4 V Thermal Shutdown Junction temperature Temp activated +150 °C Temp deactivated +130 °C (1) Ceramic capacitors, CIN = 2.2µF, CFILTER = 1µF, and COUT = 0.1µF. (2) During UL1950 recognition test only. 3 www.ti.com SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, VS = nominal, IOUT = 10mA, COUT = 0.1µF ceramic, and CIN = 2.2µF ceramic, unless otherwise noted(1). DCR02 SERIES PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 3 pF Internal oscillator frequency 720 800 880 kHz External synchronization frequency 720 880 kHz External synchronization signal high 2.5 5.0 V 0 0.4 V −40 +70 °C Synchronization Pin Max external capacitance on SYNC pin External synchronization signal low 2.5 Temperature Range Operating (1) Ceramic capacitors, CIN = 2.2µF, CFILTER = 1µF, and COUT = 0.1µF. (2) During UL1950 recognition test only. 4 www.ti.com SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 FUNCTIONAL DESCRIPTION OVERVIEW The DCR02 series offers isolation from an unregulated power supply operating from a choice of input voltages. This series provides a variety of regulated output voltages at a nominal output power of 2W. POWER STAGE The input supply is chopped at a frequency of 400kHz (internal oscillator divided by 2), which is used to drive the center-tapped toroidal transformer. RECTIFICATION The transformer output is full wave rectified and smoothed by the external capacitor connected to VREC. REGULATOR The internal low-dropout regulator provides a well-regulated output voltage throughout the operating range of the device. OSCILLATOR AND WATCHDOG The DCR02 uses an internal saw-tooth generator to provide the 800kHz onboard oscillator that is used to drive the power switching circuit. The operation of the oscillator is monitored by the watchdog, which will tri-state the output driver circuit if the oscillator fails or if the SYNC pin is taken low (shutdown mode). When the SYNC pin is returned high, normal operation resumes. SYNCHRONIZATION If more than one DCR02 is being used, beat frequencies and other electrical interference can be generated. This interference is due to the small variations in switching frequencies between the converters. The DCR02 overcomes this by allowing devices to be synchronized to one another. Up to eight devices can be synchronized by connecting the SYNC pins together, with care being taken to minimize the capacitance of tracking. Significant stray capacitance on the SYNC pin reduces the frequency of the internal oscillator. If this reduction is large, the DCR02 may be taken out with its optimized operating parameters, and saturation of the magnetics may result, damaging the device. If devices are synchronized, it should be noted that all devices will draw maximum current simultaneously at start up. This can cause the input voltage to dip. Should it fall below the minimum input voltage, the devices may not start up. A low equivalent series resistance (ESR) 2.2µF ceramic capacitor should be connected as close to the device input pins as possible. If more than eight devices are required to be synchronized, it is recommended that external synchronization be used. Details of this procedure are contained in application report SBAA035, External Synchronization of the DCP01/02 Series of DC/DC Converters, available for download at www.ti.com. CONSTRUCTION The DCR02 is manufactured using the same technology as standard IC packages. There is no substrate within the package. The DCR02 is constructed using a driver IC, low-dropout voltage regulator, rectifier diodes, and a wound magnetic toroid, all mounted on a leadframe. The DCR02 requires no special printed circuit board (PCB) assembly processing, since there is no solder within the package. The result is an isolated DC/DC converter with inherently high reliability. 5 www.ti.com SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 DECOUPLING ADDITIONAL FUNCTIONS Ripple Reduction DISABLE/ENABLE Due to the very low forward resistance of the DMOS switching transistors, high-current demands are placed upon the input supply for a short time. By placing a good quality low ESR 2.2µF ceramic capacitor close to the IC supply input pins, the effects on the power supply can be minimized. The DCR02 can be disabled or enabled by driving the SYNC pin using an open drain CMOS gate. If the SYNC pin is pulled low, the DCR02 will be disabled. The disable time depends upon the external loading. The internal disable function is implemented in 2µs. Removal of the pull down will enable the DCR02. The high switching frequency of 400kHz allows relatively small values of capacitors to be used for filtering the rectified output voltage. A good quality, low ESR 1µF ceramic capacitor placed close to the VREC pin and output ground will reduce the ripple. Capacitance loading on the SYNC pin should be minimized in order to prevent a reduction in the internal oscillator frequency. See application report SBAA035 for information on how to nullify the effects of additional capacitance on the SYNC pin. The oscillator frequency can be measured at VREC, as this is the fundamental frequency of the ripple component. It is not recommended that the DCR02 be fitted using an IC socket because this degrades performance. The output at VREC is full wave rectified and produces a ripple of 800kHz. OUTPUT ENABLE/DISABLE It is recommended that a 0.1µF low ESR ceramic capacitor be connected close to the output pin and ground to reduce noise on the output. The capacitor values listed are minimum values. If lower ripple is required, the ceramic filter capacitor should be increased in value to 2.2µF. The regulated output of the DCR02 can be disabled by pulling the ENABLE pin low (by connecting ENABLE to 0VOUT). Holding the ENABLE pin high (connect ENABLE to VREC) enables the regulated output voltage, thus allowing the output to be controlled from the isolated side, as shown in Figure 1. NOTE: As with all switching power supplies, the best performance is only obtained with low ESR ceramic capacitors connected close to the respective buses. If low ESR ceramic capacitors are not used, the ESR will generate a voltage drop when the capacitor is supplying the load power. Often a larger capacitor is chosen for this purpose when a low ESR smaller capacitance performs just as well. ERROR FLAG The DCR02 has an ERROR pin which provides a power good flag, as long as the internal regulator is in regulation. U1 VIN VS VO1 VOUT RERR 10kΩ ERROR DCR CIN(1) 02 VREC ERROR REN 10kΩ ENABLE SYNC 0V COUT 0.1µF C FILTER 1µF 0V SW1 (see text) NOTE: (1) Required 2.2µF low ESR ceramic capacitor. Figure 1. DCR02 with a Single Output 6 0VOUT www.ti.com SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 GENERATING TWO POSITIVE OUTPUT VOLTAGES APPLICATION NOTES DCR02 SINGLE VOLTAGE OUTPUT Two DCR02s can be used to create two +5V output voltages, as shown in Figure 2. The two DCR02s are connected in self-synchronization, thus locking the oscillators of both devices to a single frequency. The DCR02 can be used to provide a single voltage output by connecting the circuit as shown in Figure 1. The ERROR output signal will be pulled up to the value of VOUT for the particular DCR02 being used. The value of RERR will depend on the loading on the ERROR line; however, the total load on the ERROR line must not exceed the value given in the specification. The ERROR and ENABLE facilities can be used in a similar configuration for a single DCR02. The filter capacitors connected to the VREC pins (CFILTER) should be kept separate from each other and connected in close proximity to the respective DCR02. If similar output voltages are being used, it is not recommended that a single filter capacitor (with an increased capacitance) be used with both VREC pins connected together, since this could result in the overloading of one of the devices. The output can be permanently enabled by connecting the ENABLE pin to the VREC pin. The DCR02 can be enabled remotely by connecting the ENABLE pin to VREC via a pull-up resistor (REN); the value of this resistor is not critical for the DCR02 since only a small current flows. Switch SW1 can be used to pull the ENABLE pin low, thus disabling the output. The switching devices can be a bipolar transistor, FET, or a mechanical device; the main load that it will see is REN. U1 VIN VS VO1 VOUT RERR 10kΩ CIN (1) DCR 02 ERROR ERROR VREC SYNC 0V CFILTER 1µF ENABLE COUT 0.1µF 0V 0VOUT U2 VIN VO2 VOUT VS RERR 10kΩ CIN (1) DCR 02 ERROR VREC SYNC 0V ENABLE ERROR CFILTER 1µF COUT 0.1µF 0V NOTE: (1) Required 2.2µF low ESR ceramic capacitor. Figure 2. Generating Two Positive Voltages from Self-Synchronized DCR02s 7 www.ti.com SBVS028A − DECEMBER 2000 − REVISED APRIL 2004 GENERATION OF DUAL POLARITY VOLTAGES FROM TWO SELF-SYNCHRONIZED DCR02s the supplies must be connected in a star formation, with the tracks made as wide as possible. If the SYNC pin is being used, the tracking between device SYNC pins should be short, to avoid stray capacitance. If the SYNC pin is not being used, it is advisable to place a guard ring (connected to input ground) around this pin to avoid any noise pickup. Two DCR02s can be configured to produce a dual polarity supply (that is, ±5V); the circuit must be connected as shown in Figure 3. It should be observed that both DCR02s are positive voltage regulators; therefore the ERROR, ENABLE, and VREC pins are relative to their respective devices, 0V, and must not be connected together. The output should be taken from the device using ground and power planes. This will ensure minimum losses. A good quality, low ESR ceramic capacitor placed as close as practical across the input will reduce reflected ripple and ensure a smooth startup. PCB LAYOUT Additionally, a good quality, low ESR ceramic capacitor placed as close as practical across the rectifier output terminal and output ground will also give the best ripple and noise performance. RIPPLE AND NOISE Careful consideration should be given to the layout of the PCB in order for the best results to be obtained. The DCR02 is a switching power supply and as such can place high peak current demands on the input supply. In order to avoid the supply falling momentarily during the fast switching pulses, ground and power planes should be used to track the power to the input of DCR02; this will also serve to reduce noise on the circuit. If this is not possible, THERMAL MANAGEMENT Due to the high power density of this device, it is advisable to provide a ground plane on the output. The output regulator is mounted on a copper leadframe, and a ground plane will serve as an efficient heatsink. U1 VIN VS VPOS O/P VOUT ERROR DCR CIN(1) 02 VREC ENABLE SYNC 0V CFILTER 1µF COUT 0.1µF 0V 0V U2 VIN VS VOUT ERROR DCR CIN(1) 02 VREC ENABLE SYNC 0V CFILTER 1µF 0V COUT 0.1µF VNEG O/P NOTE: (1) Required 2.2µF low ESR ceramic capacitor. Figure 3. Dual Polarity Voltage Generation from Two Self-Synchronized DCR02s 8 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) DCR021205P ACTIVE PDIP NVE 10 20 TBD CU SNPB Level-NA-NA-NA DCR021205P-U ACTIVE SOP DVS 10 20 TBD CU SNPB Level-NA-NA-NA DCR022405P ACTIVE PDIP NVE 10 20 TBD Call TI Level-NA-NA-NA DCR022405P-U ACTIVE SOP DVS 10 20 TBD Call TI Level-NA-NA-NA DCR022405P-U/700 ACTIVE SOP DVS 10 700 TBD Call TI Level-NA-NA-NA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI055 – APRIL 2001 NVE (R-PDIP-T10/18) PLASTIC DUAL-IN-LINE 0.920 (23,37) 0.880 (22,35) D 18 10 0.280 (7,11) 0.240 (6,10) D 1 9 Index Area E 0.070 (1,78) 0.045 (1,14) 0.195 (4,95) 0.115 (2,92) Base Plane –C– Seating Plane 0.325 (8,26) 0.300 (7,62) 0.210 (5,33) MAX E 0.005 (0,13) MIN 4 PL Full Lead D 0.100 (2,54) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25) M C 0.150 (3,81) 0.115 (2,92) 0.300 (7,63) 0.014 (0,36) 0.008 (0,20) 0.015 (0,38) MIN 0.060 (1,52) 0.000 (0,00) 0.430 (10,92) MAX F F 4202497/A 03/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001-AC with the exception of lead count. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. A visual index feature must be located within the cross-hatched area. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MPDS113 – OCTOBER 2001 DVS (R-PDSO-G10/18) PLASTIC SMALL-OUTLINE PACKAGE 0.920 (23,37) 0.880 (22,35) C 18 10 0.280 (7,11) 0.240 (6,10) Index Area 1 C 9 0.022 (0,56) 0.014 (0,36) 0.195 (4,95) D 0.070 (1,78) 0.115 (2,92) 0.210 (5,33) MAX 0.045 (1,14) 0.325 (8.26) 0.300 (7,62) 0.043 (1,10) 0.025 (0,65) Base Plane Seating Plane 0.005 (0,13) MIN 4 PL Full Lead 0.420 (10,70) 0.405 (10,30) 0.014 (0,36) 0.008 (0,20) C L 0°± 5° 0.057 (1,45) 0.045 (1,15) 0.100 (2,54) C 0.015 (0,38) MIN 4203553/B 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). D. Maximum dimension does not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25) E. Distance between leads including dambar protrusions to be 0.005 (0,13) minimum. F. A visual index feature must be located within the cross–hatched area. G. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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