ALSC ASM4SSTVF16857-48VT Ddr 14-bit registered buffer Datasheet

August 2004
ASM4SSTVF16857
rev 2.0
DDR 14-Bit Registered Buffer
LVCMOS level at a valid logic state since VREF may
Features
•
not be stable during power-up.
Fully JEDEC JC40 - JC42.5 compliant for DDR1
applications to include: PC1600, PC2100, PC2700
To ensure that outputs are at a defined logic state
& PC3200 ( > JEDEC defined DDR 400 @
before a stable clock has been supplied, RESETB must
200MHz )
be held at a logic low level during power-up.
•
Low voltage operation; VDD: 2.3V - 2.7V.
•
SSTL_2 Class II outputs.
In
•
Differential clock inputs.
application, RESETB is specified to be asynchronous
•
Available in 48 pin TSSOP and TVSOP packages.
with respect to
the
JEDEC
defined
Registered
DDR
DIMM
CLK/CLKB; therefore, no timing
relationship can be guaranteed between the two
signals. When entering a low-power standby mode, the
Product Description
The ASM4SSTVF16857 is a universal 14-bit register
(D F/F based), designed for 2.3V to 2.7V VDD . The
device supports SSTL_2 I/O levels, and is fully
compliant with the JEDEC JC40, JC42.5 DDR I
specifications covering PC1600, PC2100, PC2700, and
PC3200 operational ranges. 14-bit refers to 2Q outputs
for each D input - designed for use in Stacked Registers
(stacked memory devices), Buffered DIMM applications.
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) along with a controlled reset
(RESETB). The positive edge of CLK is used to trigger
register will be cleared and the outputs will be driven to
a logic low level quickly relative to the time to disable
the differential input receivers. This ensures there are
no “glitches” on any output. However, when coming out
of low power standby mode, the register will become
active quickly relative to the time taken to enable the
differential input receivers. When the data inputs are at
a logic level low and the clock is stable during the lowto-high transition of RESETB until the input receivers
are fully enabled, the design ensures that the outputs
will remain at a logic low level.
Applications
the data transfer, and CLKB is used to maintain
sufficient noise margins, whereas the RESETB input is
designed and intended for use at power-up.
The ASM4SSTVF16857 supports a low power standby
mode of operation.
A logic low level at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic low state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
•
JEDEC and Non JEDEC DDR Memory Modules
•Planar configurations
•Supports PC1600 - PC2100 - PC2700 - PC3200
•
SSTL_2I/O
•
Provides a complete support solution for JEDEC
JC42.5 (JC45) DDR I RDIMMs’ when used with the
ASM5CVF857 Zero Delay Buffer.
off. Note that RESETB should be supported with a
Alliance Semiconductor
2575, Augustine Drive  Santa Clara, CA  Tel: 408.855.4900  Fax: 408.855.4999  www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004
ASM4SSTVF16857
rev 2.0
Block Diagram
CLK
CLKB
RESETB
D1
VREF
ASM4SSTVF16857
38
39
34
R
Q1
CLK
D1
48
35
To 13 other channels
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ASM4SSTVF16857
Pin Configurations
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLKB
CLK
VDD
GND
VREF
RESETB
D8
D9
D10
D11
D12
VDD
GND
D13
D14
48-pin TSSOP & TVSOP
6.10 mm body, 0.50 mm pitch - TSSOP
4.40mm body, 0.40mm pitch - TSSOP (TVSOP)
DDR 14-Bit Registered Buffer
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August 2004
ASM4SSTVF16857
rev 2.0
Pin Descriptions
Pin #
Pin Name
Type
Description
1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24
Q (14:1)
O
Data output.
3, 8, 13, 17, 22, 27, 36, 46
GND
P
Ground to entire chip.
4, 9, 12, 16, 21
VDDQ
P
Output supply voltage.
25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48
D(14:1)
I
Data input.
38
CLK
I
Positive clock input.
39
CLKB
I
Negative clock input.
28, 37, 45
VDD
P
Core supply voltage.
34
RESETB
I
Rest Active low.
35
VREF
I
Input reference voltage.
Truth Table1
Inputs
Q Outputs
RESETB
CLK
CLKB
D
Q
L
X or floating
X or floating
X or floating
L
H
H
H
H
L
L
X
Q0
H
L or H
L or H
2
Note:
1. H=High signal level, L=Low signal level, = transition from low to high, = transition from high to low, X = don’t care
2. Output level before the indicated steady state input conditions were established.
DDR 14-Bit Registered Buffer
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August 2004
ASM4SSTVF16857
rev 2.0
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Storage Temperature
-65
+150
°C
Supply Voltage
-0.5
3.6
V
-0.5
VDD + 0.5
V
-0.5
VDD + 0.5
V
1
Input Voltage
1,2
Output Voltage
Input Clamp Current
± 50
mA
Output Clamp Current
±50
mA
Continuous Output Current
±50
mA
VDD, VDDQ or GND current/pin
100
mA
Package Thermal Impedance3
55
°C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged
periods can affect device reliability.
DDR 14-Bit Registered Buffer
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August 2004
ASM4SSTVF16857
rev 2.0
Recommended Operating Conditions
Guaranteed by design. Not 100% tested in production.
Parameter
VDD
VDDQ
VREF
VTT
VI
Description
Supply voltage
Output supply voltage
Reference voltage
(VREF = VDDQ/2)
Min
Typ
Max
Unit
2.3
2.5
2.7
V
PC1600,
PC2100,
PC2700
2.3
PC3200
2.5
PC1600,
PC2100,
PC2700
1.15
PC3200
1.25
1.3
1.35
VREF - 0.04
VREF
VREF + 0.004
V
VDD
V
Termination voltage
Input voltage
2.7
V
2.7
1.25
1.35
V
0
VIH(DC)
DC input high voltage
VIH(AC)
AC input high voltage
VIL(DC)
DC input low voltage
VREF - 0.15
V
VIL(AC)
AC input low voltage
VREF - 0.31
V
VIH
Data
Inputs
Input high voltage level
VREF + 0.15
V
VREF + 0.31
V
1.7
V
RESETB
VIL
Input low voltage level
VICR
Common mode input range
VID
Differential input voltage
VIX
Cross-point voltage of differential clock pair
IOH
CLK
0.97
CLKB
0.36
(VDDQ/2) - 0.2
0.7
V
1.53
V
V
(VDDQ/2) +0.2
V
High-level output current
-20
mA
IOl
Low-level output current
20
mA
TA
Operating free-air temperature
70
°C
0
DDR 14-Bit Registered Buffer
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August 2004
ASM4SSTVF16857
rev 2.0
DC Electrical Characteristics - PC1600, PC2100, PC2700
TA = 0°C to 70°C, VDD = 2.5 ± 0.2V, and VDDQ = 2.5±0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol
Parameter
VIK
Test conditions
VDD
II = -18 mA
Min
Typ
2.3 V
Max
Units
-1.2
V
IOH = -100 A
2.3 V to 2.7 V
VDD - 0.2
V
IOH = -16 mA
2.3 V
1.95
V
IOL = 100 A
2.3 V to 2.7 V
0.2
V
IOL = 16 mA
2.3 V
0.35
V
VI = VDD or GND
2.7 V
±5
A
RESETB = GND
2.7 V
0.01
A
2.7 V
25
mA
VOH
VOL
II
All inputs
Standby
(static)
IDD
Operating
(static)
Dynamic
operating
(clock only)
VI = VIH(AC) or VIL(AC) ,
RESETB = VDD
RESETB = VDD,
VI = VIH(AC) or VIL(AC) ,
CLK and CLKB switching
IO = 0
2.7 V
28
2.7 V
15
A/clock
MHz
50% duty cycle
IDDD
Dynamic
operating
(per each
data input)
RESETB = VDD, VI = VIH(AC) or
VIL(AC), CLK and CLKB =
switching 50% duty cycle;
/clock
MHz/data
One data input switching at half
input
clock frequency, 50% duty cycle
rOH
Output high
IOH = -20 mA
2.3 V to 2.7 V
7
rOL
Output low
IOL = 20 mA
2.3 V to 2.7 V
7
13.5
20

20

4

|rOH - rOL|
rO(D)
each
IO = 20 mA, T A = 25 C
2.5 V
separate bit
Data inputs
Ci
VI = VREF ± 310 mV, VICR = 1.25 V,
2.5 V
2.5
3.5
pF
2.5 V
2.5
3.5
pF
2.5V
2.5
3.5
pF
VI(PP) = 360 mV
CLK & CLKB
RESETB
VI = VDD or GND
DDR 14-Bit Registered Buffer
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August 2004
ASM4SSTVF16857
rev 2.0
DC Electrical Characteristics -PC3200
TA = 0°C to 70°C, VDD = 2.6 ± 0.2V, and VDDQ = 2.6±0.2V (unless otherwise stated)
Guaranteed by design. Not 100% production tested.
Symbol
Parameters
VIK
Test conditions
VDD (V)
II = -18 mA
Min
Typ
2.5
IOH = -100 A
Max
Units
-1.2
V
2.5 V to 2.7
VDD - 0.2
V
IOH = -8 mA
2.5
1.95
V
IOL = 100 A
2.5 V to 2.7
0.2
V
IOL = 8 mA
2.5
0.35
V
VI = VDD or GND
2.7
±5
A
RESETB = GND
2.7
0.01
A
2.7
25
mA
VOH
VOL
II
All inputs
Standby
(static)
IDD
Operating
(static)
Dynamic
operating
(clock only)
VI = VIH(AC) or VIL(AC) ,
RESETB = VDD
RESETB = VDD,
VI = VIH(AC) or VIL(AC) ,
CLK and CLKB switching
2.7
328
2.7
15
A/clock
MHz
IO = 0
50% duty cycle
RESETB = VDD,
IDDD
Dynamic
operating (per
each data
input)
VI = VIH(AC) or VIL(AC) ,
CLK and CLKB =
/clock
switching 50% duty cycle;
MHz/data
One data input switching
input
at half clock frequency,
50% duty cycle
rOH
Output high
IOH = -20 mA
2.5 V to 2.7
7
rOL
Output low
IOL = 20 mA
2.5 V to 2.7
7
rO(D)
|rOH - rOL| each
separate bit
Data inputs
Ci
13.5
20

20

4

IO = 20 mA, T A = 25 C
2.6
VI = VREF ± 310 mV, VICR = 1.25 V,
2.6
2.5
3.5
pF
2.6
2.5
3.5
pF
2.6
2.5
3.5
pF
VI(PP) = 360 mV
CLK & CLKB
RESETB
VI = VDD or GND
DDR 14-Bit Registered Buffer
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August 2004
ASM4SSTVF16857
rev 2.0
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted).
Guaranteed by design. Not 100% production tested.
* this parameter is not necessarily production tested.
VDDQ = 2.5V±0.2V
Symbol
Min
fCLOCK
tW
tACT*
tINACT*
Clock frequency
Max
Min
200
Pulse duration, CK, CKLB high or low
Unit
2.5
Max
270
2.5
MHz
ns
Differential inputs active time
22
22
ns
Differential inputs inactive time
22
22
ns
Setup time, fast slew rate
tS
0.75
0.4
0.9
0.6
0.75
0.4
0.9
0.6
ns
ns
Data before CLK, CLKB
Setup time, slow slew rate
Hold time, fast slew rate
th
ns
ns
Data after CLK, CLKB
Hold time, slow slew rate
tSL
VDDQ = 2.6V±0.1V
Parameters
Output slew rate, measurement point at 20% and 80%
1
4
1
4
V/ns
Note:
1. Data inputs must be low for a minimum time of tACT max, after which RESETB is taken high.
2. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tINACTmax after which RESETB is taken low.
3. For data signal input slew rate >=V/ns
4. For data signal input slew rate >=0.5 V/ns and < 1V/ns
5. CLK,CLKB signals input slew rates are >=1V/ns
DDR 14-Bit Registered Buffer
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August 2004
ASM4SSTVF16857
rev 2.0
Switching Characteristics - PC1600, PC2100, PC2700
(Over recommended operating free-air temperature range unless otherwise noted.)
Symbol
From (input)
VDD = 2.5 V ± 0.2 V
To (output)
fmax
Units
Min
Typ
Max
200
–
–
MHz
2.8
ns
5.0
ns
tPD
CLK, CLKB
Q
1.1
tphl
RESETB
Q
–
–
Switching Characteristics - PC3200
(Over recommended operating free-air temperature range unless otherwise noted.)
Symbol
From (input)
To (output)
VDD = 2.6 V ± 0.1 V
Min
fmax
Typ
Max
280
tPD
CLK, CLKB
Q
tphl
RESETB
Q
1.1
DDR 14-Bit Registered Buffer
Units
MHz
2.2
ns
5.0
ns
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ASM4SSTVF16857
rev 2.0
Parameter Measurement Information (VDD = 2.5 V ± 0.2V)
VTT
RL = 50 
From output under test
Test point
CL = 30 pF1
Load circuit
1
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics:
PRR  10 MHz, Zo = 50 , input slew rate = 1 V/ns ± 20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
VTT = VREF = VDDQ/2.
VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
tPLH and tPHL are the same as tpd.
Input active and inactive times
LVCMOS RESETB
VDD/2
Input
IDD
VDD
VDD /2
0V
tinact
1
tact
IDDH
90%
10%
1
IDDL
IDD tested with clock and data inputs held at V
DD
or GND, and I O = 0 mA.
Pulse duration
tw
Input
VREF
VIH
VREF
VIL
Setup and hold times
VI(pp)
ts
Input
Propagation delay times
VICR
Timing input
VREF
th
VREF
DDR 14-Bit Registered Buffer
VIH
VIL
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ASM4SSTVF16857
rev 2.0
VI(pp)
Timing input
Output
VICR
VICR
tPLH
tPHL
VTT
VTT
LVCMOS RESETB
Input
VOH
VOL
VIH
VDD/2
VIL
tPHL
Output
VTT
VOH
VOL
DDR 14-Bit Registered Buffer
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ASM4SSTVF16857
rev 2.0
Package Dimensions (48- Pin TSSOP)
c
N
Millimeters
L
Min
Max
Min
Max
A
–
1.20
–
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.17
0.27
0,007
0.011
c
0.09
0.20
0.0035
0.008
E1 E
Index area
2
D

A2
A
e
b
A1
D
Seating plane
aaaC
Inches
Symbol
See variations below
E
E1
8.10 basic
6.00
e
6.10 mm (240 mil) body,
0.50 mm (0.020 mil) pitch TSSOP
L
6.20
0.50 basic
0.45
N
0.75
0.319 basic
0.236
0.244
0.020 basic
0.018
0.030
See variations below
a
0
8
0
8
aaa
–
0.10
–
0.004
Variations:
D (mm)
D (inch)
N
48
DDR 14-Bit Registered Buffer
Min
Max
Min
Max
12.40
12.60
0.488
0.496
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ASM4SSTVF16857
rev 2.0
Package Dimensions (Alternate size)
c
N
Millimeters
L
E1 E
Index area
2
D

A2
A
e
b
A1
Min
Max
Min
Max
A
–
1.20
–
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.32
0.041
b
0.13
0.23
0,005
0.009
c
0.09
0.20
0.0035
0.008
D
Seating plane
aaaC
See variations below
E
E1
6.40 basic
4.30
e
4.40 mm (173 mil) body,
0.40 mm (16 mil) pitch TVSOP
Inches
Symbol
L
4.50
0.40 basic
0.45
0.75
N
0.252 basic
0.169
0.177
0.016 basic
0.018
0.030
See variations below
a
0
8
0
8
aaa
–
0.08
–
0.003
:
Variations
D (mm)
D (inch)
N
48
DDR 14-Bit Registered Buffer
Min
Max
Min
Max
9.60
9.80
0.378
0.386
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ASM4SSTVF16857
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Ordering Codes
Ordering Number
Marking
Package Type
ASM4SSTVF16857-48TT
AS4SSTVF16857T
48-pin TSSOP, tube
ASM4SSTVF16857-48TR
AS4SSTVF16857T
48-pin TSSOP, tape and reel
ASM4SSTVF16857-48VT
AS4SSTVF16857V
48-pin TVSOP, tube
ASM4SSTVF16857-48VR
AS4SSTVF16857V
48-pin TVSOP, tape and reel
DDR 14-Bit Registered Buffer
Quantity
per reel
Temperature
0C to 70C
2500
0C to 70C
0C to 70C
2500
0C to 70C
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August 2004
ASM4SSTVF16857
rev 2.0
Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright ÿ Alliance Semiconductor
All Rights Reserved
Advance Information
Part Number: ASM4SSTVF16857
Document Version: v2.0
© Copyright 2004 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance.
Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is
under development, significant changes to these specifications are possible. The information in this product data
sheet is intended to be general descriptive information for potential customers and users, and is not intended to
operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any
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related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as
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manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
DDR 14-Bit Registered Buffer
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ASM4SSTVF16857
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DDR 14-Bit Registered Buffer
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