CXD3519TQ Reference Voltage and Driver IC for LCD Description The CXD3519TQ is suitable IC for applying reference voltage for gamma correction which is necessary for TFT liquid crystal display. This IC has a built-in 9 channels of rail-to-rail buffer circuit which enables 2-input switch and a common driver circuit. Features • Built-in 9 channels of rail-to-rail buffer circuit • Built-in common driver circuit • Current consumption: 3.6mA (typ.) • Package: 48-pin TQFP 48 pin TQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS – 0.3 to +6.0 V • Input pin voltage VI VSS – 0.3 to VDD + 0.3 V • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation (Ta ≤ 85°C) 220 mW PD Structure CMOS IC Applications Small liquid crystal monitor Operating Conditions • Supply voltage VDD 4.5 to 5.5 (5.0 typ.) • Operating temperature Topr –35 to +85 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00Y07-PS CXD3519TQ NC VL4 VH4 VL5 VH5 VL6 VH6 VL7 VH7 VL8 VH8 NC Block Diagram 36 35 34 33 32 31 30 29 28 27 26 25 NC 37 24 NC GND 38 23 GND V6 39 22 V7 V5 40 21 V8 V4 41 20 NC NC 42 19 VDD VDD 43 18 V2 V1 44 17 V3 V0 45 16 GND GND 46 15 VDD buff 1 2 3 4 5 6 7 8 9 10 11 12 VL2 VH1 VL1 VH0 VL0 SW SW GND NC 13 NC VH2 NC 48 VL3 14 COMOUT VH3 NC 47 –2– CXD3519TQ Pin Description Pin No. Symbol 1 VH3 2 VL3 3 VH2 4 VL2 5 VH1 6 VL1 7 VH0 8 VL0 26 VH8 27 VL8 28 Pin voltage Equivalent circuit 0.5 to 4.0V (max.: 2.0Vp-p) DC input when SW is high. DC input when SW is low. DC input when SW is high. VDD DC input when SW is low. DC input when SW is high. 1 26 VH 0.2 to 4.8V 5 30 DC input when SW is high. 7 32 DC input when SW is low. 34 DC input when SW is low. 30 VH6 8 33 31 VL6 35 32 VH5 VH4 35 VL4 45 V0 44 V1 18 V2 39 V6 22 21 DC input when SW is high. 4 29 VL7 34 DC input when SW is high. 2 27 29 VL5 DC input when SW is low. 3 28 VH7 33 VL DC input when SW is low. 6 31 DC input when SW is high. DC input when SW is low. DC input when SW is high. 0.5 to 4.0V (max.: 2.0Vp-p) GND DC input when SW is low. DC input when SW is high. DC input when SW is low. V0 output. VDD 0.2 to 4.8V V1 output. V2 output. 17 39 18 40 V6 output. V7 21 41 V7 output. V8 22 44 V8 output. 17 V3 41 V4 40 V5 45 0.5 to 4.0V V3 output. V4 output. GND V5 output. VDD 9 Input switch. For V0 to V8 output, VL is output for low; VH for high. For COMOUT output, VDD level is output for low; GND level for high. Also, Pins 9 and 10 are connected internally. Input the same signal, or input one signal and leave the other signal open. SW 9 10 10 Description SW GND –3– CXD3519TQ Pin No. Symbol Pin voltage Equivalent circuit Description VDD 14 COMOUT 14 COMOUT COM output. GND 15 VDD 5.0V 5V power supply. 19 VDD 5.0V 5V power supply. 43 VDD 5.0V 5V power supply. 11 GND GND. 16 GND GND. 23 GND GND. 38 GND GND. 46 GND GND. 12 NC No connected. 13 NC No connected. 20 NC No connected. 24 NC No connected. 25 NC No connected. 36 NC No connected. 37 NC No connected. 42 NC No connected. 47 NC No connected. 48 NC No connected. Note) • GND Make sure that Pins 11, 16, 23, 38 and 46 are connected to GND potential, and do not release them. • Decoupling capacitor Locate decoupling capacitor connected between power supply and GND as near IC pin as possible. • Design VH and VL input pins not to have capacity. –4– CXD3519TQ Electrical Characteristics (Ta = 25°C, VDD = 5V) No. Item Symbol Conditions Min. Typ. Max. Unit — 3.6 6.0 mA 1 Current consumption ICC Input voltage = 2.5V, No load 2 VH, VL input current high IIH Input voltage = 4.8V –0.1 — 0.1 µA 3 VH, VL input current low IIL Input voltage = 0.2V –0.1 — 0.1 µA 4 SW input current high IISH Input voltage = 5V –10 — 10 µA 5 SW input current low IISL Input voltage = 0V –10 — 10 µA 6 VREF voltage gain AV Input voltage = 0.2 to 4.8V 0.985 — — V/V 7 SW input voltage high VIH 2.0 — — V 8 SW input voltage low VIL — — 0.8 V 9 VREF output voltage high VOH ISOURCE = 10mA VDD – 1.0 — — V 10 VREF output voltage low VOL ISINK = 10mA — — GND + 1.0 V 11 COMOUT output voltage high VCOH VDD – 0.1 — — V 12 COMOUT output voltage low VCOL — — GND + 0.1 V 13 VREF offset voltage VOFF — — 20 mV 14 VREF (V0, 1, 2, 6, 7, 8) load regulation 1 ∆VO1 Input voltage = 0.2 to 4.8V ISOURCE = 10mA ISINK = 10mA — ±5 ±10 mV 15 VREF (V3, 4, 5) load regulation 2 ∆VO2 Input voltage = 0.5 to 4.0V ISOURCE = 10mA ISINK = 10mA — ±7 ±14 mV 16 Setting time 1 Measurement circuits 1, 2 — — 10 µs 17 Setting time 2 Measurement circuit 3 — — 6 µs 18 Output impedance V0 – V8 — 15 — Ω ts1 ts2 ts3 ts4 Rimp ISOURCE = 10mA ISINK = 10mA –5– CXD3519TQ Measurement Circuits Measurement circuit 1 VH 4.8V 15Ω Measurement point 0.2V VL V0, V1, V2, V6, V7, V8 30nF V3, V4, V5 30nF Measurement circuit 2 VH 4.0V (max.) 15Ω Measurement point 2.0Vp-p (max.) 0.5V (min.) VL Measurement circuit 3 5.0V 15Ω Measurement point V0, COMOUT 0V SW 50% 30nF 50% 90% Output (V0 to V8) 10% ts1 ts2 10% Output (VCOM) 90% ts3 ts4 –6– CXD3519TQ Application Circuit 5V 0.01µ 47µ 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 To LCD 39 22 To LCD To LCD 40 21 To LCD To LCD 41 20 42 19 43 18 To LCD To LCD 44 17 To LCD To LCD 45 16 46 15 buff 14 48 13 1 2 3 4 5 6 7 8 9 10 11 0.01µ 47µ 47 To LCD (VCOM) 12 Polarity inverted pulse Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –7– CXD3519TQ Package Outline Unit: mm 48PIN TQFP (PLASTIC) 1.2 MAX 9.0 ± 0.2 7.0 ± 0.1 (1.0) 36 25 0.1 37 24 A 13 48 1 12 + 0.1 0.2 – 0.05 0.5 0.1 + 0.07 0.125 – 0.02 M 0.5 ± 0.2 0.1 ± 0.1 0˚ to 10˚ DETAIL A SONY CODE EIAJ CODE PACKAGE STRUCTURE TQFP-48P-L061 P-TQFP48-7X7-0.5 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN TERMINAL TREATMENT SOLDER PLATING TERMINAL MATERIAL COPPER ALLOY PACKAGE MASS 0.15g LEAD SPECIFICATIONS ITEM SPEC. LEAD MATERIAL COPPER ALLOY LEAD TREATMENT Sn-Pb 10% LEAD TREATMENT THICKNESS 5-18µm –8– Sony Corporation